Post-polishing topography generation system and method for enhanced wafer manufacturing - Patents.com

Abstract

The computing device is programmed to store a model for transforming the shape map to simulate a portion of an assembly line, receive scan data of a first inspection of a product being assembled, generate a shape map from the scan data of the first inspection, run the model using the shape map as an input to generate a final shape map of the product, compare the final shape map to one or more thresholds, determine whether the final shape map exceeds at least one of the one or more thresholds, and cause the first machine to adjust if it is determined that the final shape map exceeds at least one of the one or more thresholds.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application No. 17 / 652,571, filed February 25, 2022, the entire disclosure of which is incorporated herein by reference in its entirety. [Technical field]

[0002] The technical field relates generally to enhanced wafer manufacturing, and more specifically to enhanced wafer analysis using nanotopography. [Background technology]

[0003] Semiconductor wafers, such as silicon wafers, are commonly used as substrates in the manufacture of integrated circuit (IC) chips. Chipmakers require wafers with extremely flat and parallel surfaces to ensure that they can produce the maximum number of chips from a single wafer. After being sliced ​​from an ingot, the wafers typically undergo grinding and polishing processes to improve certain surface characteristics, such as flatness and parallelism.

[0004] To identify and address concerns about topology degradation, equipment and semiconductor material manufacturers consider the nanotopography of the wafer surface. For example, SEMI (Semiconductor Equipment and Materials International), an international semiconductor industry trade association, defines nanotopography as the deviations of the wafer surface at spatial wavelengths from about 0.2 mm to about 20 mm (SEMI Document 3089). This spatial wavelength is very close to the nanometer-scale surface features of a processed semiconductor wafer. Nanotopography measures the height deviations of the wafer surface and does not take into account the variations in wafer thickness as in traditional flatness measurements. Two techniques are commonly used to measure nanotopography: light scattering and interferometry. These techniques use light reflected from the surface of a polished wafer to detect very small surface variations.

[0005] In the semiconductor industry, companies compete to produce high-quality silicon wafers at low cost. Therefore, having a highly efficient manufacturing process with minimal losses is a competitive advantage. Manufacturing processes such as slicing and grinding with wire saws can create topographical features on the wafer, which can lead to topography degradation. In addition, typical metrology tools used to measure after these processes tend to be noisy. Also, the surface roughness is too large after these processes to allow the use of post-polishing tools. To avoid these issues, it is very important to closely monitor the post-polishing maps (e.g., in-plane distortion (IPD), nanotopography (NT), and post-polishing shape maps) at each stage of silicon wafer manufacturing. However, most post-polishing maps are only available at the final stage of manufacturing, which makes the feedback process very inefficient.

[0006] In some systems, many wafers may be processed after grinding before a problem is detected in the grinding process. Also, each manufacturing line and grinder may have specific characteristics that vary from one piece of equipment to another. Therefore, a system is needed to analyze wafers to quickly and efficiently detect potential problems, increasing efficiency while reducing material loss.

[0007] This Background section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure that are described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to better understand the various aspects of the present disclosure. As such, it should be understood that these disclosures are to be read in this light, and not as admissions of prior art. Summary of the Invention

[0008] In one embodiment, a computing device includes at least one processor (or "processor") in communication with at least one memory device. The processor is programmed to store in the at least one memory device a shape map transformation model for simulating a portion of an assembly line. The processor is also programmed to receive scan data of a first inspection of a product being assembled. The first inspection is performed at a first inspection station of the assembly line following a first device of the assembly line. The processor is further programmed to generate a shape map from the scan data of the first inspection. The processor is further programmed to run the model using the shape map as an input to generate a final shape map of the product. The processor is further programmed to compare the final shape map to one or more thresholds. The processor is further programmed to determine whether the final shape map exceeds at least one of the one or more thresholds. If a determination is made that the final shape map exceeds at least one of the one or more thresholds, the processor is programmed to adjust the first device.

[0009] In another aspect, a method of analyzing an assembly line is performed by a computing device including at least one processor in communication with at least one memory device. The method includes storing, in the at least one memory device, a shape map transformation model for simulating a portion of the assembly line. The method also includes receiving scan data of a first inspection of a product being assembled. The first inspection is performed at a first inspection station of the assembly line following a first device of the assembly line. The method further includes generating a shape map from the scan data of the first inspection. The method further includes running the model using the shape map as an input to generate a final shape map of the product. The method further includes comparing the final shape map to one or more thresholds. The method further includes determining whether the final shape map exceeds at least one of the one or more thresholds. If a determination is made that the final shape map exceeds at least one of the one or more thresholds, the method includes adjusting the first device.

[0010] Various refinements exist in the features described in connection with the above aspects. Furthermore, the above features may also incorporate additional features. These refinements and additional features may exist individually or in any combination. For example, the various features described below in connection with any of the illustrated embodiments may be incorporated in any of the above features, either alone or in any combination. [Brief description of the drawings]

[0011] [Figure 1] 1 is a block diagram showing a semiconductor wafer processing system according to one embodiment. [Diagram 2] 2 is a flowchart showing an example of a process for evaluating a wafer using the system shown in FIG. 1. [Diagram 3] 3 is a simplified block diagram of an example system for evaluating a wafer according to the system shown in FIG. 1 and using the process shown in FIG. 2. [Figure 4]FIG. 4 is a diagram illustrating an example of a configuration of a client computer device illustrated in FIG. 3. [Diagram 5] FIG. 4 illustrates an example of a configuration of a server system illustrated in FIG. [Figure 6] FIG. 2 illustrates an example of a line scanning process performed by a measurement device. [Figure 7A] 7A-7C further illustrate the example line scan process shown in FIG. 6. [Figure 7B] 7A-7C further illustrate the example line scan process shown in FIG. 6. [Figure 8A] FIG. 2 is a side view of the wafer. [Figure 8B] FIG. 2 is a side view of the wafer. [Figure 9A] FIG. 2 is a top view of the wafer showing the scan lines obtained across the wafer. [Figure 9B] FIG. 2 is a top view of the wafer showing the scan lines obtained across the wafer. [Figure 10A] We demonstrate the use of a trained neural network model to convert the post-grind topography map into a predicted post-polishing NT map. [Figure 10B] We demonstrate the use of a trained neural network model to convert a GAPI RMS map into a predicted IPD map. [Figure 11A] 1 shows an image of a wafer topography map. [Figure 11B] 11B shows an example of a graph comparing the predicted NT map shown in FIG. 11A with the actual image after grinding. [Figure 12A] 1 shows an image of a wafer topography map. [Figure 12B] 12B shows an example of a graph comparing the predicted NT map shown in FIG. 12A with the actual image after grinding. [Figure 13A] 1 shows an image of a wafer topography map. [Figure 13B] 13B shows an example of a graph comparing the predicted IPD map shown in FIG. 13A with the actual image after grinding.

[0012] Corresponding reference characters indicate corresponding parts throughout the several views of the drawings. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The described implementations relate to systems and methods for analyzing wafer data, and more particularly, to analyzing a post-processing surface of a wafer to predict the post-processing surface of the wafer. More specifically, a wafer surface analysis model executed by a computing device (1) determines a current state of the wafer, (2) predicts a post-processing state of the wafer based on the current state and the model, and (3) determines whether adjustments are required to the grinder based on the post-processing state of the wafer and one or more predefined thresholds. The systems and methods allow for feedback of the nanotopography in less time and with greater accuracy compared to previous processes, allowing adjustments to be made to improve the nanotopography to be recognized and implemented with less lag time, thereby improving quality control and / or wafer yield.

[0014] A computer system, such as a wafer surface analysis computer device and related computer systems, includes a processor and a memory. However, a processor in a computer device as referred to herein may refer to one or more processors, whether the processor is in one computing device or in multiple computing devices operating in parallel. Additionally, a memory in a computer device as referred to herein may refer to one or more memories, whether the memory is in one computing device or in multiple computing devices operating in parallel.

[0015] A processor may include any programmable system, including systems that use microcontrollers, reduced instruction set circuits (RISC), application specific integrated circuits (ASICs), logic circuits, and other circuits or processors capable of performing the functions described herein. The above examples are illustrative only, and thus are not intended to limit the definition and / or meaning of the term "processor."

[0016] The term "database" may refer to a collection of data, a relational database management system (RDBMS), or both. As used herein, a database may include any collection of data, including hierarchical databases, relational databases, flat file databases, object-relational databases, object-oriented databases, and any other structured collection of records or data stored in a computer system. The above examples are for illustrative purposes only and are not intended to limit the definition and / or meaning of the term database. Examples of RDBMS include, but are not limited to, Oracle® Database, MySQL, IBM® DB2, Microsoft® SQL Server, Sybase®, PostgreSQL, and the like. However, any database that can be used with the systems and methods described herein (Oracle is a registered trademark of Oracle Corporation, Redwood Shores, Calif.; IBM is a registered trademark of International Business Machines Corporation, Armonk, New York; Microsoft is a registered trademark of Microsoft Corporation, Redmond, Washington; and Sybase is a registered trademark of Sybase, Dublin, Calif.).

[0017] In one embodiment, the computer program is embodied in a computer readable medium. In one example, the system runs on a single computer system without requiring connection to a server computer. In a further example embodiment, the system runs in a Windows environment (Windows is a registered trademark of Microsoft Corporation, Redmond, Washington). In yet another embodiment, the system runs in a mainframe environment and a UNIX server environment (UNIX is a registered trademark of X / Open Company Limited, Reading, Berkshire, England). In yet another embodiment, the system runs in an iOS environment (iOS is a registered trademark of Cisco Systems, Inc., San Jose, California, USA). In yet another embodiment, the system runs in a Mac OS environment (Mac OS is a registered trademark of Apple Inc., Cupertino, California). In yet another embodiment, the system runs in an Android OS (Android is a registered trademark of Google, Inc., Mountain View, California). In another embodiment, the system runs in a Linux OS (Linux is a registered trademark of Linus Torvalds, Boston, Massachusetts). The application is flexible and designed to run in a variety of different environments without compromising its primary functionality. In some embodiments, the system includes multiple components distributed across multiple computing devices. One or more of the components are embodied in a computer-readable medium in the form of computer-executable instructions. The systems and processes are not limited to the specific embodiments described herein. Furthermore, each system and each process component can be implemented separately and independently from other components and processes described herein. Each component and process can also be used in combination with other assembly packages and processes.

[0018] It should be understood that elements or steps described in the singular and proceeding with "a" or "an" do not exclude a plurality of elements or steps, unless the exclusion is expressly stated. Furthermore, references to an "exemplary embodiment" or "one embodiment" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

[0019] The terms "software" and "firmware" are used interchangeably and include any computer program stored in memory for execution by a processor, including RAM memory, ROM memory, EPROM memory, EEPROM memory, and non-volatile RAM (NVRAM) memory. The above memory types are exemplary only and thus do not limit the types of memory that can be used to store computer programs.

[0020] The term "real-time" refers to at least one of the time of occurrence of relevant events, the time of measurement and collection of given data, the time of processing the data, and the time of response of the system to events and circumstances. These activities and events occur substantially instantaneously.

[0021] The systems and processes are not limited to the specific embodiments described herein. Furthermore, each system and process component can be implemented separately and independently from other components and processes described herein. Also, each component and process can be used in combination with other assembly packages and processes.

[0022] 1 shows a block diagram of a system 100 for processing semiconductor wafers. The system 100 begins with a slicer 105 in the silicon wafer manufacturing process. In an exemplary embodiment, the slicer 105 is a wire saw that cuts a disk of silicon material.

[0023] After the slicer 105 slices the wafer, the wafer is analyzed by a first metrology device 110 that measures data to generate a profile of the wafer. At this point, the wafer is not ground, etched, or polished. The first metrology device 110 provides measurement data from the ground wafer to a wafer surface analysis (WSA) computing device 115. In some embodiments, the first metrology device 110 uses a capacitance probe or a laser-based distance sensor to measure the wafer. In particular, the WAS computing device 115 uses the post-slicing shape data and the GAPI RMS data to generate in-plane distortion (IPD), nanotopography (NT), and shape distribution maps of the silicon wafer. As used herein, GAPI RMS refers to a shape-based matrix that is an index of the smoothness of the wafer substrate.

[0024] The GAPI RMS can be calculated by the WSA computing device 115. First, the WSA computing device 115 reads the raw measurement data, such as from the first measuring device 110. The raw measurement data includes thickness and bottom (or front) profiles. The WSA computing device 115 converts this raw data into multiple diameter line scan profiles. The number of diameter scan profiles can be 2, 4, 8, or more. The WSA computing device 115 calculates the least squares best fit to the thickness plane. The WSA computing device 115 calculates the raw shape diameter scan profile by the low profile plus half the thickness of the thickness best fit plane. The WSA computing device 115 smoothes the raw shape diameter scan profile by a moving average with a defined window size. The WSA computing device 115 calculates the ideal shape diameter scan profile by each raw shape diameter scan profile by one-dimensional polynomial fitting. The WSA computing device 115 determines that the delta of the feature diameter scan profile is equal to the raw feature diameter scan profile minus the ideal feature diameter scan profile.

[0025] The WSA computer device 115 calculates the weighting profile by delta shape variation and slope change within a moving window defined along the diameter direction. A threshold is also defined to detect high variation and slope change. Delta shape variation can be standard variation, variance, or range. Slope change means, for example, that the product of the left slope and the right slope is negative. GAPI represents the gap between the raw shape and the ideal shape, which is equal to the diameter of the delta shape multiplied by the weighting profile. GAPI RMS is the root mean square of GAPI.

[0026] The WSA computing device 115 analyzes the measurement data of the wafer to determine a profile of the wafer after slicing. If the determined profile exceeds any of the quality thresholds, the WSA computing device 115 can determine that the slicer 105 or other equipment needs to be adjusted.

[0027] The next device in the system 100 is the grinder 120, which may be single or double sided. Simultaneous double sided grinding grinds both sides of the wafer at the same time, producing a wafer with a highly planarized surface. These grinders 120 use a wafer clamping device to hold the semiconductor wafer during grinding. This clamping device typically includes a pair of hydrostatic pads and a grinding wheel. The pads and wheels are arranged in opposing positions to hold the semiconductor wafer vertically between them. The hydrostatic pads form a fluid barrier between each pad and the wafer surface, holding the wafer without the hard pads physically contacting the wafer during grinding. This reduces damage to the wafer that may be caused by physical clamping, and the wafer moves (rotates) tangentially relative to the pad surface, reducing friction. While this grinding process improves the flatness and / or parallelism of the ground wafer surface, it can degrade the topology of the wafer surface. Specifically, misalignment of the clamping surfaces of the hydrostatic pads and grinding wheels is known to cause such degradation. Post-grind polishing creates a highly reflective mirror surface on the ground wafer, but does not improve the topology degradation.

[0028] After the grinder 120 grinds the wafer, the measurement data is analyzed by the second measurement device 125 to generate a profile of the ground wafer. At this point, the wafer is neither etched nor polished. The second measurement device 125 provides measurement data from the ground wafer to the wafer surface analysis (WSA) computing device 115. In some embodiments, the second measurement device 125 measures the wafer using a capacitance probe or a laser-based distance sensor. In particular, the WAS computing device 115 uses the post-grind shape and GAPI (gap between raw shape and ideal shape) RMS (root mean square) data to generate in-plane distortion (IPD), nanotopography (NT), and shape distribution maps of the silicon wafer.

[0029] The WSA computing device 115 analyzes the measurement data of the wafer to determine a profile of the wafer after grinding. If the determined profile exceeds a quality threshold, the WSA computing device 115 can determine that adjustments to the grinder 120 or other equipment are necessary.

[0030] The system 100 may include multiple grinders 120, where each grinder 120 grinds a wafer, but each wafer is ground only once. In these embodiments, the WSA computing device 115 tracks the grinding results of each of the multiple grinders 120.

[0031] System 100 includes multiple post-grind devices, such as an etching device 130 for etching the ground wafer, a surface metrology device 135 for measuring the surface flatness of the etched wafer, a polishing device 140 for polishing the etched wafer, and a nanotopography measurement device 145 for measuring the nanotopography of the polished wafer. In other embodiments, other devices may be included in system 100.

[0032] The WSA computing device 115 includes a model of the device in the system 100, which simulates etching, polishing, and possibly grinding of the wafer based on measurements of the wafer, and predicts the surface of the wafer after polishing. The surface after polishing is similar to the surface measured by the nanotopography measurement device 145. As described further herein, the WSA computing device 115 generates the model based on a plurality of historical data for a plurality of manufactured wafers. The historical data is based on at least a comparison of the wafer with the first measurement device 110 (after slicing) or the second measurement device 125 (after grinding) and the nanotopography measurement device 145 (after polishing).

[0033] The WSA computing device 115 creates a model for each system 100 that it analyzes. For example, a fab may have multiple production lines for manufacturing wafers. For each production line, the WSA computing device 115 generates a separate model. In some embodiments where multiple slicers 105 or grinders 120 use the same post-grinder process, the WSA computing device 115 may use the same model.

[0034] 2 is a flow chart illustrating an exemplary process 200 for evaluating a wafer using system 100 (shown in FIG. 1). In an exemplary embodiment, the steps of process 200 are performed by WSA computing device 115 (shown at 1).

[0035] Prior to process 200, at least one neural network model is constructed. The neural network models are trained using a plurality of historical images. A first neural network model is trained to receive a shape map of a ground or sliced ​​wafer and determine a post-polishing NT map from the input shape map. A second neural network model is trained to receive a GAPI RMS map of a ground or sliced ​​wafer and determine an IPD map of the wafer. Both neural network models are trained using a plurality of historical images and a generative adversarial network (GAN).

[0036] A GAN architecture consists of a generative model to output new plausible synthetic images, and a discriminative model to classify images as either real (from the dataset) or fake (generated). The discriminative model is updated directly, while the generative model is updated via the discriminative model. Thus, the two models are trained simultaneously in an adversarial process where the generator aims to fool the discriminator, and the discriminator aims to more accurately identify fake images.

[0037] In the GAN model described herein, the generation of an output image depends on the input, which in this case is the source image. The classifier includes both the source image and the target image and must determine if the target is a plausible transformation of the source image. The generator is trained with an adversarial loss that encourages the generator to generate plausible images in the target domain. The generator is also updated with an L1 loss that is measured between the generated image and the expected output image. This additional loss encourages the generative model to create a plausible transformation of the source image. The input to the model is either 4-line scan data or 8-line scan data. Further discussion on training the model is provided below.

[0038] Wafer processing 205 may include slicing by slicer 105 and / or grinding by grinder 120 (both shown in FIG. 2). After processing 205, at least one of first measurement device 110 and second measurement device 125 (both shown in FIG. 1) measures 210 the ground wafer and sends the current measurements after processing to WSA computing device 115. WSA computing device 115 calculates a GAPI RMS map from the current measurements and calculates the GAPI RMS map from a predefined algorithm.

[0039] The WSA computing device 115 executes the neural network model described above to generate a shape map, such as a post-polish NT map and / or an IPD map. For purposes of this disclosure, the neural network model can convert a shape map to a post-polish NT map or a GAPI RMS map to an IPD map. The WSA computing device 115 then calculates predicted wafer attributes based on the shape map. These wafer attributes include, but are not limited to, average IPD, THA1010, and THA2525. THA1010 and THA2525 are nanotopography parameters calculated based on the nanotopography map. THA1010 records peak and valley difference values ​​in a moving window of 10 mm x 10 mm, which is moved across the wafer, and a particular percentile value of the recorded values ​​is considered the THA1010 value. The percentile value can vary and is typically specified by the end user. The THA2525 is similar to the THA1010, except that the window is a 25 mm by 25 mm square or a 25 mm diameter circle. The wafer attributes predict the state of the wafer at the end of processing, as measured by the nanotopography measurement tool 145.

[0040] The WSA computing device 115 compares the wafer attributes to one or more predetermined thresholds. In an exemplary embodiment, the predetermined thresholds are requirements for a proper surface of the wafer after polishing. In an exemplary embodiment, the predetermined thresholds and / or requirements are based in part on one or more user preferences from the wafer manufacturer and / or the customer purchasing the wafer.

[0041] If the wafer attributes are within the acceptable range, the WSA computing device 115 stores the data and moves on to analyze the next wafer. The stored wafer attributes can be used to refine the neural network and / or detect one or more trends. If the wafer attributes are not within the acceptable range, the WSA computing device 115 may issue a warning and adjust one or more pieces of equipment, such as the slicer 105, grinder 120, etcher 130, and polisher 140. In some embodiments, the WSA computing device 115 adjusts the equipment directly. In other embodiments, the WSA computing device 115 instructs another piece of equipment to adjust the equipment. In yet other embodiments, the WSA computing device 115 instructs a user to adjust the equipment.

[0042] The WSA computing device 115 determines that the wafer is within tolerance, but at the same time determines that one or more of the devices are no longer properly adjusted. In these embodiments, the WSA computing device 115 may determine that the device is falling out of proper adjustment based on a current trend of post-processing inspection of multiple wafers. The WSA computing device 115 may recognize the trend and determine that an adjustment will be required after a certain number of uses or a certain period of time. In these embodiments, the WSA computing device 115 may determine the next planned downtime of the system 100. If the planned downtime is before the device is expected to fall out of proper adjustment, the WSA computing device 115 may schedule the device adjustment to occur during the planned downtime. The WSA computing device 115 may determine when the device is expected to produce an out-of-tolerance wafer based on one or more predetermined thresholds, the amount of change in the post-processing results for each wafer, and the model.

[0043] The WSA computing device 115 generates the model based on multiple historical data including past post-slicing measurements by the first measuring device 110, past post-grinding measurements by the second measuring device 125, and past post-polishing measurements by the nanotopography measuring device 145. In an exemplary embodiment, the WSA computing device 115 generates the model by comparing the post-slicing / grinding wafer images with the post-polishing wafer images to determine how the wafer changes as the system 100 processes the wafer. In some embodiments, the WSA computing device 115 stores a trained generic model for a particular production line (system 100) using past inspection data from that production line. In other embodiments, the WSA computing device 115 generates the model entirely from the historical data for that production line. In still other embodiments, the model is continually updated based on the measurement data of the nanotopography measuring device 145 of the production line during production. This allows the model to most accurately model the current production line (system 100). In other embodiments, the model is updated or calibrated only every six months or other predetermined period. This embodiment is best suited when other equipment in the system 100 does not change regularly or require recalibration. In some embodiments, whenever equipment is replaced, calibrated, or otherwise modified, the model is updated and calibrated to the current conditions of the production line.

[0044] Although the system 100 and process 200 are described for a semiconductor wafer manufacturing assembly line, one skilled in the art will appreciate that the disclosure may be used with other assembly lines. In these other embodiments, the system 100 is considered an assembly line 100 for making a product. The assembly line includes a first machine 105, a first inspection station 110, a computing device 115, a second machine 140, a second inspection station 145, and optionally a third machine 120 and a third inspection station 125. In these other embodiments, the computing device 115 stores a model for simulating a portion of the assembly line 100 in at least one memory device. The computing device 115 receives scan data of a first inspection of the product being assembled. The first inspection is performed at a first inspection station 110 (or 125) in the assembly line 100 that follows the first machine 105 (or 120) in the assembly line 100. The computing device 115 runs the model using the scan data as input to generate a final profile and / or attributes of the product.

[0045] The computing device 115 compares the final profile to one or more thresholds. The computing device 115 determines whether the final profile exceeds at least one of the one or more thresholds, thereby exceeding one or more tolerance values. If it is determined that the final profile exceeds at least one of the one or more thresholds, the computing device 115 causes 240 the first device 105 (or 120).

[0046] The computing device 115 may generate a model to simulate a portion of the assembly line 100 based on the plurality of inspection data of the assembly line 100. The model generates a final profile of the product that simulates an actual profile of the product upon reaching the second inspection station 145. In some further embodiments, the second inspection station 145 is located after the completion of the assembly line 100. In some embodiments, the plurality of inspection data includes a first plurality of scan data of the plurality of individual products at the first inspection station 110 and a second plurality of scan data of the plurality of individual products at the second inspection station 145. In some further embodiments, the computing device 115 receives scan data of a second inspection of the product being assembled at the second inspection station 145. The computing device 115 compares the scan data of the second inspection to the final profile. The computing device 115 adjusts the model based on the comparison.

[0047] In another embodiment, the computing device 115 generates a model to simulate a portion of the assembly line 100. The model generates a final profile and attributes of the product that simulates the actual profile upon reaching the final inspection station 145. The model can receive scan data from the first inspection station 110 after the first processing station 105 and / or scan data from the second inspection station 125 after the second processing station 120. The computing device 115 then generates a profile of the product based on input from both inspection stations 110 and 125.

[0048] If the final profile is determined to exceed at least one of the one or more thresholds, the computing device 115 analyzes the multiple past tests to determine a trend. Based on the trend, the computing device 115 predicts the likelihood that a subsequent test of a subsequent product will exceed at least one of the one or more thresholds. Based on the trend, the computing device 115 adjusts the first device 105 or the second device 120.

[0049] 3 is a simplified block diagram of an example of a system 300 for evaluating a wafer using the process 200 shown in FIG. 2 in accordance with the system 100 shown in FIG. 1. In an exemplary embodiment, the system 300 is used to analyze a ground wafer to determine whether it will be within tolerance after polishing. Additionally, the system 300 is a real-time data analysis and classification computer system that includes a wafer surface analysis (WSA) computing device 310 (also referred to as a WSA server). The WSA computing device 310 is configured to analyze the wafer and predict future states based on the analysis.

[0050] The measurement device 305 is configured to scan the surface of the wafer to generate a profile of the wafer. More specifically, the measurement device 305 scans the nanotopography of the wafer and communicates with the WSA computing device 310. The measurement device 305 connects to the WSA computing device 310 through various wired or wireless interfaces, such as a network, such as a local area network (LAN) or wide area network (WAN), a dial-in connection, a cable modem, an Internet connection, wireless, and a special integrated services digital network (ISDN) line. The measurement device 305 receives data about the surface of the wafer and reports the data to the WSA computing device 310. In other embodiments, the measurement device 305 communicates with one or more client systems 325, which transfer the measurement data to the WSA computing device 310 in real time or near real time. In some embodiments, a first measurement device 305 measures one side of the wafer and a second measurement device 305 measures the other side of the wafer. In the exemplary embodiment, the measurement device 305 is similar to the first measurement device 110 (shown in FIG. 1), the second measurement device 125 (shown in FIG. 1), and the nanotopography measurement device 145 (shown in FIG. 1).

[0051] As described in more detail above, WSA server 310 is programmed to analyze the wafer to predict the nanotopography of the wafer surface after polishing so that system 300 can rapidly respond to changes that may cause the wafer to be out of tolerance. WSA server 310 is programmed to (1) determine the current state of the wafer, (2) predict the post-processing state of the wafer based on the current state and the model, and (3) determine whether adjustments are required to the wafer processing equipment based on the post-processing state of the wafer and one or more predefined thresholds. In an exemplary embodiment, WSA server 310 is similar to wafer surface analysis computing device 115 (shown in FIG. 1).

[0052] Client system 325 is a computer that includes a web browser or software application that allows client system 325 to communicate with WSA server 310 using the Internet, a local area network (LAN), or a wide area network (WAN). In some embodiments, client system 325 is communicatively coupled to the Internet through a number of interfaces, including, but not limited to, at least one of the following networks: the Internet, a LAN, a WAN, an Integrated Services Digital Network (ISDN), a dial-up connection, a DSL (Digital Subscriber Line), a cellular connection, a satellite connection, and a cable modem. Client system 325 is any device capable of accessing a network, such as the Internet, including, but not limited to, a desktop computer, a laptop computer, a personal digital assistant (PDA), a cellular phone, a smart phone, a tablet, a phablet, or other web-based connectable device.

[0053] Database server 315 is communicatively coupled to database 320, which stores data. In one embodiment, database 320 is a database that includes historical data and models. In some embodiments, database 320 is stored remotely from WSA server 310. In some embodiments, database 320 is distributed. In an exemplary embodiment, a person can access database 320 via client system 325 by logging on to WSA server 310.

[0054] FIG. 4 illustrates an example configuration of a client system 325 (shown in FIG. 3). A user computing device 402 is operated by a user 401. The user computing device 402 includes, but is not limited to, a first measurement device 110, a second measurement device 125, a wafer surface analysis computing device 115, a nanotopography measurement device 145 (all shown in FIG. 1), a measurement device 305, a WSA computing device 310, and a client system 325 (all shown in FIG. 3). The user computing device 402 includes a processor 405 for executing instructions. In some embodiments, the executable instructions are stored in a memory area 410. The processor 405 may include one or more processing units (e.g., a multi-core configuration). The memory area 410 is any device capable of storing and retrieving executable instructions and / or information, such as transaction data. The memory area 410 may include one or more computer-readable media.

[0055] The user computing device 402 also includes at least one media output component 415 for presenting information to the user 401. The media output component 415 is any component capable of communicating information to the user 401. In some embodiments, the media output component 415 includes an output adapter (not shown), such as a video adapter and / or an audio adapter. The output adapter is operably coupled to the processor 405 and is operably coupleable to an output device, such as a display device (e.g., a cathode ray tube (CRT), a liquid crystal display (LCD), a light emitting diode (LED) display, or an "electronic ink" display) or an audio output device (e.g., speakers or headphones). In some embodiments, the media output component 415 is configured to present a graphical user interface (e.g., a web browser and / or a client application) to the user 401. The graphical user interface may include, for example, an interface for displaying analysis results of one or more wafers. In some embodiments, the user computing device 402 includes an input device 420 for receiving input from the user 401. A user 401 may use the input device 420, for example, to select a wafer for which analysis results are to be displayed. The input device 420 may include, for example, a keyboard, a pointing device, a mouse, a stylus, a touch-sensitive panel (e.g., a touchpad or touch screen), a gyroscope, an accelerometer, a position detector, a biometric input device, and / or an audio input device. A single component, such as a touch screen, may function as both an output device for the media output component 415 and as an input device 420.

[0056] User computing device 402 also includes a communications interface 425 and may be communicatively coupled to a remote device, such as WSA server 310 (shown in FIG. 3 ). Communications interface 425 may include, for example, a wired or wireless network adapter and / or a wireless data transceiver for use in a mobile communications network.

[0057] Stored in memory area 410 are computer readable instructions for, for example, providing a user interface to user 401 via media output component 415 and optionally receiving and processing input from input device 420. The user interface may include, for example, a web browser and / or a client application. The web browser allows a user, such as user 401, to view and interact with media and other information typically embedded in web pages or websites from WSA server 310. The client application allows user 401 to interact with, for example, WSA server 310. For example, instructions may be stored by the cloud service and output of the execution of the instructions sent to media output component 415.

[0058] The processor 405 executes computer-executable instructions for implementing aspects of the present disclosure. In some embodiments, the processor 405 is transformed into a special purpose microprocessor by executing or otherwise being programmed with computer-executable instructions.

[0059] 5 illustrates an example configuration of server system 310 shown in FIG. 3. Server computing device 501 includes, but is not limited to, WSA computing device 115 (shown in FIG. 1), database server 315, and WSA server 310 (both shown in FIG. 3). Server computing device 501 also includes a processor 505 for executing instructions. The instructions may be stored in memory area 510. Processor 505 may include one or more processing units (e.g., a multi-core configuration).

[0060] The processor 505 is operatively coupled to a communications interface 515 such that the server computing device 501 can communicate with a remote device, such as another server computing device 501, another WSA server 310, or a client system 325 (shown in FIG. 3). For example, as shown in FIG. 3, the communications interface 515 may receive a request from a client system 325 over the Internet.

[0061] The processor 505 may also be operatively coupled to a storage device 534. The storage device 534 is any computer-operated hardware suitable for storing and / or retrieving data, such as data associated with the database 320 (shown in FIG. 3). In some embodiments, the storage device 534 is integrated into the server computing device 501. For example, the server computing device 501 may include one or more hard disk drives as the storage device 534. In other embodiments, the storage device 534 may be external to the server computing device 501 and accessed by multiple server computing devices 501. For example, the storage device 534 may include a storage area network (SAN), a network attached storage (NAS) system, and / or multiple storage units, such as hard disks and / or solid state disks, in a redundant array of inexpensive disks (RAID) configuration.

[0062] The processor 505 may be operatively coupled to the storage device 534 via a storage interface 520. The storage interface 520 is any component that provides the processor 505 with access to the storage device 534. The storage interface 520 may include, for example, an Advanced Technology Attachment (ATA) adapter, a Serial ATA (SATA) adapter, a Small Computer System Interface (SCSI) adapter, a RAID controller, a SAN adapter, a network adapter, and / or any component that provides the processor 505 with access to the storage device 534.

[0063] The processor 505 executes computer-executable instructions for implementing aspects of the present disclosure. In some embodiments, the processor 505 executes computer-executable instructions or is otherwise programmed to transform the processor 505 into a special-purpose microprocessor. For example, the processor 505 is programmed with instructions such as those illustrated in FIG. 2.

[0064] 6 illustrates an example of a line scan process 600 performed by measurement device 305 (shown in FIG. 3). In an exemplary embodiment, process 600 is performed by first measurement device 110, second measurement device 125, and nanotopography measurement device 145 as part of system 100 (all shown in FIG. 1), which performs process 200 (shown in FIG. 2).

[0065] According to the line scan process 600, the wafer W is supported by one or more support pins 603 that contact the first surface 605A of the wafer. The shape of the supported wafer 609 deflects as a function of gravity and the mass of the wafer W, as shown by a comparison of the shape of the wafer in a weightless state (indicated by reference numeral 607) and the shape of the wafer in a supported state (indicated by reference numeral 609). The measurement device 305 includes a first capacitance sensor 621A for measuring a plurality of distances (e.g., “distance-B”) between the first sensor 621A and the first surface 605A (e.g., the front surface) along a diameter of the supported wafer 609. Similarly, the measurement device 305 includes a second capacitance sensor 621B for measuring a plurality of distances (e.g., “distance-F”) between the second sensor 621B and the second surface 605B (e.g., the back surface) along a diameter of the supported wafer 609. The obtained data includes a line scan data set corresponding to the diameter. The line scan data set is composed of a plurality of distances measured by a first sensor 621A along a diameter of the supported wafer 609 and a plurality of distances measured by a second sensor 621B along a diameter of the supported wafer 609. The line scan data set shows a profile of the wafer along the diameter.

[0066] 7A and 7B are diagrams further illustrating an exemplary line scan process 600 (shown in FIG. 6). FIG. 7A and 7B show the line scan process 600 performed by the measurement device 305 to obtain multiple line scan data sets showing the profile of the wafer along a particular diameter. As shown in FIG. 7A, a first line scan (indicated by arrow 701) is performed along a first diameter of the wafer. In particular, the first sensor 621A is moved in a plane above the first surface 605A in a first direction along the first diameter of the wafer. The first sensor 621A measures the distance between the first sensor 621A and the first surface 605A of the wafer at a predetermined interval (i.e., pitch R, measurement frequency). The predetermined interval is shown by hatched marks on the surface of the wafer W in FIG. 7A. For example, the first sensor 621A may measure the distance at 1 or 2 mm intervals along the first diameter of the wafer. The second sensor 621B similarly moves in a plane below the second surface 605B in a first direction to measure the distance between the second sensor 621B and the second surface 605B along a first diameter of the wafer. The first diameter of the wafer may be defined as a function of a reference point. For example, in the illustrated process, the first diameter passes through a notch N located at the periphery of the wafer.

[0067] As shown in FIG. 7B, after completing the first line scan 701, the wafer W rotates (indicated by arrow 709). In particular, the rotation stage 705 located below the support pins 603 rises and lifts the wafer W to a position (indicated by reference number 707) above the support pins 603. The rotation stage rotates while supporting the wafer in the raised position 707. As a result, the wafer rotates a few degrees (θ). The rotation stage 705 lowers and repositions the rotated wafer on the support pins 603. The position of the support pins 603 relative to the second surface of the wafer is shown by the dashed lines in FIGS. 7A and 7B. Next, a line scan (indicated by arrow 715) along the second diameter of the wafer is performed. According to the illustrated process, the first and second sensors 621A and 621B are moved in a second direction opposite to the first direction along the second diameter of the wafer in a plane corresponding to the first and second surfaces 605A and 605B, respectively. As described above in connection with the first line scan 701, the first and second sensors 621A and 621B measure the distance between the sensors 621A and 621B and the first and second surfaces 605A and 605B of the wafer, respectively, at predetermined intervals along the second diameter of the wafer. The rotation 709 and line scan operations 701 and 705 are repeated to obtain each of the multiple line scan data sets.

[0068] The measurement device 305 preferably uses a self-mass compensation algorithm to determine the wafer shape in zero gravity 607. The self-mass compensation determines the wafer shape as a function of the line scan data set, wafer density, elastic constant, wafer diameter, and support pin 603 position. In one embodiment, the measurement device 305 measures one or more wafer parameters based on the wafer shape. The wafer parameters may include one or more of bow, waviness, TTV (total thickness variation), and / or GBIR (global backside ideal range).

[0069] With reference to FIG. 8A, bow and waviness are generally determined with respect to a reference plane. The reference plane is defined as a function of the contact points between the support pins 603 and the surface 605A of the wafer. Specifically, bow is defined as the absolute value of the difference between the maximum and minimum deviations of the central region from the reference plane. The central region is the locus of points that are equidistant from the front surface 605B and the back surface 605A of the wafer. Bow is defined as the amount of deviation from the reference plane at the center of the wafer. With reference to FIG. 8B, GBIR and TTV reflect the linear thickness variation of the wafer and can be calculated based on the difference between the maximum and minimum distances from the surface of the wafer to the reference plane. For example, the measurement device 305 can acquire four line scan data sets as illustrated in FIG. 9A, or eight line scan data sets as illustrated in FIG. 9B. Each line scan data set represents a diametric profile of the wafer.

[0070] With reference to the system 100 shown in FIG. 1, data acquired by the measurement devices 110, 125, and 145 to measure the nanotopography of the wafer ground by the grinder 120 is transmitted to the WSA computing device 115. For example, the line scan data set and / or the determined wafer shape may be transmitted to the WSA computing device 115. The WSA computing device 115 receives the scan data and executes computer-executable instructions to perform a number of operations to process the received scan data as described herein. In particular, the WSA computing device 115 predicts the post-polishing nanotopography of the wafer based on the received scan data. In some embodiments, the WSA computing device 115 determines grinding parameters based on the predicted nanotopography of the wafer. The operation of the grinder 120 is adjusted accordingly.

[0071] The WSA computing device 115 may access a feedback program for processing the received scan data. The received scan data may include a line scan data set and / or a determined wafer shape of the polished wafer. In particular, the WSA computing device 115 predicts a nanotopography of the wafer after polishing based on the received bow data. Because the wafer has not yet been polished when the first measurement device 110 or the second measurement device 125 measures the wafer, the nanotopography of the wafer is predicted, rather than actually measured. The WSA computing device 115 determines one or more grind parameters based on the predicted nanotopography of the wafer. In one embodiment, the WSA computing device 115 determines a shift parameter. The shift parameter indicates the magnitude and direction to move the pair of grind wheels to reduce degradation of the nanotopography due to misalignment of the grind wheels. In another embodiment, the WSA computing device 115 additionally or alternatively determines a tilt parameter. The tilt parameter indicates the angle of alignment of a pair of grinding wheels with respect to the wafer to reduce degradation of the nanotopography due to misalignment of the grinding wheels.

[0072] Based on the determined parameters, the operation of the grinder 120 or other station is adjusted. For example, in the case of the grinder 120, the grind wheels may be adjusted as specified by the determined shift and / or tilt parameters. In one embodiment, the grind wheels are adjusted as a function of the determined shift and / or tilt parameters and a predefined compensation amount. In one embodiment, the grinder 120 is configured to receive the determined grind parameters and adjust one or more components of the grinder 120 as a function of the determined grind parameters. In another embodiment, the determined grind parameters are provided to an operator, who configures the grinder 120 to adjust one or more components of the grinder 120 as a function of the determined grind parameters.

[0073] FIG. 10A illustrates the use of a trained neural network model to convert a post-grind shape map into a predicted post-polish NT map. FIG. 10B illustrates the use of a trained neural network model to convert a GAPI RMS map into a predicted IPD map. A GAN AI model 1005, which is a neural network or other artificial intelligence or machine learning based model, receives an input image 1010 and outputs a predicted output image 1015. The input image 1010 can include a shape map as shown in FIG. 10A, or a GAPI RMS map as shown in FIG. 10B.

[0074] The GAN AI model 1005 is trained on a large data set to correlate input data 1010 to an output map 1015. In a first example shown in FIG. 10A, ground (or sliced) field data, such as 4 or 8 line scans, is acquired by the first measurement device 110 or the second measurement device 125 (both shown in FIG. 1). The line data is used to create a shape map. The shape map is used as an input image 1010 to the model 1005. The model 1005 outputs a predicted post-polishing nanotopography (NT) map as an output image 1015. In some embodiments, the trained model 1005 provides a correlation between the ground 4 or 8 line scan data 1010 and the NT map 1015 with an R2 of about 80%.

[0075] In a second example shown in FIG. 10B, a GAPI RMS map is acquired by the first measurement device 110 or the second measurement device 125 (both shown in FIG. 1). The GAPI RMS map is used as an input image 1010 to a model 1005. The model 1005 outputs an in-plane distortion (IPD) map based on the predicted shape as an output image 1015. In some embodiments, the trained model 1005 provides a correlation between the GAPI RMS map 1010 and the IPD map 1015 with an R2 of about 90%.

[0076] Once both the NT map and the IPD map are available, the WSA computing device 310 can calculate different parameters, such as (but not limited to) THA1010, THA2525, average IPD, etc. The WSA computing device 310 can use these parameters to optimize the grinding, slicing, and polishing processes during the manufacturing of silicon wafers.

[0077] 11A shows images of a wafer shape map. The first image is the input image 1105, specifically the smooth dataset map after grinding. The second image is the actual image 1110, which is the actual measured wafer after grinding. The grinded actual image 1110 may be measured by the nanotopography measurement device 145 (shown in FIG. 1). The third image is the predicted NT map 1115.

[0078] FIG. 11B shows an example of a graph comparing the grinded actual image 1110 and the predicted NT map 1115 (both shown in FIG. 11A). In this example, TH2525 is calculated for both the grinded actual image 1110 and the predicted NT map 1115. The graph in FIG. 11B shows the correlation between the grinded actual image 1110 and the predicted NT map 1115 based on the calculated TH2525. The correlation plot shows an R-squared value of approximately 0.788.

[0079] 12A shows images of a wafer topography map. The first image is an input image 1205, specifically a filtered post-grind dataset map. The second image is an actual post-grind image 1210, which is an actual post-polishing measurement wafer. The actual post-grind image 1210 may be measured by a nanotopography measurement device 145 (shown in FIG. 1). The third image is a predicted NT map 1215.

[0080] FIG. 12B shows an example of a graph comparing the grinded actual image 1210 and the predicted NT map 1215 (both shown in FIG. 12A). In this example, TH2525 is calculated for both the grinded actual image 1210 and the predicted NT map 1215. The graph in FIG. 12B shows the correlation between the grinded actual image 1210 and the predicted NT map 1215 based on the calculated TH2525. The correlation plot shows an R-squared value of approximately 0.829.

[0081] 13A shows images of a wafer shape map. The first image is an input image 1305, specifically a GAPI RMS map. The second image is an actual image after ground 1310, which is the actual post-polish measurement wafer. The actual image after grind 1210 may be measured by the nanotopography measurement tool 145 (shown in FIG. 1). The third image is a predicted IPD map 1315.

[0082] FIG. 13B shows an example of a graph comparing the grinded actual image 1210 and the predicted IPD map 1315 (both shown in FIG. 13A). In this example, TH2525 is calculated for both the grinded actual image 1310 and the predicted IPD map 1315. The graph in FIG. 13B shows the correlation between the grinded actual image 1310 and the predicted IPD map 1315 based on the calculated IPD. The correlation plot shows an R-squared value of approximately 0.930.

[0083] A computing device, such as a wafer surface analysis computing device 115 (shown in FIG. 1), is configured to communicate with at least one processor 505 and at least one memory device 510 (both shown in FIG. 50). The WSA computing device 115 is programmed to store in the at least one memory device 510 a model for converting a shape map to simulate a portion of an assembly line 100 (shown in FIG. 1). The WSA computing device 115 receives scan data of a first inspection of a product being assembled. The first inspection is a first inspection station (also called the first measurement device 110, which may be the first measurement device 110 or the second measurement device 125 (both shown in FIG. 1). The first inspection station is in the assembly line 100 following the first device 105 or 120 (both shown in FIG. 1) in the assembly line 100.

[0084] The WSA computing device 115 also generates a shape map from the scan data of the first inspection and runs the model using the shape map as an input to generate a final shape map of the product. The WSA computing device 115 compares the final shape map to one or more thresholds to determine whether the final shape map exceeds at least one of the one or more thresholds. If it is determined that the final shape map exceeds at least one of the one or more thresholds, the WSA computing device 115 causes the first device to be adjusted.

[0085] The WSA computing device 115 may also calculate one or more product attributes from the final shape map. The WSA computing device 115 compares the one or more product attributes to one or more thresholds. If the one or more product attributes exceed the one or more thresholds, the WSA computing device 115 causes the first device to be adjusted.

[0086] The shape map is preferably one of a post-grind shape map and a GAPI RMS (root mean square) map. The final shape map is then one of a post-polish nanotopography map and an in-plane distortion (IPD) map, respectively. The model is a generative adversarial network (GAN) artificial intelligence model trained on past images of partially processed and fully processed products. The model converts the input shape map into a simulation of the final product shape map.

[0087] The shape map is the first shape map and the final shape map is the first final shape map. In these embodiments, the WSA computing device 115 generates a second shape map from the scan data. The second shape map is generated in a different manner than the first shape map. The WSA computing device 115 runs a model using the second shape map as an input to generate a second final shape map of the product. The WSA computing device 115 calculates one or more product attributes from the first final shape map and the second final shape map. The WSA computing device 115 compares the one or more product attributes to one or more thresholds. If the one or more product attributes exceed the one or more thresholds, the WSA computing device 115 causes the first device to adjust. In these embodiments, the first shape map is a post-grind shape map, the first final shape map is a post-polishing nanotopography map, the second shape map is a GAPI RMS (root mean square) map, and the second final shape map is an in-plane distortion (IPD) map.

[0088] The scan data is one of four line scan data or eight line scan data of the product. The product is a semiconductor wafer as described above, and the first device is one of a grinder or a slicer. The first inspection station includes a nanotopography measurement device.

[0089] The WSA computing device 115 generates one or more adjustments to the first device based on comparing the final shape map to one or more thresholds and the model. The WSA computing device 115 transmits the one or more adjustments to at least one of the user and the first device.

[0090] If the final shape map is determined to exceed at least one of the one or more thresholds, the WSA computing device 115 analyzes multiple past inspections to determine a trend. The WSA computing device 115 then predicts whether a subsequent inspection of a subsequent product is likely to exceed at least one of the one or more thresholds based on the trend. The WSA computing device 115 further adjusts the first device based on the trend.

[0091] At least one of the technical solutions enabled by this system to address the technical problems may include: (i) improved analysis of the wafer surface, (ii) reduced material loss due to malfunction or improper alignment, (iii) increased speed of wafer analysis, (iv) increased accuracy of wafer analysis, (v) reduced unnecessary adjustments to the grinder, (vi) reduced false positives and false negatives, and (vii) up-to-date analysis calibrated to each individual production line.

[0092] The computer-implemented methods may include additional, fewer, or alternative operations, including those described elsewhere herein. These methods may be implemented via one or more local or remote processors, transceivers, servers, and / or sensors (such as processors, transceivers, servers, and / or sensors onboard a vehicle or mobile device or associated with a smart infrastructure or remote servers) and / or via computer-executable instructions stored on a non-transitory computer-readable medium or media.

[0093] Additionally, the computer system may include additional, less, or alternative functionality, including those described elsewhere herein. The computer system may include or be implemented by or through computer-executable instructions stored on a non-transitory computer-readable medium or media.

[0094] The processor or processing element may be trained using supervised or unsupervised machine learning, and the machine learning program may employ a neural network that is a convolutional neural network, a deep learning neural network, a reinforcement or reinforcement learning module or program, or a composite learning module or program that learns in two or more fields or domains of interest. Machine learning may involve identifying and recognizing patterns in existing data to facilitate prediction of subsequent data. Models may be created based on example inputs to make valid and reliable predictions for new inputs.

[0095] Additionally or alternatively, machine learning programs may be trained by inputting sample data sets or specific data into the program, such as images, subject statistics and information, historical estimates, and / or actual repair costs. Machine learning programs may utilize deep learning algorithms that focus primarily on pattern recognition and may be trained after processing multiple examples. Machine learning programs may include Bayesian program learning (BPL), speech recognition and synthesis, image or object recognition, optical character recognition, and / or natural language processing, either individually or in combination. Machine learning programs may also include natural language processing, semantic analysis, automated reasoning, and / or machine learning.

[0096] Supervised and unsupervised machine learning techniques may be used. In supervised machine learning, a processing element may include example inputs and their associated outputs and attempt to discover general rules that map inputs to outputs, such that when subsequently provided with new inputs, the processing element can accurately predict the correct output based on the discovered rules. In unsupervised machine learning, a processing element may be required to find its own structure from unlabeled example inputs. In one embodiment, machine learning techniques may be used to extract data about the nanotopography of the wafer surface to predict future states.

[0097] Based on these analyses, the processing element may learn how to identify characteristics and patterns that can be applied to analyses of image data, model data, and / or other data. For example, the processing element may learn how to identify trends that occur before a grinder becomes misaligned based on a comparison of post-grind and post-polish measurements. The processing element may also learn how to identify trends that are not readily apparent, such as trends that occur before a grinder becomes misaligned, based on collected scan data.

[0098] The method and system may be implemented using engineering techniques including computer programming or computer software, firmware, hardware, or any combination or subset thereof. As disclosed above, at least one technical problem in the prior systems is the need for a cost-effective and reliable system for analyzing data to predict nanotopography. The system and method described herein address that technical problem. Furthermore, at least one technical solution to overcome the technical problem by the system may include: (i) improved analysis of the wafer surface; (ii) reduced material loss due to malfunction or improper alignment; (iii) increased speed of wafer analysis; (iv) increased accuracy of wafer analysis; and (v) calibrated up-to-date analysis for each individual production line.

[0099] The above described methods and systems may be implemented using computer programming or engineering techniques including computer software, firmware, hardware, or any combination or subset thereof, where the technical effect is achieved by performing at least one of the following steps: (a) storing in at least one memory device a model for simulating a portion of an assembly line; b) receiving scan data of a first inspection of a product being assembled, the first inspection being located at a first inspection station of the assembly line following a first device of the assembly line; c) running the model using the scan data as input to generate a final profile of the product; d) comparing the final profile to one or more thresholds; e) determining whether the final profile exceeds at least one of the one or more thresholds; f) adjusting the first device if a determination is made that the final profile exceeds at least one of the one or more thresholds; g) generating a model for simulating a portion of an assembly line based on a plurality of inspection data of the assembly line. The assembly line includes a second inspection station following the second device on the assembly line, the model generating a final profile of the product simulating an actual profile of the product upon reaching the second inspection station, the second inspection station being positioned after completion of the assembly line, the plurality of inspection data including a first plurality of scan data of the plurality of individual products at the first inspection station and a second plurality of scan data of the plurality of individual products at the second inspection station, h) receiving scan data of a second inspection of the product being assembled at the second inspection station; h) receiving scan data of a second inspection of the product being assembled at the second inspection station; i) comparing the scan data of the second inspection to the final profile; j) adjusting the model based on the comparison; k) generating one or more adjustments to the first device based on a comparison of the final profile to the one or more thresholds and the model; l) transmitting the one or more adjustments to at least one of a user and the first device.m) if a determination is made that the final profile exceeds at least one of the one or more thresholds, then at least one of the following steps is performed: i) analyzing a plurality of past tests to determine a trend, ii) predicting whether a subsequent test of a subsequent product is likely to exceed at least one of the one or more thresholds based on the trend, and iii) adjusting the first device based on the trend.

[0100] The methods may be implemented via one or more local or remote processors, transceivers, servers, and / or sensors (such as processors, transceivers, servers, and / or sensors onboard a vehicle or mobile device or associated with a smart infrastructure or remote servers) and / or via computer-executable instructions stored on a non-transitory computer-readable medium or media. Additionally, the computer systems described herein may include additional, reduced, or alternative functionality, including those described elsewhere herein. The computer systems described herein may include or be implemented via computer-executable instructions stored on a non-transitory computer-readable medium or media.

[0101] As used herein, the term "non-transitory computer-readable medium" is intended to be representative of any tangible computer-based device implemented in any method or technology for short-term and long-term storage of information, such as computer-readable instructions, data structures, program modules and sub-modules, or other data in any device. Thus, the methods described herein can be encoded as executable instructions in a tangible, non-transitory computer-readable medium (including, but not limited to, storage and / or memory devices). Such instructions, when executed by a processor, cause the processor to perform at least a portion of the methods described herein. Additionally, as used herein, the term "non-permanent computer-readable medium" includes volatile and non-volatile media, as well as removable and non-transitory media, such as firmware, physical and virtual storage, CD-ROMs, DVDs, other digital sources such as networks and the Internet, and digital means yet to be invented (with the sole exception of transitory propagating signals).

[0102] The description herein uses examples to disclose various embodiments, including the best mode, and also to enable one of ordinary skill in the art to practice various embodiments, including making and using any device or system, and performing the incorporated methods. The patentable scope of the disclosure is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the language of the claims, or if they include equivalent structural elements that do not differ insubstantial from the language of the claims.

[0103] When introducing elements of this disclosure or embodiments thereof, the articles "a," "an," "the," and "said" mean that there is one or more of the element. The terms "comprising," "including," "containing," and "having" are inclusive and mean that there may be additional elements other than the listed elements. The use of specific directional terms (e.g., "top," "bottom," "side," etc.) is for convenience of description and does not require a particular orientation of the articles being described.

[0104] Since various changes may be made in the structures and methods described above without departing from the scope of the disclosure, all matter set forth in the above description and shown in the accompanying drawings should be interpreted as illustrative and not limiting.

Claims

1. 1. A computing device including at least one processor in communication with at least one memory device, the at least one processor comprising: storing, in at least one memory device, a shape map transformation model for simulating a portion of an assembly line, wherein the model is a generative adversarial network (GAN) artificial intelligence model; receiving scan data of a first inspection of a product being assembled, where the first inspection is performed at a first inspection station on the assembly line subsequent to a first device on the assembly line, the first device being a grinder; generating a shape map from the scan data of the first examination; running the model using the shape map as input to generate a final shape map of the product; comparing the final shape map to one or more thresholds; determining whether the final shape map exceeds at least one of one or more thresholds; and adjusting the grinder if it is determined that the final shape map exceeds at least one of the one or more thresholds; A computer device programmed to:

2. The at least one processor further comprises: Calculating one or more product attributes from the final shape map; comparing one or more product attributes to one or more thresholds; and causing the first device to adjust if one or more product attributes exceed one or more thresholds; 2. A computer apparatus according to claim 1 programmed to:

3. The shape map is the shape map after grinding, The computer system of claim 1 , wherein the final shape map is a post-polishing nanotopography map.

4. The shape map is a GAPI RMS (root mean square) map, The computer apparatus of claim 1 , wherein the final shape map is an in-plane distortion (IPD) map.

5. 10. The computer system of claim 1, wherein the model converts an input shape map into a simulation of a shape map of a final product.

6. the shape map is a first shape map; the final shape map is a first final shape map; The at least one processor further comprises: generating a second shape map from the scan data, the second shape map being generated in a different manner than the first shape map; and 10. The computer apparatus of claim 1, programmed to: execute the model using the second shape map as input to generate a second final shape map of the product.

7. The at least one processor further comprises: calculating one or more product attributes from the first final shape map and the second final shape map; comparing one or more product attributes to one or more thresholds; and 7. The computer device of claim 6, programmed to: cause the first device to adjust if one or more product attributes exceed one or more thresholds.

8. the first shape map is a post-grind shape map; The first final shape map is a post-polishing nanotopography map; The second shape map is a GAPI RMS (Root Mean Square) map; The computer apparatus of claim 6 , wherein the second final shape map is an in-plane distortion (IPD) map.

9. 10. The computer device of claim 1, wherein the scan data is one of four line scan data or eight line scan data of the product.

10. 10. The computer system of claim 1, wherein the product is a semiconductor wafer.

11. the first device is one of a grinder or a slicer; The computer system of claim 10 , wherein the first inspection station includes a nanotopography measurement device.

12. The at least one processor further comprises: generating one or more adjustments to the first device based on comparing the final shape map to one or more thresholds and models; and 10. The computer device of claim 1 programmed to: transmit one or more adjustments to at least one of the user and the first device.

13. If it is determined that the final shape map exceeds at least one of the one or more thresholds, the at least one processor further: Analyze multiple past tests to determine trends; predicting the likelihood that a subsequent test of a subsequent product will exceed at least one of the one or more thresholds based on the trend; and 10. The computer device of claim 1, programmed to: adjust the first device based on the trend.

14. At least one processor further comprises: Determine planned future downtime periods; and 14. The computer apparatus of claim 13 programmed to: schedule adjustment of the first device for a planned future downtime period.

15. 1. A method of analyzing an assembly line, the method being implemented by a computing device including at least one processor in communication with at least one memory device, the method comprising: storing a model for simulating a portion of an assembly line in at least one memory device, the model being a generative adversarial network (GAN) artificial intelligence model; transforming the shape map to store a model for simulating a portion of the assembly line in at least one memory device; receiving scan data of a first inspection of a product under assembly, the first inspection being performed at a first inspection station in the assembly line subsequent to a first device in the assembly line, the first device being a grinder; generating a shape map from the scan data of the first inspection; running the model using the shape map as input to generate a final shape map of the product; comparing the final shape map to one or more thresholds; determining whether the final shape map exceeds at least one threshold; and adjusting the grinder if it is determined that the final shape map exceeds at least one threshold.

16. calculating one or more product attributes from the final shape map; comparing one or more product attributes to one or more thresholds; and 16. The method of claim 15, further comprising: adjusting the first device if one or more product attributes exceed one or more thresholds.

17. The shape map is either a post-grind shape map or a GAPI RMS (root mean square) map; 16. The method of claim 15, wherein the final shape map is one of a post-polishing nanotopography map of an in-plane distortion (IPD) map.

18. the shape map is a first shape map; The final shape map is a first final shape map, and further generating a second shape map from the scan data, the second shape map being generated in a different manner than the first shape map; and 16. The method of claim 15, further comprising: running the model using the second shape map as input to generate a second final shape map of the product.

19. calculating one or more product attributes from the first final shape map and the second final shape map; comparing one or more product attributes to one or more thresholds; and 20. The method of claim 18, further comprising: adjusting the first device if one or more product attributes exceed one or more thresholds.

20. the first shape map is a post-grind shape map; The first final shape map is a post-polishing nanotopography map; The second shape map is a GAPI RMS (root mean square) map, and The method of claim 18, wherein the second final shape map is an in-plane distortion (IPD) map.

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