Resistor Networks with Adaptive Resistance for Digital-to-Analog Converters (DACs)

Abstract

A method and apparatus for adaptively adjusting the resistance of a resistor network in a digital-to-analog converter (DAC), such as a current steering DAC for a transmit chain. An exemplary DAC typically includes a plurality of DAC cells. One or more of the DAC cells typically include a current source and a resistor network. The resistor network includes a plurality of resistive elements, has an adjustable resistance, and is coupled between a power supply rail and the current source. In this manner, the DAC may support a wide range of full-scale currents while maintaining a higher degeneration voltage and reduced noise and mismatch for a given headroom. In certain aspects, one or more of the DAC cells further include a plurality of switches (e.g., implemented with PFETs) coupled to one or more of the resistive elements and configured to adjust the resistance of the resistor network.

Description

[Technical field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Patent Application No. 17 / 659,531, filed April 18, 2022, which is incorporated by reference herein in its entirety.

[0002] Certain aspects of the present disclosure relate generally to electronic circuits, and more particularly, to digital-to-analog converters (DACs). [Background technology]

[0003] Wireless communication devices are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcast, etc. Such wireless communication devices may transmit and / or receive radio frequency (RF) signals via any of a variety of suitable radio access technologies (RATs), including, but not limited to, Fifth Generation (5G) New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobility (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, wireless local area network (WLAN) RATs (e.g., WiFi), and the like.

[0004] A wireless communication network may include several base stations that can support communication for several mobile stations. A mobile station (MS) may communicate with a base station (BS) via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base station to the mobile station, and the uplink (or reverse link) refers to the communication link from the mobile station to the base station. A base station may transmit data and control information to a mobile station on the downlink and / or receive data and control information from a mobile station on the uplink. A base station and / or a mobile station may include a transmission digital-to-analog converter (TxDAC), which may be used to convert digital signals to analog signals for signal processing (e.g., filtering, upconversion, and amplification) before transmission by one or more antennas. Summary of the Invention

[0005] The systems, methods, and devices of the present disclosure each have several aspects, no one of which is solely responsible for its desirable attributes. Without limiting the scope of the present disclosure as expressed by the following claims, several features will now be briefly described. After considering this discussion, and especially after reading the section entitled "Description of the Preferred Embodiments," one will understand how the features of the present disclosure provide advantages including improved full-scale current scaling in digital-to-analog converters (DACs), while maintaining maximized (or at least relatively high) degeneration voltages, which may result in reduced output noise and mismatch.

[0006] Certain aspects of the present disclosure provide a DAC. The DAC generally includes a plurality of DAC cells. One or more of the DAC cells generally includes a current source and a resistor network comprising a plurality of resistive elements. The resistor network has an adjustable resistance and is coupled between a power supply rail and the current source.

[0007] Certain aspects of the present disclosure provide a wireless device that includes a DAC as described herein, one or more antennas, and one or more transmit paths coupled between one or more outputs of the DAC and the one or more antennas.

[0008] Certain aspects of the present disclosure provide a method of digital-to-analog conversion. The method generally includes receiving a digital input code at an input of a DAC that includes a plurality of DAC cells and generating an analog output signal via the DAC based on the digital input code. One or more of the plurality of DAC cells generally includes a current source and a resistor network that includes a plurality of resistive elements. The resistor network has an adjustable resistance and is coupled between a power supply rail and the current source.

[0009] To the accomplishment of the foregoing and related ends, the one or more aspects include the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of only a few of the various ways in which the principles of the various aspects may be employed and the description is intended to include all such aspects and their equivalents.

[0010] So that the above-mentioned features of the present disclosure may be understood in detail, a more particular description thereof, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the accompanying drawings, in which it is to be noted, however, that the accompanying drawings show only certain exemplary embodiments of the present disclosure, and therefore should not be considered as limiting the scope of the present disclosure, since the present description may admit of other equally effective embodiments. [Brief description of the drawings]

[0011] [Figure 1]FIG. 1 is a diagram of an example wireless communication network in which aspects of the present disclosure may be practiced. [Diagram 2] FIG. 1 is a block diagram conceptually illustrating an example base station (BS) and user equipment (UE) design in which aspects of the present disclosure may be practiced. [Figure 3A] 1 is a block diagram of an example radio frequency (RF) transceiver in which aspects of the present disclosure may be practiced. [Figure 3B] 1 is a block diagram of an example RF transceiver having multiple transmit paths in which aspects of the present disclosure may be practiced. [Figure 4A] 1 is a schematic diagram of an example digital-to-analog converter (DAC) having a resistor network with adjustable resistance in accordance with certain aspects of the present disclosure. [Figure 4B] 4B illustrates an example implementation of the DAC of FIG. 4A in accordance with certain aspects of the present disclosure. [Figure 5A] FIG. 1 is a schematic diagram illustrating an alternative exemplary circuit for implementing an adjustable resistor network in a DAC in accordance with certain aspects of the present disclosure. [Figure 5B] FIG. 1 is a schematic diagram illustrating an alternative exemplary circuit for implementing an adjustable resistor network in a DAC in accordance with certain aspects of the present disclosure. [Figure 5C] FIG. 1 is a schematic diagram illustrating an alternative exemplary circuit for implementing an adjustable resistor network in a DAC in accordance with certain aspects of the present disclosure. [Figure 5D] FIG. 1 is a schematic diagram illustrating an alternative exemplary circuit for implementing an adjustable resistor network in a DAC in accordance with certain aspects of the present disclosure. [Figure 6] 1 is a flow diagram of an example operation of digital-to-analog conversion in accordance with certain aspects of the present disclosure.

[0012] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments without specific recitation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0013] Certain aspects of the present disclosure relate to techniques and apparatus for digital-to-analog conversion, such as digital-to-analog converters (DACs) having adjustable resistor networks that can allow the voltage drop across the resistor network to be set to a desired voltage based on different full-scale currents (as set by bias currents) of the DAC.

[0014] Various aspects of the present disclosure will now be described more fully with reference to the accompanying drawings. However, the present disclosure may be embodied in many different forms and should not be construed as limited to any specific structure or function presented throughout the present disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of the present disclosure is intended to encompass all aspects of the present disclosure disclosed herein, regardless of whether they are implemented independently of or in combination with any other aspects of the present disclosure. For example, an apparatus can be implemented or a method can be practiced using any number of the aspects described herein. In addition, the scope of the present disclosure is intended to encompass such an apparatus or method that is practiced using other structures, functions, or structures and functions in addition to or other than the various aspects of the present disclosure described herein. It will be understood that any aspect of the present disclosure disclosed herein can be embodied by one or more elements of a claim.

[0015] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0016] As used herein, the term "connected with" in various tenses of the verb "connect" can mean that element A is directly connected to element B, or that other elements may be connected between element A and element B (i.e., element A is indirectly connected to element B). In the case of electrical components, the term "connected with" can also be used herein to mean electrically connecting element A and element B (and any components electrically connected between them) using a wire, trace, or other conductive material.

[0017] Exemplary Wireless System 1 illustrates an example wireless communication network 100 in which aspects of the present disclosure may be practiced. For example, the wireless communication network 100 may be a New Radio (NR) system (e.g., a fifth generation (5G) NR network), an Evolved Universal Terrestrial Radio Access (E-UTRA) system (e.g., a fourth generation (4G) network), a Universal Mobile Telecommunications System (UMTS) (e.g., a second generation / third generation (2G / 3G) network), or a Code Division Multiple Access (CDMA) system (e.g., a 2G / 3G network), or may be configured for communication according to an IEEE standard, such as one or more of the 802.11 standards.

[0018] 1, the wireless network 100 may include a number of base stations (BSs) 110a-110z (each also referred to herein individually as a “BS 110” or collectively as the “BSs 110”) and other network entities. A BS may also be referred to as an access point (AP), an evolved Node B (eNodeB or eNB), a next generation Node B (gNodeB or gNB), or some other terminology.

[0019] The BSs 110 may provide communication coverage for a particular geographic area, sometimes referred to as a "cell," and may be fixed or may move according to the location of the mobile BS 110. In some examples, the BSs 110 may be interconnected to one another and / or to one or more other BSs or network nodes (not shown) in the wireless communications network 100 through various types of backhaul interfaces (e.g., direct physical connections, wireless connections, virtual networks, etc.) using any suitable transport network. In the example shown in FIG. 1, the BSs 110a, 110b, and 110c may be macro BSs for the macro cells 102a, 102b, and 102c, respectively. The BS 110x may be a pico BS for the pico cell 102x. The BSs 110y and 110z may be femto BSs for the femto cells 102y and 102z, respectively. The BSs may support one or more cells.

[0020] The BS 110 communicates with one or more user equipments (UEs) 120a-120y (each also referred to herein individually as a “UE 120” or collectively as “UEs 120”) in the wireless communications network 100. The UEs may be fixed or mobile and may also be referred to as user terminals (UTs), mobile stations (MSs), access terminals, stations (STAs), clients, wireless devices, mobile devices, or some other terminology. A user terminal may be a wireless device such as a cellular phone, a smartphone, a personal digital assistant (PDA), a handheld device, a wearable device, a wireless modem, a laptop computer, a tablet, a personal computer, etc.

[0021] The BS 110 is considered to be the transmitting entity in the downlink and the receiving entity in the uplink. The UE 120 is considered to be the transmitting entity in the uplink and the receiving entity in the downlink. As used herein, a "transmitting entity" is an independently operating apparatus or device capable of transmitting data over a frequency channel, and a "receiving entity" is an independently operating apparatus or device capable of receiving data over a frequency channel. In the following description, the subscript "dn" denotes downlink and the subscript "up" denotes uplink. N up UEs may be selected for simultaneous transmission on the uplink, dn N UEs may be selected for simultaneous transmission on the downlink. up is N dn may or may not be equal to N up and N dn , may be a static value or may change at each scheduling interval. Beam-steering or some other spatial processing technique may be used at BS 110 and / or UE 120.

[0022] The UEs 120 (e.g., 120x, 120y, etc.) may be dispersed throughout the wireless communications network 100, and each UE 120 may be fixed or mobile. The wireless communications network 100 may include relay stations (e.g., relay station 110r), also referred to as relays, that receive transmissions of data and / or other information from an upstream station (e.g., BS 110a or UE 120r) and forward transmissions of data and / or other information to a downstream station (e.g., UE 120 or BS 110) or relay transmissions between UEs 120 to facilitate communication between the devices.

[0023] The BS 110 may communicate with one or more UEs 120 at any given moment on the downlink and the uplink. The downlink (or forward link) is the communication link from the BS 110 to the UEs 120, and the uplink (or reverse link) is the communication link from the UEs 120 to the BS 110. The UEs 120 may also communicate peer-to-peer with other UEs 120.

[0024] The wireless communication network 100 may use multiple transmit antennas and multiple receive antennas for data transmission on the downlink and uplink. The BS 110 may use N transmit antennas to achieve transmit diversity for downlink transmissions and / or receive diversity for uplink transmissions. ap The UE 120 may be equipped with N antennas. u The set may receive downlink transmissions and transmit uplink transmissions. Each UE 120 may transmit user-specific data to and / or receive user-specific data from the BS 110. In general, each UE 120 may be equipped with one or multiple antennas. u The UEs 120 may have the same or different number of antennas.

[0025] The wireless communication network 100 may be a time division duplex (TDD) system or a frequency division duplex (FDD) system. For a TDD system, the downlink and uplink share the same frequency band. For an FDD system, the downlink and uplink use different frequency bands. The wireless communication network 100 may also utilize a single carrier or multiple carriers for transmission. Each UE 120 may be equipped with a single antenna (e.g., to keep costs down) or multiple antennas (e.g., if the additional cost can be supported).

[0026] A network controller 130 (sometimes referred to as a "system controller") may communicate with the set of BSs 110 to provide coordination and control for these BSs 110 (e.g., via a backhaul). In some cases (e.g., in a 5G NR system), the network controller 130 may include a centralized unit (CU) and / or a distributed unit (DU). In certain aspects, the network controller 130 may be in communication with a core network 132 (e.g., a 5G core network (5GC)), which provides various network functions such as access and mobility management, session management, user plane functions, policy control functions, authentication server functions, integrated data management, application functions, network exposure functions, network repository functions, network slice selection functions, etc.

[0027] In certain aspects of the present disclosure, the BS 110 and / or the UE 120 may include a digital-to-analog converter (DAC) having an adjustable resistor network, as described in more detail herein.

[0028] FIG. 2 illustrates example components of a BS 110a and a UE 120a (eg, from the wireless communications network 100 of FIG. 1) in which aspects of the disclosure may be implemented.

[0029] On the downlink, at the BS 110a, the transmit processor 220 may receive data from the data source 212, control information from the controller / processor 240, and / or possibly other data (e.g., from the scheduler 244). Various types of data may be sent on different transport channels. For example, control information may be designated for a physical broadcast channel (PBCH), a physical control format indicator channel (PCFICH), a physical hybrid automatic repeat request (HARQ) indicator channel (PHICH), a physical downlink control channel (PDCCH), a group common PDCCH (GC PDCCH), etc. Data may be designated for a physical downlink shared channel (PDSCH), etc. A medium access control (MAC) control element (MAC-CE) is a MAC layer communication structure that may be used for control command exchange between wireless nodes. The MAC-CE may be carried in a shared channel, such as a PDSCH, a physical uplink shared channel (PUSCH), or a physical sidelink shared channel (PSSCH).

[0030] The processor 220 may process (e.g., encode and symbol map) the data and control information to obtain data symbols and control symbols, respectively. The transmit processor 220 may also generate reference symbols, such as for a primary synchronization signal (PSS), a secondary synchronization signal (SSS), a PBCH demodulation reference signal (DMRS), and a channel state information reference signal (CSI-RS).

[0031] A transmit (TX) multiple-input, multiple-output (MIMO) processor 230 may perform spatial processing (e.g., precoding) on ​​the data symbols, control symbols, and / or reference symbols, if applicable, and may provide output symbol streams to modulators (MODs) in transceivers 232a-t. Each modulator in transceivers 232a-t may process a respective output symbol stream (e.g., for orthogonal frequency division multiplexing (OFDM), etc.) to obtain an output sample stream. Each of the transceivers 232a-t may further process (e.g., convert to analog, amplify, filter, and upconvert) the output sample stream to obtain a downlink signal. The downlink signals from the transceivers 232a-t may be transmitted via antennas 234a-t, respectively.

[0032] At the UE 120a, the antennas 252a-252r may receive the downlink signals from the BS 110a and may provide received signals to the transceivers 254a-254r, respectively. The transceivers 254a-254r may condition (e.g., filter, amplify, downconvert, and digitize) each received signal to obtain input samples. Each demodulator (DEMOD) in the transceivers 232a-232t may further process the input samples (e.g., for OFDM, etc.) to obtain received symbols. A MIMO detector 256 may obtain received symbols from all demodulators in the transceivers 254a-254r, perform MIMO detection on the received symbols if applicable, and provide detected symbols. The receive processor 258 may process (e.g., demodulate, deinterleave, and decode) the detected symbols, provide decoded data for UE 120a to a data sink 260, and provide decoded control information to the controller / processor 280.

[0033] On the uplink, at the UE 120a, a transmit processor 264 may receive and process data (e.g., for the physical uplink shared channel (PUSCH)) from a data source 262 and control information (e.g., for the physical uplink control channel (PUCCH)) from a controller / processor 280. The transmit processor 264 may also generate reference symbols for a reference signal (e.g., a sounding reference signal (SRS)). The symbols from the transmit processor 264 may be precoded by a TX MIMO processor 266, if applicable, and further processed by modulators (MODs) in transceivers 254a-254r (e.g., for single-carrier frequency division multiplexing (SC-FDM), etc.) and transmitted to the BS 110a. At BS 110a, the uplink signal from UE 120a may be received by antenna 234, processed by demodulators in transceivers 232a-232t, detected by a MIMO detector 236 if applicable, and further processed by a receive processor 238 to obtain decoded data and control information sent by UE 120a. Receive processor 238 may provide the decoded data to a data sink 239 and the decoded control information to a controller / processor 240.

[0034] Memories 242 and 282 may store data and program codes for the BS 110a and the UE 120a, respectively. The memories 242 and 282 may also interface with the controllers / processors 240 and 280, respectively. A scheduler 244 may schedule UEs for data transmission on the downlink and / or uplink.

[0035] The antennas 252, processors 258, 264, 266, and / or controller / processor 280 of the UE 120a and / or the antennas 234, processors 220, 230, 238, and / or controller / processor 240 of the BS 110a may be used to implement the various techniques and methods described herein.

[0036] In certain aspects of the disclosure, the transceiver 232 and / or the transceiver 254 may include a digital-to-analog converter (DAC) with an adjustable resistor network, as described in more detail herein.

[0037] NR may utilize Orthogonal Frequency Division Multiplexing (OFDM) with Cyclic Prefix (CP) on the uplink and downlink. NR may support half-duplex operation using Time Division Duplex (TDD). OFDM and Single Carrier Frequency Division Multiplexing (SC-FDM) partition the system bandwidth into multiple orthogonal subcarriers, which are also commonly referred to as tones, bins, etc. Each subcarrier may be modulated with data. Modulation symbols may be sent in the frequency domain with OFDM and in the time domain with SC-FDM. The spacing between adjacent subcarriers may be fixed, and the total number of subcarriers may depend on the system bandwidth. The system bandwidth may also be partitioned into subbands. For example, a subband may cover multiple resource blocks (RBs).

[0038] Introduction to mmWave (millimeter wave) wireless communications In wireless communications, the electromagnetic spectrum is often subdivided into various classes, bands, channels, or other characteristics. The subdivision is often based on wavelength or frequency, which may also be referred to as carriers, subcarriers, frequency channels, tones, or subbands.

[0039] 5G networks may utilize several frequency ranges, possibly defined by standards such as the third Generation Partnership Project (3GPP®) standards. For example, 3GPP technical standard TS 38.101 currently defines Frequency Range 1 (FR1) as including 600 MHz to 6 GHz, although specific uplink and downlink allocations may be outside of this general range. Thus, FR1 is often referred to (interchangeably) as the "sub-6 GHz" band.

[0040] Similarly, TS 38.101 currently defines Frequency Range 2 (FR2) as including 26-41 GHz, although again, specific uplink and downlink allocations may be outside of this general range. FR2 is sometimes referred to (interchangeably) as the "millimeter wave" ("mmW" or "mmWave") band because the wavelengths at these frequencies are between 1 millimeter and 10 millimeters, although it is distinct from the extremely high frequency (EHF) bands (30 GHz to 300 GHz) identified by the International Telecommunications Union (ITU) as "millimeter wave" bands.

[0041] Communications using mmWave / near mmWave radio frequency bands (e.g., 3 GHz to 300 GHz) may have higher path loss and shorter communication range compared to lower frequency communications. As discussed above with respect to FIG. 1, a base station (e.g., base station 110) configured to communicate using mmWave / near mmWave radio frequency bands may utilize beamforming with a UE (e.g., UE 120) to improve path loss and communication range.

[0042] Example RF Transceiver 3A is a block diagram of an example radio frequency (RF) transceiver circuit 300A according to certain aspects of the disclosure. The RF transceiver circuit 300A includes at least one transmit (TX) path 302 (also referred to as a "transmit chain") for transmitting signals via one or more antennas 306, and at least one receive (RX) path 304 (also referred to as a "receive chain") for receiving signals via the antenna 306. When the TX path 302 and the RX path 304 share an antenna 306, the paths may be connected to the antenna via an interface 308, which may include any of a variety of suitable RF devices, such as a switch, a duplexer, a diplexer, a multiplexer, etc.

[0043] To receive in-phase (I) and / or quadrature (Q) baseband analog signals from a digital-to-analog converter (DAC) 310a, the TX path 302 may include a baseband filter (BBF) 312, a mixer 314, a driver amplifier (DA) 316, and a power amplifier (PA) 318. The BBF 312, the mixer 314, the DA 316, and the PA 318 may be included within a radio frequency integrated circuit (RFIC). In certain aspects, the PA 318 may be external to the RFIC.

[0044] In certain aspects, the DAC 310a may be implemented by any of a variety of suitable high-speed DAC topologies, such as a current steering DAC. In certain aspects, the DAC 310a may be implemented using an adjustable resistor network, as described in more detail below. The BBF 312 filters the baseband signal received from the DAC 310a, and the mixer 314 mixes the filtered baseband signal with a transmit local oscillator (LO) signal to convert the baseband signal to a different frequency (e.g., upconvert from baseband to radio frequency). This frequency conversion process generates sum and difference frequencies between the LO frequency and the frequency of the baseband signal. The sum and difference frequencies are called "beat frequencies." The beat frequency is typically in the RF range, and therefore the signal output by the mixer 314 is typically an RF signal, which may be amplified by the DA 316 and / or the PA 318 before transmission by the antenna(s) 306. Although one mixer 314 is illustrated, several mixers may be used to upconvert the filtered baseband signal to one or more intermediate frequencies and then upconvert the intermediate frequency signal to a frequency for transmission.

[0045] The RX path 304 may include a low noise amplifier (LNA) 324, a mixer 326, and a baseband filter (BBF) 328. The LNA 324, the mixer 326, and the BBF 328 may be included in one or more RFICs, which may or may not be the same RFIC that includes the TX path components. RF signals received via the antenna(s) 306 may be amplified by the LNA 324, and the mixer 326 mixes the amplified RF signal with a receive local oscillator (LO) signal to convert (e.g., downconvert) the RF signal to a different baseband frequency. The baseband signal output by the mixer 326 may be filtered by the BBF 328 before being converted to digital I and / or Q signals by an analog-to-digital converter (ADC) 330 for digital signal processing.

[0046] A particular transceiver may employ a frequency synthesizer with a variable frequency oscillator (e.g., a voltage controlled oscillator (VCO) or a digitally controlled oscillator (DCO)) to generate a stable, tunable LO with a particular tuning range. Thus, the transmit LO may be generated by the TX frequency synthesizer 320, which may be buffered or amplified by an amplifier 322 before being mixed with the baseband signal in the mixer 314. Similarly, the receive LO may be generated by the RX frequency synthesizer 332, which may be buffered or amplified by an amplifier 334 before being mixed with the RF signal in the mixer 326. In certain aspects, a single frequency synthesizer may be used for both the TX path 302 and the RX path 304. In certain aspects, the TX frequency synthesizer 320 and / or the RX frequency synthesizer 332 may include a frequency multiplier, such as a frequency doubler, driven by an oscillator (e.g., a VCO) within the frequency synthesizer.

[0047] The controller 336 (e.g., the controller / processor 280 of FIG. 2) may direct the operation of the RF transceiver circuitry 300A, such as transmitting signals via the TX path 302 and / or receiving signals via the RX path 304. The controller 336 may be a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof. The memory 338 (e.g., the memory 282 of FIG. 2) may store data and / or program code for operating the RF transceiver circuitry 300A. The controller 336 and / or the memory 338 may include control logic (e.g., complementary metal oxide semiconductor (CMOS) logic).

[0048] 3B is a block diagram of an example RF transceiver circuit 300B according to certain aspects of the disclosure. The RF transceiver circuit 300B may be similar to the RF transceiver circuit 300A, but has multiple TX paths 302a and 302b (collectively referred to as "TX paths 302"). The TX path 302a may include a baseband filter (BBF) 312a, a mixer 314a, a driver amplifier (DA) 316a, and a power amplifier (PA) 318a. The TX path 302b may include similar components to the TX path 302a (e.g., a BBF 312b, a mixer 314b, a DA 316b, and a PA 318b). The components of the TX path 302a may be the same as or different from the components of the TX path 302b. The RF transceiver circuitry 300B may also include a DAC 310b to support multiple radio access technologies (RATs), such as sub-6 GHz and mmWave transmissions.

[0049] The RF transceiver circuitry 300B (more specifically, the DAC 310b and the TX path 302) may support multiple wireless transmission scenarios, such as sub-6 GHz and millimeter wave (mmWave) wireless transmission scenarios. For example, the RF transceiver circuitry 300B may transmit signals using a first wireless communication technology (e.g., 3G, 4G, 5G, etc.) operating below 6 GHz and a second wireless communication technology (e.g., mmWave 5G, IEEE 802.11ad, or 802.11ay in the 24 to 60 GHz band) operating above 6 GHz. In one example, the RF transceiver circuitry 300B may process sub-6 GHz signals through the TX path 302a and may process mmWave signals through the TX path 302b (or vice versa). As used herein, the sub-6 GHz band may include, in some examples, a frequency band between 300 and 6000 MHz, and in some examples, a band within the range of 6000 MHz and / or 7000 MHz.

[0050] In some cases where the DAC 310b supports both the sub-6 GHz and mmWave frequency ranges and utilizes a current-steering DAC topology, the DAC 310b may be referred to as a "converged current-steering DAC." In a converged current-steering DAC, different full-scale currents (I FS ) specifications, a wide range of I FS In some examples, the DAC 310b may have an I equal to a base value (e.g., × or 1×) for sub-6 GHz technology. FS and for mmWave technology, I equal to 2 to 4 times (e.g., 2× or 4×) the base value. FS In some cases, I equal to eight times the base value (e.g., 8×) FS For example, for sub-6 GHz, FS has a base value of 1 × = 0.25 mA, then for mmWave, I FS can be equal to 0.50 or 1.00 mA. Although each output of the DAC 310b shown in FIG. 3B is shown as a single-ended output, it can represent a differential output current.

[0051] For ease of understanding, FIGS. 1, 2, 3A, and 3B provide a wireless communication system as an example application in which certain aspects of the present disclosure may be implemented, although certain aspects described herein may be used for digital-to-analog conversion in any of a variety of other suitable systems (e.g., audio systems or other electronic systems).

[0052] Exemplary DAC with Adaptive Resistor Network A current-steering digital-to-analog converter (DAC) is one exemplary architecture for high-performance digital-to-analog conversion in many wireless transmitters. One type of current-steering DAC is a resistor-degenerated (R-deg) current-steering DAC. Compared to some other DAC architectures, the R-deg current-steering DAC can provide reduced flicker noise, mismatch drift with temperature changes, gate leakage, and lateral area (e.g., footprint).

[0053] FIG. 4A illustrates an exemplary DAC 400 (which may, for example, implement the DAC 310a of FIG. 3A or the DAC 310b of FIG. 3B). The core of the DAC 400 includes n DAC cells 4021-402. n (collectively referred to as “DAC cells 402” and individually referred to as “DAC cell 402”), where n is an integer greater than 1. Each DAC cell 402 includes at least one current source 412 1 ,...,412 N (collectively referred to as “current sources 412” and individually referred to as “current sources 412”), and a resistor network coupled between a power supply rail (e.g., VDDA) and the current sources to provide degeneration resistance.

[0054] Each resistor network may include multiple resistive elements. For example, the DAC cell 4021 includes N+1 degenerate resistive elements R degS10 ,R degS11 ,...,R deg S1N DAC cell 402 n is the N+1 degenerate resistance element R degSN0 ,R degSN1 ,...,R deg SNN For ease of explanation, the resistive elements of the resistor network will be referred to collectively as “resistive element R deg " or individually "resistance element R deg As shown, in certain embodiments, the resistive element R deg may be coupled in series. In some examples, a resistive element R degThe nodes between may be referred to as "taps" of the resistor network.

[0055] Each of the current sources 412 includes at least one transistor (e.g., transistor M CS " Transistor M CS1 ,...,M CSN ), which may be implemented, for example, by a p-type metal-oxide-semiconductor (PMOS) transistor as shown in FIG. 4A.

[0056] The DAC 400 may also include a number of DAC switches 404 coupled between a current source 412 and an output 406 (labeled “DAC_out”) of the DAC 400. Depending on a digital input signal provided to an input of the DAC 400, each bit of the DAC 400 associated with a DAC cell 402 may control the respective cell's switch 404 (or the respective cell's differential switch) to source or block current from the cell's current source 412 to the DAC output 406. The currents sourced from the individual DAC cells 402 may be combined (e.g., using a current summation) to provide an analog output signal at the DAC output 406. The DAC output 406 may be coupled to one or more baseband filters (e.g., the BBF(s) 312 of FIG. 3A or FIG. 3B), or any of a variety of other suitable circuits. Although the DAC output 406 is shown in FIG. 4A as a single-ended output, it may also be implemented as a pair of differential current outputs.

[0057] The DAC 400 may also include a bias branch 408 (also referred to as the “reference branch” of the current mirror, in which the bias branch 408 has a reference current source, and the current sources 412 in the DAC cells 402 are controlled based on the reference current). The bias branch 408 may be configured to control the current of the current source(s) 412 in one or more of the DAC cells 402. The bias branch 408 may be configured to bias the current mirror transistor M CM , the power rail and the current mirror transistor M CMand a resistor network coupled between the bias branch 408 and the transistor M CM (shorted to the gate) of the DAC cell 402 (and the control input of the current source 412 in one or more of the DAC cells 402 (e.g., the transistor M CS , gate of transistor M) and a reference potential node (e.g., analog ground, labeled "VSSA" in FIG. 4A). The bias current source 410 can be configured to generate a bias current having a value equal to a base value (e.g., 1x) or a multiple of the base value (e.g., 2x, 3x, 4x, ..., nx). The bias branch 408 also includes a power rail (VDDA) and a transistor M CM (and the control inputs of the current sources 412 in one or more of the DAC cells 402) ("C FB "). This capacitive element C FB can provide, for example, noise filtering.

[0058] The degeneration voltage of the DAC cell 402 may be defined as the voltage drop (e.g., current-resistance (IR) drop) across the resistor network (e.g., between the power rail (VDDA) and the current source 412). FS ) may be defined as the sum of the currents generated by the current sources 412. I FS can be controlled by bias current source 410. The size of current source 412 is determined based on the maximum I FS The DAC 400 can be selected based on the maximum I FS However, when the DAC 400 operates at a nominal I FS (For example, maximum I FSWhen operating at a lower current (less than half of the I), the degeneration voltage of the DAC cell 402 will be reduced. Current noise and mismatch are inversely proportional to the degeneration voltage of the DAC cell 402. Thus, as a result of a lower degeneration voltage, the DAC 400 may suffer from increased noise and mismatch. Furthermore, in conventional current steering DAC architectures, the degeneration voltage of a DAC cell 402 scales linearly with the current generated by the current source 412 in that DAC cell 402, and the power supply rail voltage may be limited, so I FS It can be difficult to scale up

[0059] Therefore, if the DAC is nominally I FS What is needed is an apparatus and technique for maintaining the degeneration voltage at (or at least near) a maximum value, even when operating at 100 MHz. Certain aspects of the present disclosure provide techniques and circuits for adaptively adjusting the resistance of a resistor network in a DAC based on a bias current. With adjustable resistance, the degeneration voltage can be maximized (or at least increased) for a given value of bias current (and a given headroom). A higher degeneration voltage can provide reduced output noise and mismatch.

[0060] 4A also illustrates an exemplary implementation of a resistor network with adjustable resistance for use in a DAC 400, according to certain aspects of the disclosure. This implementation is coupled to one or more of the resistive elements and adjusts the I FS The present invention introduces a plurality of switches configured to adjust the resistance of the resistor network based on

[0061] Resistance element R of resistor network deg may be coupled in series, and a tap of the resistor network may be connected to a resistive element R deg As shown in FIG. 4A, a first switch Ifs1 of the multiple switches may be connected to a first tap of the resistor network (e.g., R degS10 and R degS11) and the current source 412 of the DAC cell 402. In a particular aspect, a second switch Ifs2 of the plurality of switches may be coupled between a second tap of the resistor network, different from the first tap, and the current source 412. For example, the second switch Ifs2 may be coupled between a second tap of the resistor network (e.g., a node between R degS11 and another resistive element (not shown)) and a current source 412.

[0062] In certain aspects, as described in more detail below, at least one of the multiple switches may be configured to be in an open or closed state based on the value of the bias current.

[0063] As shown in FIG. 4B, each of the switches has a negative gate-source voltage (V gs ) can be implemented by a transistor, such as a p-channel field-effect transistor (PFET) having a negative V gs A PFET having a PFET transistor M may have low current leakage when the transistor is off. The source of each network transistor in a DAC cell 402 may be coupled to a different tap (e.g., a node between resistive elements) of the resistor network of the respective DAC cell 402. In addition, the drain of each network transistor in a DAC cell 402 may be coupled to a current source 412 (e.g., a node between resistive elements) of the respective DAC cell 402. CS The source of the

[0064] 5A, 5B, 5C, and 5D are schematic diagrams illustrating alternative exemplary circuits for implementing resistor networks with adjustable resistance according to certain aspects of the present disclosure. In certain aspects, the resistive elements in these exemplary circuits may have the same resistance.

[0065] As shown in circuit 500A of FIG. 5A, a resistor network is coupled in series (R deg1 , R deg2 , R deg3 , and Rdeg4 1. The resistor network may be implemented by four resistive elements (labeled R 1 and R 2 ) that are connected to a first tap 502 of the resistor network (e.g., labeled R 2 ). The resistor network may be used to support a full-scale current of a particular DAC cell, which may be equal to 1, 2, or 4 times (e.g., 1×, 2×, or 4×) the base value of the bias current (Ibias). As shown, a first switch Ifs1 switches a first tap 502 of the resistor network (e.g., labeled R 3 ) to a first tap 502 of the resistor network (e.g., labeled R 4 ) that is connected to a first resistor network (e.g., labeled R 5 ). deg2 and R deg3 ) and a power rail (e.g., VDDA). IMSB is the most significant bit (MSB) current, which is essentially the current output by the current source of that DAC cell. In some examples, the circuit 500A also includes a second tap 504 of the resistor network (e.g., a node between resistive element R deg3 and R deg4 ) and the power rail.

[0066] In some examples, when the bias current is set to a value equal to the base value (e.g., 1×), the first switch Ifs1 and the second switch Ifs2 may be configured to be in an open state. In some examples, when the bias current is set to a value equal to twice the base value (e.g., 2×), the first switch Ifs1 may be configured to be in a closed state and the second switch Ifs2 may be configured to be in an open state. In some examples, when the bias current is set to a value equal to four times the base value (e.g., 4×), the second switch Ifs2 may be configured to be in a closed state and the first switch Ifs1 may be configured to be in an open state.

[0067] In the alternative circuit 500B of FIG. 5B, for example, a first portion of a plurality of resistive elements (e.g., series-coupled R deg1 and R deg2 ) is switched on by a first switch Ifs1 of the plurality of switches to a second portion of the plurality of resistive elements (e.g., R deg3 and R deg4In other words, the first switch Ifs1 can be selectively coupled to the resistive element R deg2 Connect the terminals of the resistor element R deg3 In some examples, a second switch Ifs2 selectively couples to a terminal of the first tap 506 of the resistor network (resistive element R deg2 terminal) and transistor M CS In some examples, a third switch Ifs3 may be coupled between the second tap 508 of the resistor network (resistive element R deg3 The input terminal of the input terminal of the power supply may be coupled between the power supply rail.

[0068] In certain aspects, when the bias current is set to a value equal to a base value (e.g., 1×), the first switch Ifs1 may be configured to be in a closed state, and the second switch Ifs2 and the third switch Ifs3 may be configured to be in an open state. In certain aspects, when the bias current is set to a value equal to twice the base value (e.g., 2×), the first switch Ifs1 and the second switch Ifs2 may be configured to be in a closed state, and the third switch Ifs3 may be configured to be in an open state. In some examples, when the bias current is set to a value equal to four times the base value (e.g., 4×), the second switch Ifs2 and the third switch Ifs3 may be configured to be in a closed state, and the first switch Ifs1 may be configured to be in an open state (labeled

[0069]

number

[0070] In the alternative circuit 500C of FIG. 5C, for example, a first portion of a plurality of resistive elements (e.g., serially coupled R deg1 and R deg2 ) is switched on by a first switch Ifs1 of the plurality of switches to a second portion of the plurality of resistive elements (e.g., R deg3 and R deg4In other words, the first switch Ifs1 can be selectively coupled to the resistive element R deg2 Connect the terminals of the resistor element R deg3 In some examples, the alternative circuit 500C also includes a resistor network first tap 510 (resistive element R deg3 terminal) and transistor M CS In some examples, the alternative circuit 500C may also include a second switch Ifs2 coupled between the source of the resistor network 512 (resistive element R deg2 In some examples, the alternative circuit 500C may also include a third switch Ifs3 coupled between the third tap 514 of the resistor network (resistive element R deg1 terminal) and transistor M CS The input may include a fourth switch Ifs4 coupled between the input and the source of the input.

[0071] In a particular example, when the bias current is set to a value equal to the base value (e.g., 1×), the first switch Ifs1 may be configured to be in a closed state, and the second switch Ifs2, the third switch Ifs3, and the fourth switch Ifs4 may be configured to be in an open state. In a particular aspect, when the bias current is set to a value equal to twice the base value (e.g., 2×), the first switch Ifs1 and the second switch Ifs2 may be configured to be in a closed state, and the third switch Ifs3 and the fourth switch Ifs4 may be configured to be in an open state. In some aspects, when the bias current is set to a value equal to four times the base value (e.g., 4×), the first switch Ifs1 and the fourth switch Ifs4 may be configured to be in a closed state, and the second switch Ifs2 and the third switch Ifs3 may be configured to be in an open state. In some examples, when the bias current is set to a value equal to eight times the base value (e.g., 8×), the third switch Ifs3 and the fourth switch Ifs4 may be configured to be in a closed state, and the first switch Ifs1 may be configured to be in an open state (labeled

[0072]

number

[0073] In certain embodiments, each switch of the plurality of switches is connected to a current source (e.g., a transistor M CS 5D ) and a different resistive element of the plurality of resistive elements selectively coupled in parallel. For example, the alternative circuit 500D of FIG. 5D may include a first resistive element R deg1 In some examples, the alternative circuit 500D may also include a first switch Ifs1 coupled between the first resistor R deg2 In some examples, the alternative circuit 500D may also include a third resistive element R deg3 a third switch Ifs3 coupled between the current source and a fourth resistive element R deg4 and a fourth switch Ifs4 coupled between the current source.

[0074] For the alternative circuit 500D, when the set of switches is in a closed state, the resistive elements coupled to the set of switches will be coupled in parallel with each other. In certain aspects, when the bias current is set to a value equal to the base value (e.g., 1×), the first switch Ifs1 may be configured to be in a closed state, and the second, third, and fourth switches may be configured to be in an open state. In certain aspects, when the bias current is set to a value equal to twice the base value (e.g., 2×), the first switch Ifs1 and the second switch Ifs2 may be configured to be in a closed state, and the third switch Ifs3 and the fourth switch Ifs4 may be configured to be in an open state. In some examples, when the bias current is set to a value equal to four times the base value (e.g., 4×), all of the switches Ifs1-Ifs4 may be configured to be in a closed state. Thus, if all four resistive elements have the same resistance, the degeneration voltage Vdeg will be the same in all three configurations (depending on the tolerance of the resistors).

[0075] Although a particular number of resistive elements and switches are shown in FIGS. 5A-5D, it should be understood that more or fewer resistive elements and / or switches may be used.

[0076] Aspects of the present disclosure may provide reduced output noise and / or lower mismatch compared to some other DAC architectures.

[0077] Exemplary Conversion Operations 6 is a flow diagram of an example operation 600 for digital-to-analog conversion according to certain aspects of the disclosure. The operation 600 may be performed, for example, by a digital-to-analog converter (DAC) having a resistor network with adjustable resistance (e.g., DAC 400).

[0078] The operations 600 may begin, at block 602, by receiving a digital input code at an input of a DAC that includes a number of DAC cells (e.g., DAC cell 402). One or more of the DAC cells may include a current source (e.g., current source 412) and a number of resistive elements (e.g., resistive elements R deg1 , R deg2 , R deg3 , and R deg4 ) (e.g., the resistor networks in circuits 500A, 500B, 500C, and 500D). The resistor networks may have adjustable resistance and may be coupled between a power supply rail (e.g., VDDA) and a current source. In block 604, the DAC may generate an analog output signal based on the digital input code.

[0079] According to certain aspects, the operations 600 further involve adjusting a resistance of a resistor network in one or more of the DAC cells. The adjustment may include selectively closing a plurality of switches (e.g., switches Ifs1-Ifs4) in one or more of the DAC cells. The plurality of switches may be coupled to one or more of the resistive elements. In certain aspects, the operations 600 may further include adjusting a bias current (e.g., Ibias) via an adjustable bias current source (e.g., adjustable bias current source 410) and controlling a current of a current source in one or more of the DAC cells based on the bias current. In certain aspects, adjusting the resistance of the resistor network in one or more of the DAC cells involves controlling a state (e.g., open or closed) of at least one of the plurality of switches based on a value of the bias current.

[0080] According to a particular aspect, the resistive elements (of the plurality of resistive elements) are coupled in series, a node between the resistive elements is a tap of a resistor network, a first switch (e.g., switch Ifs1) of the plurality of switches is coupled between a first tap of the resistor network and a current source, and a second switch (e.g., switch Ifs2) of the plurality of switches is coupled between a second tap of the resistor network and a current source, the second tap being different from the first tap. In this case, controlling the state of at least one of the plurality of switches may involve closing the first switch and opening the second switch when the value of the bias current is set to a base value, and opening the first switch and closing the second switch when the value of the bias current is set to a value different from the base value. For example, controlling the state of at least one of the plurality of switches may include opening the first switch and closing the second switch when the value of the bias current is set to twice the base value.

[0081] According to a particular aspect, the resistive elements (of the plurality of resistive elements) are coupled in series, a node between the resistive elements is a tap (e.g., taps 502, 504) of the resistor network, and a first switch (e.g., switch Ifs1) of the plurality of switches is coupled between the first tap (e.g., tap 502) of the resistor network and a power supply rail. In this case, controlling the state of at least one switch of the plurality of switches may involve opening the first switch when the value of the bias current is set to a base value, and closing the first switch when the value of the bias current is set to a value different from the base value. In a particular aspect, a second switch (e.g., switch Ifs2) of the plurality of switches is coupled between a second tap (e.g., tap 504) of the resistor network and a power supply rail, the second tap being different from the first tap. In this case, controlling the state of at least one switch of the plurality of switches may include opening the first switch and the second switch when the value of the bias current is set to a base value, closing the first switch and opening the second switch when the value of the bias current is set to twice the base value, and opening the first switch and closing the second switch when the value of the bias current is set to four times the base value.

[0082] According to certain aspects, a first portion of the plurality of resistive elements (e.g., resistive elements Rdeg1 and Rdeg2) is selectively coupled to a second portion of the plurality of resistive elements (e.g., resistive elements Rdeg3 and Rdeg4) by a first switch of the plurality of switches (e.g., switch Ifs1 in FIG. 5B or FIG. 5C), and a second switch of the plurality of switches (e.g., switch Ifs2 in FIG. 5B or FIG. 5C) is coupled between a first tap of the resistor network (e.g., tap 506 in FIG. 5B or tap 510 in FIG. 5C) and a current source. In this case, controlling a state of at least one of the plurality of switches may involve closing the first switch and opening the second switch when the value of the bias current is set to a base value, and closing the first switch and opening the second switch when the value of the bias current is set to a value different from the base value. In certain aspects, a third switch of the plurality of switches (e.g., switch Ifs3 in FIG. 5B ) is coupled between a second tap of the resistor network (e.g., tap 508 in FIG. 5B ) and a power rail, the second tap being different from the first tap. In this case, closing the first switch and the second switch may include closing the first switch and the second switch when the value of the bias current is set to twice the base value, and controlling the state of at least one of the plurality of switches may further involve opening the first switch and closing the second switch and the third switch when the value of the bias current is set to four times the base value. In other aspects, a third switch of the plurality of switches (e.g., switch Ifs4 in FIG. 5C ) is coupled between a second tap of the resistor network (e.g., tap 514 in FIG. 5C ) and a current source, the second tap being different from the first tap. In this case, closing the first switch and the second switch may include closing the first switch and the second switch when the value of the bias current is set to twice the base value, and controlling the state of at least one of the plurality of switches may further involve closing the first switch and the third switch and opening the second switch when the value of the bias current is set to four times the base value.In certain aspects, a fourth switch of the plurality of switches (e.g., switch Ifs3 of FIG. 5C ) is coupled between a third tap of the resistor network (e.g., tap 512) and a power rail, the third tap being different from the first tap and the second tap. In this case, controlling a state of at least one switch of the plurality of switches may further involve opening the first switch and the second switch and closing the third switch and the fourth switch when the value of the bias current is set to eight times the base value.

[0083] According to certain aspects, a first switch (e.g., switch Ifs1 in FIG. 5D ) of the plurality of switches is coupled in series with a first resistive element (e.g., resistive element Rdeg1) between a power supply rail and a current source, and a second switch (e.g., switch Ifs2 in FIG. 5D ) of the plurality of switches is coupled in series with a second resistive element (e.g., resistive element Rdeg2) between the power supply rail and the current source. In this case, controlling a state of at least one of the plurality of switches may involve closing the first switch and opening the second switch when a value of the bias current is set to a base value, and closing the first switch and the second switch such that the first resistive element and the second resistive element are coupled in parallel when a value of the bias current is set to a value different from the base value. In a particular aspect, a third switch (e.g., switch Ifs3 in FIG. 5D ) of the plurality of switches is coupled in series with a third resistive element (e.g., resistive element Rdeg3) between the power supply rail and the current source, and a fourth switch (e.g., switch Ifs4 in FIG. 5D ) of the plurality of switches is coupled in series with a fourth resistive element (e.g., resistive element Rdeg3) between the power supply rail and the current source. In this case, controlling the state of at least one of the plurality of switches may further include closing the first switch and the second switch and opening the third switch and the fourth switch when the value of the bias current is set to twice the base value, and opening the first switch, the second switch, the third switch, and the fourth switch when the value of the bias current is set to four times the base value.

[0084] Exemplary Aspects In addition to the various aspects described above, specific combinations of aspects are within the scope of the present disclosure, some of which are detailed below.

[0085] Aspect 1: A digital-to-analog converter (DAC) comprising a plurality of DAC cells, one or more of which comprises a current source and a resistor network comprising a plurality of resistive elements having adjustable resistance coupled between a power supply rail and the current source.

[0086] Aspect 2: The DAC of aspect 1, wherein one or more of the DAC cells further comprise a plurality of switches coupled to one or more of the resistive elements and configured to adjust the resistance of the resistor network.

[0087] Aspect 3: The DAC of aspect 1 or aspect 2, further comprising an adjustable bias current source configured to generate a bias current and coupled between a control input of the current source in one or more of the DAC cells and a reference potential node of the DAC.

[0088] Aspect 4: The DAC of aspect 3, wherein at least one of the plurality of switches is configured to be in an open or closed state based on a value of the bias current.

[0089] Aspect 5: One or more of the switches have a negative gate-source voltage (V gs 5. The DAC of any one of embodiments 2-4, comprising a p-channel field effect transistor (PFET) having a

[0090] Example 6: A DAC according to any of Examples 1 to 5, wherein a plurality of resistive elements are coupled in series and a node between the resistive elements comprises a tap of the resistor network.

[0091] Example 7: The DAC of any one of Examples 2-6, wherein a first switch of the plurality of switches is coupled between a first tap of the resistor network and a current source.

[0092] Aspect 8: The DAC of aspect 7, wherein a second switch of the plurality of switches is coupled between a second tap of the resistor network and the current source, the second tap being different from the first tap.

[0093] Example 9: The DAC of any one of Examples 2-6, wherein a first switch of the plurality of switches is coupled between a first tap of the resistor network and a power supply rail.

[0094] Example 10: The DAC of example 9, wherein a second switch of the plurality of switches is coupled between a second tap of the resistor network and the power rail, the second tap being different from the first tap.

[0095] Aspect 11: A DAC as described in any of aspects 2 to 6, wherein a first portion of the plurality of resistive elements is selectively coupled to a second portion of the plurality of resistive elements by a first switch of the plurality of switches, and a second switch of the plurality of switches is coupled between a first tap of the resistor network and a current source.

[0096] Example 12: The DAC of example 11, wherein a third switch of the plurality of switches is coupled between a second tap of the resistor network and the power rail, the second tap being different from the first tap.

[0097] Aspect 13: A DAC described in any of aspects 2 to 6, wherein a first switch of the plurality of switches is coupled in series to a first resistive element between the power supply rail and the current source, and a second switch of the plurality of switches is coupled in series to a second resistive element between the power supply rail and the current source, and when the first switch and the second switch are in a closed state, the first resistive element and the second resistive element are coupled in parallel.

[0098] Aspect 14: A wireless device comprising a DAC as described in any one of aspects 1 to 13, the wireless device further comprising one or more antennas and one or more transmit paths coupled between one or more outputs of the DAC and the one or more antennas.

[0099] Aspect 15: A method for digital-to-analog conversion comprising: receiving a digital input code at an input of a digital-to-analog converter (DAC) having a plurality of DAC cells; and generating an analog output signal via the DAC based on the digital input code, wherein one or more of the plurality of DAC cells comprises a current source and a resistor network comprising a plurality of resistive elements having adjustable resistance and coupled between a power supply rail and the current source.

[0100] Aspect 16: The method of aspect 15, further comprising adjusting a resistance of a resistor network within one or more of the DAC cells, where the adjusting comprises selectively closing a plurality of switches within one or more of the DAC cells, the plurality of switches being coupled to one or more of the resistive elements.

[0101] Example 17: The method of example 15 or 16, further comprising adjusting a bias current via an adjustable bias current source and controlling a current of a current source in one or more of the DAC cells based on the bias current.

[0102] Aspect 18: The method of aspect 16 or 17, wherein adjusting the resistance of a resistor network in one or more of the DAC cells includes controlling a state of at least one of a plurality of switches based on a value of a bias current, and the state of at least one of the plurality of switches includes an open state or a closed state.

[0103] Aspect 19: The method of any of aspects 16-18, wherein a plurality of resistive elements are coupled in series, a node between the resistive elements comprises a tap of a resistor network, a first switch of the plurality of switches is coupled between a first tap of the resistor network and a current source, a second switch of the plurality of switches is coupled between a second tap of the resistor network and the current source, the second tap being different from the first tap, and controlling a state of at least one of the plurality of switches includes closing the first switch and opening the second switch when a value of the bias current is set to a base value, and opening the first switch and closing the second switch when the value of the bias current is set to a value different from the base value.

[0104] Aspect 20: The method of aspect 19, wherein controlling the state of at least one of the plurality of switches includes opening a first switch and closing a second switch when a value of the bias current is set to twice the base value.

[0105] Aspect 21: A method according to any of aspects 16-18, wherein a plurality of resistive elements are coupled in series, a node between the resistive elements comprises a tap of a resistor network, a first switch of the plurality of switches is coupled between the first tap of the resistor network and a power supply rail, and controlling a state of at least one of the plurality of switches includes opening the first switch when a value of a bias current is set to a base value, and closing the first switch when the value of the bias current is set to a value different from the base value.

[0106] Aspect 22: The method of aspect 21, wherein a second switch of the plurality of switches is coupled between a second tap of the resistor network and a power rail, the second tap being different from the first tap, and controlling a state of at least one of the plurality of switches includes opening the first switch and the second switch when a value of the bias current is set to a base value, closing the first switch and opening the second switch when the value of the bias current is set to twice the base value, and opening the first switch and closing the second switch when a time period of the bias current value is set to four times the base value.

[0107] Aspect 23: A method according to any of aspects 16-18, wherein a first portion of the plurality of resistive elements is selectively coupled to a second portion of the plurality of resistive elements by a first switch of the plurality of switches, and a second switch of the plurality of switches is coupled between a first tap of the resistor network and a current source, and controlling a state of at least one of the plurality of switches includes closing the first switch and opening the second switch when a value of the bias current is set to a base value, and closing the first switch and the second switch when the value of the bias current is set to a value different from the base value.

[0108] Aspect 24: The method of aspect 23, wherein a third switch of the plurality of switches is coupled between a second tap of the resistor network and the power supply rail, the second tap being different from the first tap, and closing the first switch and the second switch includes closing the first switch and the second switch when a value of a bias current is set to twice a base value, and controlling a state of at least one of the plurality of switches further includes opening the first switch and closing the second switch and the third switch when a value of a bias current is set to four times a base value.

[0109] Aspect 25: The method of aspect 23, wherein a third switch of the plurality of switches is coupled between a second tap of the resistor network and the current source, the second tap being different from the first tap, and closing the first switch and the second switch includes closing the first switch and the second switch when a value of the bias current is set to twice a base value, and controlling a state of at least one of the plurality of switches further includes closing the first switch and the third switch and opening the second switch when a value of the bias current is set to four times the base value.

[0110] Aspect 26: The method of aspect 25, wherein a fourth switch of the plurality of switches is coupled between a third tap of the resistor network and the power rail, the third tap being different from the first tap and the second tap, and controlling a state of at least one of the plurality of switches further includes opening the first switch and the second switch and closing the third switch and the fourth switch when the value of the bias current is set to eight times the base value.

[0111] Aspect 27: A method according to any of aspects 16-18, wherein a first switch of the plurality of switches is coupled in series with a first resistive element between a power supply rail and a current source, and a second switch of the plurality of switches is coupled in series with a second resistive element between the power supply rail and the current source, and controlling a state of at least one of the plurality of switches includes: closing the first switch and opening the second switch when a value of a bias current is set to a base value, and closing the first switch and the second switch such that the first resistive element and the second resistive element are coupled in parallel when the value of the bias current is set to a value different from the base value.

[0112] Aspect 28: The method of aspect 27, wherein a third switch of the plurality of switches is coupled in series with a third resistive element between the power supply rail and the current source, and a fourth switch of the plurality of switches is coupled in series with a fourth resistive element between the power supply rail and the current source, and controlling a state of at least one of the plurality of switches further includes: closing the first switch and the second switch and opening the third switch and the fourth switch when a value of the bias current is set to twice a base value, and opening the first switch, the second switch, the third switch, and the fourth switch when a value of the bias current is set to four times the base value.

[0113] conclusion Described herein are digital-to-analog converter (DAC) architectures for addressing reduced degeneration voltages when the DAC operates at a nominal full-scale current. Certain aspects of the present disclosure provide techniques and circuits for adaptively adjusting the resistance of a resistor network in the DAC (e.g., based on a full-scale current that can vary based on an adjustable bias current). With adjustable resistances, the degeneration voltage can be maximized (or at least increased) for a given value of bias current. The increased degeneration voltage can provide reduced output noise and mismatch from the DAC.

[0114] The above description provides examples and is not intended to limit the scope, applicability, or examples set forth in the claims. Changes may be made in the function and arrangement of the elements described without departing from the scope of the disclosure. Various embodiments may omit, substitute, or add various procedures or components as appropriate. For example, the methods described may be performed in an order different from that described, and various steps may be added, omitted, or combined. Also, features described with respect to some embodiments may be combined in some other embodiments. For example, an apparatus may be implemented or a method may be practiced using any number of aspects described herein. In addition, the scope of the disclosure is intended to cover such apparatus or methods practiced using other structures, functions, or structures and functions in addition to or other than the various aspects of the disclosure described herein. It is to be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of a claim. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0115] The various operations of the methods described above may be performed by any suitable means capable of performing the corresponding functions, which may include various hardware and / or software component(s) including, but not limited to, circuits, application-specific integrated circuits (ASICs), or processors, and / or various hardware and / or software module(s). In general, where there are operations illustrated in figures, those operations may have corresponding counterpart means-plus-function components.

[0116] As used herein, a phrase referring to "at least one of" a list of items refers to any combination of those items, including single members. By way of example, "at least one of a, b, or c" is intended to encompass a, b, c, ab, ac, bc, and abc, as well as any combination having multiples of the same element (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or a, b, and c in any other order).

[0117] The methods disclosed herein include one or more steps or actions for achieving the described method. The steps and / or actions of those methods may be interchanged with one another without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order of specific steps and / or actions and / or the use of those steps and / or actions may be modified without departing from the scope of the claims.

[0118] It should be understood that the claims are not limited to the precise configuration and components illustrated above. Various modifications, changes and variations may be made in the arrangement, operation and details of the methods and apparatus described above without departing from the scope of the claims.

Claims

1. A DAC comprising multiple digital-to-analog converter (DAC) cells, wherein one or more of the DAC cells are A current source and A resistor network comprising a plurality of resistor elements having adjustable resistance and coupled between the power rail and the current source, One or more of the DAC cells further comprises a plurality of switches configured to be coupled to one or more of the resistor elements and to adjust the resistance of the resistor network, The plurality of resistors are connected in series, The nodes between the resistor elements are provided with taps in the resistor network. The first switch among the plurality of switches is coupled between the first tap of the resistor network and the current source. DAC.

2. The DAC according to claim 1, further comprising an adjustable bias current source configured to generate a bias current, coupled between the control input of the current source in one or more of the DAC cells and the reference potential node of the DAC.

3. The DAC according to claim 2, wherein at least one of the plurality of switches is configured to be open or closed based on the value of the bias current.

4. One or more of the aforementioned switches have a negative gate-source voltage (V ｇｓ The DAC according to claim 1, comprising a p-channel field-effect transistor (PFET) having ).

5. The DAC according to claim 1, wherein a second switch among the plurality of switches is coupled between a second tap of the resistor network and the current source, and the second tap is different from the first tap.

6. A DAC comprising a plurality of digital-to-analog converter (DAC) cells, wherein one or more of the DAC cells are A current source and A resistor network comprising a plurality of resistor elements having adjustable resistance and coupled between the power rail and the current source, One or more of the DAC cells further comprises a plurality of switches configured to be coupled to one or more of the resistor elements and to adjust the resistance of the resistor network, The plurality of resistors are connected in series, The nodes between the resistor elements are provided with taps in the resistor network. The first switch among the plurality of switches is coupled between the first tap of the resistor network and the power rail. DAC.

7. The DAC according to claim 6, wherein a second switch among the plurality of switches is coupled between a second tap of the resistor network and the power rail, and the second tap is different from the first tap.

8. A DAC comprising a plurality of digital-to-analog converter (DAC) cells, wherein one or more of the DAC cells are A current source and A resistor network comprising a plurality of resistor elements having adjustable resistance and coupled between the power rail and the current source, One or more of the DAC cells further comprises a plurality of switches configured to be coupled to one or more of the resistor elements and to adjust the resistance of the resistor network, The first portion of the plurality of resistive elements is selectively coupled to the second portion of the plurality of resistive elements by the first switch among the plurality of switches. The second switch among the plurality of switches is coupled between the first tap of the resistor network and the current source. DAC.

9. The DAC according to claim 8, wherein a third switch among the plurality of switches is coupled between a second tap of the resistor network and the power rail, and the second tap is different from the first tap.

10. A DAC comprising a plurality of digital-to-analog converter (DAC) cells, wherein one or more of the DAC cells are A current source and A resistor network comprising a plurality of resistor elements having adjustable resistance and coupled between the power rail and the current source, One or more of the DAC cells further comprises a plurality of switches configured to be coupled to one or more of the resistor elements and to adjust the resistance of the resistor network, The first switch among the plurality of switches is connected in series with a first resistive element between the power rail and the current source. A second switch among the plurality of switches is connected in series with a second resistive element between the power rail and the current source. When the first switch and the second switch are in the closed state, the first resistive element and the second resistive element are connected in parallel. DAC.

11. A wireless device comprising a DAC according to any one of claims 1, 6, 8, or 10, wherein the wireless device is One or more antennas, A wireless device further comprising one or more transmission paths coupled between one or more outputs of the DAC and one or more antennas.

12. Receiving a digital input code at the input of the digital-to-analog converter (DAC) according to any one of claims 1 to 10, A method for digital-to-analog conversion, comprising generating an analog output signal via the DAC based on the digital input code.

13. The method according to claim 12, further comprising adjusting the resistance of the resistor network in one or more of the DAC cells, wherein the adjustment includes selectively closing one or more of the multiple switches in one or more of the DAC cells.

14. Adjusting the bias current via the adjustable bias current source, The method according to claim 13, referencing claim 2, further comprising controlling the current of the current source in one or more of the DAC cells based on the bias current.

15. The method according to claim 14, wherein adjusting the resistance of the resistor network in one or more of the DAC cells includes controlling the state of at least one of the plurality of switches based on the value of the bias current, and the state of at least one of the plurality of switches includes an open state or a closed state.

16. The digital input code is received at the input of the digital-to-analog converter (DAC) according to claim 11, A method for digital-to-analog conversion, comprising generating an analog output signal via the DAC based on the digital input code.

17. The method of claim 16, further comprising adjusting the resistance of the resistor network in one or more of the DAC cells, wherein the adjustment includes selectively closing one or more of the plurality of switches in one or more of the DAC cells.

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