Usefulness of impedance tuning in vector space defined by transmission dose

Abstract

Embodiments disclosed herein include a method of impedance tuning in a semiconductor processing tool, in an embodiment, the method includes measuring voltages and currents on a transmission line, converting analog voltage and current signals to digital voltage and current signals, calculating a u-vector from the digital voltage and current signals, calculating a C1 position of a first capacitor with a real component of the u-vector, and calculating a C2 position of a second capacitor with an imaginary component of the u-vector.

Description

[Background technology]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims priority to U.S. Patent Application No. 17 / 737,677, filed May 5, 2022, the entire contents of which are incorporated herein by reference.

[0002] Embodiments relate to the field of semiconductor manufacturing, and in particular to semiconductor processing tools configured to provide impedance tuning with transmission line optimization. [Technical field]

[0003] In plasma processing tools, the plasma is ignited by a cathode coupled to the process gases in the chamber. In most tools, the power source is coupled to the cathode through an impedance matching network (sometimes simply called a "matcher"). The matcher allows the impedance of the system to be adjusted to match the impedance of the load to which the cathode is coupled. The load has a wide range of impedances dictated by parameters such as process conditions and chamber geometry. Impedance matching is important for efficient power transfer from the power source to the load.

[0004] Impedance tuning algorithms are typically either heuristic search algorithms or model-based algorithms. Heuristic search is a guided search and is not always guaranteed to converge to a tuned solution. Model-based solutions are computationally complex. Furthermore, the efficiency of the tuning process is predicated on mode 4887P1354l accuracy and proper gain scheduling to facilitate convergence. Scaling is also an issue with such algorithms as they require tuning for each impedance match. Furthermore, the tricky aspects of such algorithms make them difficult to deploy in high volume manufacturing (HVM) environments. Summary of the Invention

[0005] Embodiments disclosed herein include a method of impedance tuning in a semiconductor processing tool, in an embodiment, the method includes measuring voltages and currents on a transmission line, converting analog voltage and current signals to digital voltage and current signals, calculating a u-vector from the digital voltage and current signals, calculating a C1 position of a first capacitor with a real component of the u-vector, and calculating a C2 position of a second capacitor with an imaginary component of the u-vector.

[0006] The embodiment may further include a semiconductor processing tool comprising a power source, an impedance matching network comprising a first capacitor and a second capacitor, a cathode, a power processing module, and sensors for measuring values ​​including an incident voltage, an incident current, a reflected voltage, and a reflected current, the measured values ​​being used by the power processing module to adjust the impedance of the impedance matching network.

[0007] The embodiment may further include a method of impedance tuning in a semiconductor processing tool, in an embodiment, the method includes measuring a voltage and a current on a transmission line, where the voltage includes an incident voltage and a reflected voltage, and the current includes an incident current and a reflected current, converting the analog voltage and current signals to digital voltage and current signals, calculating a u-vector from the digital voltage and current signals, where the u-vector is a three-element vector, calculating a C1 position of a first capacitor with a real component of the u-vector, and calculating a C2 position of a second capacitor with an imaginary component of the u-vector, where the three elements of the u-vector result in an orientation in the impedance tuning space that matches an output load condition of the semiconductor processing tool. [Brief description of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of a plasma processing tool including a central control architecture according to an embodiment. [Diagram 2] FIG. 2 is a plan view of a sensor having a current loop, a voltage ring, and a guard ring according to an embodiment. [Diagram 3] FIG. 2 is a schematic diagram of a transmission line having sensors for detecting reflected and incident voltages and currents according to an embodiment. [Figure 4] FIG. 2 is a process flow diagram of a process for impedance tuning in a semiconductor processing tool, according to an embodiment. [Diagram 5] FIG. 1 illustrates a block diagram of an exemplary computer system that may be used with a processing tool, according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] The system described herein includes sensors for measuring voltage and current in a semiconductor tool. In the following description, numerous specific details are presented to provide a thorough understanding of the embodiments. It will be apparent to one of ordinary skill in the art that the embodiments may be practiced without these specific details. In other instances, well-known aspects have not been described in detail so as not to unnecessarily obscure the embodiments. Furthermore, it should be understood that the various embodiments illustrated in the accompanying figures are illustrative representations and are not necessarily drawn to scale.

[0010] As discussed above, existing tuning algorithms (e.g., heuristic-based search and model-based search) have limitations that make such algorithms unsuitable for HVM environments. Accordingly, embodiments disclosed herein include the use of transmission doses to construct a vector space used to tune the impedance of a system. For example, to optimize transmission line parameters for optimal power transfer from the input to the output of an impedance tuning device, u-vectors with up to three elements can be used to create vector fields with non-overlapping quadrant representations. Such a three-element vector approach is computationally unintensive and allows for real-time control of systems in HVM environments.

[0011] Moreover, the embodiments are highly scalable. For example, there are no limitations on the topology or variations of the impedance matching network. There is no need for gain scheduling. The control gain is derived from the reactance of the control surface (e.g., the control of the variable capacitor). Furthermore, there are no limitations on the impedance matching architecture. That is, mechanical or solid-state variable capacitors can be used according to various embodiments.

[0012] 1, a more detailed schematic diagram of a plasma processing tool 100 is shown, according to an embodiment. In one embodiment, the plasma processing tool 100 includes a plasma chamber 120. The plasma chamber 120 includes a cathode 122 for coupling received power to one or more gases flowing into the plasma chamber 120. In one embodiment, the plasma chamber 120 may be suitable for any plasma processing typical of a semiconductor manufacturing environment. For example, the plasma chamber 120 may be a plasma etch chamber, a plasma deposition chamber, a plasma processing chamber, etc. In certain embodiments, the plasma chamber 120 may be a plasma enhanced chemical vapor deposition (PECVD) chamber, a physical vapor deposition (PVD) chamber, or a plasma enhanced atomic layer deposition (PEALD) chamber.

[0013] In one embodiment, the plasma chamber 120 may be coupled to a power supply architecture. For example, the power supply architecture may include one or more power sources 1321-132. n In the illustrated embodiment, multiple power sources 132 are shown. However, it should be understood that in some embodiments, a single power source 132 may be used. In one embodiment, the power source 132 may include any type of power source. For example, the power source 132 may be an RF power source, a microwave power source, a direct current (DC) power source, a pulsed DC power source, or the like, or any combination of these power source types.

[0014] In one embodiment, the power supply 132 may be coupled to the cathode 122 through an impedance matching network 130. The impedance matching network 130 changes the impedance of the power delivery architecture to match a load within the chamber 120. Due to changes in process conditions (e.g., gas flow rates, pressure, temperature, etc.), the impedance of the load may vary. Thus, the impedance matching network 130 is used to match the varying impedance to provide an efficient power delivery within the chamber (i.e., with no or minimal reflected power).

[0015] In one embodiment, the sensors 151 and 152 may be provided on either side of the impedance matching network 130. For example, the sensors 1511-151 n 151 may be upstream of the impedance matching network 130 and the sensor 152 may be downstream of the impedance matching network 130. The "upstream" side may refer to the input side of the matching network 130 and the "downstream" side may refer to the output side of the matching network 130. As shown, multiple sensors 1511-151 may be connected to the impedance matching network 130. nis provided upstream of the impedance matching network 130. The number of sensors 151 may be equal to the number of power sources 132. That is, each power source 132 may have its own dedicated sensor 151. The downstream side of the impedance matching network 130 may have a single sensor 152. However, it should be understood that if there is more than one output from the matching network 130, there may be additional sensors 152. For example, if there are two outputs (e.g., for a center of the chamber 120 and an end of the chamber 120), there may be two sensors 152.

[0016] If there are multiple sensors 151, 1ーn can be fabricated on a single PCB, i.e., a single module can contain multiple sensors. Generally, the embodiments described herein include electrical shielding techniques that limit cross-coupling between sensors on a single PCB.

[0017] In FIG. 1, the sensors 151 and 152 are generally shown as blocks. However, it should be understood that the sensors 151 and 152 may be similar to any of the sensor architectures described in more detail below. For example, each sensor 151 and / or 152 may be a transmission line voltage and transmission line current (i.e., V / I) sensor. The transmission line voltage may be detected by an embedded voltage ring, and the transmission line current may be detected by a current loop. In a particular embodiment, the sensor includes an aperture through which a conductive device (e.g., an RF cable) having a concentric ring of electrically insulating material is threaded. Features on the sensor can pick up the current and voltage passing along the transmission line. For example, the current loop picks up the current, and the voltage ring detects the voltage.

[0018] In one embodiment, the sensors 151 and 152 may be communicatively coupled to the processing power control module 134. For example, in FIG. 1, an RF processing power control module 134 may be provided. However, it should be understood that the processing module may be a microwave processing power control module 134, a DC processing power control module, etc., depending on the type of power source 132 included in the tool 100. In one embodiment, the sensors 151 and 152 provide voltage and / or current to the processing power control module. In one embodiment, the processing power control module 134 may have external connections for various physical layers and protocols, such as standard industrial connections such as Ethernet (ENET) and EtherCAT.

[0019] In one embodiment, the processing power control module 134 may be coupled to the impedance matching network by an analog / digital link. The analog / digital link may enable the processing power control module 134 to send a control signal to the impedance matching network 130. For example, the control signal may be used to adjust the capacitance of a variable capacitor in the impedance matching network 130. Additionally, the processing power control module 134 may be coupled to the power source 132 by an analog / digital link. Thus, the processing power control module 134 is capable of coordinated impedance adjustment.

[0020] 2, a top view of a sensor 250 is shown, according to an embodiment. As shown, the sensor 250 is fabricated on a PCB 253. The sensor 250 may include a current loop 254 and a voltage ring 265 within the current loop 254. The current loop 254 and the voltage ring 265 may pass through the PCB 253 and surround an aperture 260.

[0021] In one embodiment, the current loop 254 includes an inner via 255 B and outer via 255 AThe vias 255 may be coupled to each other by a trace 256 on the top side of the PCB 253 and by a trace 257 on the bottom side of the PCB 253. In the illustrated embodiment, the current loop 254 includes a pair of windings around an aperture 260.

[0022] In one embodiment, the voltage ring 265 may include an inner conductive ring 266 and an outer conductive ring 268. An insulating ring 267 may be provided between the inner ring 266 and the outer ring 268. The inner ring 266 may be a voltage pick-up surface and the outer ring 268 may be grounded. In one embodiment, the inner ring 266 may define an outer periphery of the aperture 260.

[0023] In one embodiment, the sensor 250 may further include a guard ring 270 that surrounds the outer periphery of the current loop 254. In one embodiment, the guard ring 270 may be grounded. The guard ring 270 may include vias (not shown) that connect the guard ring 270 to a ring on the bottom side of the PCB 253 of similar size and shape. Thus, an electrical shielding barrier is provided around the pickup components of the sensor 250. This may improve sensor performance.

[0024] In one embodiment, the voltage ring 265 may be coupled to a pick-up circuit 281 on the PCB 253. The pick-up circuit 281 in FIG. 2 is shown diagrammatically as a dashed box. However, it should be understood that the pick-up circuit 281 may include features such as filters and amplifiers. In one embodiment, a pad 283 is provided. The pad 283 may be suitable for attachment of a connector (not shown) to feed back voltage information to a processing module (e.g., the processing module described in more detail above).

[0025] In one embodiment, the current loop 254 may be coupled to a pick-up circuit 282 on the PCB 253. The pick-up circuit 282 in FIG. 2 is shown diagrammatically as a dashed box. However, it should be understood that the pick-up circuit 282 may include features such as filters and amplifiers. In one embodiment, a pad 284 is provided. The pad 284 may be suitable for attachment of a connector (not shown) to feed back the current information to a processing module (e.g., a processing module as described in more detail above).

[0026] In one embodiment, the pick-up circuit 281 is electrically isolated from the pick-up circuit 282. The two sets of pick-up circuits 281 and 282 allow for reduced mutual coupling between the two circuits. Thus, the performance of the sensor 250 can be improved. In one embodiment, the electrical isolation can be achieved by a conductive strip 285 provided between the two sets of pick-up circuits 281 and 282. In one embodiment, the conductive strip 285 can be grounded. In some embodiments, the conductive strip 285 is electrically coupled to the guard ring 270. The conductive strip 285 can be provided on the top surface of the PCB 253. In other embodiments, vias can be provided below the strip 285 to extend the electrical isolation through the thickness of the PCB 253.

[0027] 3, a schematic diagram of a transmission line 361 between a power source 332 and a system load 333 is shown, according to an embodiment. In an embodiment, the power source 332 may be similar to any of the power sources 132 described in more detail above. For example, in some embodiments, the power source 332 may be an RF power source. In an embodiment, the load 333 may be the load of a plasma processing chamber. For example, a cathode may be coupled to a processing gas in a plasma chamber. The chamber conditions may determine the load of the transmission line 361. That is, changes in pressure, temperature, gas flow rate, etc. may result in changes in the load 333 of the transmission line 361. An impedance matching network (not shown) matches the impedance of the transmission line 361 to the impedance of the load 333 to provide efficient power delivery.

[0028] In an embodiment, the transmission line 361 may include a transmission line sensor 340. The transmission line sensor 340 may be substantially similar to the sensor 250 described in more detail above. For example, the transmission line sensor 340 may have a magnetic field coupling component 351 and a capacitive coupling component 352. The magnetic field coupling component 351 may be a current loop and the capacitive coupling component 352 may be a voltage ring as described in more detail above. The magnetic field coupling component 351 couples the measured current I m , and the capacitive coupling component 352 provides the measured voltage V m In an embodiment, the measured current I m is the incident current I i and reflected current I r and a measured voltage V m is the incident voltage V i and reflected voltage V r The measured current I m and the measured voltage V m may be transmitted to a power processing module (not shown). The power processing module may be communicatively coupled to the impedance matching network. Thus, the power processing module may use the measured voltage V m and the measured current I m may be used.

[0029] 4, a process flow diagram of a process 480 for tuning the impedance of a semiconductor processing tool, such as a plasma processing tool, according to an embodiment is shown. In an embodiment, the process 480 may be performed on a power processing module, such as a process power control module as described in more detail above. The process 480 may result in identifying the impedance of a load (e.g., a plasma load) and is configured to set the positioning of a first variable capacitor and a second variable capacitor in an impedance matching network to match the impedance of a transmission line to the impedance of the load.

[0030] In an embodiment, process 480 begins with operation 481, which includes measuring the voltage and current on the transmission line. In an embodiment, the measured voltage and measured current may include both incident and reflected portions. For example, the measured voltage may be the reflected voltage (V r ) and incident voltage (V i Similarly, the measured current may include the reflected current (I r ) and the incident current (I i ).

[0031] The measured current and the measured voltage may be detected by a sensor, such as sensor 250, described in more detail above. For example, the one or more sensors may include a current loop and a voltage ring. In an embodiment, the sensor is disposed along a transmission line between the power source and the load (e.g., a plasma load). In some embodiments, the one or more sensors are disposed before an impedance matching network, after an impedance matching network, and / or before and after an impedance matching network. Although described herein as a single sensor, it should be understood that multiple sensors may be used in accordance with various embodiments described herein.

[0032] In an embodiment, process 480 may continue with operation 482. Operation 482 includes converting the analog voltage and current signals to digital voltage and current signals. The analog to digital conversion may be performed in a power processing module (e.g., similar to the RF processing power control module described above). For example, the conversion may be performed in an analog-to-digital converter (ADC), or the like.

[0033] In an embodiment, process 480 may continue to operation 483. Operation 483 includes calculating a u-vector having three elements from the digital voltage signal and the digital current signal. In an embodiment, the three elements of the u-vector may be calculated using Equations 1-3. TIFF2025515003000002.tif41170

[0034] In an embodiment, the process 480 may continue to operation 484. Operation 484 includes calculating a C1 position at the real component of the u-vector. The C1 position is a position of the first variable capacitor in the impedance matching network. Although referred to as having a "position", it should be understood that the first variable capacitor may be a solid capacitor and no mechanical positioning may be used to set the capacitance of the first variable capacitor. In an embodiment, the C1 position may be calculated using Equation 4. TIFF2025515003000003.tif6170

[0035] In Equation 4, α is the gain value, is the real-valued component of the u-vector, d is a second vector that provides a linear combination of the u-vector via a dot product, and the angular rotation component, TIFF2025515003000005.tif5170u-vector replacement. In an embodiment, α takes a value corresponding to the reactance range of the first variable capacitor.

[0036] In an embodiment, the process 480 may continue to operation 485. Operation 485 includes calculating a C2 position at the imaginary component of the u-vector. The C2 position is the position of the second variable capacitor in the impedance matching network. Although referred to as having a "position", it should be understood that the second variable capacitor may be a solid capacitor and may not require mechanical positioning to set the capacitance of the second variable capacitor. In an embodiment, the C2 position may be calculated using Equation 5. TIFF2025515003000006.tif6170

[0037] In Equation 4, β is the gain value, is the imaginary-valued component of the u-vector, d is a second vector that provides a linear combination of the u-vector via a dot product, and the angular rotation component, TIFF2025515003000008.tif5170u-vector replacement. In an embodiment, β takes a value corresponding to the reactance range of the second variable capacitor. In general, TIFF2025515003000009.tif7170 is the ratio of C1 range to C2 range. In an embodiment, the elements of u are minimized by proper positioning of C1 and C2, resulting in a tuned condition for optimal power transfer from input to output as any numerator term for u→0.

[0038] It should be appreciated that vectors u of up to three elements result in vector fields with non-overlapping quadrant representations, optimizing the transmission line parameters for optimal power transfer from the input to the output of the impedance tuning device. Moreover, the computational burden of such an approach is significantly lower than other tuning algorithms (such as heuristic search algorithms or model-based algorithms). Thus, the embodiments described herein allow for computation and operation in real-time control systems. Moreover, such embodiments are easily scalable and are not limited to a single architecture. For example, there are no limitations on the topology or variants of the impedance matching network. Furthermore, there is no need for gain scheduling. Instead, the control gains are derived from the reactance of the control surface. It should be appreciated that in yet another embodiment, the type of impedance matching is not limited. Mechanical or solid-state variable capacitors can be used in the impedance matching network according to various embodiments.

[0039] Referring now to FIG. 5, a block diagram of an exemplary computer system 500 of a processing tool is shown according to an embodiment. In one embodiment, the computer system 500 is coupled to the processing tool and controls processing within the processing tool. The computer system 500 may be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, or the Internet. The computer system 500 may operate in the role of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The computer system 500 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web appliance, a server, a network router, switch, or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify operations to be performed by that machine. Additionally, although only a single machine is shown as computer system 500, the term "machine" should further be interpreted to include any collection of machines (e.g., computers) that individually or in concert execute a set (or sets) of instructions to perform any one or more of the methodologies described herein.

[0040] The computer system 500 may include a computer program product, or software 522, having a non-transitory machine-readable medium having instructions stored thereon that may be used to program the computer system 500 (or other electronic devices) to perform processes according to embodiments. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (in the form of electrical, optical, acoustic, or other propagated signals (e.g., infrared signals, digital signals, etc.)), etc.

[0041] In one embodiment, computer system 500 includes a system processor 502, a main memory 504 (e.g., read only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), a static memory 506 (e.g., flash memory, static random access memory (SRAM), etc.), and a secondary memory 518 (e.g., a data storage device), which communicate with each other via a bus 530.

[0042] The system processor 502 represents one or more general-purpose processing devices, such as a microsystem processor or a central processing unit. More specifically, the system processor may be a complex instruction set computing (CISC) microsystem processor, a reduced instruction set computing (RISC) microsystem processor, a very long instruction word (VLIW) microsystem processor, a system processor that executes other instruction sets, or a system processor that executes a combination of instruction sets. The system processor 502 may also be one or more special-purpose processing devices, such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal system processor (DSP), a network system processor, etc. The system processor 502 is configured to execute processing logic 526 for performing the operations described herein.

[0043] The computer system 500 may further include a system network interface device 508 for communicating with other devices or machines. The computer system 500 may further include a video display unit 510 (e.g., a liquid crystal display (LCD), a light emitting diode display (LED), or a cathode ray tube (CRT)), an alphanumeric input device 512 (e.g., a keyboard), a cursor control device 514 (e.g., a mouse), and a signal generating device 516 (e.g., a speaker).

[0044] The secondary memory 518 may include a machine-accessible storage medium 532 (or, more specifically, a computer-readable storage medium) having stored thereon one or more sets of instructions (e.g., software 522) that embody any one or more of the methods or functions described herein. The software 522 may also reside, completely or at least partially, within the main memory 504 and / or the system processor 502 while being executed by the computer system 500, and the main memory 504 and the system processor 502 may also constitute machine-readable storage media. The software 522 may further be transmitted and received over the network 520 via the system network interface device 508. In one embodiment, the network interface device 508 may operate using RF, optical, acoustic, or inductive coupling.

[0045] While the illustrated embodiment shows the machine-accessible storage medium 532 as a single medium, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. Furthermore, the term "machine-readable storage medium" should be taken to include any medium that is capable of storing or encoding a set of instructions that are executed by a machine and that cause the machine to perform any of one or more of the methods. Thus, the term "machine-readable storage medium" should be taken to include, but is not limited to, solid-state memories, optical media, and magnetic media.

[0046] In the foregoing specification, certain exemplary embodiments have been described. It will be apparent that various modifications may be made thereto without departing from the scope of the following claims. The specification and drawings are therefore to be regarded in an illustrative rather than a restrictive sense.

Claims

1. 1. A method of impedance tuning in a semiconductor processing tool, comprising: Measuring the voltage and current on the transmission line; converting the analog voltage and current signals into digital voltage and current signals; calculating a u-vector from the digital voltage signals and the digital current signals; Calculating a C1 position of a first capacitor with the real component of the u-vector; Calculating the C2 position of a second capacitor with the imaginary component of the u-vector; The method includes:

2. The method of claim 1 , wherein the u-vector is a three-element vector.

3. The method of claim 2 , wherein the three elements of the u-vector result in an orientation in impedance tuning space that matches an output load condition of the semiconductor processing tool.

4. The method of claim 1 , wherein the voltage comprises an incident voltage and a reflected voltage, and the current comprises an incident current and a reflected current.

5. The method of claim 1, wherein the positioning of C1 and C2 minimizes an element of the u-vector and drives the u-vector towards zero.

6. The method of claim 5, wherein the u-vector being 0 is the tool's tuned state.

7. The method of claim 1 , wherein calculating the C1 and C2 positions comprises using a dot product of the u-vector and d-vector.

8. The method of claim 7 , wherein the d-vector includes an angular rotation component.

9. The method of claim 1 , wherein the first capacitor and the second capacitor are in a matching network.

10. The method of claim 1 , wherein the semiconductor processing tool is a plasma processing tool.

11. 2. The method of claim 1, wherein the semiconductor processing tool comprises a power supply, a matching network, and a cathode, and sensors are provided across the matching network for measuring the voltage and the current in the transmission line.

12. 1. A semiconductor processing tool comprising: power supply, an impedance matching network comprising a first capacitor and a second capacitor; Cathode, A power processing module, a sensor for measuring values ​​including incident voltage, incident current, reflected voltage, and reflected current, the measured values ​​being used by the power processing module to adjust the impedance of the impedance matching network; 13. A semiconductor processing tool comprising:

13. The semiconductor processing tool of claim 12 , wherein the sensor comprises a current loop and a voltage ring.

14. The semiconductor processing tool of claim 12, wherein the measured values ​​are used to form a three element u-vector.

15. 15. The semiconductor processing tool of claim 14, wherein a dot product of the three element u-vector and a d-vector with an angular rotation component is used to find tuned positions of the first capacitor and the second capacitor.

16. The semiconductor processing tool of claim 12 , wherein the semiconductor processing tool is a plasma processing chamber.

17. The semiconductor processing tool of claim 12 , wherein the first capacitor and the second capacitor are variable solid-state capacitors and / or variable mechanical capacitors.

18. 1. A method of impedance tuning in a semiconductor processing tool, comprising: Measuring voltages and currents on a transmission line, the voltages including incident and reflected voltages and the currents including incident and reflected currents; converting the analog voltage and current signals into digital voltage and current signals; calculating a u-vector from the digital voltage signal and the digital current signal, the u-vector being a three-element vector; Calculating a C1 position of a first capacitor with the real component of the u-vector; calculating a C2 position of a second capacitor with an imaginary component of the u-vector, the three elements of the u-vector resulting in an orientation in impedance tuning space that matches an output load condition of the semiconductor processing tool; The method includes:

19. The method of claim 18, wherein calculating the C1 and C2 positions comprises using a dot product of the u-vector and d-vector.

20. The method of claim 19, wherein the d-vector includes an angular rotation component.

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