Pulse Etching Process

Abstract

A method of etching a sample is described. The method includes performing a plasma etch pulse. The plasma etch pulse is performed by directing a gas flow including silicon tetrachloride (SiCl4) and a diluent toward the sample. While directing the gas flow, a bias power is applied to achieve a bias state for a first period of time. A source power is then applied to achieve a source state for a second period of time, after which a recovery state is achieved for a third period of time without applying bias power and source power. The plasma etch pulse is repeated until a desired amount of the sample is etched.

Description

[Technical field]

[0001] Embodiments of the present disclosure generally relate to a method for etching a sample, the method including a pulsed etching process.

[0002] In the semiconductor industry, devices are produced by numerous manufacturing processes to produce smaller and smaller structures. As device geometries shrink, controlling the uniformity and repeatability of device processing becomes increasingly difficult, especially in upstream processing.

[0003] Current plasma etch processes have several chemistries that are used in combination with a pulsed source and bias voltage. These chemistries include chlorine (Cl), hydrogen bromide (HBr), or a combination thereof. These plasma etch processes are typically two-state systems where source power is applied in a first state, followed by bias power in a second state. These systems have been found to produce a V-shaped profile in the sample after the plasma etch is performed. The V-shape that forms in the etched substrate results in undesirable device performance, as the width of the device varies with depth. Therefore, there is a need to improve the plasma etch process to provide a more uniform profile (e.g., a linear profile, etc.) throughout the depth of the sample. Overview

[0004] In some embodiments of the present disclosure, a method of etching a sample is provided. The method can include performing a plasma etch pulse. In some embodiments, the plasma etch pulse can include directing a gas flow including silicon tetrachloride (SiCl4) and a diluent toward the sample, applying a bias power to achieve a bias state for a first period while directing the flow of SiCl4 and the diluent toward the sample, applying a source power to achieve a source state for a second period, and not applying the bias power and the source power to achieve a recovery state for a third period. In some embodiments of the method, the plasma etch pulse can be repeated until a target amount of the sample is etched.

[0005] In another embodiment of the present disclosure, a method of etching a substrate is provided, the substrate comprising a stack of alternating layers of Si and SiGe. The method includes bringing a chamber containing the substrate to a pressure of about 0.1 mT to about 500 mT, bringing the substrate to a temperature of about -50°C to about 300°C, generating a plasma from a gas flow comprising silicon tetrachloride (SiCl4) and a diluent comprising argon (Ar), helium (He) or a mixture thereof, and directing the plasma toward the substrate to etch the stack of alternating layers of Si and SiGe on the substrate.

[0006] Yet another embodiment of the present disclosure provides a method of etching a sample, comprising performing a plasma etch pulse and repeating the plasma etch pulse until a target amount of the sample is etched, the performing of the plasma etch pulse in the method including applying a bias power to achieve a bias state for a first period of time, applying a source power to achieve a source state for a second period of time, and not applying the bias power or the source power to achieve a recovery state for a third period of time while directing a flow of gas and diluent toward the sample. [Brief description of the drawings]

[0007] The present disclosure is illustrated by way of example and not limitation in the accompanying drawings, in which like references indicate like elements. It should be noted that different references to "embodiments" in the present disclosure do not necessarily refer to the same embodiment, but that such references refer to at least one. [Figure 1] 1 illustrates a cross-sectional view of one embodiment of a processing chamber. [Figure 2A] 1 illustrates a cross-sectional view of one embodiment of multiple layers of a sample. [Figure 2B] FIG. 1 illustrates a cross-sectional view of one embodiment of multiple layers of a sample that has been etched such that the sample has a U-shaped profile. [Figure 3A] 1 shows a sample with multiple layers to be etched. [Figure 3B] 3B illustrates the sample of FIG. 3A after being etched according to an embodiment of the present disclosure. [Figure 4A] The sample of FIG. 3B is shown after further deposition of layers and prior to etching. [Figure 4B] 4B illustrates the sample of FIG. 4A after being etched according to an embodiment of the present disclosure. [Diagram 5] 1 is a flow chart illustrating a method for etching a sample according to an embodiment of the present disclosure. [Figure 6] 1 illustrates a plasma etch pulse according to one embodiment of the present disclosure. Detailed Description

[0008] In an embodiment disclosed herein, a method of etching a sample is described. The method of etching a sample includes performing a plasma etch pulse, which includes directing a gas flow containing silicon tetrachloride (SiCl4) and a diluent at the sample. To improve the profile of the sample, SiCl4 can be used in combination with a three-step plasma etch pulse process. It has been found that the use of SiCl4 in combination with the disclosed three-step plasma etch pulse reduces the variation in trench width across the trench depth of the etched sample (i.e., substrate) compared to a conventional plasma etch process using chlorine (Cl2), hydrogen bromide (HBr), and / or nitrogen (N2).

[0009] The plasma etch process of the present disclosure may use a three-state pulsing scheme. In the three-state pulsing scheme, a first state may be a bias state where bias power is applied. The first state lasts for a first period of time. In some embodiments, the bias power may have a power of about 100 W to about 5000 W and a bias frequency of about 400 kHz to about 60 MHz may be applied. A second state of the pulsing scheme is a source state, where source power may be applied for a second period of time where no bias power is applied. In embodiments, the source power may be about 100 W to about 5000 W. A third state may be a recovery state where neither bias power nor source power is applied for a third period of time. During etching, multiple plasma etch pulses may be applied until a target etch depth is reached.

[0010] Conventional plasma etch processes use a two-state pulse scheme where source power is applied before bias power is applied. It has been found that applying bias power before source power, as performed in the embodiments herein, is advantageous for generating a capacitively coupled plasma. It has also been found that the bias state followed by a source state where only source power is applied allows for mask preservation of the etch mask on the substrate due to the gas chemistry of SiCl4 with Ar and He and the source power depositing a protective layer on the sample. The protective layer helps preserve the etch mask (which may be a hard mask, for example) on the sample and enhances the selectivity between silicon and the etch mask. It has also been found that when the source power is turned off, the electron density and electron temperature drop rapidly. Thus, by introducing a recovery state after the source state, when the plasma etch pulse is repeated, the electron temperature of the next iteration of the first state will be lower than that of the second state. The inventors have found that this drop in electron temperature correlates with a drop in ion temperature, which improves directional control during etching. Thus, in the absence of a third state in the plasma etch pulse, the plasma density and electron temperature remain high after the application of source power. Higher electron temperatures also lead to higher ion temperatures. Higher ion temperatures result in more random motion of ions in the bulk plasma, leading to a wider angular distribution and higher variability in the etch profile. Thus, a three-state etch pulse, including first a bias state, then a source state, and then a recovery state, was found to improve directional control of the etching of samples, especially samples containing alternating stacks of Si and SiGe layers when used with SiCl4 chemistry.

[0011] Thus, embodiments of the etching method according to the present disclosure allow for more directional etching in the first state, i.e., application of bias power, at least in part because the plasma is cooled in the third state before the next pulse.

[0012] Disclosed herein are embodiments of a method of etching a sample, including performing a plasma etch pulse and repeating the plasma etch pulse until a target amount of the sample is etched. The plasma etch pulse can include directing a gas flow including SiCl4 and a diluent at the sample, applying a bias power to achieve a bias state for a first period while directing the flow of SiCl4 and a diluent at the sample, followed by applying a source power to achieve a source state for a second period, followed by a recovery state for a third period without applying bias power and source power. In some embodiments, the source power is not applied during the bias state, and the bias power is not applied during the source state.

[0013] In some embodiments, the bias power may be from about 100 watts (W) to about 5,000 watts (W), from about 200 W to about 2,000 W, from about 300 W to about 1,500 W, from about 500 W to about 1,250 W, or from about 600 W to about 1,000 W.

[0014] Some embodiments are described herein with reference to a sample having alternating silicon (Si) and silicon germanium (SiGe) layers. The sample may include a gate-all-around transistor, which may be etched using methods according to the disclosed embodiments. The methods described herein may also be beneficially used to etch many other types of substrates, such as substrates having Si and / or SiGe layers.

[0015] Referring now to the drawings, FIG. 1 is a cross-sectional view of a process chamber 100 (e.g., a semiconductor processing chamber) having one or more chamber components according to an embodiment of the present disclosure. The process chamber 100 can be used for processes in which a corrosive plasma environment and / or corrosive chemicals are provided. For example, the process chamber 100 can be a chamber for a plasma etch reactor (also called a plasma etcher). Examples of chamber components that may be exposed to plasma in the process chamber 100 include a substrate support assembly 148, an electrostatic chuck (ESC), a ring (e.g., a process kit ring or a single ring), chamber walls, a base, a showerhead 130, a gas distribution plate, a liner, a liner kit, a shield, a plasma screen, a flow equalizer, a cooling base, a chamber viewport, a chamber lid, a nozzle, a process kit ring, etc.

[0016] In one embodiment, the processing chamber 100 includes a chamber body 102 and a showerhead 130 that enclose an interior volume 106. The showerhead 130 may or may not include a gas distribution plate. For example, the showerhead may be a multi-piece showerhead including a showerhead base and a showerhead gas distribution plate bonded to the showerhead base. Alternatively, the showerhead 130 may be replaced by a lid and nozzle in some embodiments, and by multiple pie-shaped showerhead compartments and plasma generating units in other embodiments. The chamber body 102 may be fabricated from aluminum, stainless steel, or other suitable materials. The chamber body 102 generally includes a sidewall 108 and a bottom 110. Any of the showerhead 130 (or lid and / or nozzle), sidewall 108, and / or bottom 110 may include a multi-layer plasma-resistant coating.

[0017] The outer liner 116 may be disposed adjacent the sidewall 108 and may protect the chamber body 102. The outer liner 116 may be a halogen-containing gas resistant material, such as Al2O3 or Y2O3. In some embodiments, the outer liner 116 may be coated with a multi-layer plasma resistant ceramic coating.

[0018] An exhaust port 126 may be defined in the chamber body 102 and couple the interior volume 106 to a pumping system 128. The pumping system 128 may include one or more pumps and a throttle valve used to evacuate and regulate the pressure of the interior volume 10 of the processing chamber 100.

[0019] The showerhead 130 can be supported on the sidewall 108 of the chamber body 102 and / or on the top of the chamber body. The showerhead 130 (or lid) can be opened to make the interior volume 106 of the processing chamber 100 accessible and can be closed to seal the processing chamber 100. A gas panel 158 can be coupled to the processing chamber 100 and provide process gases and / or carrier gases to the interior volume 106 via the showerhead 130 or the lid and nozzles. Examples of process gases that can be supplied by the gas panel 158 and used to process substrates / samples in the processing chamber 100 include silicon-containing gases such as silicon tetrachloride (SiCl4). Examples of carrier gases (also referred to herein as diluents) include N2, He, Ar, and other gases that are inert to the process gases (e.g., non-reactive gases). The showerhead 130 includes a number of gas supply holes 132 throughout the showerhead 130. The showerhead 130 can be made of or include aluminum, anodized aluminum, an aluminum alloy (e.g., Al6061), or an anodized aluminum alloy. In some embodiments, the showerhead includes a gas distribution plate (GDP) bonded to the showerhead. The GDP can be, for example, Si or SiC. Additionally, the GDP can include a number of holes that align with the holes in the showerhead.

[0020] The substrate support assembly 148 is disposed within the interior volume 106 of the processing chamber 100 below the showerhead 130. The substrate support assembly 148 holds a substrate 144 (e.g., a wafer) during processing. The substrate support assembly 148 may include an electrostatic chuck that secures the substrate 144 during processing, a metal cooling plate bonded to the electrostatic chuck, and / or one or more additional components. An inner liner may cover the periphery of the substrate support assembly 148. The inner liner may be a halogen-containing gas resistant material such as Al2O3 or Y2O3. In some embodiments, the substrate support assembly, a portion of the substrate support assembly, and / or the inner liner may be coated with a metal layer and a barrier layer.

[0021] The process chamber 100 may be an etch chamber configured to perform the pulse etch processes described herein. In an embodiment, the pulse etch process is performed to etch one or more layers disposed on a substrate 144. For example, the substrate 144 may be a semiconductor wafer, a glass plate, a SiGe wafer, or other type of substrate. In one embodiment, the one or more layers disposed on the substrate 144 include a stack of alternating layers of Si and Ge.

[0022] FIG. 2A illustrates a cross-sectional view of an article 200 including a substrate 206 having an alternating stack of silicon (Si) and silicon germanium (SiGe) layers. In one embodiment, article 200 corresponds to substrate 144 of FIG. 1. Substrate 206 includes Si layers 260, 240, 220 and SiGe layers 250, 230, 210 stacked thereon in stack 290. In some embodiments, the Si and SiGe layers may be in the form of nanosheets (e.g., layers having a thickness in nm). In one embodiment, the Si layers may be 0% to 200% thicker than the SiGe layers. In one embodiment, the Si layers are about 20% thicker than the SiGe layers. In one embodiment, the thickness of all the Si layers is about the same. The thickness of all the SiGe layers may be about the same, which may be different from the thickness of the Si layers. Alternatively, the thicknesses of the different Si layers may be different and / or the thicknesses of the different SiGe layers may be different. In other embodiments, the thicknesses of the Si and SiGe layers may be approximately the same as each other.

[0023] A patterned mask 280 (also called an etch mask) may cover the top layer 260 of the stack 290. The patterned mask 280 may be a soft mask or a hard mask. Possible hard masks include polysilicon hard masks and metal hard masks such as tungsten hard masks and titanium nitride hard masks. The patterned mask 280 includes open areas 270 that expose the underlying layers to etching chemicals during the etching process. Additionally, the patterned mask 280 includes cover areas that protect the underlying layers from the etching chemicals. Areas of the stack 290 that are not protected by the patterned mask 280 under the open areas 270 can undergo the etching process.

[0024] Article 200 can be etched through patterned mask 280 to form cavities or trenches approximately similar in shape to the openings in patterned mask 280. The etchant will also etch patterned mask 280, typically at an etch rate.

[0025] 2B shows a cross-sectional view of an article 204 including a substrate 206 having a stack of alternating Si layers 260, 240, 220 and SiGe layers 250, 230, 210 that has been etched according to embodiments of the present disclosure, particularly the method described in FIG. 5. In this process, a cavity 400 has been etched into the Si and SiGe layers. In one embodiment, the cavity 400 has a tapered cross-sectional shape with a U-shaped profile, with the bottom of the cavity being slightly narrower than the top of the cavity. In particular, the sidewalls of the trench or hole formed from the etching process described in the embodiments herein are nearly vertical, in contrast to sidewalls produced by conventional etching processes.

[0026] Figure 3A shows a sample having multiple layers to be etched and may correspond to an embodiment of a perspective view of article 204. Figure 3B shows the sample of Figure 3A after being etched with a first etching process according to an embodiment of the present disclosure.

[0027] Figure 4A shows the sample of Figure 3B after further deposition of layers and prior to a second etching process, and Figure 4B shows the sample of Figure 4A after etching in a second etching process according to an embodiment of the present disclosure.

[0028] FIG. 3A illustrates an article 300, such as a gate-all-around transistor. The article 300 includes a stack of alternating Si layers 310, 330, 350, 370 and SiGe layers 320, 340, 360. The layers of the article 300 may be stacked on a substrate 380, which may be formed of SiGe, Si, glass, or other materials. In an embodiment, the Si layers 310, 330, 350, 370 and the SiGe layers 320, 340, 360 may be in the form of nanosheets. In an embodiment, the Si layers may be 0% to 200% thicker than the SiGe layers. In an embodiment, the Si layers may be about 20% thicker than the SiGe layers. In an embodiment, the thickness of all the Si layers is approximately the same. Also, the thickness of all the SiGe layers is approximately the same, which may be different from the thickness of the Si. Alternatively, the thicknesses of the different Si layers may be different and / or the thicknesses of the different SiGe layers may be different. In other embodiments, the thickness of the Si layer and the SiGe layer may be approximately the same. The article 300 of FIG. 3A may be etched according to the method 500 of FIG. 5 after a pattern mask (not shown) is placed on the top layer (such as the Si layer 310 shown). FIG. 3B shows the article 300 after it has been etched according to the method 500 of FIG. 5. As can be seen in FIG. 3B, the Si layers 310, 330, 350, 370 and the SiGe layers 320, 340, 360 are etched to form a plurality of spaces (e.g., trenches) 390. A single space 390 may be etched, or multiple spaces may be etched.

[0029] In FIG. 4A, an article 400, such as a gate-all-around transistor, is shown according to an embodiment of the present disclosure. The article 400 can include a patterned mask 414 (e.g., a hard mask) and spacers 412. The spacers 412 can be approximately orthogonal to a trench 490 (e.g., corresponding to trench 390 in FIG. 3B). The patterned mask 414 can be along the entire length of the spacer 412 or along a portion of the length of the spacer 412. The spacers 412 can be offset from one another by gaps 492. Although only two spacers are shown, a device under fabrication will typically include many such spacers. The spacers 412 can surround the Si layers 410, 430, 450, 470 and the SiGe layers 420, 440, 460. The article 400 can also include a shallow trench isolation 416 formed in or on a substrate 480, which can be formed of SiGe, Si, glass, or other materials. In an embodiment, the article 400 can be etched according to the method 500 of Figure 5. Figure 4B shows the article 400 etched according to an embodiment described herein. In Figure 4B, the Si layers 410, 430, 450, 470 and the SiGe layers 420, 440, 460 have been etched to remove excess layers outside the spacer 412. In this way, the Si and SiGe layers are approximately flush with the spacer 412 and there are no Si and / or SiGe layers outside the spacer 412.

[0030] 5 is a flow chart depicting a method 500 of etching a sample and / or article according to an embodiment of the present disclosure. In the method 500, in block 501, the sample and / or article is inserted into an etching chamber. The etching chamber may be a plasma etching chamber. In block 502, the chamber is brought to a target temperature and pressure (e.g., using one or more heating elements and / or pumps). The pressure of the chamber may be about 0.1 mT to about 500 mT, about 1 mT to about 400 mT, about 5 mT to about 300 mT, about 10 mT to about 200 mT, about 25 mT to about 100 mT, or about 1 mT to about 100 mT, or any subrange or value therein. The chamber temperature may be from about -50°C to about 300°C, from about -25°C to about 250°C, from about 0°C to about 120°C, from about 25°C to about 100°C, or from about 50°C to about 75°C, or any subrange or value described herein. In one embodiment, the target substrate temperature is at least 40°C. It has been found that temperatures below 40°C may increase the isodensity etch rate load.

[0031] Once the target temperature and pressure are reached, the plasma etch process can proceed by forming a plasma including SiCl4 and one or more additional gases (e.g., carrier gas or diluent). The plasma etch process can be a pulsed plasma etch process. In one embodiment, a plasma etch pulse / cycle is performed on the sample and / or article at block 503. At block 504, a plasma etch pulse is performed by directing a gas flow including SiCl4 and diluent at the sample and / or article. The total gas supply flow rate of SiCl4 and diluent is about 50 sccm to about 2000 sccm, about 100 sccm to about 1500 sccm, about 150 sccm to about 1250 sccm, about 200 sccm to about 1000 sccm, about 250 sccm to about 750 sccm, or any subrange or value therein. The amount of SiCl4 in the total gas feed stream is from about 5 mol% to about 80 mol%, from about 5 mol% to about 70 mol%, from about 5 mol% to about 60 mol%, from about 5 mol% to about 50 mol%, from about 5 mol% to about 40 mol%, from about 10 mol% to about 80 mol%, from about 10 mol% to about 70 mol%, from about 20 mol% to about 70 mol%, from about 20 mol% to about 60 mol%, from about 30 mol% to about 50 mol%, or any subrange or value therein.

[0032] The diluent may include Ar, He, or a combination thereof. Additionally or alternatively, the diluent may include one or more additional inert gases. The amount of Ar in the total gas feed flow may be about 5 mol% to about 15 mol%, about 7.5 mol% to about 12.5 mol%, or about 9 mol% to about 11 mol%, or any subrange or value therein. The amount of He in the total gas feed flow may be about 5 mol% to about 90 mol%, about 10 mol% to about 80 mol%, about 15 mol% to about 75 mol%, about 25 mol% to about 65 mol%, about 30 mol% to about 60 mol%, about 35 mol% to about 55 mol%, or any subrange or value therein.

[0033] In block 506, a bias power is applied to the sample / article to achieve a bias condition for a first period of time. The bias power may be about 10 watts (W) to about 5,000 watts (W), about 200 W to about 2,000 W, about 300 W to about 3,000 W, about 400 W to about 2,500 W, about 500 W to about 2,000 W, about 600 W to about 1,500 W, or about 750 W to about 1,250 W, or any subrange or value herein. A higher bias power results in a straighter profile (e.g., a more vertical trench sidewall profile), a less curvature in the profile, and less selectivity to the pattern mask. The bias power may be a time-averaged power. The bias frequency may be about 400 kHz to about 60 MHz, about 400 kHz to about 40 MHz, about 400 kHz to about 35 MHz, about 400 kHz to about 27 MHz, about 400 kHz to about 20 MHz, or about 800 kHz to about 10 MHz, or any subrange or value described herein. Two example frequencies that can be used may be 13 MHz and 2 MHz. It has been shown that a frequency of 2 MHz may be less selective to the pattern mask than a frequency of 14 MHz. The first period during which bias power is applied may be about 10 μsec (μsec) to about 1 msec (msec), about 30 μsec to about 1 msec, about 50 μsec to about 1 msec, about 70 μsec to about 1 msec, or about 85 μsec to about 1 msec, or any subrange or value described herein. In block 508, the bias power is stopped after the first period has ended.

[0034] After terminating the bias power, in block 510, source power is applied to achieve a source state for a second period. The source power may be about 10 W to about 5000 W, about 200 W to about 2,000 W, about 300 W to about 3,000 W, about 400 W to about 2,500 W, about 500 W to about 2,000 W, about 600 W to about 1,500 W, or about 750 W to about 1,250 W, or any subrange or value herein. The source power may be a time-averaged source power (e.g., source power x duty cycle). The source frequency may be about 10 MHz to about 5 MHz, or about 13 MHz, or any subrange or value herein.

[0035] In some embodiments, the second period of time during which source power is applied may be from about 10 μsec to about 1 ms, from about 30 μsec to about 1 ms, from about 50 μsec to about 1 ms, from about 70 μsec to about 1 ms, or from about 85 μsec to about 1 ms, or any subrange or value described herein.

[0036] In some embodiments, the ratio of the first period to the second period can be about 1:10 to about 10:1, about 1:9 to about 9:1, about 1:8 to about 8:1, about 1:7 to about 7:1, about 1:6 to about 6:1, about 1:5 to about 5:1, about 1:4 to about 4:1, about 1:3 to about 3:1, about 1:2 to about 2:1, or about 1:1, or any subrange or value denoted herein.

[0037] After the second time period in block 510 is completed, the source power is turned off in block 511. Then, no bias power or source power is applied to the chamber and a recovery state is achieved in a third time period in block 512. The third time period may be from about 10 μsec to about 1 msec, from about 50 μsec to about 1 msec, from about 60 μsec to about 1 msec, from about 70 μsec to about 1 msec, from about 80 μsec to about 1 msec, or from about 85 μsec to about 1 msec, or any subrange or value therein.

[0038] In some embodiments, the ratio of the third period to the sum of the first period and the second period is about 1:1 to about 90:1, about 1:1 to about 80:1, about 1:1 to about 70:1, about 1:1 to about 60:1, about 1:1 to about 50:1, about 1:1 to about 40:1, about 1:1 to about 30:1, about 1:1 to about 20:1, about 1:1 to about 10:1, or about 1:1 to about 5:1, or any subrange or value herein. In some embodiments, the third period of the recovery state is longer than either the first period or the second period, thereby allowing for a reduction in electron temperature. A reduction in electron temperature correlates with a reduction in ion temperature, which can improve directional control during etching.

[0039] A three-state etch pulse (505-512) including first a bias state (506, 508), then a source state (510, 511), and then a recovery state (512) has been shown to improve directional control of the etching of a sample, particularly a sample including an alternating stack of Si and SiGe layers when using a SiCl4 chemistry.

[0040] After the third period of time, in block 513, the sample / article may be inspected to see if the target amount has been etched. Alternatively or additionally, it may be determined whether the target amount of the sample / article has been etched based on the time the etching process was run. If the etching process has not been run for the target time (e.g., according to an etch recipe), the target amount of the sample / article may not have been etched. If the target amount of the sample / article has not been etched, the plasma etch pulse process of blocks 504-512 may be repeated. If the target amount of the sample / article has been etched, the sample / article is removed from the etch chamber in block 514.

[0041] The pulsed plasma etch process described in method 500 achieves low plasma density by performing a bias state before the source state and using a long recovery state (e.g., more than 50% of the total pulse time). High plasma density (e.g., as achieved with continuous wave source power) reduces the etch rate due to increased deposition from the feed gas (SiCl4), which is undesirable. However, the low plasma density achieved in the embodiment increases the etch rate, to about 0.1 nm / sec. Additionally, the pulsing scheme described herein produces a highly directional ion flux with low plasma density in the bias state, while the recovery state maintains low plasma density.

[0042] FIG. 6 illustrates a plasma etch pulse cycle according to an embodiment of the present disclosure. In FIG. 6, the plasma etch pulse cycle has three states. In the first state, a bias state 605 is achieved. The bias state 605 can be achieved by block 506 described with reference to FIG. 5. The second state in FIG. 6 is a source state 610. The source state can be achieved by block 510 described with reference to FIG. 5. The third state of the plasma etch pulse is a recovery state 615. The recovery state can be achieved as described in blocks 511 and 512 with reference to FIG. 6. In FIG. 6, the duration of the bias state 605 can be about 2% to about 10%, or about 5% of the plasma etch pulse cycle. The duration of the source state 610 is about 2% to about 10%, or about 5% of the plasma etch pulse cycle, and the duration of the recovery state 615 is about 80% to about 96%, or about 90% of the plasma etch pulse cycle.

[0043] In the above description, numerous specific details are provided, such as examples of specific systems, components, methods, etc., to provide a thorough understanding of some embodiments of the present invention. However, it will be apparent to one of ordinary skill in the art that at least some embodiments of the present invention can be practiced without these specific details. In other instances, well-known components or methods have not been described in detail or have been shown in simple block diagram form in order to avoid unnecessarily obscuring the present invention. Thus, the specific details described are merely examples. A particular implementation may vary from these illustrative details, but still be within the scope of the present invention.

[0044] References throughout this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the term "or" does not mean exclusive "or", but rather inclusive "or". When the term "about" or "approximately" is used herein, this means that the nominal value presented is accurate to within 10%.

[0045] Although the operations of the methods herein are shown and described in a particular order, the order of the operations of each method may be changed such that certain operations are performed in the reverse order, or such that certain operations are performed at least in part concurrently with other operations. In other embodiments, instructions or sub-operations of separate operations may be performed intermittently and / or alternatingly.

[0046] It should be understood that the above description is intended to be illustrative, and not limiting. Many other embodiments will become apparent to those skilled in the art upon reading and understanding the above description. The scope of the present invention should therefore be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. 1. A method for etching a sample, comprising the steps of: Executing a plasma etching pulse, Silicon tetrachloride (SiCl ４ directing a gas flow containing the gas and a diluent toward the sample; SiCl ４ and applying a bias power to achieve a bias condition of a first duration while directing a flow of diluent toward the sample. applying a source power to achieve a source state for a second period; performing a plasma etch pulse including achieving a recovery state for a third period without applying bias power and source power; The method includes repeating the plasma etch pulses until a desired amount of the sample is etched.

2. The method of claim 1 , wherein no source power is applied during the bias state and no bias power is applied during the source state.

3. The method of claim 1 , wherein the bias power is from about 100 W to about 5000 W.

4. The method of claim 1 , wherein the bias frequency is from about 400 kHz to about 60 MHz.

5. The method of claim 1 , wherein the plasma etching pulse is performed at a pressure between about 0.1 mT and about 500 mT.

6. The method of claim 1, wherein the plasma etching pulse is performed at a temperature of about -50°C to about 300°C.

7. The method of claim 1 , wherein the source power is from about 100 W to about 5000 W.

8. The method of claim 1 , wherein the diluent comprises argon (Ar), helium (He), or a mixture thereof.

9. The gas flow comprises SiCl in an amount of about 5 mol % to about 80 mol %. ４ The method of claim 1 , comprising:

10. 9. The method of claim 8, wherein the gas flow comprises Ar in an amount between about 5 mol % and about 15 mol % and He in an amount between about 5 mol % and about 90 mol %.

11. 2. The method of claim 1, wherein the first period of time is from about 10 μsec to about 1 ms, the second period of time is from about 10 μsec to about 1 ms, and the third period of time is from about 10 μsec to about 1 ms.

12. The method of claim 1 , wherein the ratio of the first time period to the second time period is from about 1:10 to about 10:

1.

13. 10. The method of claim 1, wherein the ratio of the third period of time to the sum of the first period of time and the second period of time is from about 1:1 to about 90:

1.

14. The method of claim 1 , wherein the gas flow rate is between about 50 sccm and about 2000 sccm.

15. The method of claim 1 , wherein the portion of the sample etched by the plasma etch pulses comprises multiple alternating layers of silicon and silicon germanium.

16. The method of claim 1 , wherein the plasma etching process creates a U-shaped profile in the sample.

17. 1. A method for etching a substrate comprising a stack of alternating layers of Si and SiGe, comprising: allowing a chamber containing the substrate to reach a pressure of about 0.1 mT to about 500 mT; allowing the substrate to reach a temperature of about -50°C to about 300°C; Silicon tetrachloride (SiCl ４ generating a plasma from a gas flow comprising argon (Ar), helium (He) or a diluent comprising a mixture thereof; A method comprising: directing a plasma at a substrate to etch a stack of alternating layers of Si and SiGe on the substrate.

18. The gas flow comprises SiCl in an amount of about 5 mol % to about 80 mol %. ４ 20. The method of claim 17, comprising:

19. 1. A method for etching a sample, comprising the steps of: Executing a plasma etching pulse, applying a bias power to achieve a bias condition of a first duration while directing a flow of gas and diluent toward the sample; applying a source power to achieve a source state for a second period; performing a plasma etch pulse including achieving a recovery state for a third period without applying bias power and source power; The method includes repeating the plasma etch pulses until a desired amount of the sample is etched.

20. The gas is SiCl ４ 20. The method of claim 19, comprising:

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