Modular quantum chip design with overlapping connections

Abstract

A quantum computing (QC) chip module includes an interposer chip having a footprint. Qubit chip bumps are bonded to the interposer chip and positioned such that the qubit chip extends beyond the footprint of the interposer chip. The interposer chip extends beyond an edge of the qubit chip. A wiring harness is connected to the interposer chip.

Description

[Technical field]

[0001] The present disclosure relates generally to quantum computing, and more particularly to quantum computing chip design. [Background technology]

[0002] Superconducting quantum computing is the implementation of quantum computers in superconducting electronic circuits. Quantum computing studies the application of quantum phenomena for information processing and communication. Various models of quantum computing exist, the most common of which include the concepts of qubits and quantum gates. A qubit is a generalization of a bit that has two possible states, but can be in a quantum superposition of both states. A quantum gate is a generalization of a logic gate, but given the initial state of one or more qubits, describes the transformation that the qubit undergoes after a gate is applied to that qubit. Various components, such as low-noise amplifiers, which can operate in different thermal isolation stages, can be used to communicate with the qubits. Many quantum phenomena, such as superposition and entanglement, have no analogues in the classical computing world and therefore may require special structures, techniques and materials.

[0003] Quantum computing requires a large number of qubits to achieve the potential proposed by those skilled in the art. Currently, most of the existing silicon-based devices are increasingly larger versions of the original smaller devices, e.g., all qubits are fabricated on one chip. Once the qubit count exceeds the order of magnitude of about 1000, it becomes difficult or impossible to fabricate such monolithic devices, both for reasons of the required wafer size and for practical concerns such as tool availability or yield issues. There is therefore interest in modular manufacturing methods, focusing on densely packed chips to facilitate maintaining high-quality bus connections between modules. Summary of the Invention

[0004] According to one embodiment, a quantum computing (QC) chip module includes an interposer chip having a footprint. Qubit chip bumps are bonded to the interposer chip and positioned such that the qubit chip extends beyond the footprint of the interposer chip. The interposer chip extends beyond the edges of the qubit chip, and a wiring harness is connected to the interposer chip. This configuration allows the qubit chips to overhang from the interposer to form a capacitively coupled bus between adjacent qubit chips.

[0005] In one embodiment, the wiring harness includes a superconducting flexible cable. The qubit chips are controlled and read out by electrical signals in the superconducting flexible cable. The use of superconducting cable minimizes heat and electrical signal losses.

[0006] According to one embodiment, a quantum computing (QC) chip module assembly includes a plurality of QC chip modules connected in a row. Each QC chip module includes an interposer chip having a footprint. A qubit chip is bump bonded to the interposer chip and positioned such that the qubit chip extends beyond the footprint of the interposer chip. The interposer chip extends beyond an edge of the qubit chip. A wiring harness is connected to the interposer chip, the wiring harness including a superconducting flexible cable. The qubit chip is controlled and read out by electrical signals in the superconducting flexible cable. The assembly provides improved dimensional accuracy by using the edges of the interposer to position the modules relative to one another.

[0007] In one embodiment, the multiple QC modules include qubit chips, interposer chips, and wiring harnesses arranged in an L-shape configuration, where the L-shape allows for the placement of qubit chips such that they overhang adjacent modules to facilitate capacitively coupled buses between adjacent qubit chips.

[0008] In one embodiment, in each QC module, a wiring harness is attached to two regions of the interposer chip to form a T-shape with the qubit chips disposed on the interposer chip. An increasing amount of qubits can be disposed on the interposer by connecting the wiring harnesses in the two regions of the interposer chip.

[0009] In one embodiment, the gap between the qubit chip and the interposer chip is defined by the final bump height of the bump bonds connecting the qubit chip to the interposer chip and is the same as the gap between the qubit chip and the interposer chip in every module of a multiple QC chip module. Having the "same" plate height provides for more precise configuration of the components of the QC module.

[0010] According to one embodiment, a method of constructing a quantum computing (QC) chip module assembly includes connecting a plurality of QC chip modules connected in a row. Each QC chip module includes an interposer chip having a footprint and a qubit chip bump-bonded to the interposer chip and positioned such that the qubit chip extends beyond the footprint of the interposer chip. The interposer chip extends beyond an edge of the qubit chip. A wiring harness is connected to the interposer chip, the wiring harness including a superconducting flexible cable. The qubit chip is controlled and read out by electrical signals in the superconducting flexible cable. The method allows the qubit chip to overhang an adjacent module and form a capacitive coupling with the adjacent QC module.

[0011] In one embodiment, the method further includes arranging the qubit chip, the interposer chipper chip, and the wiring harness in an L-shape that facilitates placing multiple QC modules together to form a capacitively coupled bus.

[0012] In one embodiment, in each QC module, the wiring harness is attached to two regions of the interposer chip to form a T-shape with the qubit chips disposed on the interposer chip. The T-shape more than doubles the number of qubits that can be connected to the interposer, allowing for larger and denser circuitry.

[0013] In one embodiment, the method further includes defining a gap between the qubit chip and the interposer chip by a final bump height of a bump bond connecting the qubit chip to the interposer chip. The defined gap is the same as the gap between the qubit chip and the interposer chip in every module of the multiple QC modules. This method provides a more uniform, dimensionally accurate configuration.

[0014] These and other features will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.

[0015] The drawings are of exemplary embodiments. They do not depict all embodiments. Other embodiments may be used in addition or instead. Details that may be obvious or unnecessary may be omitted to save space or for a more effective explanation. Some embodiments may be practiced with additional components or steps, or without all the components or steps illustrated, or both. When the same number appears in different drawings, it refers to the same or similar components or steps. [Brief description of the drawings]

[0016] [Figure 1] FIG. 1 is a plan view of a quantum computing module assembly having a substantially L-shaped configuration, consistent with an illustrative embodiment. [Diagram 2] FIG. 1 is a plan view of one quantum computing module and a quantum computing module assembly having a substantially T-shaped configuration, consistent with an illustrative embodiment. [Diagram 3] FIG. 13 illustrates an arrangement of a vertical gap between a cantilevered qubit chip and an adjacent interposer, consistent with an illustrative embodiment. [Figure 4]FIG. 13 illustrates a coupling scheme in which a qubit is coupled to an adjacent qubit on the next qubit chip, consistent with an illustrative embodiment. [Diagram 5] FIG. 13 illustrates two types of rigid backers that may be used to reduce inter-module gaps between one qubit chip and an adjacent interposer, consistent with an illustrative embodiment. [Figure 6] FIG. 13 illustrates a cantilevered gap with a controlled downstop, consistent with an illustrative embodiment. [Figure 7] FIG. 13 illustrates solder ball height tuning through the use of under-bump metallurgy, consistent with an illustrative embodiment. [Figure 8] 1 is a graph of calculated bus length versus capacitance between chips, consistent with an illustrative embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0017] overview In the following detailed description, numerous specific details are set forth as examples to provide a thorough understanding of the relevant teachings. However, it should be understood that the present teachings may be practiced without such details. In other instances, well-known methods, procedures, components or circuits, or combinations thereof, have been described at a relatively high level without detailed descriptions to avoid unnecessarily obscuring aspects of the present teachings. It should be understood that the present disclosure is not limited to the depictions in the drawings, and that there may be fewer or more elements than those shown and described.

[0018] Certain terms are used herein to indicate what may be considered idealized behavior, such as "lossless," "superconductor," or "superconducting," that is not completely ideal, but is intended to be within acceptable tolerances for a given application. For example, some level of loss or tolerance may be acceptable such that the resulting materials and structures may still be referred to by these "idealized" terms.

[0019] FIG. 1 illustrates a plan view 100 of one quantum computing module 101 and a quantum computing module assembly 140 having a substantially L-shaped configuration, consistent with an exemplary embodiment. The quantum computing module 101 includes an interposer 105 with a qubit chip 110 thereon and a wiring harness 120 attached to the interposer 105 by solder bump bonds 115. The qubit chip 110 extends to the right beyond the interposer. The interposer 105 extends substantially vertically from the qubit chip 110. The quantum computing module 101 may be controlled and read out by electrical connections in a flexible cable of the flexible wiring harness 120. In one embodiment, the flexible wiring harness 120 may be a superconducting flexible cable to minimize heat loss and electrical signal loss.

[0020] The quantum computing module assembly 140 includes a plurality of quantum computer modules 101 connected by an arrangement in a row. Although four quantum computing modules 101 are shown in the quantum computing module assembly 140, it should be understood that more than four modules 101 or fewer than four modules 101 can be connected. In this embodiment, an overhanging qubit chip 110 is spaced over the right adjacent interposer. This overhang can be used to form a capacitive coupling bus between adjacent qubit chips. A side view 150 of the assembled module is also shown, showing the qubit chip 110 and flexible wiring harness 120 positioned over the interposer 105 and rigid backer 130, which may have alignment ridges 131. Precision dicing of the interposer 105 and qubit chips 110 along with precise bonding with an accuracy of a few micrometers makes it possible to use the edges of the interposer to position the modules 101 relative to each other and relative to alignment edges 131 built into the rigid backer 130.

[0021] Additional features of the quantum computing modules of the present disclosure are disclosed herein.

[0022] Exemplary embodiments 2 illustrates a top view 200 of one quantum computing module 201 and a quantum computing module assembly 240 having a substantially T-shaped configuration, consistent with an exemplary embodiment. In the example of FIG. 2, flexible wiring harnesses 220 may be connected to two sides of an interposer 205. The arrangement of qubit chips 210 and wiring harnesses 220 as illustrated may provide twice as many electrical connections as compared to the L-shaped module 140 of FIG. 1. The arrangement of solder bumps 215 and rigid backer 230 with ridges 231 is also illustrated in a side view of the assembly.

[0023] FIG. 3 illustrates a quantum computing module assembly 340 arrangement 300 having a vertical gap 325 between a cantilevered qubit chip 310 and an adjacent interposer 305, consistent with an exemplary embodiment. The drawing illustrates a vertical gap 325 between the cantilevered qubit chip 310 and the adjacent right interposer 305R. Solder bumps 315 are used to bond the qubit chip 310 to the interposer chip 305. The bumps 315 may be selected from a variety of configurations including, but in no way limited to, indium, indium alloys such as InSn, lead-based alloys, SnAuCu, and the like, used to bond the qubit chip 310 to the interposer chip 305. The gap 325 between the qubit chip 310 and the interposer chip 305 is defined by the final bump height and is the same as the qubit-interposer gap in any module. Details of the qubit coupling are illustrated with reference to FIG. 4.

[0024] FIG. 4 shows a coupling scheme 400 in which a qubit 409 on a qubit chip 410 of an assembly 401 is coupled to an adjacent qubit on the next qubit chip, consistent with an exemplary embodiment. The qubit 409 is located on the bottom surface of the qubit chip 410, as in other embodiments. A front view 450 of the assembly is also shown. At the right edge, the qubit bus capacitively couples across the gap between the qubit 409 and the adjacent interposer 405 (in the area of ​​oval 425) and capacitively couples upward through superconducting bump 415 to the adjacent qubit on the next qubit chip. An equivalent coupling scheme might use inductive coupling instead of capacitive coupling. The thick black lines indicate superconducting metal traces and pads.

[0025] In one embodiment, the qubit chip 410 and interposer chip 405 as shown in FIG. 4 may have through-silicon vias (TSVs) for mode protection and isolation, and the interposer additionally uses TSVs for signal transmission to a multi-level wiring layer on the back side of the thin interposer chip 405.

[0026] 5 illustrates two types of rigid backers 500 used to reduce the inter-module gap between one qubit chip and an adjacent interposer, consistent with an example embodiment. If the gap (defined by the bump bonds) between the qubit and interposer chips is larger than desired (e.g., if the gap is on the order of 50 microns), a controlled reduction in the gap between the qubit chip and the adjacent interposer may be performed.

[0027] A controlled reduction in the gap is achieved by using a flat rigid backer 530 to hold all the modules. The flat rigid backer 530 results in an inter-module gap 525 (e.g., between one qubit chip 510 with qubits 509 and an adjacent interposer 505) that is the same as the intra-module bump gap. Alternatively, a stepped rigid backer 545 may be used. The stepped rigid backer 545 is stepped by an amount "d". As a result, the inter-module gap 529 using the stepped rigid backer 545 is reduced from the nominal gap by the amount d. For example, with a bump-defined gap of 50 microns and a step height "d" in the backer of 40 microns, the inter-module gap is 10 microns. Note that the stepped backer 545 can be stepped several times to connect multiple such modules, each with a reduced inter-module gap.

[0028] FIG. 6 shows a module assembly 600 having a cantilevered gap 601 with controlled downstops 616, 617 consistent with an exemplary embodiment. The cantilevered gap 629 achieved by using a stepped backer plate 627 effectively reduces the inter-module gap. However, this reduced gap may vary depending on the bump-defined intra-module gap control and machining tolerances in the manufacture of the backer plate 627. To address the gap reduction, an operation is described to form a controlled downstop in the interposer. While the use of downstops using micromachined silicon is known in some fields, the solution of the present invention offers the advantages of simplicity and ease of manufacture. An interposer wafer 605 is fabricated with a controlled volume of solder placed on the under-bump metallurgy region as shown on the left. Circle 615 indicates an under-bump metallization (UBM) film, in this case coated with gold. After reflow, the bumps form chamfered spheres of solder 616, 617 where the bottom of the solder ball flows to the perimeter of the UBM. By adjusting the diameter of select UBM patches or the amount of solder present or both, significantly lower solder areas can be formed to act as standoffs for adjacent modules. In mechanical placement, the interposer 605 is pressed down onto the backer 627 and the qubit chip 610 is lightly pressed down onto the rigid solder downstops 616, 617.

[0029] FIG. 7 illustrates tuning of solder ball height through the use of under-bump metallurgy, consistent with an exemplary embodiment. A variable diameter UBM may be used to tune the gap between the qubit chip and the interposer. A larger UBM area 715 provides a lower solder standoff. The gap 725 between the qubit chip 710 and the adjacent interposer 705 is reduced. The solder area with a significantly lower solder height is relatively incompressible and therefore acts as a mechanical downstop.

[0030] Standoff UBM size may depend on the details, but a simple calculation is that the standoff UBM may be in the range of 400-700 microns in diameter to achieve a height of 5 μm.

[0031] FIG. 8 is a graph of qubit bus length to provide calculated coupling capacitance between chips consistent with an exemplary embodiment. The graph suggests that larger capacitance between chips is likely with increasing numbers of qubits. For example, to achieve 200 fF with a 5 micron gap, circular pads with a diameter of 380 microns are recommended, which is on the verge of practicality. Further optimization (e.g., larger coupling capacitors at the qubits) will be investigated.

[0032] conclusion The description of various embodiments of the present teachings is presented for illustrative purposes, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used in this specification are selected to best explain the principles of the embodiments, practical applications, or technical improvements to the technology found in the market, or to enable other skilled in the art to understand the embodiments disclosed herein.

[0033] While what is considered to be the best mode and / or other embodiments have been described above, it should be understood that various modifications may be made thereto, that the subject matter disclosed herein may be implemented in a variety of forms and embodiments, and that the present teachings may be applied to numerous applications, only a few of which are described herein. It is intended by the following claims to claim any and all applications, modifications, and variations that fall within the true scope of the present teachings.

[0034] The components, acts, steps, features, objects, benefits, and advantages discussed herein are merely exemplary. Neither them nor any description thereof is intended to limit the scope of protection. Although various advantages have been discussed herein, it should be understood that not all embodiments necessarily include all advantages. Unless otherwise stated, all measurements, values, ratings, positions, dimensions, sizes, and other specifications given herein, including those in the following claims, are approximate rather than precise. They are intended to have a reasonable range consistent with the functions to which they relate and those customary in the art to which they relate.

[0035] Numerous other embodiments are contemplated, including embodiments having fewer, additional, or different or combinations of components, steps, features, objects, benefits, and advantages, including embodiments having components and / or steps in a different arrangement and / or order.

[0036] The diagrams in the drawings herein illustrate the architecture, functionality, and operation of possible implementations according to various embodiments of the present disclosure.

[0037] Although the foregoing has been described in connection with exemplary embodiments, the term "exemplary" means merely an example, not best or optimal. Except as stated immediately above, nothing described or illustrated is intended or should be intended to dedicate to the public any component, step, feature, object, benefit, advantage, or equivalent, whether or not recited in the claims.

[0038] The terms and expressions used herein are understood to have ordinary meanings consistent with such terms and terms with respect to their corresponding respective areas of investigation and study, unless a specific meaning is otherwise indicated herein. Relative terms such as first, second, etc. may be used only to distinguish one entity or operation from another, without necessarily requiring or implying any such actual relationship or order between those entities or operations. The terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements may include other elements not expressly listed or inherent to such process, method, article, or apparatus, rather than including only those elements. An element preceded by "a" or "an" does not, without further constraints, preclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element.

[0039] The Abstract of the Disclosure is provided to enable the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features have been grouped together in various embodiments for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

Claims

1. 1. A quantum computing (QC) chip module, comprising: an interposer chip having a footprint; a qubit chip bump-bonded to the interposer chip, the qubit chip positioned to extend beyond the footprint of the interposer chip, the interposer chip extending beyond an edge of the qubit chip; a wiring harness connected to the interposer chip.

2. the wiring harness includes a superconducting flexible cable; 10. The QC chip module of claim 1, wherein the qubit chip is controlled and read out by electrical signals in the superconducting flexible cable.

3. 3. The QC chip module of claim 2, wherein a gap between the qubit chip and the interposer chip is defined by a final bump height of the bump bond connecting the qubit chip to the interposer chip.

4. the qubit chip extends horizontally beyond the interposer; 4. The QC chip module of claim 3, wherein the interposer and the qubit chips extend in a substantially vertical direction.

5. 1. A quantum computing (QC) chip module assembly, comprising: A plurality of QC chip modules connected in a series, each QC chip module comprising: an interposer chip having a footprint; a qubit chip bump-bonded to the interposer chip, the qubit chip positioned to extend beyond the footprint of the interposer chip, the interposer chip extending beyond an edge of the qubit chip; a wiring harness connected to the interposer chip; the wiring harness includes a superconducting flexible cable; A quantum computing (QC) chip module assembly, wherein the qubit chips are controlled and read out by electrical signals in the superconducting flexible cable.

6. 6. The QC chip module assembly of claim 5, wherein the plurality of QC modules have the qubit chips, the interposer chipper chips, and the wiring harnesses arranged in an L-shape.

7. 7. The QC chip module assembly of claim 5 or 6, wherein in each QC chip module, the wiring harness is attached to two regions of the interposer chip to form a T-shape with the qubit chip disposed on the interposer chip.

8. 8. The QC chip module assembly of claim 5, wherein a gap between the qubit chip and the interposer chip is defined by a final bump height of the bump bond connecting the qubit chip to the interposer chip and is the same size as the gap between the qubit chip and the interposer chip in every module of the plurality of QC chip modules.

9. 9. The QC chip module assembly of claim 5, wherein the plurality of QC chip modules are arranged in a tiled configuration to form an air-gapped connection between the qubit chip of a first QC chip module and the interposer chip of an adjacent QC chip module.

10. The QC chip module assembly of claim 5 , wherein the plurality of QC chip modules are disposed on a rigid backer.

11. The QC chip module assembly of claim 10 , wherein the rigid backer includes alignment ridges to facilitate in-plane alignment of the plurality of QC chip modules.

12. 11. The QC chip module assembly of claim 10, wherein the rigid backer includes a step for lifting each subsequently placed QC chip module a fixed height relative to a previously placed module.

13. 11. The QC chip module assembly of claim 10, wherein the interposer chip includes standoffs incorporated therein to maintain a substantially constant gap between the interposer chip of a first QC chip module and the qubit chips of adjacent QC modules of the plurality of QC chip modules.

14. the rigid backer holds all of the plurality of QC modules; 11. The QC chip module assembly of claim 10, wherein the inter-module gap between one qubit chip and an adjacent interposer is the same as the intra-module bump gap.

15. 11. The QC chip module assembly of claim 10, wherein coupling between qubit chips on adjacent QC modules comprises capacitive coupling across an air gap between the adjacent QC modules.

16. 11. The QC chip module assembly of claim 10, wherein coupling between qubit chips on adjacent QC modules comprises inductive coupling between the adjacent QC modules.

17. 1. A method of constructing a quantum computing (QC) chip module assembly, comprising: connecting a plurality of QC chip modules connected in a series; each QC chip module includes an interposer chip having a footprint and a qubit chip bump-bonded to the interposer chip and positioned such that the qubit chip extends beyond the footprint of the interposer chip; the interposer chip extends beyond an edge of the qubit chip; connecting a wiring harness connected to the interposer chip, the wiring harness including a superconducting flexible cable; A method of constructing a quantum computing (QC) chip module assembly comprising controlling and reading out the qubit chip with electrical signals in the superconducting flexible cable.

18. 20. The method of claim 17, further comprising arranging the qubit chip, the interposer chipper chip, and the wiring harness in an L-shape.

19. 19. The method of claim 17 or 18, wherein in each QC module, the wiring harness is attached to two regions of the interposer chip to form a T-shape with the qubit chips disposed on the interposer chip.

20. 20. The method of claim 17, further comprising defining a gap between the qubit chip and the interposer chip by a final bump height of the bump bond connecting the qubit chip to the interposer chip, the defined gap being the same as a gap between the qubit chip and the interposer in every module of the plurality of QC modules.

21. 21. The method of any of claims 17-20, further comprising arranging the plurality of QC modules in a tiled configuration to form air-gapped connections between the qubit chips of a first QC chip module and the interposer chips of an adjacent QC chip module.

22. 22. The method of any of claims 17 to 21, further comprising disposing the plurality of QC chip modules on a rigid backer.

23. 23. The method of claim 22, further comprising an alignment ridge to the rigid backer to facilitate in-plane alignment of the plurality of QC chip modules.

24. 23. The method of claim 22, further comprising a step in the rigid backer to raise each subsequently placed QC module by a fixed height relative to a previously placed QC module.

25. fabricating the interposer chip with a controlled volume of solder disposed on an under bump metallurgy (UBM) region; 25. The method of claim 24, further comprising: reflowing the solder bump into a chamfered sphere by causing a bottom of the solder ball to flow to a periphery of the UBM area.

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