Multilayer ceramic capacitor with ultra-wideband performance

Abstract

The broadband multilayer ceramic capacitor may include a first external termination and a second external termination. A first portion of the first external termination may be spaced from a first portion of the second external termination by a first external termination spacing distance. The first active electrode layer may include a rectangular first active electrode connected with the first external termination. The second active electrode layer may include a rectangular second active electrode connected with the second external termination. The outermost active electrode layer closest to the outer surface of the capacitor may be spaced from the outer surface by an outermost active-to-surface distance. A ratio of capacitor thickness in the Z direction to outermost active-to-surface distance may be 1.1 or greater. A ratio of capacitor length in the longitudinal direction to first external termination spacing distance may be 15 or greater.

Description

[Technical field]

[0001] Related Applications This application claims priority to U.S. Provisional Patent Application No. 63 / 341,000, which has a filing date of May 12, 2022, and which is incorporated by reference herein. [Background technology]

[0002] The diversity of modern technological applications creates a need for efficient electronic components and integrated circuits for use in electronic components. Capacitors are the basic building blocks used for filtering, coupling, bypassing, and other aspects of such modern applications, which may include wireless communications, alarm systems, radar systems, circuit switching, matching networks, and many other applications. Dramatic increases in the speed and packing density of integrated circuits, in particular, necessitate advances in coupling capacitor technology. High capacitance coupling capacitors have increasingly more important performance characteristics when exposed to the high frequencies of many current applications. Because capacitors are important for such a wide variety of applications, the accuracy and efficiency of the capacitors are essential. Thus, many specific aspects of capacitor design have focused on improving performance characteristics. Summary of the Invention [Means for solving the problem]

[0003] According to an embodiment of the present invention, a broadband multilayer ceramic capacitor may comprise a monolithic body including a plurality of dielectric layers stacked in a Z-direction, the monolithic body having a first end opposite a second end. A first external termination may be disposed along the first end of the monolithic body. The first external termination may include a first portion extending along an outer surface of the monolithic body. A second external termination may be disposed along the second end of the monolithic body. The second external termination may include a first portion extending along an outer surface of the monolithic body. The first portion of the first external termination may be spaced from the first portion of the second external termination by a first external termination spacing distance. The active electrode area may include a plurality of first active electrode layers and a plurality of second active electrode layers. The plurality of first active electrode layers may include at least one active electrode that is rectangular in shape. The plurality of second active electrode layers may include at least one second active electrode that is rectangular in shape. The plurality of first active electrode layers may be connected with the first external termination. The plurality of second active electrode layers may be connected with the second outer termination. The active electrode region may include an outermost active electrode layer. The outermost active electrode layer may be spaced from the outer surface by an outermost-active-to-surface distance. The monolithic body may have a thickness along the Z direction. A ratio of the thickness to the outermost-active-to-surface distance may be 1.1 or greater. The capacitor may have a capacitor length extending in a longitudinal direction. A ratio of the capacitor length to the first outer termination spacing distance may be 15 or greater.

[0004] According to another embodiment of the invention, a device may include a mounting surface and a broadband laminated ceramic capacitor. The broadband laminated ceramic capacitor may include a monolithic body including a plurality of dielectric layers stacked in a Z-direction, the monolithic body may have a first end opposite a second end. A first external termination may be disposed along the first end of the monolithic body. The first external termination may include a first portion extending along an outer surface of the monolithic body. A second external termination may be disposed along the second end of the monolithic body. The second external termination may include a first portion extending along an outer surface of the monolithic body. The first portion of the first external termination may be spaced from the first portion of the second external termination by a first external termination spacing distance. The active electrode area may include a plurality of first active electrode layers and a plurality of second active electrode layers. The plurality of first active electrode layers may include at least one active electrode that is rectangular in shape. The plurality of second active electrode layers may include at least one second active electrode that is rectangular in shape. The plurality of first active electrode layers may be connected to a first external termination. The plurality of second active electrode layers may be connected to a second external termination. The active electrode region may include an outermost active electrode layer. The outermost active electrode layer may be spaced from the outer surface by an outermost active-to-surface distance. The monolithic body may have a thickness along a Z direction. A ratio of the thickness to the outermost active-to-surface distance may be 1.1 or greater. The capacitor may have a capacitor length extending in a longitudinal direction. A ratio of the capacitor length to the first external termination spacing distance may be 15 or greater.

[0005] According to another embodiment of the present invention, a method of forming a broadband multilayer ceramic capacitor may include forming a plurality of active electrodes on a plurality of active electrode layers. A first active electrode layer of at least one of the plurality of active electrode layers may comprise a first active electrode. A second active electrode layer of at least one of the plurality of active electrode layers may comprise a second active electrode. The method may also include stacking the plurality of active electrode layers and the plurality of dielectric layers to form a monolithic body having an outer surface. The plurality of active electrode layers may include an outermost active electrode layer disposed proximate to the outer surface of the monolithic body of the plurality of active electrode layers. The method may further include depositing a first external termination along a first end of the capacitor. The first external termination may be connected with the first active electrode layer. The first external termination may include a first portion extending along the outer surface of the capacitor. The method may also include depositing a second external termination along a second end of the capacitor opposite the first end. The second external termination may be connected with the second active electrode layer. The second external termination may include a first portion extending along an outer surface of the capacitor. The outermost active electrode layer may be spaced from the outer surface by an outermost active-to-surface distance. The monolithic body may have a thickness along a Z direction. A ratio of the thickness to the outermost active-to-surface distance may be 1.1 or greater. The capacitor may have a capacitor length extending longitudinally. A ratio of the capacitor length to the first external termination spacing distance may be 15 or greater.

[0006] A full and enabling disclosure of the present invention, including the best mode thereof, to one skilled in the art, is set forth more particularly in remaining portions of the specification, including reference to the accompanying figures. [Brief description of the drawings]

[0007] [Figure 1A] FIG. 2 is a cross-sectional side view of an embodiment of a capacitor according to an aspect of the present disclosure. [Figure 1B] FIG. 1B is an exploded side view of one embodiment of adjacent active electrode layers of the capacitor of FIG. 1A according to aspects of the present disclosure. [Diagram 2]FIG. 1B is a circuit diagram of an embodiment of the capacitor shown in FIG. 1A according to an aspect of the present disclosure. [Figure 3A] 1A-1C are diagrams of shielding electrode layers that may be included in the shielding electrode regions of various embodiments of capacitors according to aspects of the present disclosure. [Figure 3B] 1A-1C are diagrams of other embodiments of shielding electrode layers that may be included in the shielding electrode regions of various embodiments of capacitors according to aspects of the present disclosure. [Figure 4] FIG. 13 is a cross-sectional side view of another embodiment of a capacitor according to an aspect of the present disclosure. [Figure 5A] 5 is a top view of an anchor electrode of the capacitor of FIG. 4 according to various embodiments of the present disclosure. [Figure 5B] 5 is a top view of an anchor electrode of the capacitor of FIG. 4 according to various embodiments of the present disclosure. [Figure 5C] 5 is a top view of an anchor electrode of the capacitor of FIG. 4 according to various embodiments of the present disclosure. [Figure 6] FIG. 13 is a cross-sectional side view of another embodiment of a capacitor according to an aspect of the present disclosure. [Figure 7] FIG. 13 is a cross-sectional side view of yet another embodiment of a capacitor according to aspects of the present disclosure. [Figure 8A] FIG. 8 is an exploded side view of one embodiment of adjacent active electrode layers of the capacitor of FIG. 7 in accordance with aspects of the present disclosure. [Figure 8B] FIG. 8B is a diagram of the capacitive area of ​​the first active electrode layer of FIG. 8A according to an embodiment of the present disclosure. [Figure 8C] FIG. 8B is a capacitive area diagram of the second active electrode layer of FIG. 8A according to an embodiment of the present disclosure. [Figure 9] FIG. 13 is a cross-sectional side view of yet another embodiment of a capacitor according to aspects of the present disclosure. [Figure 10] FIG. 1B is a diagram of insertion loss curves for the capacitors of FIG. 1A in accordance with an embodiment of the present disclosure. [Figure 11] FIG. 1B is a diagram of insertion loss curves for the capacitors of FIG. 1A in accordance with an embodiment of the present disclosure. [Figure 12]FIG. 1B is a diagram of insertion loss curves for the capacitors of FIG. 1A in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0008] It will be appreciated by those skilled in the art that this discussion is a description of exemplary embodiments only and is not intended as limiting the broader aspects of the invention.

[0009] Broadly speaking, the present subject matter is directed to capacitors, such as for wideband and / or ultra-wideband applications. The capacitors include alternating dielectric and electrode layers that may form at least a portion of a monolithic body of the capacitor. By arranging the dielectric and electrode layers in a stacked or laminated configuration, the capacitor may be referred to as a stacked capacitor, and in particular, a stacked ceramic capacitor, for example, if the dielectric layers include ceramic.

[0010] The capacitor may comprise a monolithic body including a plurality of dielectric layers stacked in a Z-direction. A first external termination may be disposed along a first end of the capacitor. The first external termination may include a first portion extending along an outer surface of the monolithic body of the capacitor. A second external termination may be disposed along a second end of the capacitor longitudinally opposite the first end. The second external termination may include a first portion extending along the outer surface of the monolithic body. The first portion of the first external termination and the first portion of the second external termination may be spaced apart longitudinally by a first external termination spacing distance.

[0011] The outer surface can be a top surface of the monolithic body of the capacitor or a bottom surface of the monolithic body. The top surface and bottom surface of the monolithic body are opposite each other along the Z direction. In an embodiment, the first outer termination and the second outer termination can each include a first portion extending along a first outer surface of the monolithic body, a second portion extending along a second outer surface of the monolithic body, etc., to extend along two or more outer surfaces of the monolithic body of the capacitor. For example, in an embodiment, the first outer termination can include a second portion extending along a second outer surface of the monolithic body, and the second outer termination can include a second portion extending along the second outer surface of the monolithic body. The second portion of the first outer termination and the second portion of the second outer termination can be longitudinally spaced apart by a second outer termination spacing distance. In an embodiment of a capacitor including a first portion of a first external termination, a first portion of a second external termination, a second portion of the first external termination, and a second portion of the second external termination, the first portion of each of the first and second external terminations can extend along one of the top and bottom surfaces of the monolithic body, and the second portion of each of the first and second external terminations can extend along the other of the top and bottom surfaces of the monolithic body.

[0012] The first external termination spacing distance and / or the second external termination spacing distance can be relatively small such that a fringe effect capacitance is created between the external terminations. The fringe effect capacitance can contribute to the superior high frequency performance of the capacitor. For example, the capacitor can have a capacitor length between the first end and the second end in a longitudinal direction. The ratio of the capacitor length to the first external termination spacing distance can be greater than about 2, in some embodiments greater than about 3, in some embodiments greater than about 5, in some embodiments greater than about 7, in some embodiments greater than about 10, in some embodiments greater than about 20, in some embodiments greater than about 30, and in some embodiments greater than about 35. Further, the ratio of the capacitor length to the second external termination spacing distance can be greater than about 2, in some embodiments greater than about 3, in some embodiments greater than about 5, in some embodiments greater than about 7, in some embodiments greater than about 10, in some embodiments greater than about 20, in some embodiments greater than about 30, and in some embodiments greater than about 35.

[0013] In some embodiments, the first outer edge spacing distance can be less than 250 microns, in some embodiments less than 200 microns, in some embodiments less than 175 microns, in some embodiments less than 150 microns, in some embodiments less than 100 microns, in some embodiments less than 75 microns, in some embodiments less than 50 microns, in some embodiments less than 40 microns, in some embodiments less than 30 microns, and in some embodiments less than 20 microns. Similarly, in some embodiments, the second outer edge spacing distance can be less than 250 microns, in some embodiments less than 200 microns, in some embodiments less than 175 microns, in some embodiments less than 150 microns, in some embodiments less than 100 microns, in some embodiments less than 75 microns, in some embodiments less than 50 microns, in some embodiments less than 40 microns, in some embodiments less than 30 microns, and in some embodiments less than 20 microns. For example, in some embodiments, the first outer end spacing distance and / or the second outer end spacing distance can be in the range from about 1 micron to about 250 microns, in some embodiments, from about 5 microns to about 200 microns, in some embodiments, from about 10 microns to about 150 microns, and in some embodiments, from about 15 microns to about 100 microns.

[0014] The capacitor may include an active electrode region having a plurality of active electrode layers. In some embodiments, the plurality of active electrode layers may include a first active electrode layer connected to a first external termination and a second active electrode layer connected to a second external termination. For example, the first active electrode layer may include a first active electrode connected to a first external termination and the second active electrode layer may include a second active electrode connected to a second external termination. The first active electrode layer may overlap the second active electrode layer in a longitudinal direction. The overlap between the first active electrode layer and the second active electrode layer may provide a capacitance between the first external termination and the second external termination. The first active electrode layer may overlap the second active electrode layer along an overlap distance. The overlap distance may be a substantial portion of the length of the capacitor. The ratio of the overlap distance to the capacitor length may be greater than about 0.4, in some embodiments greater than about 0.5, and in some embodiments greater than about 0.6. For example, the overlap distance can range from about 0.4 to about 0.98, in some embodiments from about 0.5 to about 0.95, and in some embodiments, from about 0.6 to about 0.9.

[0015] In some embodiments, the active electrode region includes an outermost active electrode layer, which may be the active electrode layer closest to the outer surface of the monolithic body. The outermost active electrode layer may be spaced from the outer surface by an outermost active-to-surface distance. The outermost active-to-surface distance may be relatively small such that a fringe effect capacitance is created between the active electrode and the outer termination. The fringe effect capacitance may contribute to the superior performance of the capacitor, especially at the lower frequencies of the capacitor's frequency range.

[0016] The monolithic body or capacitor can have a thickness along the Z direction, and in some embodiments the ratio of thickness to distance from the outermost active surface to the surface is 1.1 or greater, in some embodiments 2 or greater, in some embodiments 3 or greater, in some embodiments 5 or greater, in some embodiments 10 or greater, in some embodiments 20 or greater, in some embodiments 30 or greater, in some embodiments 40 or greater, and in some embodiments 50 or greater.

[0017] In some embodiments, the distance from the outermost active to the surface can be 150 microns or less, in some embodiments, 125 microns or less, in some embodiments, 100 microns or less, in some embodiments, 90 microns or less, in some embodiments, 75 microns or less, in some embodiments, 60 microns or less, in some embodiments, 40 microns or less, in some embodiments, 25 microns or less, in some embodiments, 15 microns or less, in some embodiments, 10 microns or less, and in some embodiments, 5 microns or less. By way of example, the distance from the outermost active to the surface can range from about 1 micron to about 150 microns, in some embodiments, from about 5 microns to about 100 microns, in some embodiments, from about 10 microns to about 90 microns, and in some embodiments, from about 15 microns to about 50 microns.

[0018] The active electrode area can have an active electrode area thickness in the Z direction. The active electrode area thickness can be defined between the lowest active electrode layer and the highest active electrode layer. The ratio of capacitor thickness to active electrode area thickness can range from about 1.1 to about 20, in some embodiments from about 1.5 to about 10, and in some embodiments from about 1.7 to about 5.

[0019] In an embodiment, a first active electrode layer of the plurality of active electrode layers can include a first active electrode connected to a first external termination and a second active electrode connected to a second external termination. The second electrode can be coplanar with the first electrode. A second active electrode layer of the plurality of active electrode layers can include a third active electrode connected to the first external termination and a fourth active electrode connected to the second external termination. The third active electrode can be coplanar with the fourth active electrode. The first active electrode can overlap the fourth active electrode in a longitudinal direction. The overlap between the first active electrode and the fourth active electrode can provide a capacitance between the first external termination and the second external termination. The first active electrode can overlap the fourth active electrode along an overlap distance. The overlap distance can be a substantial portion of the length of the capacitor. The ratio of the overlap distance to the capacitor length can be greater than about 0.4, in some embodiments greater than about 0.5, and in some embodiments greater than about 0.6. For example, the overlap distance can range from about 0.4 to about 0.98, in some embodiments from about 0.5 to about 0.95, and in some embodiments from about 0.6 to about 0.9.

[0020] The active electrodes can have a configuration that provides a fringe effect capacitance between the coplanar electrodes. This fringe effect capacitance can also contribute to the superior high frequency performance of the device. For example, the first and second active electrodes can form a relatively small edge gap that can provide a fringe effect capacitance between the active electrodes. For example, an edge gap distance can be formed between the first and second active electrodes in the longitudinal direction. In some embodiments, the edge gap can be less than about 250 microns, in some embodiments, less than about 150 microns, in some embodiments, less than about 120 microns, in some embodiments, less than about 100 microns, and in some embodiments, less than about 80 microns.

[0021] In some embodiments, the capacitor may include one or more shielding electrode layers. The shielding electrode layers may have various shapes and configurations. As an example, each shielding electrode layer may include a pair of opposing coplanar shielding electrodes. In some embodiments, the shielding electrodes may be generally square or rectangular. In other embodiments, the shielding electrodes may be generally stepped or notched.

[0022] The shielding electrode layer may be located within the monolithic body. The shielding electrode may be located between the active electrode region and an outer surface of the monolithic body, such as a lower surface of the monolithic body or a top surface of the monolithic body. In an embodiment, the broadband multilayer ceramic capacitor may not have a shielding electrode above the multiple active electrode layers in the Z direction. In an embodiment, the broadband multilayer ceramic capacitor may not have a shielding electrode above the bottommost electrode layer of the multiple active electrode layers in the Z direction.

[0023] The shielding electrodes are generally spaced apart from the active electrodes by a shield-to-active distance such that the shielding electrode areas are spaced apart and / or distinct from the active electrode areas. The active electrode layers of the multiple active electrode layers may be uniformly spaced apart from one another in the Z direction by an active electrode spacing distance that may be referred to as a "drop." The shielding-to-active distance may be greater than the active electrode spacing distance. For example, the shielding-to-active distance may be two or more times the active electrode spacing distance, in some embodiments three or more times, in some embodiments four or more times, in some embodiments five or more times, and in some embodiments ten or more times.

[0024] By way of example, the active electrode spacing distance can range from about 0.1 microns to about 2 microns, and in some embodiments from about 0.2 microns to about 0.5 microns. The shield to active distance can range from about 5 microns to about 80 microns, and in some embodiments from about 10 microns to about 70 microns, and in some embodiments from about 20 microns to about 60 microns, and in some embodiments from about 30 microns to about 50 microns.

[0025] The shielding electrode region may comprise an outermost shielding electrode layer, which may be the shielding electrode layer closest to the outer surface of the monolithic body. The outermost shielding electrode layer may be spaced from the outer surface by a distance from the outermost shield to the surface. The monolithic body or capacitor may have a thickness along the Z direction, and in some embodiments, the ratio of the thickness to the distance from the outermost shield to the surface is 1.1 or greater, in some embodiments 2 or greater, in some embodiments 3 or greater, in some embodiments 5 or greater, in some embodiments 10 or greater, and in some embodiments 20 or greater.

[0026] The shielding electrode region may have a shielding electrode region thickness in the Z direction. The shielding electrode region thickness may be defined between an outermost shielding electrode of the shielding electrode region and an innermost shielding electrode of the shielding electrode region with respect to the Z direction. The ratio of the capacitor thickness to the shielding electrode region thickness may range from about 1.1 to about 20, in some embodiments from about 1.5 to about 10, and in some embodiments from about 1.7 to about 5.

[0027] In some embodiments, the capacitor may include a dielectric region between the active electrode region and the top of the capacitor and / or between the active electrode region and the bottom of the capacitor. For example, a first dielectric region may extend from the active electrode region to a first outer surface of the capacitor, such as the top or bottom surface of the broadband laminated ceramic capacitor, and a second dielectric region may extend from the active electrode region to a second outer surface of the capacitor, such as the other of the top or bottom surface of the capacitor. As another example, the active electrode region may be positioned between the dielectric region and the shielding electrode region in the Z direction. As yet another example, a first dielectric region may extend from the active electrode region to the outer surface of the broadband laminated ceramic capacitor, and a second dielectric region may extend from the active electrode region to the shielding electrode region.

[0028] The dielectric region may be free of active and / or shielding electrodes. For example, in an embodiment, the dielectric region may include one or more floating electrodes and / or dummy electrode tabs. For example, the dielectric region between the active and shielding electrode regions may include one or more dummy electrode tabs that may aid in forming the external terminations. The dummy electrode tabs generally extend less than about 40% of the length of the capacitor from each end of the capacitor. For example, a first plurality of dummy electrode tabs may be connected to a first external termination, and a second plurality of dummy electrode tabs may be connected to a second external termination.

[0029] In some embodiments, the dielectric region may be free of electrode layers that extend over 40% of the length of the capacitor, in some embodiments, free of electrode layers that extend over 30% of the length of the capacitor, in some embodiments, free of electrode layers that extend over 20% of the length of the capacitor, in some embodiments, free of electrode layers that extend over 15% of the length of the capacitor, in some embodiments, free of electrode layers that extend over 10% of the length of the capacitor, in some embodiments, free of electrode layers that extend over 5% of the length of the capacitor, and in some embodiments, free of electrode layers that extend over 2% of the length of the capacitor. However, in other embodiments, the dielectric region may be free of all electrode layers.

[0030] The broadband laminate ceramic capacitor can have a capacitor thickness in the Z direction between the top and bottom surfaces. The dielectric region can have a dielectric region thickness in the Z direction. The ratio of capacitor thickness to dielectric region thickness can be about 1.1 or greater, in some embodiments about 2 or greater, in some embodiments about 5 or greater, in some embodiments about 10 or greater, in some embodiments about 20 or greater, in some embodiments about 30 or greater, in some embodiments about 40 or greater, and in some embodiments about 50 or greater. In some embodiments, the dielectric region extends between the outermost active electrode layer and the outer surface of the broadband laminate ceramic capacitor such that the dielectric region thickness is the same as the distance from the outermost active to the surface.

[0031] The broadband multilayer ceramic capacitor may be part of, assembled with, and / or integrated into a device, such as a device that operates over a wide range of frequencies. The capacitor may be configured for mounting to a mounting surface of the device. More specifically, the capacitor may be mounted to a mounting surface such that each active electrode layer of the capacitor's multiple active electrode layers extends parallel to the mounting surface. A capacitor mounted in such a horizontal orientation, with the active electrodes extending parallel to the mounting surface of the device, may perform better than a capacitor configured as described herein that is mounted with a vertical electrode orientation. For example, a broadband multilayer ceramic capacitor mounted in a horizontal orientation may exhibit a lower insertion loss over a frequency range than a broadband multilayer ceramic capacitor mounted in a vertical orientation. As an example, a broadband multilayer ceramic capacitor mounted in a horizontal orientation may exhibit an insertion loss within a range of about 0.0 dB to about −0.8 dB over a frequency range of about 5 GHz to about 67 GHz, while a broadband multilayer ceramic capacitor mounted in a vertical orientation may exhibit an insertion loss within a range of about −1.5 dB to about −2.0 dB over a frequency range of about 5 GHz to about 67 GHz.

[0032] The dimensions and spacing of the external terminations may be selectively configured in combination with the spacing of the active electrode area to the outer surface of the capacitor and / or the dimensions of the capacitor to provide improved inductance and capacitance along a larger frequency range than previous capacitors. For example, the first and / or second external termination spacing distances may be selected to provide an inductance loop that improves the response characteristics of the capacitor over a first frequency range. The configuration of the active electrode area, such as the outermost active to surface distance, may be selected to provide a fringe effect capacitance that improves the response of the capacitor over a second frequency range that extends higher or lower than the first frequency range, a second frequency range that is the same as the first frequency range, or a second frequency range that is entirely different from the first frequency range. Additionally, the outermost active to surface distance can be selected to provide an inductance loop that improves the response of the capacitor over a third frequency range that extends above or below the first frequency range, a third frequency range that is the same as the first frequency range, or a third frequency range that is entirely different from the first frequency range, which can be the same as the second frequency range or can be different from the second frequency range. For example, a smaller first outer termination spacing distance can improve performance over a first higher frequency range, and a secondary capacitor can be formed between the outermost active electrode and a termination extending along the outer surface of the monolithic body that improves performance over a second lower frequency range with a smaller outermost active to surface distance.

[0033] The outermost active to surface distance may define a cover layer between the electrodes and the outer surface of the capacitor, which may be minimized in some embodiments to form a relatively thin cover layer that may improve inductance and capacitance over both the first and second frequency ranges, e.g., over all operating frequencies of the capacitor. The outer termination spacing distance (such as the first outer termination spacing distance and / or the second outer termination spacing distance) may be minimized to improve inductance at higher frequencies in the operating frequency range of the capacitor. In at least some embodiments, the minimum outer termination spacing distance in combination with the relatively small outermost active to surface distance may provide better high frequency performance of the capacitor than any one feature by itself and / or may improve performance of the capacitor over a wider frequency range than any one feature by itself. Thus, while one or more features as described herein may improve capacitor performance over at least a portion of the frequency band of the capacitor, a combination of one or more features as described herein may provide better performance of the capacitor over the entire frequency band than any one or more features by themselves.

[0034] A broadband multilayer ceramic capacitor as described herein can exhibit low insertion loss over a wide range of frequencies. Generally, insertion loss is the loss of power through a capacitor and can generally be measured using any method known in the art. For example, the capacitor can exhibit an insertion loss of greater than about -1.20 dB, in some embodiments greater than about -1.10 dB, in some embodiments greater than about -0.90 dB, and in some embodiments greater than about -0.80 dB from about 1 GHz to about 67 GHz. In some embodiments, the capacitor can exhibit an insertion loss of greater than about -0.60 dB, in some embodiments greater than about -0.50 dB, in some embodiments greater than about -0.45 dB, and in some embodiments greater than about -0.40 dB from about 1 GHz to about 40 GHz.

[0035] In some embodiments, the capacitor may exhibit an insertion loss of greater than about -0.30 dB at about 10 GHz, in some embodiments, greater than about -0.25 dB at about 10 GHz, and in some embodiments, greater than about -0.20 dB at about 10 GHz. The capacitor may exhibit an insertion loss of greater than about -0.60 dB at about 20 GHz, in some embodiments, greater than about -0.50 dB at about 20 GHz, in some embodiments, greater than about -0.40 dB at about 20 GHz, and in some embodiments, greater than about -0.30 dB. The capacitor may exhibit an insertion loss of greater than about -0.40 dB at about 30 GHz, in some embodiments, greater than about -0.35 dB at about 30 GHz, in some embodiments, greater than about -0.30 dB at about 30 GHz, in some embodiments, greater than about -0.25 dB at about 30 GHz, and in some embodiments, greater than about -0.20 dB at about 30 GHz. The capacitor may exhibit an insertion loss of greater than about -0.60 dB at about 40 GHz, and in some embodiments, greater than about -0.50 dB at about 40 GHz, and in some embodiments, greater than about -0.40 dB at about 40 GHz, and in some embodiments, greater than about -0.30 dB at about 40 GHz. The capacitor may exhibit an insertion loss of greater than about -1.20 dB at about 50 GHz, and in some embodiments, greater than about -0.90 dB at about 50 GHz, and in some embodiments, greater than about -0.80 dB at about 50 GHz, and in some embodiments, greater than about -0.50 dB at about 50 GHz. The capacitor may exhibit an insertion loss of greater than about -1.10 dB at about 60 GHz, and in some embodiments, greater than about -0.90 dB at about 60 GHz, and in some embodiments, greater than about -0.80 dB at about 60 GHz, and in some embodiments, greater than about -0.60 dB at about 60 GHz.

[0036] In some embodiments, the broadband multilayer ceramic capacitor may exhibit an insertion loss in the range of about -0.05 dB to about -0.40 dB from about 5 GHz to about 20 GHz, in some embodiments in the range of about -0.10 dB to about -0.40 dB from about 10 GHz to about 20 GHz, in some embodiments in the range of about -0.05 dB to about -0.40 dB from about 20 GHz to about 30 GHz, in some embodiments in the range of about -0.05 dB to about -0.60 dB from about 30 GHz to about 40 GHz, in some embodiments in the range of about -0.05 dB to about -1.20 dB from about 40 GHz to about 50 GHz, in some embodiments in the range of about -0.05 dB to about -1.20 dB from about 50 GHz to about 60 GHz, and in some embodiments in the range of about -0.05 dB to about -1.10 dB from about 60 GHz to about 67 GHz.

[0037] I. Example Embodiments Turning to FIG. 1A, an embodiment of a broadband laminated ceramic capacitor 100 is disclosed. FIG. 1A is a schematic cross-sectional side view of an embodiment of a capacitor 100 according to aspects of the present disclosure. The laminated capacitor 100 shown in the embodiment of FIG. 1A has a monolithic body 98 including multiple dielectric layers stacked in a Z-direction 136 and extending in a longitudinal direction 132 between a first end 19 and an opposing second end 21. A first external termination 118 is disposed along the first end 19, and a second external termination 120 is disposed along the second end 21. The first external termination 118 includes a first portion 140 that extends along an outer surface, such as the lower surface 20, of the monolithic body, and similarly, the second external termination 120 includes a first portion 144 that extends along an outer surface, such as the lower surface 20, of the monolithic body. A first portion 140 of the first outer termination 118 is spaced from a first portion 144 of the second outer termination 120 by a first outer termination spacing distance 142 .

[0038] Similarly, in one embodiment, the first outer termination 118 includes a second portion 146 that extends along the other outer surface, such as the top surface 18 of the monolithic body, and the second outer termination 120 includes a second portion 150 that extends along the other outer surface, such as the top surface 18 of the monolithic body. The second portion 146 of the first outer termination 118 is spaced from the second portion 150 of the second outer termination 120 by a second outer termination spacing distance 148. The top surface 18 of the monolithic body 98 can be opposite the bottom surface 20 along the Z direction 136.

[0039] In some embodiments, the first exterior end spacing distance 142 is the same as the second exterior end spacing distance 148. In other embodiments, the first exterior end spacing distance 142 and the second exterior end spacing distance 148 are not equal to one another. For example, in some embodiments, the first exterior end spacing distance 142 is greater than the second exterior end spacing distance 148, and in other embodiments, the first exterior end spacing distance 142 is less than the second exterior end spacing distance 148.

[0040] In some embodiments, the first exterior end spacing distance 142 is less than about 250 microns, in some embodiments less than about 200 microns, in some embodiments less than about 175 microns, in some embodiments less than about 150 microns, in some embodiments less than about 100 microns, in some embodiments less than about 75 microns, in some embodiments less than about 50 microns, in some embodiments less than about 40 microns, in some embodiments less than about 30 microns, and in some embodiments less than about 20 microns. In some embodiments, the second exterior end spacing distance 148 is less than about 250 microns, in some embodiments less than about 200 microns, in some embodiments less than about 175 microns, in some embodiments less than about 150 microns, in some embodiments less than about 100 microns, in some embodiments less than about 75 microns, in some embodiments less than about 50 microns, in some embodiments less than about 40 microns, in some embodiments less than about 30 microns, and in some embodiments less than about 20 microns. For example, in some embodiments, first outer end spacing distance 142 and / or second outer end spacing distance 148 are in the range from about 1 micron to about 250 microns, in some embodiments, from about 5 microns to about 200 microns, in some embodiments, from about 10 microns to about 150 microns, and in some embodiments, from about 15 microns to about 100 microns.

[0041] Additionally, the capacitor can have a capacitor length 17 extending between the first end 19 and the second end 21 in the longitudinal direction 132. The ratio of the capacitor length 17 to the first external end spacing distance 142 and / or the ratio of the capacitor length 17 to the second external end spacing distance 148 can be about 2 or greater, such as about 3 or greater, about 5 or greater, about 7 or greater, about 10 or greater, about 20 or greater, about 30 or greater, or about 35 or greater.

[0042] As shown in FIG. 1A, the stacked capacitor 100 may include multiple electrode regions 10 stacked in a Z-direction 136. The multiple electrode regions 10 may include a dielectric region 12, an active electrode region 14, a shielding electrode region 16, and a second or additional dielectric region 115. The active electrode region 14 may be positioned between the dielectric region 12 and the shielding electrode region 16 in the Z-direction 136. The dielectric region 12 may extend from the active electrode region 14 to a top surface 18 of the broadband stacked ceramic capacitor 100. The second or additional dielectric region 115 may extend from the active electrode region 14 to the shielding electrode region 16.

[0043] The electrode region 10 may include multiple dielectric layers. Some of the dielectric layers may have electrode layers formed thereon. In general, the thicknesses of the dielectric layers and electrode layers are not limited and may be any thickness as desired depending on the performance characteristics of the capacitor. For example, the thickness of the electrode layer may be about 500 nm or more, such as about 1 μm or more, such as about 2 μm or more, such as about 3 μm or more, such as about 4 μm or more to about 10 μm or less, such as about 5 μm or less, such as about 4 μm or less, such as about 3 μm or less, such as about 2 μm or less, without limitation. For example, the electrode layer may have a thickness of about 1 μm to about 2 μm. Also, in one embodiment, the thickness of the dielectric layer may be determined according to the aforementioned thicknesses of the electrode layer. Such thicknesses of the dielectric layer may also apply to the layer between any active electrode layers and / or shielding electrode layers when present as defined herein.

[0044] Generally, the present invention provides a multi-layer capacitor having a unique electrode arrangement and configuration that provides various benefits and advantages. In this regard, it should be understood that the materials used in constructing the capacitor need not be limited and can be any of those commonly used in the art and can be formed using any method commonly known in the art.

[0045] In general, the dielectric layers are typically formed from materials having a relatively high dielectric constant (K), such as from about 10 to about 40,000, in some embodiments from about 50 to about 30,000, and in some embodiments, from about 100 to about 20,000.

[0046] In this regard, the dielectric material may be a ceramic, which may be provided in a variety of forms, such as a wafer (e.g., pre-fired) or as a dielectric material that is co-fired within the device itself.

[0047] Specific examples of high dielectric material types include, for example, NPO(COG) (up to about 100), X7R (from about 3,000 to about 7,000), X7S, Z5U, and / or Y5V materials. It should be understood that the foregoing materials are described by their industry accepted definitions, some of which are standard classifications established by the Electronic Industries Association (EIA) and as such should be recognized by those skilled in the art. For example, such materials can include ceramics. Such materials can include perovskites such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate, lead lanthanum zirconate titanate), and bismuth sodium titanate. In one specific embodiment, for example, a perovskite having the chemical formula Ba x Sr 1-x TiO 3 Barium strontium titanate ("BSTO") may be used, where x is from 0 to 1, and in some embodiments from about 0.15 to about 0.65, and in some embodiments from about 0.25 to about 0.6. Other suitable perovskites include, for example, Ba x Ca 1-x TiO 3 (wherein x is from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6), Pb x Zr1-x TiO 3 ("PZT"), where x ranges from about 0.05 to about 0.4, lead lanthanum zirconium titanate ("PLZT"), lead titanate (PbTiO 3 ), barium calcium zirconium titanate (BaCaZrTiO 3 ), sodium nitrate (NaNO 3 ), KNbO 3 , LiNbO 3 , LiTaO 3 , PbNb 2 O 6 , PbTa 2 O 6 , KSr(NbO 3 ), and NaBa 2 (NbO 3 ) 5 KHb 2 PO 4 Additional complex perovskites include A[B1 1 / 3 B2 2 / 3 ]O 3 A may be a material, where A is Ba x Sr 1-x (x can range from 0 to 1), and B1 is Mg y Zinc 1-y (y can range from 0 to 1), and B2 is Ta z Nb 1-z where z can be a value from 0 to 1. In one specific embodiment, the dielectric layer can include titanate.

[0048] The electrode layer can be formed from any of a variety of different metals as known in the art. The electrode layer can be made from a metal, such as a conductive metal. Materials can include precious metals (e.g., silver, gold, palladium, platinum, etc.) and base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), as well as various combinations thereof. In addition to sputtered titanium / tungsten (Ti / W) alloys, sputtered layers of chromium, nickel, and gold may also be suitable. The electrodes may be made from low resistance materials, such as silver, copper, gold, aluminum, palladium, etc. In one specific embodiment, the electrode layer can include nickel or an alloy thereof.

[0049] A plurality of first active electrode layers 102 and a plurality of second active electrode layers 104 may be disposed within the active electrode area 14 of the capacitor 100. More specifically, as shown in FIG. 1A, the active electrode area 14 may include the first electrode layers 102 and the second electrode layers 104 in an alternating arrangement. For example, the plurality of first electrode layers 102 and the plurality of second electrode layers 104 may be disposed in an alternating mirror configuration. As further shown in FIG. 1A, the first active electrode layer 102 may be connected to a first external termination 118, and the second active electrode layer 104 may be connected to a second external termination 120.

[0050] Additionally, the first active electrode layer 102 can overlap the second active electrode layer along an overlap distance 122. Additionally, the side cross-sectional view of Figure 1A shows the capacitor 100 having a total of four first electrode layers 102 and three second electrode layers 104. However, it should be understood that any number of electrode layers 102, 104 can be used to obtain a desired capacitance for a desired application.

[0051] 1B, each active electrode layer 102, 104 can have an electrode width 126. More specifically, in the embodiment shown in FIG. 1B, each first active electrode layer 102 has an electrode width 126 and each second active electrode layer 104 has an electrode width 126. The electrode width 126 can affect the capacitance, for example, between the outermost active electrode layer and the first portion 140 of the first external termination 118 and the first portion 144 of the second external termination 120, and / or between the outermost active electrode layer and the second portion 146 of the first external termination 118 and the second portion 150 of the second external termination 120.

[0052] 1A, the capacitor 100 may include one or more shielding electrode layers 15 in the shielding electrode region 16. The shielding electrode layers 15 may have various configurations, as described below with reference to, for example, FIGS. 3A and 3B, which show that the shielding electrode layer 15 may include a first shielding electrode 22 and a second shielding electrode 24.

[0053] The shielding electrode area 16 can be positioned within the capacitor 100 between the active electrode area 14 and the top surface 18 and / or between the active electrode area 14 and an outer surface of the monolithic body 98, such as between the active electrode area 14 and the bottom surface 20. The shielding electrode layer 15 is generally spaced apart from the active electrode layers 102, 104 by a shield-to-active distance 67 such that the first shielding electrode 22 and the second shielding electrode 24 are distinct from the active electrodes. For example, the active electrode layers 102, 104 can be uniformly spaced apart from one another in the Z direction 136 by an active electrode spacing distance 105, sometimes referred to as a "drop." The shielding-to-active distance 67 can be greater than the active electrode spacing distance 105. For example, the shielding-to-active distance 67 can be greater than the active electrode spacing distance 105 by a factor of two or more. By way of example, the active electrode spacing distance 105 can range from about 0.5 microns to about 5 microns. Shield to active distance 67 can be greater than about 5 microns, in some embodiments greater than about 10 microns, in some embodiments greater than about 20 microns, and in some embodiments greater than about 30 microns.

[0054] 1A, in some embodiments, the capacitor 100 may be devoid of active electrode layers 102, 104 in an additional dielectric region 115 (e.g., a second dielectric region) between the active electrode region 14 and the shielding electrode region 16 in the Z direction 136. However, in other embodiments, the dielectric region 115 between the active electrode region 14 and the shielding electrode region 16 may include one or more dummy electrode tabs that may help form an external termination, as shown, for example, in FIG.

[0055] 1A , in some embodiments, the broadband multilayer ceramic capacitor 100 can have a capacitor thickness 56 in the Z direction 136 between the top surface 18 and the bottom surface 20. The dielectric region 12 can have a dielectric region thickness 58 in the Z direction 136. In some embodiments, the ratio of the capacitor thickness 56 to the dielectric region thickness 58 can be about 10 or greater.

[0056] The active electrode area 14 may have an active electrode area thickness 59 in the Z direction 136. The active electrode area 14 may be free of the shielding electrodes 22, 24 and / or may include only overlapping electrodes. The active electrode area thickness 59 may be defined between the lowest active electrode layer 101 and the highest active electrode layer 103 with respect to the Z direction 136. The ratio of the capacitor thickness 56 to the active electrode area thickness 59 may range from about 1.1 to about 20.

[0057] Additionally, the region between the active electrodes 102, 104 and the underside 20 of the capacitor 100, formed in the embodiment of FIG. 1A by the second or additional dielectric region 115 and the shielding electrode region 16, may be relatively thin. More specifically, the outermost active-to-surface distance 60 between the outermost active electrode layer and the outer surface of the monolithic body 98 (such as between the lowest active electrode layer 101 and the underside 20 as shown in FIG. 1A) may be relatively small or minimized to form a relatively thin cover layer between the active electrodes 102, 104 and the outer surface of the monolithic body 98. For example, the ratio of the capacitor thickness 56 to the outermost active-to-surface distance 60 may be greater than about 2. For example, in some embodiments, the ratio of the capacitor thickness 56 to the outermost active to surface distance 60 can be 1.1 or greater, in some embodiments, 2 or greater, in some embodiments, 3 or greater, in some embodiments, 5 or greater, in some embodiments, 10 or greater, in some embodiments, 20 or greater, in some embodiments, 30 or greater, in some embodiments, 40 or greater, and in some embodiments, 50 or greater. Further, in some embodiments, the outermost active to surface distance 60 can be 150 microns or less, in some embodiments, 125 microns or less, in some embodiments, 100 microns or less, in some embodiments, 90 microns or less, in some embodiments, 75 microns or less, in some embodiments, 60 microns or less, in some embodiments, 40 microns or less, in some embodiments, 25 microns or less, in some embodiments, 15 microns or less, in some embodiments, 10 microns or less, and in some embodiments, 5 microns or less. By way of example, the outermost active to surface distance 60 can range from about 1 micron to about 150 microns, in some embodiments from about 5 microns to about 100 microns, in some embodiments from about 10 microns to about 90 microns, and in some embodiments from about 15 microns to about 50 microns.

[0058] As shown in the embodiment of FIG. 1A, the cover layer or outermost active to surface distance 60 includes the shielding electrode region 16 and the second or additional dielectric region 115. In an embodiment, the dielectric region 12 extends between the outermost active electrode layer and the outer surface of the broadband multilayer ceramic capacitor such that the dielectric region 12 defines a cover layer and the dielectric region thickness 58 is the same as the outermost active to surface distance 60. For example, referring to FIG. 9, a broadband multilayer ceramic capacitor 900 is shown comprising a first dielectric region 12 extending from the active electrode region 14 to the top surface 18 and a second dielectric region 12 extending from the active electrode region 14 to the bottom surface 20, with the second dielectric region 12 having a dielectric region thickness 58 the same as the outermost active to surface distance 60.

[0059] In some embodiments, the outermost shield-to-surface distance 63 may be defined as the distance between the shielding electrodes 22, 24 and an outer surface of the capacitor 100, such as the bottom surface 20 of the capacitor 100 as shown in FIG. 1A. When multiple shielding electrode layers 15 are included, the outermost shield-to-surface distance 63 may be defined as the distance between the outer surface, such as the top surface 18 for the shielding electrode area 16 between the top surface 18 and the active electrode area 14, or the bottom surface 20 for the shielding electrode area 16 between the active electrode area 14 and the bottom surface 20, and the outermost shielding electrode layer 137 (FIG. 4). The ratio of the capacitor thickness 56 to the outermost shield-to-surface distance 63 may be greater than about 2. For example, in some embodiments, the ratio of the capacitor thickness 56 to the outermost shield-to-surface distance 63 may be 1.1 or greater, in some embodiments, 2 or greater, in some embodiments, 3 or greater, in some embodiments, 5 or greater, in some embodiments, 10 or greater, and in some embodiments, 20 or greater.

[0060] As previously described, the shielding electrodes 22, 24 may be spaced apart from the active electrode layers 102, 104 by a shield-to-active distance 67. In the embodiment of FIG. 1A, the shield-to-active distance 67 is defined in the Z direction 136 between the lowest active electrode 101 and the shielding electrode layer 15 closest to the lowest active electrode 101. In an embodiment including two or more shielding electrode layers 15, such as that shown in FIG. 4, the shield-to-active distance 67 is defined between the innermost shielding electrode layer 138 and the active electrode layer 102, 104 closest to the innermost shielding electrode layer 138. The ratio of the shield-to-active distance 67 to the outermost shield-to-surface distance 63 may range from about 1 to about 20, in some embodiments from about 2 to about 10, and in some embodiments from about 3 to about 5.

[0061] Generally, for the embodiments discussed herein, the first external termination 118 and the second external termination 120 can be formed from any of a variety of different materials as known in the art. For example, the external terminations 118, 120 can be made from a metal, such as a conductive metal. The external termination materials can include precious metals (e.g., silver, gold, palladium, platinum, etc.) and base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), as well as various combinations thereof. In one specific embodiment, the external terminations 118, 120 can include copper or an alloy thereof.

[0062] The external terminations 118, 120 may be formed using any method commonly known in the art. The external terminations 118, 120 may be formed using techniques such as sputtering, painting, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant spray / airbrush, and the like.

[0063] In one embodiment, the external terminations 118, 120 may be formed to be relatively thick. For example, the external terminations 118, 120 may be formed by applying thick film strips of metal (e.g., by dipping the capacitor in a liquid external termination material) to the exposed portions of the electrode layers. Such metal may be glass-based and may include silver or copper. By way of example, such strips may be printed and sintered onto the capacitor. Thereafter, an additional plating layer of metal (e.g., nickel, tin, solder, etc.) may be created over the termination strips such that the capacitor may be soldered to a substrate. Such application of thick film strips may be performed using any method commonly known in the art (e.g., by a termination press and print wheel to transfer a metal-loaded paste over the exposed electrode layers).

[0064] The thickly plated outer terminations 118, 120 may have an average thickness of about 150 μm or less, such as about 125 μm or less, such as about 100 μm or less, such as about 80 μm or less. The thickly plated outer terminations 118, 120 may have an average thickness of about 25 μm or more, such as about 75 μm or more, such as about 35 μm or more, such as about 50 μm or more. For example, the thickly plated outer terminations 118, 120 may have an average thickness of about 25 μm to about 150 μm, such as about 35 μm to about 125 μm, such as about 50 μm to about 100 μm.

[0065] In other embodiments, the external terminations 118, 120 may be formed such that each external termination is a thin film plating of metal. Such a thin film plating may be formed by depositing a conductive material, such as a conductive metal, onto exposed portions of the electrode layer. For example, the leading edge of the electrode layer may be exposed to allow for the formation of a plated terminal.

[0066] The thin plated external terminations 118, 120 may have an average thickness of about 50 μm or less, such as about 40 μm or less, such as about 30 μm or less, such as about 25 μm or less. The thin plated external terminations 118, 120 may have an average thickness of about 5 μm or more, such as about 10 μm or more, such as about 15 μm or more. For example, the external terminations 118, 120 may have an average thickness of about 5 μm to about 50 μm, such as about 10 μm to about 40 μm, such as about 15 μm to about 30 μm, such as about 15 μm to about 25 μm.

[0067] In general, the external terminations 118, 120 may comprise plated terminals. For example, the external terminations 118, 120 may comprise electroplated terminals, electroless plated terminals, or a combination thereof. For example, the electroplated terminals may be formed via electrolytic plating. The electroless plated terminals may be formed via electroless plating.

[0068] When multiple layers make up the external terminations, the external terminations may include electroplated and electroless plated terminations. For example, electroless plating may be used initially to deposit an initial layer of material. Then, the plating technique may be switched to an electrochemical plating system, which may allow for a more rapid build-up of material.

[0069] When forming the plated terminations 118, 120 by any plating method, the leading edges of the lead tabs of the electrode layers exposed from the body of the capacitor are exposed to a plating solution, such as by immersing the capacitor in the plating solution.

[0070] The plating solution includes a conductive material, such as a conductive metal, to form the plated terminations, i.e., a conductive material is used to form the plated terminals. Such conductive material may be any of the materials described above or any material as is commonly known in the art. For example, the plating solution may be a nickel sulfamate bath solution or other nickel solution, such that the plated layer and external terminations include nickel. Alternatively, the plating solution may be a cuprate bath or other suitable copper solution, such that the plated layer and external terminations include copper.

[0071] It should also be understood that the plating solution may contain other additives as are commonly known in the art. For example, the additives may include other organic additives and mediators that can aid in the plating process. Additives may also be used to provide a plating solution at a desired pH. In one embodiment, a resistance reducing additive may be used in the solution to aid in complete plating coverage and adhesion of the plating material to the capacitor and exposed leading edges of the lead tabs.

[0072] The capacitor may be exposed, submerged, or immersed in the plating solution for a predetermined length of time. Such exposure time may be, but is not necessarily limited to, a length of time sufficient to deposit sufficient plating material to form plated terminations. In this regard, the time must be sufficient to allow for the formation of continuous connections between the desired exposed adjacent leading edges of lead tabs of a given polarity of each electrode layer in a set of alternating dielectric and electrode layers.

[0073] Generally speaking, the difference between electrolytic plating and electroless plating is that electrolytic plating uses an electrical bias, such as by using an external power supply. Typically, electrolytic plating solutions are electrolytic, with a bias current of, for example, 10-15 amp / ft 2(rated at 9.4 volts). The connections can be made with a negative connection to the capacitor requiring the formation of a plated terminal and a positive connection to a solid material in the same plating solution (e.g., Cu in a Cu plating solution). That is, the capacitor is biased to a polarity opposite that of the plating solution. Using this method, the conductive material of the plating solution is attracted to the metal of the exposed leading edge of the lead tab of the electrode layer.

[0074] Prior to submerging or exposing the capacitor to the plating solution, various pretreatment steps may be employed. These steps may be performed for a variety of purposes, including promoting, accelerating, and / or improving adhesion of the plating material to the leading edges of the lead tabs.

[0075] An initial cleaning step may also be used prior to plating or any other pretreatment step. This step may be used to remove oxide buildup that forms on exposed lead tabs of the electrode layer. This cleaning step may be particularly useful to help remove nickel oxide buildup when the internal electrodes or other conductive elements are formed from nickel. Cleaning of the component may be effected by complete immersion in a pre-cleaning bath, such as one that includes an acid cleaner. In one embodiment, exposure may be for a predetermined period of time, such as on the order of about 10 minutes. Cleaning may alternatively be effected by a chemical polishing or herparizing step.

[0076] Also, a step to activate the exposed metal leading edge of the electrode layer lead tab may be performed to facilitate deposition of conductive material. Activation may be accomplished by immersion in palladium salts, photo-patterned palladium metalorganic precursors (through a mask or laser), screen-printed or inkjet-deposited palladium compounds, or electrophoretic palladium deposition. It should be understood that palladium-based activation is currently disclosed only as an example of an activation solution that often works well with activation for exposed tab portions formed from nickel or its alloys. However, it should be understood that other activation solutions may be utilized.

[0077] Also, alternatively or in addition to the activation step described above, an activation dopant may be introduced into the conductive material when forming the electrode layer of the capacitor. For example, when the electrode layer includes nickel and the activation dopant includes palladium, a palladium dopant may be introduced into the nickel ink or composition that forms the electrode layer. Doing so may eliminate the palladium activation step. It should further be understood that some of the above-mentioned operating methods, such as organometallic precursors, deposit themselves simultaneously with the glass former for increased adhesion to the generally ceramic body of the capacitor. When the activation step is taken as described above, traces of the activator material may often remain on the exposed conductive parts before and after plating of the terminals.

[0078] Also, post-processing steps after plating may be used. Such steps may be performed for a variety of purposes, including promoting and / or improving adhesion of materials. For example, a heating (or annealing) step may be used after performing a plating step. Such heating may be performed via baking, laser exposure, UV exposure, microwave exposure, arc welding, etc.

[0079] As indicated herein, the external termination may include at least one plating layer. In one embodiment, the external termination may include only one plating layer. However, it should be understood that the external termination may include multiple plating layers. For example, the external termination may include a first plating layer and a second plating layer. The external termination may also include a third plating layer. The materials of these plating layers may be any of those previously described, as generally known in the art.

[0080] For example, one plating layer, such as the first plating layer, may include copper or an alloy thereof. Another plating layer, such as the second plating layer, may include nickel or an alloy thereof. Another plating layer, such as the third plating layer, may include a combination of materials, such as tin, lead, gold, or an alloy. Alternatively, an initial plating layer may include nickel, followed by a plating layer of tin or gold. In other embodiments, an initial plating layer of copper may be formed, followed by a layer of nickel.

[0081] In one embodiment, the initial or first plated layer can be a conductive metal (e.g., copper). This area can then be covered with a second layer comprising a resistor-polymer material for encapsulation. The area can then be polished to selectively remove the resistive polymer material and then plated again with a third layer comprising a conductive metal material (e.g., copper).

[0082] The second layer above the initial plated layer may correspond to a solder barrier layer, such as a nickel-solder barrier layer. In some embodiments, the layer may be formed by electroplating an additional layer of metal (e.g., nickel) onto an initial electrolessly or electrolytically plated layer (e.g., plated copper). Other exemplary materials for the solder barrier layer include nickel-phosphorus, gold, and silver. The third layer in the solder barrier layer may correspond to a conductive layer, such as Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable plated solder, in some embodiments.

[0083] A layer of metal plating may also be subsequently formed over such metal plating by an electroplating step to provide a resistive alloy or a more resistive metal alloy coating, such as an electroless Ni-P alloy, although it should be understood that any metal coating may be included as one skilled in the art would understand from the full disclosure herein.

[0084] It should be understood that any of the foregoing steps may be performed as a bulk process, such as a barrel plating process, a fluidized bed plating process, and / or a flow-through plating termination process, all of which are commonly known in the art. Such bulk processes allow multiple components to be processed at once, providing an efficient and rapid termination process. This is a particular advantage over traditional termination methods, such as printing thick film terminations, which require processing of individual components.

[0085] In some embodiments, a combination of external termination configurations may be used for the first external termination 118 and / or the second external termination 120. For example, in some embodiments, the first external termination 118 and the second external termination 120 may be a combination of FCT (fine copper termination) and thick film termination. For example, FCT may be applied to each end of the monolithic body 98 and a thick film termination may be applied over each FCT termination. Other combinations of termination formation techniques and / or configurations may also be used.

[0086] As described herein, the formation of the external termination is generally guided by the location of the exposed leading edge of the lead tab of the electrode layer. Such a phenomenon may be referred to as "self-determining" because the formation of the external plated terminal is determined by the configuration of the exposed conductive metal of the electrode layer at selected peripheral locations in the capacitor. In an embodiment, the capacitor may include a "dummy tab" to provide exposed conductive metal along a portion of the monolithic body of the capacitor that does not include other electrodes (e.g., active or shielding electrodes). In an embodiment, one or more "dummy tabs," "dummy electrodes," anchor tabs, and / or anchor electrodes may be additional features for a nucleation function that occurs, for example, during a FCT (fine copper termination electroless plating) process. Such dummy or anchor tabs or electrodes may be positioned internally or externally relative to the monolithic component to nucleate the metallized plating material to form the external plated terminal in the FCT process.

[0087] It should be understood that additional techniques for forming the capacitor terminations are possible within the scope of the present technology. Example alternatives include, but are not limited to, forming the terminations by plating, magnetic, masking, electrophoretic / electrostatic, sputtering, vacuum deposition, printing, or other techniques for forming both thick film or thin film conductive layers.

[0088] 2 shows a circuit diagram of the capacitor 100 shown in FIG. 1A. It is understood that various capacitive elements may be defined in the capacitor 100, and that various gap and / or spacing distance dimensions may be selectively designed to obtain desired respective capacitance values ​​for the capacitive elements of the capacitor 100. More specifically, the configuration and various parameters of the capacitor, such as the number of electrode layers, the surface area of ​​the overlapping central portions of the electrode pairs, the distance between the separating electrodes, the dielectric constant of the dielectric material, etc., may be selected to achieve the desired capacitance value. Nevertheless, a capacitor as disclosed herein may include an arrangement of combined series and parallel capacitors to achieve effective wideband performance.

[0089] 2, the primary capacitor P may generally correspond to a relatively large capacitance adapted for operation in a generally lower frequency range, such as on the order of between about a few kilohertz (kHz) to about 200 megahertz (MHz), while the secondary capacitors D1 and D2 may generally correspond to relatively smaller value capacitors configured to operate in a relatively higher frequency range, such as on the order of between about 200 megahertz (MHz) to large gigahertz (GHz). For example, the secondary capacitor D1 may correspond to a smaller value capacitor than the primary capacitor P and may be configured to operate at a higher frequency than the primary capacitor P, and the secondary capacitor D2 may correspond to a smaller value capacitor than the secondary capacitor D1 and may be configured to operate at a higher frequency than the secondary capacitor D1. As previously described, the primary capacitor P, secondary capacitor D1, and secondary capacitor D2 can each be formed by a capacitive element defined by capacitor 100 (or the stacked capacitors of various embodiments described herein), with the capacitance value of each capacitor P, D1, D2 being determined based on selected values ​​of one or more dimensions described herein. For example, a thinner cover layer or outermost active-to-surface distance 60 can be selected to provide a capacitance value for improving the low frequency performance of the capacitor, while a smaller first outer termination spacing distance 142 can be selected to provide a capacitance value for improving the high frequency performance of the capacitor.

[0090] 3A illustrates a shielding electrode layer 26 that may be included within the shielding electrode region 16 (shown in FIG. 1A ) in the monolithic body of the capacitor 100. As previously indicated, the first shielding electrode 22 may be parallel to a longitudinal direction 132 (e.g., parallel to the top surface 18 and bottom surface 20 shown in FIG. 1A ). The first shielding electrode 22 may be aligned with a lateral direction 134 and may have a first longitudinal edge 28 that faces away from the first outer termination 118 (shown in FIG. 1A ) and the first end 19. The first shielding electrode 22 may be aligned with a lateral direction 134 and may have a second longitudinal edge 30 that faces away from the first outer termination 118 (shown in FIG. 1A ) and the first end 19. The second longitudinal edge 30 may be offset in the longitudinal direction 132 from the first longitudinal edge 28 a shield electrode offset distance 32 to define a step 25 .

[0091] The second shielding electrode 24 may be connected with the second outer end 120 (shown in FIG. 1A ) and the second end 21. The second shielding electrode 24 may be approximately aligned with the first shielding electrode 22 in the Z direction 136 (shown in FIG. 1A ). The second shielding electrode 24 may have a similar configuration to the first shielding electrode 22. For example, the second shielding electrode 24 may have a first longitudinal edge 28 aligned with the lateral direction 134 and facing away from the second outer end 120 (shown in FIG. 1A ) and the second end 21. The second shielding electrode 24 may have a second longitudinal edge 30 aligned with the lateral direction 134 and facing away from the second outer end 120 (shown in FIG. 1A ) and the second end 21. The second longitudinal edge 30 of the second shielding electrode 24 may be offset in the longitudinal direction 132 from the first longitudinal edge 28 of the second shielding electrode 24 by a shielding electrode offset distance 32 to define a step 25 .

[0092] A first shielding volume area 34 may be formed between a first longitudinal edge 28 of the first shielding electrode 22 and a first longitudinal edge 28 of the second shielding electrode 24. A second shielding volume area 36 may be formed between a second longitudinal edge 30 of the first shielding electrode 22 and a second longitudinal edge 30 of the second shielding electrode 24. In an embodiment, a width 38 of the first longitudinal edge 28 in the lateral direction 134 may be smaller than a width 40 of the first shielding electrode 22 in the lateral direction 134.

[0093] A first shielding gap distance 42 may be formed in the longitudinal direction 132 between the first longitudinal edge 28 of the first shielding electrode 22 and the first longitudinal edge 28 of the second shielding electrode 24. A second shielding gap distance 44 may be formed in the longitudinal direction 132 between the second lateral edge 30 of the first shielding electrode 22 and the second lateral edge 30 of the second shielding electrode 24.

[0094] In an embodiment, a third shielding gap distance 46 may be formed between a third longitudinal edge 48 of the first shielding electrode 22 and a third longitudinal edge 48 of the second shielding electrode 24. A third shielding volume area 51 may be formed between a third longitudinal edge 48 of the first shielding electrode 22 and a third longitudinal edge 48 of the second shielding electrode 24. In an embodiment, the third shielding gap distance 46 may be approximately equal to the second shielding gap distance 44 such that the third shielding volume area 51 may be substantially similar in size and shape to the second shielding volume area 36. For example, in an embodiment, the first shielding electrode 22 and / or the second shielding electrode 24 may be symmetrical about a longitudinal centerline 50 extending in the longitudinal direction 132.

[0095] However, in other embodiments, the third shielded gap distance 46 may be larger or smaller than the second shielded gap distance 44 such that the third shielded volume area 51 is sized and / or shaped differently from the second shielded volume area 36 and creates a different volume than the second volume area.

[0096] It should be appreciated that in an embodiment, one or more of the shielding electrodes 22, 24 may be rectangular. Stated another way, the shielding electrode offset distance 32 may be zero or approximately zero such that the first longitudinal edge 28 and the second longitudinal edge 30 are aligned or approximately aligned.

[0097] FIG. 3B illustrates another embodiment of a shielding electrode layer 26 that may be included in the shielding electrode region 16 (shown in FIG. 1A ) in the monolithic body of the capacitor 100. The first shielding electrode 22 may be parallel to the longitudinal direction 132 (e.g., parallel to the top surface 18 and the bottom surface 20 shown in FIG. 1A ). The first shielding electrode 22 may be connected to the first external termination 118 (shown in FIG. 1A ) and the first end 19. The first shielding electrode 22 may have a generally square or rectangular shape. The second shielding electrode 24 may be connected to the second external termination 120 (shown in FIG. 1A ) and the second end 21. The second shielding electrode 24 may be approximately aligned with the first shielding electrode 22 in the Z direction 136 (shown in FIG. 1A ). The second shielding electrode 24 may have a similar configuration to the first shielding electrode 22.

[0098] A single shielding volume area 34 may be formed between the first shielding electrode 22 and the second shielding electrode 24. More specifically, in the embodiment of FIG. 3B, the first shielding electrode 22 is aligned with the lateral direction 134 and has a first outer end 118 (shown in FIG. 1A ) and a longitudinal edge 28 facing away from the first end 19. Similarly, the second shielding electrode 24 is aligned with the lateral direction 134 and has a second outer end 120 (shown in FIG. 1A ) and a longitudinal edge 28 facing away from the second end 21. A shielding gap distance 42 may be formed between the longitudinal edge 28 of the first shielding electrode 22 and the longitudinal edge 28 of the second shielding electrode 24 in the longitudinal direction 132. As shown in FIG. 3B, a capacitive region 34 is formed in the gap between the longitudinal edge 28 of the first shield electrode 22 and the longitudinal edge 28 of the second shield electrode 24 .

[0099] Referring back to FIG. 1A , the capacitor 100 may be part of a device 1 that includes a mounting surface 5. As shown in FIG. 1A , in an embodiment, the capacitor 100 is configured for mounting to the mounting surface 5, which may be any surface known in the art to which a capacitor may be mounted or coupled. As further shown in FIG. 1A , the capacitor 100 is mounted to the mounting surface 5 such that each of a plurality of active electrode layers 102, 104 of the capacitor 100 extends parallel to the mounting surface. As described elsewhere herein, the capacitor 100 in a horizontal orientation as shown in the figure, with the active electrodes extending parallel to the mounting surface 5, may perform better than a capacitor configured as described herein mounted with a vertical electrode orientation.

[0100] Referring to Figure 4, a schematic cross-sectional side view of another embodiment of a broadband stacked capacitor is provided. Similar to capacitor 100 shown in Figure 1A, stacked capacitor 400 shown in the embodiment of Figure 4 includes a first external termination 118 disposed along a first end 19 and a second external termination 120 disposed along a second end 21 opposite first end 19 in a longitudinal direction 132. Also as described with respect to capacitor 100, capacitor 400 can include multiple dielectric layers and multiple electrode layers, with the electrode layers interleaved in spaced apart relation with a dielectric layer positioned between each adjacent electrode layer.

[0101] More specifically, in the embodiment of FIG. 4 , the capacitor 400 has a monolithic body 98 including multiple dielectric layers stacked in the Z direction 136 and extending between a first end 19 and an opposing second end 21, with a first external termination 118 disposed along the first end 19 and a second external termination 120 disposed along the second end 21. The first external termination 118 includes a first portion 140 that extends along an outer surface, such as the lower surface 20, of the monolithic body, and similarly, the second external termination 120 includes a first portion 144 that extends along an outer surface, such as the lower surface 20, of the monolithic body. The first portion 140 of the first external termination 118 is spaced from the first portion 144 of the second external termination 120 by a first external termination spacing distance 142. Similarly, in one embodiment, the first external termination 118 includes a second portion 146 that extends along the other outer surface, such as the top surface 18, of the monolithic body, and the second external termination 120 includes a second portion 150 that extends along the other outer surface, such as the top surface 18, of the monolithic body. The second portion 146 of the first external termination 118 is spaced from the second portion 150 of the second external termination 120 by a second external termination spacing distance 148. The first external termination spacing distance 142 and / or the second external termination spacing distance 148 can be configured as described with respect to the capacitor 100 shown in FIG. 1A, e.g., the first external termination spacing distance 142 can be the same as or different from the second external termination spacing distance 148 and / or can be within one of the ranges specified.

[0102] Also, as indicated above, the capacitor 400 may include a shielding electrode. For example, as shown in Figure 4, the stacked capacitor 400 may include a first shielding region 210 and a second shielding region 212, each of which may include one or more shielding electrode layers 26, for example as described above with respect to Figures 3A and 3B. In an embodiment, the shielding regions 210, 212 may be separated from the active electrode region 14 by a dielectric region (e.g., not including any electrode layers).

[0103] A shielding electrode region thickness 61 may be defined in the Z direction 136. The shielding electrode region thickness 61 may be defined between an outer surface of the capacitor 100 (such as the top surface 18 as shown in FIG. 4) and an outermost electrode layer (such as the highest electrode layer 103 as shown in FIG. 4) of the multiple active electrode layers 102, 104. A ratio of the capacitor thickness 56 to the shielding electrode region thickness 61 may range from about 1.1 to about 20.

[0104] The shielding electrode layer 26 may have a first shielding electrode configuration in which each shielding electrode 22, 24 is generally rectangular, for example, as described with respect to Figure 3B. In other embodiments, the shielding electrode layer 26 may have a second shielding electrode configuration in which the shielding electrodes 22, 24 include a step 25, for example, as described above with reference to the electrodes of Figure 3A.

[0105] As previously described, an active electrode area 14 may be disposed between the first shielded area 210 and the second shielded area 212. The active electrode area 14 may include multiple alternating active electrode layers 102, 104, which may be configured, for example, as described with reference to FIG. 1A or, in other embodiments, with reference to FIGS. 8A-8C. Also, a pair of ceramic covers 214 may be disposed along the top and / or bottom surfaces of the capacitor 400. The ceramic covers 214 may include a dielectric material that is the same or similar to the dielectric material of the multiple dielectric layers.

[0106] 4, in an embodiment, the stacked capacitor 400 may also include anchor electrode regions 402, 404, 406, and / or 408. For example, the stacked capacitor 400 may include a first anchor electrode region 404 above the active electrode region 14. Additionally, the first shielding electrode region 210 including the shielding electrode layer 26 may be positioned above the first anchor electrode region 404, such as above the first anchor electrode region 404. Also, the second anchor electrode region 402 may be positioned above the first shielding electrode region 210, such as above the first shielding electrode region 210. Similarly, the stacked capacitor 400 may include a third anchor electrode region 406 below the active electrode region 14, such as directly below the active electrode region 14. Additionally, the second shielding electrode region 212 including the shielding electrode layer 26 may be positioned below the third anchor electrode region 406, such as directly below the third anchor electrode region 406. Also, the fourth anchor electrode region 408 may be positioned below the second shielding electrode region 212, such as directly below the second shielding electrode region 212. In this regard, the active electrode region 14 may be disposed between the first anchor electrode region 404 and the third anchor electrode region 406, for example. The active electrode region 14 may be configured as previously described with reference to Figures 1, 2A, 2B, and 2C.

[0107] 5A, the anchor electrode regions 402, 404, 406, and / or 408 may comprise a plurality of anchor electrode layers 410 each having a pair of anchor electrodes 412. The anchor electrodes 412 may include a pair of electrode arms 414. Each electrode arm 414 of the anchor electrodes 412 may comprise a main portion 428 and a stepped portion 430. More specifically, the electrode arm 414 of a first anchor electrode 412 may comprise a first longitudinal edge 416 that extends in the lateral direction 134 and may define an edge of the stepped portion 430. A second longitudinal edge 418 may extend in the lateral direction 134 and may define an edge of the main portion 428 of the arm 414. The first longitudinal edge 416 may be offset in the longitudinal direction 132 from the second longitudinal edge 418 by an arm offset distance 420. In this manner, the electrode arm 414 of the anchor electrode 412 may include a step 426 offset inwardly from an outer lateral edge 425 of the anchor electrode 412 .

[0108] One or both electrode arms 414 of the first anchor electrode 412 and / or the second anchor electrode 412 may include a respective main portion 428 and a stepped portion 430. For example, both arms 414 of both electrodes 412 may include a respective main portion 428 and stepped portion 430, such as that shown in FIG. 5A. A stepped arm gap 422 may be formed between the stepped portions 430 of the aligned arms 414. A main arm gap 424 may be formed between the main portions 428 of the aligned arms 414.

[0109] 5B and 5C, the anchor electrode 412 can have a variety of configurations. For example, with reference to FIG. 5B, in an embodiment, the electrode arm 414 of the anchor electrode 412 may not include a step. For example, such an electrode may be posed in a C-shaped configuration without a step. With reference to FIG. 5C, the step 426 may be offset from the inner lateral edge 427 of the arm 414 of the anchor electrode 412. Still other configurations are possible. For example, in an embodiment, the step 426 may be offset from both the outer lateral edge 425 and the inner lateral edge 427.

[0110] Referring to FIG. 6, a schematic cross-sectional side view of another embodiment of a broadband stacked capacitor is provided. Similar to the capacitor 100 shown in FIG. 1A, the stacked capacitor 600 shown in the embodiment of FIG. 6 includes a monolithic body 98 including multiple dielectric layers stacked in a Z-direction 136 and extending between a first end 19 and an opposing second end 21. A first external termination 118 is disposed along the first end 19, and a second external termination 120 is disposed along the second end 21. The first external termination 118 includes a first portion 140 that extends along an outer surface, such as the lower surface 20, of the monolithic body, and similarly, the second external termination 120 includes a first portion 144 that extends along an outer surface, such as the lower surface 20, of the monolithic body. The first portion 140 of the first external termination 118 is spaced from the first portion 144 of the second external termination 120 by a first external termination spacing distance 142. Similarly, in one embodiment, the first external termination 118 includes a second portion 146 that extends along the other outer surface, such as the top surface 18, of the monolithic body, and the second external termination 120 includes a second portion 150 that extends along the other outer surface, such as the top surface 18, of the monolithic body. The second portion 146 of the first external termination 118 is spaced from the second portion 150 of the second external termination 120 by a second external termination spacing distance 148. The first external termination spacing distance 142 and / or the second external termination spacing distance 148 can be configured as described with respect to the capacitor 100 shown in FIG. 1A, e.g., the first external termination spacing distance 142 can be the same as or different from the second external termination spacing distance 148 and / or can be within one of the ranges specified.

[0111] 6, in some embodiments, the dielectric region 12 and / or the additional dielectric region 115 may be devoid of electrode layers extending from the first end 19 or the second end 21 of the capacitor 600 for more than about 40% of the length 17 of the capacitor 600. For example, in such embodiments, the dielectric region 12 and / or the additional dielectric region 115 may include one or more floating electrodes and / or dummy electrode tabs. However, in other embodiments, the dielectric region 12 and / or the additional dielectric region 115 may be devoid of all electrode layers, for example, as described above with reference to FIG. 1A.

[0112] In some embodiments, the broadband multilayer ceramic capacitor 600 may not have a shielding electrode 22, 24 above the plurality of active electrode layers 102, 104 in the Z direction 136. For example, in some embodiments, the broadband multilayer ceramic capacitor 600 may not have a shielding electrode 22, 24 above the lowest active electrode layer 101 of the plurality of active electrode layers 102, 104 in the Z direction 136. Further, in some embodiments, the capacitor 600 may not have a shielding electrode 22, 24 below the plurality of active electrode layers 102, 104 in the Z direction 136. For example, in some embodiments, the capacitor 600 may not have a shielding electrode 22, 24 below the highest active electrode layer 103 of the plurality of active electrode layers 102, 104 in the Z direction 136.

[0113] As previously described, in some embodiments, the capacitor 600 includes dummy tab electrodes 52, 54, which may aid in the deposition and / or formation of the terminals 118, 120, for example, using a fine copper termination process. The dummy tab electrodes 52, 54 may extend less than about 40% of the capacitor length 17 from the first end 19 or the second end 21. For example, in some embodiments, the dummy tab electrodes 52, 54 may extend less than about 40%, in some embodiments less than about 30%, in some embodiments less than about 25%, in some embodiments less than about 20%, in some embodiments less than about 15%, and in some embodiments less than about 10% of the capacitor length 17. Also, in some embodiments, the region 115 between the shield electrode region 16 and the active electrode region 14 may include dummy tab electrodes 55, 57, which may be configured similarly to the dummy tab electrodes 52, 54.

[0114] In an embodiment, the capacitor 100 may include one or more floating electrodes. In the embodiment of FIG. 6, the floating electrode 152 is positioned in the dielectric region 12. However, in other embodiments, the one or more floating electrodes 152 may be positioned in the active electrode region 14. Generally, such floating electrodes 152 are not directly connected to the external terminations 118, 120. The floating electrodes 152 may be positioned and configured according to any method known in the art. For example, the one or more floating electrodes may be provided to overlap at least a portion, such as a central portion, of the first and / or second active electrodes of the active electrode layer. In this regard, the floating electrode layer may be layered and arranged in an alternating manner with the first and second electrode layers, and in this regard, such layers may be separated by a dielectric layer. Also, such floating electrodes may have any shape as generally known in the art. For example, in one embodiment, the floating electrode layer may include at least one floating electrode having a dagger-like configuration. In other embodiments, the floating electrode may be similar in configuration and shape to the first active electrode layer 102 as described herein.

[0115] FIG. 7 illustrates another example embodiment of a capacitor 700 according to aspects of the disclosure. The capacitor 700 may generally be similar to the capacitor 100 of FIG. 1A, except that the capacitor 700 of FIG. 7 may include an additional shielding electrode region 166 and may include a first active electrode layer 102 having two active electrodes 106, 108 and a second active electrode layer 104 having two active electrodes 107, 109, as further described in connection with FIGS. 8A-8C. The capacitor 700 may generally be symmetrical about a longitudinal centerline 165. The additional shielding electrode region 166 may be generally configured like the shielding electrode region 16. The dielectric region 168 between the active electrode region 14 and the additional shielding electrode region 166 may generally be absent or absent from the electrode layer that extends for more than 40% of the length 17 of the capacitor 700 (e.g., the region 168 may include a dummy electrode in some embodiments). Capacitor 700 may be mounted to mounting surface 5 of device 1 as shown in FIG. 7 and described in more detail in connection with FIG. 1A.

[0116] As previously mentioned, in certain embodiments of the capacitor as described herein, each active electrode layer 102, 104 may include one or more active electrodes, as shown in connection with the capacitor 700 in FIG. 7. FIG. 8A shows an exploded perspective view of one embodiment of an active electrode pattern for one or more electrodes in the active electrode region 14 according to aspects of the present disclosure. As shown in the embodiment of FIG. 8A, the first electrode layer 102 includes a first active electrode 106 and a second active electrode 108. The first active electrode 106 may be connected to a first external termination 118 (FIG. 7), and the second active electrode 108 may be connected to a second external termination 120 (FIG. 7). A dielectric material 124 separates the first active electrode 106 from the second active electrode 108 within the first active electrode layer 102.

[0117] As further shown in Figure 8A, the second electrode layer 104 can be configured similarly to the depicted first electrode layer 102 of the capacitor 700. In the illustrated embodiment, the depicted second electrode layer 104 comprises a third active electrode 107 and a fourth active electrode 109. The third active electrode 107 can be connected to a first external termination 118 (Figure 7) and the fourth active electrode 109 can be connected to a second external termination 120 (Figure 7). A dielectric material 124 separates the third active electrode 107 from the fourth active electrode 109 within the second active electrode layer 104.

[0118] As further shown in FIG. 8A, the first active electrode 106 can be coplanar with the second active electrode 108. Similarly, the third active electrode 107 can be coplanar with the fourth active electrode 109. Additionally, the first active electrode 106 can overlap the fourth active electrode 109 in the longitudinal direction 132. The first active electrode 106 can overlap the fourth active electrode along an overlap distance 122 (FIG. 7). As shown in FIG. 7 and FIG. 8A, in at least some embodiments, the stacked capacitor 700 can include alternating first active electrode layers 102 and second active electrode layers 104. The side cross-sectional view of FIG. 7 shows that the capacitor 700 has a total of four first electrode layers 102 and three second electrode layers 104. However, it should be understood that any number of electrode layers 102, 104 can be used to obtain a desired capacitance for a desired application.

[0119] 8B and 8C, a capacitive region can be formed between the first active electrode 106 and the second active electrode 108 of the first electrode layer 102, and a capacitive region can be formed between the third active electrode 107 and the fourth active electrode 109 of the second electrode layer 104. More specifically, in the embodiment shown in FIG. 8B and 8C, an end gap distance 110 is defined between an end 112 of the first active electrode 106 and an end 114 of the second active electrode 108, and an end gap distance 111 is defined between an end 113 of the third active electrode 107 and an end 117 of the fourth active electrode 109. As shown in the embodiment of FIG. 8B, a capacitive region 116 can be formed between the end 112 of the first active electrode 106 and the end 114 of the second active electrode 108. Additionally, as shown in the embodiment of FIG. 8C, a capacitive region 119 may be formed between an end 113 of the third active electrode 107 and an end 117 of the fourth active electrode 109 .

[0120] Referring to FIG. 9, a schematic cross-sectional side view of another embodiment of a capacitor 900 is provided. It is understood that the capacitor 900 may be similar to the capacitor 100 previously described in connection with FIG. 1A. However, the capacitor 900 shown in FIG. 9 lacks the shielding electrode region 16 and includes more active electrode layers 102, 104 than the embodiment shown in FIG. 1A. Thus, as previously described, some embodiments of a multilayer ceramic capacitor lack a shielding electrode and may include any suitable number of active electrode layers. As also shown in FIG. 9, the capacitor 900 may be mounted to a mounting surface 5 in a device 1 as shown in FIG. 9 and as described in more detail in connection with FIG. 1A.

[0121] Additionally, the dielectric region 12 between the active electrodes 102, 104 and the top surface 18 and bottom surface 20 of the capacitor 900 is relatively thin, such that the outermost active-to-surface distance 60 between the outermost active electrode layer and the exterior surface (such as between the lowest active electrode layer 101 and bottom surface 20 as shown in FIG. 9) is relatively small. For example, the ratio of the capacitor thickness 56 to the outermost active-to-surface distance 60 can be greater than about 2. For example, in some embodiments, the ratio of the capacitor thickness 56 to the outermost active-to-surface distance 60 can be 1.1 or greater, in some embodiments, 2 or greater, in some embodiments, 3 or greater, in some embodiments, 5 or greater, in some embodiments, 10 or greater, in some embodiments, 20 or greater, in some embodiments, 30 or greater, in some embodiments, 40 or greater, and in some embodiments, 50 or greater. Further, in some embodiments, the distance 60 from the outermost active surface can be 150 microns or less, in some embodiments, 125 microns or less, in some embodiments, 100 microns or less, in some embodiments, 90 microns or less, in some embodiments, 75 microns or less, in some embodiments, 60 microns or less, in some embodiments, 40 microns or less, in some embodiments, 25 microns or less, in some embodiments, 15 microns or less, in some embodiments, 10 microns or less, and in some embodiments, 5 microns or less.

[0122] II. Test Method A test assembly may be used to test performance characteristics, such as insertion loss and return loss, of a capacitor according to aspects of the present disclosure. For example, the capacitor may be mounted on a test board. Input and output lines may be connected to the test board. The test board may include microstrip lines that electrically connect the input and output lines to respective external terminations of the capacitor.

[0123] An input signal can be applied to the input line using a source signal generator (e.g., an 1806 Keithley 2400 series Source Measure Unit (SMU), such as a Keithley 2410-C SMU), and the resulting output signal of the capacitor can be measured at the output line (e.g., using the source signal generator). This is repeated for capacitors of various configurations to generate insertion loss curves, such as those described below in connection with Examples 1-3.

[0124] III. Working Examples Example 1 FIG. 10 shows a number of insertion loss response curves 1000 (S 21 ) is shown. The plurality of capacitors 100 have an outermost active-to-surface distance 60 of approximately 1.2 mils or 30.5 microns. Each capacitor 100 of the plurality of capacitors 100 is mounted to a test substrate in a horizontal orientation, with the electrodes of the capacitor 100 extending parallel to the test substrate.

[0125] As shown by response curve 1000, the insertion loss of the capacitor was greater than -0.20 dB for frequencies ranging from about 1 GHz to about 12 GHz and from about 22 GHz to about 32 GHz. The insertion loss of the capacitor was greater than -0.30 dB for frequencies ranging from about 12 GHz to about 22 GHz and from about 32 GHz to about 37 GHz. The insertion loss of the capacitor was greater than -0.60 dB for frequencies ranging from about 37 GHz to about 47 GHz. The insertion loss of the capacitor was greater than -0.80 dB for frequencies ranging from about 47 GHz to about 60 GHz and greater than -0.90 dB for frequencies ranging from about 60 GHz to about 67 GHz.

[0126] Example 2 FIG. 11 shows a number of insertion loss response curves 1100 (S1100) for a number of broadband multilayer ceramic capacitors 100 having a 0201 case size, a capacitance of 220 nF, and a first external termination spacing distance 142 of about 10 mils or about 250 microns. 21 ) is shown. The plurality of capacitors 100 have an outermost active-to-surface distance 60 of approximately 1.2 mils or 30.5 microns. Each capacitor 100 of the plurality of capacitors 100 is mounted to a test substrate in a horizontal orientation, with the electrodes of the capacitor 100 extending parallel to the test substrate.

[0127] As shown by response curve 1100, the capacitor insertion loss was greater than -0.25 dB for frequencies ranging from about 1 GHz to about 15 GHz and from about 25 GHz to about 37 GHz. The capacitor insertion loss was greater than about -0.50 dB for frequencies ranging from about 15 GHz to about 25 GHz and from about 37 GHz to about 60 GHz. The capacitor insertion loss was greater than -0.60 dB for frequencies ranging from about 60 GHz to about 67 GHz.

[0128] Example 3 FIG. 12 shows a number of insertion loss response curves 1200 (S) for a number of broadband multilayer ceramic capacitors 100 having a 0201 case size, a capacitance of 100 nF, an outermost active-to-surface distance 60 of approximately 1.4 mils or 35.6 microns, and a capacitor thickness 56 of 22 mm. 21 ) Each capacitor 100 of the plurality of capacitors 100 is mounted to a test substrate in a horizontal orientation, with the electrodes of the capacitor 100 extending parallel to the test substrate.

[0129] FIG. 12 shows a number of insertion loss response curves 1250 (S) for a number of stacked capacitors 100 having a 0201 case size, a capacitance of 100 nF, an outermost active to surface distance 60 of approximately 1.2 mils or 30.5 microns, and a capacitor thickness 56 of 15 mm. 21Each capacitor 100 of the plurality of capacitors 100 is mounted to a test substrate in a horizontal orientation, with the electrodes of the capacitor 100 extending parallel to the test substrate.

[0130] As shown by curve 1200 in FIG. 12, the insertion loss of the 22 mm thick capacitor was greater than −0.50 dB for frequencies ranging from about 1 GHz to about 43 GHz, greater than −1.00 dB for frequencies ranging from about 43 GHz to about 60 GHz, and greater than −1.20 dB for frequencies ranging from about 60 GHz to about 67 GHz.

[0131] As shown by curve 1250 in FIG. 12, the insertion loss of the 15 mm thick capacitor was greater than −0.50 dB for frequencies ranging from about 1 GHz to about 37 GHz, greater than −1.00 dB for frequencies ranging from about 37 GHz to about 48 GHz and from about 53 GHz to about 67 GHz, and greater than −1.20 dB for frequencies ranging from about 48 GHz to about 53 GHz.

[0132] These and other modifications and variations of the present invention may be implemented by those skilled in the art without departing from the spirit and scope of the present invention. It should also be understood that aspects of the various embodiments can be substituted in whole or in part. Moreover, those skilled in the art will appreciate that the foregoing description is by way of example only and is not intended to limit the invention as further described in the appended claims. [Explanation of symbols]

[0133] 1 Device 5 Mounting surface 10 electrode area 12 Dielectric Region 14 Active electrode area 15 Shielding electrode layer 16 Shield electrode area 17 Capacitor length 18 Top 19 First End 20 Bottom side 21 Second End 22 First shielding electrode 24 Second shielding electrode 25 steps 26 Shielding electrode layer 28 first longitudinal edge 30 Second horizontal edge 32 Shield electrode offset distance 34 First shielding capacity area 36 Second shielding capacity area 38 Width of first longitudinal edge 28 40 Width of the first shielding electrode 22 42 First shielding gap distance 44 Second shielding gap distance 46 Third shielding gap distance 48 Third Longitudinal Edge 50 Longitudinal centerline 51 Third shielding capacity area 52, 54 Dummy tab electrodes 55, 57 Dummy tab electrodes 56 Capacitor thickness 58 Dielectric Region Thickness 59 Active electrode area thickness 60 Distance from outermost active site to surface 61 Shield electrode area thickness 63 Distance from outermost occlusion to surface 67 Distance from occlusion to activity 98 Monolithic Body 100 Wideband multilayer ceramic capacitor 101 lowest active electrode layer 102 First active electrode layer 103 Highest active electrode layer 104 Second active electrode layer 105 Active electrode spacing distance 106 First active electrode 107 Third active electrode 108 Second active electrode 109 Fourth Active Electrode 110 End Gap Distance 111 End clearance distance 112 End of the first active electrode 106 113 End of the third active electrode 107 114 End of second active electrode 108 115 Second or additional dielectric region 116 capacity area 117 End of the fourth active electrode 109 118 First external termination, plated termination 119 Capacity area 120 Second external termination, plated termination 122 Overlap Distance 124 Dielectric Materials 126 Electrode width 132 Longitudinal 134 Horizontal 136 Z direction 137 Outermost shield electrode layer 138 Innermost shielding electrode layer 140 First portion of first external termination 118 142 First outer end spacing distance 144 first portion of second external termination 120 146 second portion of first external termination 118 148 Second outer end spacing 150 Second portion of second external termination 120 152 Floating Electrode 166 Additional Shielding Electrode Area 168 Dielectric Region 210 first shielding electrode region 212 second shielding electrode region 214 Ceramic Cover 400 Stacked Capacitor 402 Second Anchor Electrode Region 404 First Anchor Electrode Region 406 Third Anchor Electrode Region 408 Fourth Anchor Electrode Region 410 Anchor electrode layer 412 Anchor Electrode 414 Electrode Arm 416 First Longitudinal Edge 418 Second longitudinal edge 420 Arm deviation distance 422 Step arm gap 424 Main arm clearance 425 outer lateral edge 426 Step 427 Inner lateral edge 428 Main part 430 Step part 600, 700, 900 Wideband multilayer ceramic capacitors 1000, 1100, 1200, 1250 Insertion Loss Response Curves D1, D2 Secondary capacitor P Primary Capacitor

Claims

1. A wideband multilayer ceramic capacitor, a monolithic body including a plurality of dielectric layers stacked in a Z direction, the monolithic body having a first end opposite a second end; a first outer termination disposed along the first end of the monolithic body, the first outer termination including a first portion extending along an outer surface of the monolithic body; a second outer termination disposed along the second end of the monolithic body, the second outer termination including a first portion extending along the outer surface of the monolithic body, the first portion of the first outer termination being spaced from the first portion of the second outer termination by a first outer termination spacing distance; an active electrode area including a plurality of first active electrode layers and a plurality of second active electrode layers, the plurality of first active electrode layers including at least one active electrode that is rectangular in shape, the plurality of second active electrode layers including at least one second active electrode that is rectangular in shape, the plurality of first active electrode layers connected with the first external termination, and the plurality of second active electrode layers connected with the second external termination; Equipped with the active electrode region includes an outermost active electrode layer, the outermost active electrode layer being spaced from the outer surface by an outermost active-to-surface distance; The monolithic body has a thickness along the Z direction, the ratio of the thickness to the distance from the outermost active surface to the surface is 1.1 or more; the capacitor has a longitudinally extending capacitor length; A broadband multilayer ceramic capacitor, wherein the ratio of said capacitor length to said first external termination spacing distance is 15 or greater.

2. 2. The wideband multilayer ceramic capacitor of claim 1, wherein the distance from the outermost active layer to the surface is 150 microns or less.

3. 2. The broadband multilayer ceramic capacitor of claim 1, wherein said first external termination spacing distance is less than or equal to 250 microns.

4. 2. The broadband multilayer ceramic capacitor of claim 1, configured to be mounted on a mounting surface with a first active electrode layer of each of the plurality of first active electrode layers and a second active electrode layer of each of the plurality of second active electrode layers extending parallel to the mounting surface.

5. 5. The broadband multilayer ceramic capacitor of claim 4, exhibiting an insertion loss of greater than about -1.2 dB from about 5 GHz to about 67 GHz.

6. 2. The broadband multilayer ceramic capacitor of claim 1, wherein said outer surface is a bottom surface of said monolithic body.

7. 2. The broadband multilayer ceramic capacitor of claim 1, wherein said outer surface is a top surface of said monolithic body.

8. 10. The broadband multilayer ceramic capacitor of claim 1, further comprising a shield electrode region positioned between said active electrode region and said outer surface.

9. 10. The broadband multilayer ceramic capacitor of claim 1, further comprising a dielectric region positioned between said active electrode region and said second outer surface of said monolithic body in said Z direction.

10. 10. The broadband multilayer ceramic capacitor of claim 9, wherein the second outer surface is opposite the outer surface along the Z direction.

11. 10. The broadband multilayer ceramic capacitor of claim 9, wherein a dielectric region has no electrode layers extending from the first end of the monolithic body or the second end of the monolithic body more than 40% of the capacitor length.

12. 10. The broadband multilayer ceramic capacitor of claim 9, wherein said dielectric region is free of electrode layers.

13. 2. The broadband multilayer ceramic capacitor of claim 1, further comprising at least one floating electrode not connected to the first external termination or the second external termination, the at least one floating electrode being disposed in a dielectric region positioned between a shield electrode region and a top surface of the capacitor in the Z direction.

14. 10. The broadband multilayer ceramic capacitor of claim 1, exhibiting an insertion loss of greater than about -1.0 dB at about 67 GHz.

15. 10. The broadband multilayer ceramic capacitor of claim 1, exhibiting an insertion loss of greater than about -0.6 dB at about 40 GHz.

16. 10. The broadband multilayer ceramic capacitor of claim 1, exhibiting an insertion loss of greater than about -0.2 dB at about 10 GHz.

17. 10. The broadband multilayer ceramic capacitor of claim 1, exhibiting an insertion loss of greater than about -0.5 dB from about 5 GHz to about 20 GHz.

18. 10. The broadband multilayer ceramic capacitor of claim 1, exhibiting an insertion loss of greater than about -0.6 dB from about 20 GHz to about 40 GHz.

19. 10. The broadband multilayer ceramic capacitor of claim 1, exhibiting an insertion loss of greater than about -1.0 dB from about 40 GHz to about 50 GHz.

20. 10. The broadband multilayer ceramic capacitor of claim 1, exhibiting an insertion loss of greater than about -1.2 dB from about 50 GHz to about 60 GHz.

21. 10. The broadband multilayer ceramic capacitor of claim 1, exhibiting an insertion loss of greater than about -1.2 dB from about 60 GHz to about 67 GHz.

22. A mounting surface; A wideband multilayer ceramic capacitor, a monolithic body including a plurality of dielectric layers stacked in a Z direction, the monolithic body having a first end opposite a second end; a first outer termination disposed along the first end of the monolithic body, the first outer termination including a first portion extending along an outer surface of the monolithic body; a second outer termination disposed along the second end of the monolithic body, the second outer termination including a first portion extending along the outer surface of the monolithic body, the first portion of the first outer termination being spaced from the first portion of the second outer termination by a first outer termination spacing distance; and an active electrode area including a plurality of first active electrode layers and a plurality of second active electrode layers, the plurality of first active electrode layers including at least one active electrode that is rectangular in shape, the plurality of second active electrode layers including at least one second active electrode that is rectangular in shape, the plurality of first active electrode layers connected with the first external termination, and the plurality of second active electrode layers connected with the second external termination; A wideband multilayer ceramic capacitor comprising: Equipped with the active electrode region includes an outermost active electrode layer, the outermost active electrode layer spaced from the outer surface by an outermost active-to-surface distance, the monolithic body having a thickness along the Z direction, the ratio of the thickness to the outermost active-to-surface distance being 1.1 or greater; the capacitor has a capacitor length extending in a longitudinal direction, the ratio of the capacitor length to the first outer termination spacing distance being 15 or greater; A device, wherein the broadband multilayer ceramic capacitor is mounted to the mounting surface in a horizontal orientation such that an active electrode layer of each of the plurality of active electrode layers extends parallel to the mounting surface.

23. 23. The device of claim 22, wherein each first active electrode layer of the plurality of first active electrode layers comprises at least one active electrode that is rectangular in shape.

24. 23. The device of claim 22, wherein each second active electrode layer of the plurality of second active electrode layers comprises at least one active electrode that is rectangular in shape.

25. 23. The device of claim 22, wherein the outermost active to surface distance is no greater than 100 microns and the first outer termination spacing distance is no greater than 75 microns.

26. 1. A method for forming a broadband multilayer ceramic capacitor, comprising: forming a plurality of active electrodes on a plurality of active electrode layers, wherein at least one first active electrode layer of the plurality of active electrode layers comprises a first active electrode and at least one second active electrode layer of the plurality of active electrode layers comprises a second active electrode; stacking the plurality of active electrode layers and a plurality of dielectric layers to form a monolithic body having an outer surface, the plurality of active electrode layers including an outermost active electrode layer disposed proximate to the outer surface of the monolithic body of the plurality of active electrode layers; depositing a first external termination along a first end of the capacitor, the first external termination connecting with the first active electrode layer, the first external termination including a first portion extending along the outer surface of the capacitor; depositing a second external termination along a second end of the capacitor opposite the first end, the second external termination connecting with the second active electrode layer, the second external termination including a first portion extending along the outer surface of the capacitor; Including, the outermost active electrode layer is spaced from the outer surface by an outermost active-to-surface distance; The monolithic body has a thickness along the Z direction, the ratio of the thickness to the distance from the outermost active surface to the surface is 1.1 or more; the capacitor has a longitudinally extending capacitor length; wherein a ratio of the capacitor length to a first external termination spacing distance is 15 or greater.

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