Advanced high resolution OLED sub-pixel circuits and patterning methods

Abstract

The embodiments described herein relate to a subpixel. The subpixel includes an anode, an overhang structure, an isolation structure, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by an adjacent first pixel isolation structure (PIS) and an adjacent second PIS. The overhang structure is disposed on the first PIS. The overhang structure includes a second structure disposed on the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past a top surface of the first structure. The first structure is disposed on the first PIS. The isolation structure is disposed on the second PIS. The OLED material is disposed on the anode and on the top surface of the isolation structure. A cathode is disposed on the OLED material and on the top surface of the isolation structure.

Description

[Technical field]

[0001] FIELD OF THE DISCLOSURE The embodiments described herein relate generally to displays. More particularly, the embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in displays, such as organic light emitting diode (OLED) displays. [Background technology]

[0002] Input devices including display devices may be used within a variety of electronic systems. An organic light-emitting diode (OLED) is a light-emitting diode (LED) in which the light-emitting electroluminescent layer is a film of organic compounds that emits light in response to an electric current. OLED devices are classified as bottom-emitting devices if the emitted light passes through a transparent or semi-transparent bottom electrode and substrate on which the panel is fabricated. Top-emitting devices are classified based on whether the light emitted from the OLED device passes through a lid that is added after the device is fabricated. OLEDs are used today to make display devices for many electronic devices. Today's electronics manufacturers are pushing to reduce the size of these display devices while at the same time providing higher resolution than was possible just a few years ago.

[0003] Currently, the patterning of OLED pixels is based on processes that limit panel size, pixel resolution, and substrate size. Photolithography should be used to pattern the pixels, rather than utilizing fine metal masks. Currently, the patterning of OLED pixels requires the organic materials to be stripped after the patterning process. When stripped, the organic materials cause particle problems that impair OLED performance. Therefore, there is a need in the art for sub-pixel circuits and methods of forming sub-pixel circuits to increase the number of pixels per inch and provide improved OLED performance. Summary of the Invention

[0004] In one embodiment, a subpixel is provided. The subpixel includes an anode, an overhang structure, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by an adjacent first pixel separating structure (PIS) and an adjacent second PIS. The overhang structure is disposed on the first PIS. The overhang structure includes a second structure disposed on the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past a top surface of the first structure. The first structure is disposed on the first PIS. An isolation structure is disposed on the second PIS. An OLED material is disposed on the anode and on the top surface of the isolation structure. A cathode is disposed on the OLED material and on the top surface of the isolation structure.

[0005] In another embodiment, a device is disclosed. The device includes a plurality of subpixel lines. Each subpixel line includes at least a first subpixel and a second subpixel. The first subpixel and the second subpixel each include an anode, an overhang structure, an isolation structure, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by an adjacent first pixel isolation structure (PIS) and an adjacent second PIS. The overhang structure is disposed on the first PIS. The overhang structure includes a second structure disposed on the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past a top surface of the first structure. The first structure is disposed on the first PIS. The isolation structure is disposed on the second PIS. One of the isolation structures separates the first pixel from the second pixel. The OLED material is disposed on the anode and on a top surface of the isolation structure. The OLED material of the first subpixel and the second subpixel emits a first color, and a cathode is disposed over the OLED material and over a top surface of the separating structure.

[0006] In another embodiment, a method of forming a device is disclosed, the method includes depositing an anode and a PIS layer over a substrate, removing portions of the PIS layer to form a first PIS and a second PIS, depositing a first structural layer, an intermediate layer, and a second structural layer over the substrate, depositing and patterning a first resist over the second structural layer, removing portions of the second structural layer and the intermediate layer using ion beam milling to form a second structure and an intermediate structure, removing the first resist from the second structure, depositing and patterning a second resist over the first structural layer, dry etching and removing portions of the first structural layer to form a first structure, depositing an organic light emitting diode (OLED) material, a cathode, and an encapsulation layer, depositing and patterning a third resist in a first subpixel, ashing and removing portions of the OLED material, the cathode, and the encapsulation layer, and removing the third resist. The second structural layer is deposited by sputter deposition.

[0007] So that the above-listed features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly outlined above may be had by reference to embodiments, some of which are illustrated in the accompanying drawings, which should be noted, however, that the accompanying drawings represent only exemplary embodiments and therefore should not be considered as limiting the scope of the present disclosure, which may embrace other embodiments that are equally effective. [Brief description of the drawings]

[0008] [Figure 1A] 1A is a schematic cross-sectional view of a subpixel circuit taken along section line 1A-1A, according to an embodiment. [Figure 1B] FIG. 1B is a schematic cross-sectional view of a subpixel circuit taken along section line 1B-1B, according to an embodiment. [Figure 1C] 1C is a schematic cross-sectional view of a sub-pixel circuit having a line-type architecture, according to an embodiment, taken along section line 1C-1C. [Diagram 2] 1 is a schematic cross-sectional view of an overhang structure according to an embodiment. [Diagram 3] 4 is a flow diagram of a method for forming a sub-pixel, according to an embodiment. [Figure 4A] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4B] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4C] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4D] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4E] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4F] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4G] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4H] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4I] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4J] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4K] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4L] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4M] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4N] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4O]1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4P] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4Q] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 4R] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Diagram 5] 1 is a schematic cross-sectional view of an overhang structure according to an embodiment. [Figure 6] 4 is a flow diagram of a method for forming a sub-pixel, according to an embodiment. [Figure 7A] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7B] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7C] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7D] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7E] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7F] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7G] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7H] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7I] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7J] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7K]1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7L] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7M] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7N] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7O] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7P] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7Q] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 7R] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 8] 1 is a schematic cross-sectional view of an overhang structure according to an embodiment. [Figure 9] 4 is a flow diagram of a method for forming a sub-pixel, according to an embodiment. [Figure 10A] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10B] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10C] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10D] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10E] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10F] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10G]1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10H] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10I] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10J] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10K] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10L] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10M] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10N] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10O] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10P] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10Q] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. [Figure 10R] 1A-1D are schematic cross-sectional views of a substrate during a method of forming a sub-pixel according to an embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] For ease of understanding, the same reference numbers have been used, where possible, to designate identical elements common to the figures, and it is contemplated that elements disclosed in one embodiment may be beneficially utilized on other embodiments unless specifically stated otherwise.

[0010] FIELD OF THE DISCLOSURE The embodiments described herein relate generally to displays. More particularly, the embodiments described herein relate to sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in displays, such as organic light emitting diode (OLED) displays. In various embodiments, the sub-pixels use advanced overhang structures to enhance the functionality of the displays.

[0011] In one embodiment, a subpixel is provided. The subpixel includes an anode, an overhang structure, an isolation structure, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by an adjacent first pixel isolation structure (PIS) and an adjacent second PIS. The overhang structure is disposed on the first PIS. The overhang structure includes a second structure disposed on the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past a top surface of the first structure. The first structure is disposed on the first PIS. The isolation structure is disposed on the second PIS. The OLED material is disposed on the anode and on the top surface of the isolation structure. A cathode is disposed on the OLED material and on the top surface of the isolation structure.

[0012] In one embodiment, a device is disclosed. The device includes a plurality of subpixel lines. Each subpixel line includes at least a first subpixel and a second subpixel. The first subpixel and the second subpixel each include an anode, an overhang structure, an isolation structure, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by an adjacent first pixel isolation structure (PIS) and an adjacent second PIS. The overhang structure is disposed on the first PIS. The overhang structure includes a second structure disposed on the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past a top surface of the first structure. The first structure is disposed on the first PIS. The isolation structure is disposed on the second PIS. One of the isolation structures separates the first pixel from the second pixel. The OLED material is disposed on the anode and on a top surface of the isolation structure. The OLED material of the first subpixel and the second subpixel emits a first color, and a cathode is disposed over the OLED material and over a top surface of the separating structure.

[0013] In another embodiment, a method of forming a device is disclosed, the method includes depositing an anode and a PIS layer over a substrate, removing portions of the PIS layer to form a first PIS and a second PIS, depositing a first structural layer, an intermediate layer, and a second structural layer over the substrate, depositing and patterning a first resist over the second structural layer, removing portions of the second structural layer and the intermediate layer using ion beam milling to form a second structure and an intermediate structure, removing the first resist from the second structure, depositing and patterning a second resist over the first structural layer, dry etching and removing portions of the first structural layer to form a first structure, depositing an organic light emitting diode (OLED) material, a cathode, and an encapsulation layer, depositing and patterning a third resist in a first subpixel, ashing and removing portions of the OLED material, the cathode, and the encapsulation layer, and removing the third resist. The second structural layer is deposited by sputter deposition.

[0014] Each of the embodiments of the subpixel circuit described herein includes a plurality of subpixels, each of which is defined by adjacent overhanging structures present in the subpixel circuit. Although the figures show two subpixels, each of which is defined by adjacent overhanging structures, the subpixel circuits of the embodiments described herein include a plurality of subpixels, such as two or more subpixels. Each subpixel has an OLED material configured to emit white, red, green, blue, or other color light when energized. For example, the OLED material of a first subpixel emits red light when energized, the OLED material of a second subpixel emits green light when energized, and the OLED material of a third subpixel emits blue light when energized.

[0015] The overhangs are permanent in the subpixel circuit, and include at least a second structure disposed on the first structure. The adjacent overhang structures that define each subpixel of the subpixel circuit of the display define the formation of the subpixel circuit using deposition, and define that the overhang structures remain in place after the subpixel circuit is formed. Evaporation is used to deposit the OLED materials (including the hole injection layer (HIL), hole transport layer (HTL), emissive layer (EML) and electron transport layer (ETL)) and the cathode. In some examples, an encapsulation layer may be disposed by deposition. In embodiments that include one or more capping layers, the capping layer is disposed between the cathode and the encapsulation layer. The overhang structures and the deposition angle set by the deposition source define the deposition angle. That is, the overhang structures, together with the deposition angle set by the deposition source, define the shadowing effect during deposition. To deposit at a specific angle, the deposition source is configured to emit deposition material at a specific angle relative to the overhang structures. An encapsulation layer for each subpixel is disposed over the cathode, with the encapsulation layer extending under at least a portion of each adjacent overhang structure and along a sidewall of each adjacent overhang structure.

[0016] FIG. 1A is a schematic cross-sectional view of a sub-pixel circuit 100 according to an embodiment. The cross-sectional view of FIG. 1A is taken along section line 1A-1A (e.g., pixel plane) of FIG. 1C. FIG. 1B is a schematic cross-sectional view of a sub-pixel circuit 100 according to an embodiment. The cross-sectional view of FIG. 1B is taken along section line 1B-1B (e.g., line plane) of FIG. 1C. The sub-pixel circuit 100 includes a substrate 102. A base layer 121 may be patterned on the substrate 102. The base layer 121 may include, but is not limited to, a CMOS layer. A metal-containing layer (e.g., anode 104) may be patterned on the base layer 121, and the metal-containing layer (e.g., anode 104) is defined by adjacent first pixel separating structures (PIS) 126A and second PIS 126B disposed on the substrate 102. In one embodiment, the anode 104 is pre-patterned on the base layer 121. For example, the base layer 121 is pre-patterned with an indium tin oxide (ITO) anode 104. The anode 104 may be disposed on the substrate 102. The anode 104 is configured to act as the anode for each subpixel. In one embodiment, the anode 104 is a layer stack of a first transparent conductive oxide (TCO) layer, a second metal-containing layer disposed on the first TCO layer, and a third TCO layer disposed on the second metal-containing layer. The anode 104 may include, but is not limited to, chromium, titanium, gold, silver, copper, aluminum, ITO, combinations thereof, or other suitable conductive materials.

[0017] The first PIS 126A and the second PIS 126B are disposed on the substrate 102. The first PIS 126A and the second PIS 126B may be disposed on the base layer 121. The first PIS 126A is disposed along a line plane. The line plane extends along a first direction. The second PIS 126B is disposed along a pixel plane. The pixel plane extends along a second direction. The first direction is perpendicular to the second direction. The first PIS 126A and the second PIS 126B include one of an organic material, an organic material having an inorganic coating disposed thereon, or an inorganic material. The organic material of the first PIS 126A and the second PIS 126B includes, but is not limited to, polyimide. The inorganic material of the first PIS 126A and the second PIS 126B includes, but is not limited to, silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (Si 2 N 2 O), magnesium fluoride (MgF 2 ) or a combination thereof. Adjacent first and second PISs 126A and 126B define respective sub-pixels and expose the anode 104 of each sub-pixel circuit 100.

[0018] The subpixel circuit 100 has a number of subpixel lines (e.g., a first subpixel line 106A and a second subpixel line 106B). The subpixel lines are adjacent to each other along a pixel plane. Each subpixel line includes at least two subpixels. For example, the first subpixel line 106A includes a first subpixel 108A and a second subpixel 108B, and the second subpixel line 106B includes a third subpixel 108C and a fourth subpixel 108D. The first subpixel 108A and the second subpixel 108B are aligned along the line plane. The third subpixel 108C and the fourth subpixel 108D are aligned along the line plane. Although FIG. 1A shows a first subpixel line 106A and a second subpixel line 106B, the subpixel circuit 100 of the embodiments described herein may include more than one subpixel line, such as a third subpixel line 106C (shown in FIG. 1B) and a fourth subpixel. Each subpixel line has an OLED material configured to emit white, red, green, blue, or other color light when energized. For example, the OLED material of the first subpixel line 106A emits red light when energized, the OLED material of the second subpixel line 106B emits green light when energized, the OLED material of the third subpixel line 106C emits blue light when energized, and the OLED material of the fourth subpixel emits another color light when energized. The OLED material within one pixel line may be configured to emit the same color light when energized. For example, the OLED material of the first subpixel 108A and the second subpixel 108B in the first subpixel line 106A emits red light when energized, and the OLED material of the third subpixel 108C and the fourth subpixel 108D in the second subpixel line 106B emits green light when energized.

[0019] Each subpixel line includes adjacent overhang structures 110, and adjacent subpixel lines share adjacent overhang structures 110 in the pixel plane. The overhang structures 110 are present in the subpixel circuit 100. The overhang structures 110 further define each subpixel line of the subpixel circuit 100. Each overhang structure 110 includes adjacent overhangs 109. The adjacent overhangs 109 are defined by overhang extensions 109A of the second structure 110B that extend laterally past the top surface 105 of the first structure 110A. The first structure 110A is disposed on the top surface 103A of the first PIS 126A. The first end point 120A of the bottom surface 118 of the first structure 110A may extend to or past the first edge 117A of the first PIS 126A. The second end point 120B of the bottom surface of the first structure 110A may extend to or past the second edge 117B of the first PIS 126A. The second structure 110B is disposed on the first structure 110A. The second structure 110B may be disposed on the top surface 105 of the first structure 110A. The second structure 110B may also be disposed on the intermediate structure 110C. The intermediate structure 110C may be disposed on the top surface 105 of the first structure 110A. The intermediate structure 110C may be a seed layer or an adhesion layer. The seed layer functions as a current path for the subpixel circuit 100. The seed layer may include a titanium (Ti) material. The adhesion promotion layer improves adhesion between the first structure 110A and the second structure 110B. The adhesion layer may include a chromium (Cr) material.

[0020] In one embodiment, the overhang structure 110 includes a second structure 110B of a conductive inorganic material and a first structure 110A of a non-conductive inorganic material. The conductive material of the second structure 110B includes copper (Cu), aluminum (Al), aluminum neodymium (AlNd), molybdenum (Mo), molybdenum tungsten (MoW), or combinations thereof. The non-conductive material of the first structure 110A includes amorphous silicon (a-Si), titanium (Ti), silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), silicon oxynitride (Si 2 N 2 O) or a combination thereof. The overhang structure 110 can remain in place, i.e., the overhang structure 110 is permanent.

[0021] Adjacent overhangs 109 are defined by overhang extensions 109A. To form overhang extensions 109A, at least the bottom surface 107 of the second structure 110B is wider than the top surface 105 of the first structure 110A. The overhang extensions 109A of the second structure 110B form overhangs 109 and allow the second structure 110B to shadow the first structure 110A. The shadowing of the overhangs 109 defines the deposition of OLED material 112 and cathode 114. The OLED material 112 may include one or more of an HIL, an HTL, an EML, and an ETL. The OLED material 112 is disposed over and in contact with the anode 104. The OLED material 112 may be disposed under adjacent overhangs 109 and in contact with the sidewalls 111 of the first structure 110A. In one embodiment, the OLED material 112 is different from the material of the first structure 110A, the second structure 110B, and the intermediate structure 110C. The cathode 114 is disposed on the OLED material 112 and extends under the adjacent overhang 109. The cathode 114 may extend past the end of the OLED material 112. The cathode 114 may contact the sidewall 111 of the first structure 110A. The overhang structure 110 and the deposition angle set by the deposition source define the deposition angle. That is, the overhang structure together with the deposition angle set by the deposition source define the shadowing effect during deposition.

[0022] The cathode 114 includes a conductive material such as a metal. For example, the cathode 114 includes, but is not limited to, silver, magnesium, chromium, titanium, aluminum, ITO, or a combination thereof. In one embodiment, the material of the cathode 114 is different from the materials of the first structure 110A, the second structure 110B, and the intermediate structure 110C. In some embodiments, the OLED material 112 and the cathode 114 are disposed on the sidewall 113 of the second structure 110B of the overhang structure 110 in the pixel plane, for example, as shown in FIG. 1A as applied to the subpixel circuit 100. In other embodiments, the OLED material 112 and the cathode 114 are disposed on the top surface 115 of the second structure 110B of the overhang structure 110 in the pixel plane. In other embodiments, the OLED material 112 and the cathode 114 end on the sidewall 111 of the first structure 110A. That is, OLED material 112 and cathode 114 are not disposed on the sidewalls 113 of second structure 110B or on the top surface 115 of second structure 110B in the pixel plane.

[0023] Each subpixel 106 includes an encapsulation layer 116. The encapsulation layer 116 may be or may correspond to a local passivation layer. The encapsulation layer 116 of each subpixel is disposed over the cathode 114 (and the OLED material 112), and the encapsulation layer 116 extends along the sidewall 111 of each of the first structure 110A and the second structure 110B under at least a portion of each of the overhangs 109. The encapsulation layer 116 is disposed over the cathode 114 and extends in the pixel plane to contact at least the cathode 114 over the sidewall 111 of the first structure 110A. In some embodiments, the encapsulation layer 116 extends to contact the sidewall 111 of the first structure 110A. 1A and 1B, the encapsulation layer 116 extends to contact the second structure 110B at the underside of the overhanging extension 109A, the sidewalls 113 of the second structure 110B, and the top surface 115 of the second structure 110B. In some embodiments, the encapsulation layer 116 extends to contact the second structure 110B at the underside of the overhanging extension 109A and extends to be disposed above the OLED material 112 and the cathode 114 when the OLED material 112 and the cathode 114 are disposed on the sidewalls 113 and top surface 115 of the second structure 110B. In some embodiments, the encapsulation layer 116 terminates at the sidewalls 111 of the first structure 110A. That is, the encapsulation layer 116 is not disposed on the sidewall 113 of the second structure 110B of the overhang structure 110, the top surface 115 of the second structure 110B, or the bottom surface of the overhang extension 109A. The encapsulation layer 116 comprises a non-conductive inorganic material, such as a silicon-containing material. The silicon-containing material may be Si 3 N 4 The material may include

[0024] Each subpixel line includes adjacent isolation structures 125, and in the line plane, adjacent subpixels share adjacent isolation structures 125. The isolation structures 125 are present in the subpixel circuit 100. The isolation structures 125 further define each subpixel of the subpixel line of the subpixel circuit 100. The isolation structures 125 are disposed on the top surface 103B of the second PIS 126B. A first end point 129A of a bottom surface 128 of the isolation structure 125 may extend to or past the first edge 127A of the second PIS 126B. A second end point 129B of a bottom surface 128 of the isolation structure 125 may extend to or past the second edge 127B of the second PIS 126B.

[0025] OLED material 112 is disposed in the line plane over and in contact with anode 104 and isolation structures 125. Cathode 114 is disposed in the line plane over OLED material 112. Encapsulation layer 116 is disposed in the line plane over cathode 114. As shown in FIG. 1B, OLED material 112, cathode 114 and encapsulation layer 116 maintain continuity along the length of the line plane to pass current across each subpixel 106.

[0026] In embodiments including one or more capping layers, the capping layer is disposed between the cathode 114 and the encapsulation layer 116. For example, a first capping layer and a second capping layer are disposed between the cathode 114 and the encapsulation layer 116. Each of the embodiments described herein may include one or more capping layers disposed between the cathode 114 and the encapsulation layer 116. The first capping layer may include an organic material. The second capping layer may include an inorganic material, such as lithium fluoride. The first capping layer and the second capping layer may be deposited by evaporation. In another embodiment, the subpixel circuit 100 further includes at least one global passivation layer disposed over the overhang structure 110 and the encapsulation layer 116. In yet another embodiment, the subpixel includes an intermediate passivation layer disposed over the overhang structure 110 of each of the subpixels 106 and between the encapsulation layer 116 and the global passivation layer.

[0027] FIG 1C is a schematic cross-sectional view of a subpixel circuit 100 having a line-based architecture 101C, according to an embodiment. The top cross-sectional view of FIG 1C is taken along section line 1C-1C of FIG 1A. The line-based architecture 101C includes a plurality of pixel apertures 124. As shown in FIG 1A and FIG 1B, each of the pixel apertures 124 is bounded by an overhanging structure 110 in the pixel plane and bounded by an isolation structure 125 in the line plane, with the overhanging structure 110 and the isolation structure 125 defining each of the subpixel lines and subpixels of the line-based architecture 101C.

[0028] FIG. 2 is a schematic cross-sectional view of overhang structure 110. Overhang structure 110 is shown without OLED material 112, cathode 114, encapsulation layer 116, base layer 121, or substrate 102. Top surface 115 of second structure 110B has a width W1 from first bottom edge 152A to second bottom edge 152B. Width W1 is about 0.4 μm to about 1.2 μm. Bottom surface 118 of first structure 110A has a width W2 from first end point 120A of bottom surface 118 to second end point 120B of bottom surface 118. Width W2 is about 0.6 μm to about 1.4 μm. Top surface 105 of first structure 110A has a width W3. Width W3 is 0.2 μm to about 0.8 μm. The first PIS 126A has a width W4 from the first edge 117A to the second edge 117B. The width W4 is 0.4 μm to about 1.2 μm. The width W4 and the width W1 may be equal or approximately equal. The upper surface 115 of the second structure 110B has a width W5. The width W5 is about 0.2 μm to about 1.0 μm.

[0029] The overhanging structure 110 has a height H1 from the top surface 103A of the first PIS 126A to the bottom surface 107 of the second structure 110B. The height H1 is about 0.1 μm to about 0.5 μm. The height H1 may be the height of the first structure 110A, or may be the height of the first structure 110A and the intermediate structure 110C. The second structure 110B has a height H2 from the bottom surface 107 to the top surface 115. The height H2 is about 0.15 μm to about 0.25 μm. The width of the top surface 115 of the second structure 110B is smaller than the width of the bottom surface 107 of the second structure 110B. The sidewall 113 of the second structure 110B has an angle θ of about 15° to about 45° with respect to the overhanging vector 154.

[0030] The subpixel circuit 100 has a pitch p. The pitch p is the distance from the first edge 117A of the first PIS 126A to the first edge 117A of the adjacent first PIS 126A. The pitch p is about 2 μm to about 8 μm. The subpixel circuit 100 has a distance D1 from the second end point 120B of the first structure 110A of the overhang structure 110 to the first end point 120A of the first structure 110A of the adjacent overhang structure 110. The distance D1 is about 2 μm to about 6 μm. The subpixel circuit 100 has a distance D2 (e.g., the width of the anode 104) from the second edge 117B of the first PIS 126A to the first edge 117A of the first PIS 126A of the adjacent overhang structure 110. The distance D2 is 2 μm to about 6 μm. The distance D1 and the distance D2 may be equal or approximately equal. The overhanging structure 110 has a distance D3 from the first lower edge 152A or the second lower edge 152B of the second structure 110B to the sidewall 111 of the first structure 110A. The distance D3 is less than about 0.15 μm.

[0031] 3 is a flow diagram of a method 300 for forming a sub-pixel circuit 100, according to an embodiment. Figures 4A-4R are schematic cross-sectional views of a substrate 102 during a method 300 for forming a sub-pixel circuit 100, according to an embodiment described herein.

[0032] In operation 301, the anode 104 is deposited on the substrate 102 as shown in FIG. 4A (along the pixel plane). The anode 104 may be deposited on the substrate 102. In another embodiment, the anode 104 is deposited on a base layer 121. The base layer 121 is disposed on the substrate 102. The anode 104 may be deposited using metal-organic decomposition (MOD). An anode gap 104A separates the anode 104 from an adjacent anode 104.

[0033] In operation 302, a PIS layer 426 is deposited on the substrate 102 as shown in FIG 4B (along the pixel plane). The PIS layer 426 may be deposited on the anode 104 and on the base layer 121 in the anode gap 104A. The height H3 from the base layer 121 to the top surface 403 of the PIS layer 426 is about 400 nm to about 700 nm.

[0034] In operation 303, a portion of the PIS layer 426 is removed as shown in FIG. 4C (along the pixel plane). The PIS layer 426 may be removed by a wet etching process or a dry etching process. Operation 303 exposes the anode 104 and forms a plurality of first PIS 126A and second PIS 126B. In operation 304, the first PIS 126A and second PIS 126B are planarized as shown in FIG. 4D (along the pixel plane). The top surface 103A of the first PIS 126A and the top surface 103B of the second PIS 126B are aligned with the top surface of the anode 104. The first PIS 126A and second PIS 126B are cured at a temperature of about 140° C. to about 180° C. for about 10 minutes to about 20 minutes. This curing of the first PIS 126A and the second PIS 126B allows the first PIS 126A and the second PIS 126B to shrink. Planarization of the first PIS 126A and the second PIS 126B is performed after curing. This planarization process of the first PIS 126A and the second PIS 126B may be performed using chemical mechanical planarization (CMP).

[0035] In operation 305, a first structural layer 410A, a second structural layer 410B, and an intermediate layer 410C are deposited on the substrate 102 as shown in FIG. 4E (along the pixel plane). The first structural layer 410A is deposited on the anode 104 and on the first PIS 126A and the second PIS 126B. ... intermediate layer 410C. The 1 The intermediate layer 410C is deposited on the first structural layer 410A. The intermediate layer 410C has a thickness t 2The second structural layer 410B is deposited on the intermediate layer 410C. The second structural layer 410B is deposited using sputtering deposition. The second structural layer 410B has a thickness t of about 0.15 μm to about 0.25 μm. 3 has.

[0036] In operation 306, resist 406 is deposited and patterned as shown in FIG. 4F (along the pixel plane). Resist 406 is deposited on top of second structural layer 410B. Resist 406 has a width W of about 0.8 μm to about 1.2 μm. 4 The resist may be a positive resist or a negative resist. A positive resist includes a portion of the resist that, when exposed to electromagnetic radiation, is soluble in a resist developer that is applied to the resist after a pattern is written into the resist using the electromagnetic radiation. A negative resist includes a portion of the resist that, when exposed to radiation, is insoluble in a resist developer that is applied to the resist after a pattern is written into the resist using the electromagnetic radiation. The chemical composition of the resist 406 determines whether the resist is a positive resist or a negative resist. The portion of the resist 406 of the second structural layer 410B disposed thereon is patterned to form the pixel openings 124 of the line-type architecture 101C of the first subpixel line 106A. The patterning is one of a photolithography, a digital lithography process, or a laser ablation process.

[0037] In operation 307, the second structural layer 410B and intermediate layer 410C are removed in portions exposed by pixel opening 124, as shown in FIG. 4G (along the pixel plane). The second structural layer 410B and intermediate layer 410C are removed by ion beam milling. In some embodiments, portions of the first structural layer 410A may be removed, for example, less than about 50 nm of the first structural layer 410A may be removed. Operation 307 forms second structure 110B and intermediate structure 110C. In operation 308, the resist 406 is removed from second structure 110B, as shown in FIG. 4H (along the pixel plane).

[0038] In operation 309, resist 408 is deposited and patterned as shown in FIG. 4I (along the line plane). Resist 408 is deposited over first structural layer 410A. Resist 408 is deposited to a thickness t of less than about 500 nm. 4 The resist 408 has a taper of about 40°-50° from the bottom surface to the top surface, and the bottom surface of the resist 408 has a greater width than the top surface of the resist 408. The resist 408 is a positive resist or a negative resist. The chemical composition of the resist 408 determines whether the resist 408 is a positive resist or a negative resist. The portion of the first structural layer 410A on which the resist 408 is disposed is patterned to form the pixel openings 124 of the line-type architecture 101C of the first subpixel line 106A. The patterning is one of a photolithography, a digital lithography process, or a laser ablation process.

[0039] In operation 310, the portions of the first structural layer 410A exposed by the pixel opening 124 and the resist 408 are removed, as shown in FIG. 4J (along the pixel plane) and FIG. 4K (along the line plane). The first structural layer 410A and the resist 408 are removed using dry etching. Operation 310 forms the first structure 110A and the isolation structure 125. The etching process that removes the etch selectivity between the material of the second structural layer 410B corresponding to the second structure 110B, the first structural layer 410A corresponding to the first structure 110A, and the exposed portions of the second structural layer 410B and the first structural layer 410A defines the bottom surface 107 of the second structure 110B that is wider than the top surface 105 of the first structure 110A to form the overhang extension portion 109A of the adjacent overhang 109. Shadowing of adjacent overhangs 109 defines the deposition of OLED material 112 and cathode 114 .

[0040] In operation 311, the OLED material 112 and the cathode 114 of the first subpixel line 106A are deposited as shown in FIG. 4L (along the pixel plane) and FIG. 4M (along the line plane). The OLED material 112 includes an HIL material. Shadowing of adjacent overhangs 109 defines the deposition of each of the OLED material 112 and the cathode 114. The OLED material 112 and the cathode 114 may be separated (e.g., non-contiguous) along the pixel plane. The OLED material 112 and the cathode 114 maintain continuity along the line plane, e.g., the OLED material 112 and the cathode 114 are disposed over the separation structures 125. The total thickness of the OLED material 112 and the cathode 114 is about 100 nm to about 150 nm.

[0041] In operation 312, an encapsulation layer 116 is deposited as shown in FIG. 4N (along the pixel plane). The encapsulation layer 116 is deposited over the cathode 114. The thickness of the encapsulation layer is about 10 nm to about 50 nm. Shadowing of adjacent overhangs 109 defines the deposition of the encapsulation layer 116. The encapsulation layer 116 may maintain continuity along the pixel plane and the line plane.

[0042] In operation 313, a resist 412 is placed in the first subpixel line 106A as shown in FIG. 4O (along the pixel plane) and FIG. 4P (along the line plane). The resist 412 is a positive resist or a negative resist. The chemical composition of the resist 412 determines whether the resist 412 is a positive resist or a negative resist. The resist 412 is patterned to protect the first subpixel line 106A from a subsequent etching process. The resist 412 extends over the first subpixel 108A and the second subpixel 108B. The patterning is one of a photolithography, a digital lithography process, or a laser ablation process. The resist 412 has a width W6 of less than about 150 nm that extends over the top surface 115 of the second structure 110B. Width W 6 limits overexposure of OLED material 112 and cathode 114 disposed adjacent to and beneath overhang 109 .

[0043] In operation 314, as shown in FIG. 4Q (along the pixel plane), the portions of OLED material 112, cathode 114, and encapsulation layer 116 exposed by resist 412 are removed. Those portions of OLED material 112, cathode 114, and encapsulation layer 116 are removed by ashing (e.g., O 2 Ashing may be used to remove it. UV ozone (O 3 ) cleaning may be used to clean the surface of the anode 104.

[0044] In operation 315, the resist 412 is removed from the first subpixel line 106A, leaving the first subpixel 108A and the second subpixel 108B of the first subpixel line 106A, as shown in Figure 4R (along the pixel plane). Operations 311-317 may be repeated until the desired number of subpixels are formed.

[0045] 5 is a schematic cross-sectional view of an overhang structure 510. The overhang structure 510 may be used in place of the overhang structure 110 of the subpixel circuit 100. The overhang structure 510 is shown without the OLED material 112, the cathode 114, the encapsulation layer 116, the base layer 121, or the substrate 102. The overhang structure 510 includes a first structure 510A, a second structure 510B, and an intermediate structure 510C. The first structure 510A is disposed on the first PIS 126A. The intermediate structure 510C is disposed on the first structure 510A. The second structure 510B is disposed on the intermediate structure 510C. In the illustrated embodiment, the intermediate structure 510C is a seed layer that provides a current path through the subpixel circuit 100. The intermediate structure 510C includes a titanium (Ti) material.

[0046] Upper surface 515 of second structure 510B has width W7 from first upper surface edge 574A of second structure 510B to second upper surface edge 574B of second structure 510B. Width W7 is about 0.4 μm to about 1.2 μm. First structure 510A has width W8 from first end point 520A of bottom surface 518 to second end point 520B of bottom surface 518. Width W8 is about 0.6 μm to about 1.4 μm. Upper surface 505 of first structure 510A has width W9. Width W9 is 0.2 μm to about 0.8 μm. First PIS 126A has width W10 from first edge 117A to second edge 117B. Width W10 is 0.4 μm to about 1.2 μm. Bottom surface 507 of second structure 510B has width W11 from first bottom edge 552A to second bottom edge 552B. Width W11 is about 0.2 μm to about 1.0 μm. Width W7 and width W10 may be equal or approximately equal. Width W11 of bottom surface 507 of second structure 510B is smaller than the width of top surface 515 of second structure 510B.

[0047] The overhang structure 510 has a height H3 from the top surface 103A of the first PIS 126A to the bottom surface 507 of the second structure 510B. The height H4 is about 0.1 μm to about 0.5 μm. The height H4 may be the height of the first structure 510A, or may be the height of the first structure 510A and the intermediate structure 510C. The second structure 510B has a height H5 from the bottom surface 507 to the top surface 515. The height H5 is about 0.15 μm to about 0.25 μm. The sidewall 513 of the second structure 510B has an angle θ of about 15° to about 45° with respect to the overhang vector 554.

[0048] The subpixel circuit 100 has a pitch p. The pitch p is the distance from the first edge 117A of the first PIS 126A to the first edge 117A of the adjacent first PIS 126A. The pitch p is about 2 μm to about 8 μm. The subpixel circuit 100 has a distance D4 from the second end point 520B of the first structure 510A of the overhang structure 510 to the first end point 520A of the first structure 510A of the adjacent overhang structure 510. The distance D4 is about 2 μm to about 6 μm. The subpixel circuit 100 has a distance D5 (e.g., the width of the anode 104) from the second edge 117B of the first PIS 126A to the first edge 117A of the adjacent first PIS 126A. The distance D5 is 2 μm to about 6 μm. The distance D4 and the distance D5 may be equal or approximately equal. The overhanging structure 510 has a distance D6 from the first lower edge 552A or the second lower edge 552B of the second structure 510B to the sidewall 511 of the first structure 510A. The distance D6 is less than about 0.15 μm.

[0049] 6 is a flow diagram of a method 600 for forming a sub-pixel circuit 100, according to an embodiment. Figures 7A-7R are schematic cross-sectional views of a substrate 102 during a method 600 for forming a sub-pixel circuit 100, according to an embodiment described herein.

[0050] In operation 601, the anode 104 is deposited on the substrate 102 as shown in FIG. 7A (along the pixel plane). The anode 104 may be deposited on the substrate 102. In another embodiment, the anode 104 is deposited on a base layer 121. The base layer 121 is disposed on the substrate 102. The anode 104 may be deposited using metal organic decomposition (MOD). An anode gap 104A separates the anode 104 from an adjacent anode 104.

[0051] In operation 602, a PIS layer 726 is deposited on the substrate 102 as shown in Figure 7B (along the pixel plane). The PIS layer 726 may be deposited on the anode 104 and on the base layer 121 in the anode gap 104A. The height H6 from the base layer 121 to the top surface 703 of the PIS layer 726 is about 400 nm to about 700 nm.

[0052] In operation 603, a portion of the PIS layer 726 is removed as shown in FIG. 7C (along the pixel plane). The PIS layer 726 may be removed by a wet etching process or may be removed by a dry etching process. Operation 603 exposes the anode 104 and forms the first PIS 126A and the second PIS 126B. In operation 604, the first PIS 126A and the second PIS 126B are planarized as shown in FIG. 7D (along the pixel plane). The top surface 103A of the first PIS 126A and the top surface 103B of the second PIS 126B are aligned with the top surface of the anode 104. The first PIS 126A and the second PIS 126B are cured at a temperature of about 140° C. to about 180° C. for about 10 minutes to about 20 minutes. This curing of the first PIS 126A and the second PIS 126B allows the first PIS 126A and the second PIS 126B to shrink. Planarization of the first PIS 126A and the second PIS 126B is performed after curing. This planarization process of the first PIS 126A and the second PIS 126B may be performed using chemical mechanical planarization (CMP).

[0053] In operation 605, a first structural layer 710A and an intermediate layer 710C are deposited on the substrate 102 as shown in FIG. 7E (along the pixel plane). The first structural layer 710A is deposited on the anode 104, the first PIS 126A, and the second PIS 126B. ... 5 The intermediate layer 710C is deposited on the first structural layer 710A. The intermediate layer 710C has a thickness t 6 has.

[0054] In operation 606, resist 706 is deposited and patterned as shown in FIG. 7F (along the pixel plane). Resist 706 is deposited on top of intermediate layer 710C. Resist 706 has a width W of about 0.8 μm to about 1.2 μm. 12 The resist may be a positive resist or a negative resist. The positive resist includes a portion of the resist that, when exposed to electromagnetic radiation, is soluble in a resist developer that is applied to the resist after a pattern is written into the resist using the electromagnetic radiation. The negative resist includes a portion of the resist that, when exposed to radiation, is insoluble in a resist developer that is applied to the resist after a pattern is written into the resist using the electromagnetic radiation. The chemical composition of the resist 706 determines whether the resist is a positive resist or a negative resist. The resist 706 defines a gap g between adjacent resists 706. The gap g has a distance of about 3.8 μm to about 4.6 μm. The resist 706 is patterned to form pixel openings 124 of the line-type architecture 101C of the first subpixel line 106A. The patterning is one of a photolithography, a digital lithography process, or a laser ablation process.

[0055] In operation 607, a second structural layer 710B is deposited on the substrate 102 as shown in FIG. 7G (along the pixel plane). The second structural layer 710B may be deposited on the intermediate layer 710C in the gap g. The second structural layer 410B is deposited using metal electroplating. The second structural layer 710B is deposited to a thickness t of about 0.25 μm to about 0.35 μm. 7 has.

[0056] In operation 608, the resist 706 and the portion of the intermediate layer 710C disposed under the resist 706 are removed, as shown in FIG. 7H (along the pixel plane). The resist 706 and the intermediate layer 710C are removed by dry etching. Operation 607 forms the second structure 510B and the intermediate structure 510C.

[0057] In operation 609, resist 708 is deposited and patterned as shown in FIG. 7I (along the line plane). Resist 708 is deposited over first structural layer 710A. Resist 708 is deposited to a thickness t of less than about 500 nm. 8 The resist 708 has a taper of about 40°-50° from the bottom surface to the top surface, and the bottom surface of the resist 708 has a greater width than the top surface of the resist 708. The resist 708 is a positive resist or a negative resist. The chemical composition of the resist 708 determines whether the resist 708 is a positive resist or a negative resist. The portion of the first structural layer 710A on which the resist 708 is disposed is patterned to form the pixel openings 124 of the line-type architecture 101C of the first subpixel line 106A. The patterning is one of a photolithography, a digital lithography process, or a laser ablation process.

[0058] In operation 610, the portions of the first structural layer 710A exposed by the pixel opening 124 and the resist 708 are removed, as shown in FIG. 7J (along the pixel plane) and FIG. 7K (along the line plane). The first structural layer 710A and the resist 708 are removed using a dry etch. Operation 610 forms the first structure 510A and the isolation structure 525. The etch selectivity between the material of the second structural layer 610B corresponding to the second structure 510B, the first structural layer 610A corresponding to the first structure 510A, and the etching process that removes the exposed portions of the second structural layer 610B and the first structural layer 610A defines the bottom surface 507 of the second structure 510B that is wider than the top surface 505 of the first structure 510A to form the overhang extension portion 509A of the adjacent overhang 509. Shadowing of adjacent overhangs 509 defines the deposition of OLED material 112 and cathode 114 .

[0059] In operation 611, the OLED material 112 and the cathode 114 of the first subpixel line 106A are deposited as shown in FIG. 7L (along the pixel plane) and FIG. 7M (along the line plane). The OLED material 112 includes an HIL material. Shadowing of adjacent overhangs 509 defines the deposition of each of the OLED material 112 and the cathode 114. The OLED material 112 and the cathode 114 may be separated (e.g., non-contiguous) along the pixel plane. The OLED material 112 and the cathode 114 maintain continuity along the line plane, e.g., the OLED material 112 and the cathode 114 are disposed over the separation structures 525. The total thickness of the OLED material 112 and the cathode 114 is about 100 nm to about 150 nm.

[0060] In operation 612, the encapsulation layer 116 is deposited as shown in FIG. 7N (along the pixel plane). The encapsulation layer 116 is deposited over the cathode 114. The thickness of the encapsulation layer is about 10 nm to about 50 nm. Shadowing of adjacent overhangs 509 defines the deposition of the encapsulation layer 116. The encapsulation layer 116 may maintain continuity along the pixel plane and the line plane.

[0061] In operation 613, resist 712 is disposed within the first subpixel lines 106A as shown in FIG. 7O (along the pixel plane) and FIG. 7P (along the line plane). Resist 712 is a positive resist or a negative resist. The chemical composition of resist 712 determines whether resist 712 is a positive resist or a negative resist. The portion of the first structure layer 710A on which resist 712 is disposed is patterned to protect the first subpixel lines 106A from a subsequent etching process. The patterning is one of a photolithography, a digital lithography process, or a laser ablation process. Resist 712 is disposed within the first structure layer 710A with a width W of less than about 150 nm that extends above the top surface 515 of the second structure 510B. 12 It has a width W 12 limits overexposure of the OLED material 112 and cathode 114 located beneath the adjacent overhang 509 .

[0062] In operation 614, as shown in FIG. 7Q (along the pixel plane), the portions of OLED material 112, cathode 114, and encapsulation layer 116 exposed by resist 712 are removed. Those portions of OLED material 112, cathode 114, and encapsulation layer 116 are removed by ashing (e.g., O 2 Ashing may be used to remove it. UV ozone (O 3 ) cleaning may be used to clean the surface of the anode 104.

[0063] In operation 615, the resist 712 is removed from the first subpixel line 106A, leaving the first subpixel 108A and the second subpixel 108B of the first subpixel line 106A, as shown in Figure 7R (along the pixel plane). Operations 611-617 may be repeated until the desired number of subpixels are formed.

[0064] 8 is a schematic cross-sectional view of an overhang structure 810. The overhang structure 810 may be used in place of the overhang structure 110 of the subpixel circuit 100. The overhang structure 810 is shown without the OLED material 112, the cathode 114, the encapsulation layer 116, the base layer 121, or the substrate 102. The overhang structure 810 includes a first structure 810A, a second structure 810B, and an intermediate structure 810C. The first structure 810A is disposed on the first PIS 126A. The intermediate structure 810C is disposed on the first structure 810A. The second structure 810B is disposed on the intermediate structure 810C. In the illustrated embodiment, the intermediate structure 810C is a seed layer that provides a current path through the subpixel circuit 100. The intermediate structure 810C includes a titanium (Ti) material.

[0065] The second structure 810B has a width W13 from a first bottom edge 852A to a second bottom edge 852B, which defines a bottom surface 807 of the second structure. In some embodiments, the width W13 may further define a top surface 815 of the second structure 810B from a first edge 874A to a second top edge 874B. The width W13 is about 0.4 μm to about 1.2 μm. The first structure 810A has a width W14 from a first end point 820A of the bottom surface 818 to a second end point 820B of the bottom surface 818. The width W14 is about 0.6 μm to about 1.4 μm. The top surface 805 of the first structure 810A has a width W15. The width W15 is about 0.2 μm to about 0.8 μm. The first PIS 126A has a width W16 from the first edge 117A to the second edge 117B. The width W16 is 0.4 μm to about 1.2 μm.

[0066] The overhanging structure 810 has a height H7 from the top surface 103A of the first PIS 126A to the bottom surface 807 of the second structure 810B. The height H7 is about 0.1 μm to about 0.5 μm. The height H7 may be the height of the first structure 810A, or may be the height of the first structure 810A and the intermediate structure 810C. The second structure 810B has a height H8 from the bottom surface 807 to the top surface 815. The height H8 is about 0.15 μm to about 0.25 μm. The width of the top surface 815 of the second structure 810B may be equal to or approximately equal to the width of the bottom surface 807 of the second structure 810B.

[0067] The subpixel circuit 100 has a pitch p. The pitch p is the distance from the first edge 817A of the first PIS 126A to the first edge 117A of the adjacent first PIS 126A. The pitch p is about 2 μm to about 8 μm. The subpixel circuit 100 has a distance D7 from the second lower edge 852B of the first structure 810A of the overhang structure 810 to the first lower edge 852A of the first structure 810A of the adjacent overhang structure 810. The distance D7 is about 2 μm to about 6 μm. The subpixel circuit 100 has a distance D8 (e.g., the width of the anode 104) from the second edge 117B of the first PIS 126A to the first edge 117A of the adjacent first PIS 126A. The distance D8 is 2 μm to about 6 μm. The distance D7 and the distance D8 may be equal or approximately equal. The overhanging structure 810 has a distance D9 from the first lower edge 852A or the second lower edge 852B of the second structure 810B to the sidewall 811 of the first structure 810A. The distance D9 is less than about 0.15 μm.

[0068] 9 is a flow diagram of a method 900 for forming a sub-pixel circuit 100, according to an embodiment. Figures 10A-10R are schematic cross-sectional views of a substrate 102 during a method 900 for forming a sub-pixel circuit 100, according to an embodiment described herein.

[0069] In operation 901, an anode 104 is deposited on a substrate 102 as shown in FIG. 10A (along the pixel plane). The anode 104 may be deposited on the substrate 102. In another embodiment, the anode 104 is deposited on a base layer 121. The base layer 121 is disposed on the substrate 102. The anode 104 may be deposited using metal organic decomposition (MOD). An anode gap 104A separates the anode 104 from an adjacent anode 104.

[0070] In operation 902, a PIS layer 1026 is deposited on the substrate 102 as shown in Figure 10B (along the pixel plane). The PIS layer 1026 may be deposited on the anode 104 and on the base layer 121 in the anode gap 104A. The height H9 from the base layer 121 to the top surface 1003 of the PIS layer 1026 is about 400 nm to about 700 nm.

[0071] In operation 903, a portion of the PIS layer 1026 is removed as shown in FIG. 10C (along the pixel plane). The PIS layer 1026 may be removed by a wet etching process or may be removed by a dry etching process. Operation 903 exposes the anode 104 and forms the first PIS 126A and the second PIS 126B. In operation 904, the first PIS 126A and the second PIS 126B are planarized as shown in FIG. 10D (along the pixel plane). The top surface 103A of the first PIS 126A and the top surface 103B of the second PIS 126B are aligned with the top surface of the anode 104. The first PIS 126A and the second PIS 126B are cured at a temperature of about 140° C. to about 180° C. for about 10 minutes to about 20 minutes. This curing of the first PIS 126A and the second PIS 126B allows the plurality of first PIS 126A and the second PIS 126B to shrink. Planarization of the first PIS 126A and the second PIS 126B is performed after the curing. This planarization process of the plurality of first PIS 126A and the second PIS 126B may be performed using chemical mechanical planarization (CMP).

[0072] In operation 905, a first structural layer 1010A, a first intermediate layer 1010C, a second structural layer 1010B, and a second intermediate layer 1010D are deposited on the substrate 102 as shown in FIG. 10E (along the pixel plane). The first structural layer 1010A is deposited on the anode 104 and on the first PIS 126A and the second PIS 126B. ... 9 The first intermediate layer 1010C is deposited on the first structural layer 1010A. The first intermediate layer 1010C has a thickness t 10 The second structural layer 1010B is deposited on the first intermediate layer 1010C. The second structural layer 1010B is deposited using sputtering deposition. The second structural layer 1010B has a thickness t of about 0.15 μm to about 0.25 μm. 11 The second intermediate layer 1010D is deposited on the second structural layer 1010B. The second intermediate layer 1010D has a thickness t 12 The second intermediate layer 1010D includes a titanium (Ti) material.

[0073] In operation 906, a resist 1006 is deposited and patterned as shown in FIG. 10F (along the pixel plane). The resist 1006 is deposited on the second intermediate layer 1010D. The resist 1006 may have a width W17 of about 0.8 μm to about 1.2 μm. The resist is a positive resist or a negative resist. A positive resist includes portions of the resist that, when exposed to electromagnetic radiation, are soluble to a resist developer that is applied to the resist after a pattern has been written into the resist using the electromagnetic radiation, respectively. A negative resist includes portions of the resist that, when exposed to radiation, are insoluble to a resist developer that is applied to the resist after a pattern has been written into the resist using the electromagnetic radiation, respectively. The chemical composition of the resist 1006 determines whether the resist is a positive resist or a negative resist. The resist 1006 of the second structural layer 1010B is patterned overlying portions thereof to form pixel openings 124 of the line-type architecture 101C of the first subpixel line 106A. The patterning is one of a photolithography, a digital lithography process, or a laser ablation process.

[0074] In operation 907, the second structural layer 1010B and the second intermediate layer 1010D are removed from the portions exposed by the pixel opening 124, as shown in FIG. 10G (along the pixel plane). The second structural layer 1010B and the second intermediate layer 1010D are removed by dry etching. Operation 907 forms the second structure 810B and the second intermediate structure 810D. In operation 908, the resist 1006 and the first intermediate layer 1010C are removed from the second structure 110B, as shown in FIG. 10H (along the pixel plane). Operation 908 forms the intermediate structure 810C.

[0075] In operation 909, resist 408 is deposited and patterned as shown in FIG. 10I (along the line plane). Resist 1008 is deposited over the first structural layer 1010A. Resist 1008 is deposited to a thickness t of less than about 500 nm.13 The resist 1008 has a taper of about 40°-50° from the bottom surface to the top surface, and the bottom surface of the resist 1008 has a greater width than the top surface of the resist 1008. The resist 1008 is a positive resist or a negative resist. The chemical composition of the resist 1008 determines whether the resist 1008 is a positive resist or a negative resist. The portion of the first structural layer 1010A on which the resist 1008 is disposed is patterned to form the pixel openings 124 of the line-type architecture 101C of the first subpixel line 106A. The patterning is one of a photolithography, a digital lithography process, or a laser ablation process.

[0076] In operation 910, the portions of the first structural layer 1010A exposed by the pixel opening 124 and the resist 1008 are removed, as shown in FIG. 10J (along the pixel plane) and FIG. 10K (along the line plane). The first structural layer 1010A and the resist 1008 are removed using dry etching. Operation 910 forms the first structure 810A and the isolation structure 825. The etching selectivity between the material of the second structural layer 1010B corresponding to the second structure 810B, the first structural layer 1010A corresponding to the first structure 810A, and the etching process that removes the exposed portions of the second structural layer 1010B and the first structural layer 1010A defines a bottom surface 807 of the second structure 810B that is wider than the top surface 805 of the first structure 810A to form an overhang extension portion 809A of the adjacent overhang 809. Shadowing of adjacent overhangs 809 defines the deposition of OLED material 112 and cathode 114 .

[0077] In operation 911, the OLED material 112 and the cathode 114 of the first subpixel line 106A are deposited as shown in FIG. 10L (along the pixel plane) and FIG. 10M (along the line plane). The OLED material 112 includes an HIL material. Shadowing of adjacent overhangs 109 provides for the deposition of each of the OLED material 112 and the cathode 114. The OLED material 112 and the cathode 114 may be separated (e.g., non-contiguous) along the pixel plane. The OLED material 112 and the cathode 114 maintain continuity along the line plane, e.g., the OLED material 112 and the cathode 114 are disposed over the separation structures 825. The total thickness of the OLED material 112 and the cathode 114 is about 100 nm to about 150 nm.

[0078] In operation 912, the encapsulation layer 116 is deposited as shown in FIG. 10N (along the pixel plane). The encapsulation layer 116 is deposited over the cathode 114. The thickness of the encapsulation layer is about 10 nm to about 50 nm. Shadowing of adjacent overhangs 809 defines the deposition of the encapsulation layer 116. The encapsulation layer 116 may maintain continuity along the pixel plane and the line plane.

[0079] In operation 913, a resist 1012 is disposed in the first subpixel line 106A as shown in FIG. 10O (along the pixel plane) and FIG. 10P (along the line plane). The resist 1012 is a positive resist or a negative resist. The chemical composition of the resist 1012 determines whether the resist 1012 is a positive resist or a negative resist. The resist 1012 is patterned to protect the first subpixel line 106A from a subsequent etching process. The patterning is one of a photolithography, a digital lithography process, or a laser ablation process. The resist 1012 has a width W18 that extends above the top surface 815 of the second structure 810B. The width W18 is less than about 150 nm. The width W18 limits overexposure of the OLED material 112 and the cathode 114 disposed under the adjacent overhang 809.

[0080] In operation 914, as shown in FIG. 10Q (along the pixel plane), the portions of the OLED material 112, the cathode 114, and the encapsulation layer 116 exposed by the resist 1012 are removed. Those portions of the OLED material 112, the cathode 114, and the encapsulation layer 116 are removed by ashing (e.g., O 2 Ashing may be used to remove it. UV ozone (O 3 ) cleaning may be used to clean the surface of the anode 104.

[0081] In operation 915, the resist 1012 is removed from the first subpixel line 106A, leaving the first subpixel 108A and the second subpixel 108B of the first subpixel line 106A, as shown in Figure 10R (along the pixel plane). Operations 911-917 may be repeated until the desired number of subpixels are formed.

[0082] In summary, a device is disclosed. The device includes a plurality of subpixel lines. Each subpixel line includes at least a first subpixel and a second subpixel. The first subpixel and the second subpixel each include an anode, an overhang structure, an isolation structure, an organic light emitting diode (OLED) material, and a cathode. The anode is defined by an adjacent first pixel isolation structure (PIS) and an adjacent second PIS. The overhang structure is disposed on the first PIS. The overhang structure includes a second structure disposed on the first structure and an intermediate structure disposed between the second structure and the first structure. A bottom surface of the second structure extends laterally past a top surface of the first structure. The first structure is disposed on the first PIS. The isolation structure is disposed on the second PIS. One of the isolation structures separates the first pixel from the second pixel. The OLED material is disposed on the anode and on a top surface of the isolation structure. The OLED material of the first subpixel and the second subpixel emits a first color, and a cathode is disposed over the OLED material and over a top surface of the separating structure.

Claims

1. A first pixel isolation structure (PIS) arranged along a line plane, A second PIS arranged along the pixel plane, An overhanging structure disposed on the first PIS, wherein the overhanging structure is A second structure positioned on top of a first structure, wherein the bottom surface of the second structure extends laterally past the top surface of the first structure, and Adhesive layer disposed between the second structure and the first structure The overhang structure comprises the first structure which is positioned on the first PIS, A separation structure placed on the second PIS, Organic light-emitting diode (OLED) material disposed on the anode and on the upper surface of the separation structure, A cathode disposed on the OLED material and on the upper surface of the separation structure. A subpixel equipped with a subpixel.

2. The subpixel according to claim 1, wherein the first PIS and the second PIS have upper surfaces that coincide with the upper surface of the anode.

3. The subpixel according to claim 1, wherein the bottom surface of the first structure has a first endpoint extending to the first edge of the first PIS or a first endpoint extending beyond the first edge of the first PIS, and a second endpoint extending to the second edge of the first PIS or a second endpoint extending beyond the second edge of the first PIS.

4. The subpixel according to claim 1, wherein the bottom surface of the separation structure has a first endpoint extending to the first edge of the second PIS or a first endpoint extending beyond the first edge of the second PIS, and a second endpoint extending to the second edge of the second PIS or a second endpoint extending beyond the second edge of the second PIS.

5. The subpixel according to claim 1, wherein the adhesive layer comprises a chromium material.

6. A first pixel separation structure (PIS) arranged along a line plane, A second PIS arranged along the pixel plane, An overhanging structure disposed on the first PIS, wherein the overhanging structure is A second structure positioned on top of a first structure, wherein the bottom surface of the second structure extends laterally past the top surface of the first structure, and Seed layer disposed between the second structure and the first structure The overhang structure comprises the first structure which is positioned on the first PIS, A separation structure placed on the second PIS, Organic light-emitting diode (OLED) material disposed on the anode and on the upper surface of the separation structure, A cathode disposed on the OLED material and on the upper surface of the separation structure. A subpixel equipped with a subpixel.

7. The subpixel according to claim 6, wherein the seed layer comprises a titanium material.

8. The first structure is composed of amorphous silicon (a-Si), titanium (Ti), and silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 ) or silicon oxynitride (Si 2 N 2 The subpixel according to claim 1, including O).

9. The subpixel according to claim 1, wherein the second structure comprises a copper (Cu) material.

10. The subpixel according to claim 1, wherein the first PIS and the second PIS are arranged on a base layer, and the base layer is arranged on a substrate.

11. It comprises multiple subpixel lines, each subpixel line comprising at least a first subpixel and a second subpixel, and the first subpixel and the second subpixel are Adjacent first pixel isolation structures (PIS) arranged along a line plane, A second adjacent PIS arranged along the pixel plane, An overhanging structure disposed on the first PIS, wherein the overhanging structure is A second structure positioned on top of a first structure, wherein the bottom surface of the second structure extends laterally past the top surface of the first structure, and Adhesive layer or seed layer disposed between the second structure and the first structure The overhang structure has the first structure positioned on the first PIS, A separation structure disposed on the second PIS, wherein one of the separation structures separates the first pixel and the second subpixel, An organic light-emitting diode (OLED) material disposed on the anode and on the upper surface of the separation structure, wherein the OLED material of the first subpixel and the second subpixel emits a first color, A cathode disposed on the OLED material and on the upper surface of the separation structure. A device equipped with each of these features.

12. The device according to claim 11, wherein the first PIS and the second PIS have upper surfaces that coincide with the upper surface of the anode.

13. The device according to claim 11, wherein the bottom surface of the first structure has a first endpoint extending to the first edge of the first PIS or a first endpoint extending beyond the first edge of the first PIS, and a second endpoint extending to the second edge of the first PIS or a second endpoint extending beyond the second edge of the first PIS.

14. The device according to claim 11, wherein the bottom surface of the separation structure has a first endpoint extending to the first edge of the second PIS or a first endpoint extending beyond the first edge of the second PIS, and a second endpoint extending to the second edge of the second PIS or a second endpoint extending beyond the second edge of the second PIS.

15. The device according to claim 11, wherein the adhesive layer comprises a chromium material.

16. The device according to claim 11, wherein the seed layer comprises a titanium material.

17. The first structure includes amorphous silicon (a-Si), titanium (Ti), silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), or silicon oxynitride (Si 2 N 2 O), the device according to claim 11.

18. The device according to claim 11, wherein the second structure comprises a copper (Cu) material.

19. The device according to claim 11, wherein the first PIS and the second PIS are arranged on a base layer, and the base layer is arranged on a substrate.

20. The device according to claim 11, wherein the bottom surface of the second structure has a width greater than the width of the top surface of the second structure.

21. The device according to claim 11, wherein the upper surface of the second structure has a width greater than the width of the bottom surface of the second structure.

22. A method for forming a device, Depositing an anode and pixel isolation structure (PIS) layer on a substrate, The portion of the PIS layer is removed to form a first PIS arranged along the line plane and a second PIS arranged along the pixel plane. The process involves depositing a first structural layer, an adhesive material or seed material, and a second structural layer on the substrate, wherein the second structural layer is deposited by sputter deposition, and the deposition process is carried out as follows: The process involves depositing a first resist on the second structural layer and then patterning it. The second structural layer and the adhesive material or seed material are removed using ion beam milling to form the second structure and the adhesive layer or seed layer. Removing the first resist from the second structure, The process involves depositing a second resist on the first structural layer and then patterning it. The first structural layer is dry-etched and removed to form the first structure, Depositing organic light-emitting diode (OLED) material, cathode, and encapsulation layer, Depositing a third resist within the first subpixel and patterning it, The OLED material, the cathode, and the encapsulation layer are ashing and removed. Removing the third resist and Methods that include...

23. The method according to claim 22, wherein the adhesive layer contains a chromium material.

24. The method according to claim 22, wherein the adhesive layer has a thickness of less than approximately 50 nm.

25. The method according to claim 22, wherein the second structural layer comprises a copper (Cu) material.

26. The method according to claim 22, wherein the second structural layer has a thickness of about 0.15 μm to about 0.25 μm.

27. The first structural layer comprises amorphous silicon (a-Si), titanium (Ti), and silicon nitride (Si 3 N 4 ), silicon dioxide (SiO 2 ) or silicon oxynitride (Si 2 N 2 The method according to claim 22, comprising O).