Multilayer ion trap on a formed glass substrate or dielectric substrate

Abstract

In aspects of the present disclosure, the use and manufacture of trapping devices for use in quantum information processing (QIP) architectures, and more particularly, multilayer ion traps on a shaped glass or dielectric substrate (100) are described. To complete the formation of the ion trap, a method for manufacturing an ion trap is described that includes preparing the back surface of the substrate, building a multilayer stack on the top surface of the substrate, completing a back etch through the substrate, and etching through the metal (140) and dielectric (150) of the multilayer stack. Also, the shaping of the ion trap can include features, wings, and / or undercuts that narrow the trap. The ion trap manufactured using this technique can be used in a QIP system to trap atomic species supplied through holes in the back of the substrate for use as qubits in quantum operations and quantum computing.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims priority and benefit to U.S. Provisional Patent Application No. 63 / 333,781, filed on April 22, 2022, and entitled "Multilayer Ion Traps on Formed Glass or Dielectric Substrates", and U.S. Non - Provisional Patent Application No. 18 / 302,572, filed on April 18, 2023, and entitled "Multilayer Ion Traps on Formed Glass or Dielectric Substrates", the contents of which are hereby incorporated by reference in their entirety.

[0002] Technical Field Aspects of the present disclosure generally relate to trapping devices for use in quantum information processing (QIP) architectures, and more particularly, to the use and manufacture of multilayer ion traps on formed glass or dielectric substrates.

Background Art

[0003] Trapped atoms are one of the powerful implementation forms for quantum information processing or quantum computing. Atom - based qubits can be used as quantum memories in quantum computers and quantum simulators, as quantum gates, and can function as nodes in quantum communication networks. Qubits based on trapped atomic ions have a combination of rare properties. For example, qubits based on trapped atomic ions with very good coherence properties can be prepared and measured with nearly 100% efficiency and can easily interact with each other by modulating their Coulomb interactions with an appropriate external control field such as an optical field or a microwave field. These properties make atom - based qubits attractive for extended quantum operations such as quantum computing or quantum simulation.

[0004] Therefore, it is important to improve the design and manufacture of traps used to handle atom-based qubits.

Summary of the Invention

Means for Solving the Problems

[0005] To provide a basic understanding of one or more aspects, a simplified summary of such aspects is presented below. This summary is not an extensive overview of all contemplated aspects, nor is it intended to identify key or critical elements of all aspects, nor to delineate the scope of any or all aspects. Its sole purpose is to present some concepts of one or more aspects in a simplified form as a prelude to the more detailed description that follows.

[0006] Aspects of the present disclosure describe techniques for manufacturing multi-layer traps on a formed glass substrate or dielectric substrate. Types of traps manufactured by such techniques include, but are not necessarily limited to, ion traps. The term "formed" can refer to various processes or techniques that physically modify or alter at least a portion of the substrate to result in a desired form of the substrate. Forming can include forming holes through the substrate and / or more substantial forming such as trap wings, narrowing of the intermediate portion of the trap, and / or undercuts. This method includes preparing a glass substrate or dielectric substrate, constructing a multi-layer stack on the upper surface of the glass substrate or dielectric substrate, and etching from the back surface so as to completely penetrate and etch a part of the glass substrate or dielectric substrate and / or the multi-layer stack to complete the ion trap.

[0007] In an aspect of the present disclosure, preparing a back surface of a substrate for subsequent processing; after preparing the back surface of the substrate, constructing a stack of a plurality of layers on the front surface of the substrate, the stack of the plurality of layers including at least one metal layer for routing and at least one metal layer for an upper electrode; and after constructing the stack of the plurality of layers on the front surface of the substrate, forming the substrate by processing the back surface of the substrate. A method for manufacturing a trap is described.

[0008] In another aspect of the present disclosure, a QIP system using a multilayer ion trap on a formed glass substrate or dielectric substrate is described.

[0009] In an aspect of the present disclosure, a QIP system including an ion trap having a substrate made of a glass material or a dielectric material and a stack of a plurality of layers disposed on the substrate, the stack of the plurality of layers including at least one metal layer for routing, at least one dielectric layer, and at least one metal layer for an upper electrode, wherein the substrate and the stack of the plurality of layers are shaped to form holes that penetrate the substrate and extend through the stack of the plurality of layers. The QIP system further includes a source configured to provide atomic species from the back surface of the ion trap, through the holes in the substrate and the stack of the plurality of layers of the ion trap, to the front surface of the ion trap.

[0010] In an aspect of the present disclosure, an ion trap having a substrate made of a glass material or a dielectric material and a stack of a plurality of layers disposed on the substrate, the stack of the plurality of layers including at least one metal layer for routing, at least one dielectric layer, and at least one metal layer for an upper electrode, wherein the substrate and the stack of the plurality of layers are shaped to form holes that penetrate the substrate and extend through the stack of the plurality of layers.

[0011] To achieve the foregoing and related purposes, one or more aspects include features that are fully described below and particularly pointed out in the claims. In the following description and the accompanying drawings, specific exemplary features of one or more aspects are described in detail. However, these features are illustrative of some of the various ways in which the principles of the various aspects may be employed, and this specification is intended to include all such aspects and their equivalents.

[0012] The disclosed aspects will now be described in connection with the accompanying drawings, which are provided to illustrate, but not to limit, the disclosed aspects. Like reference numerals refer to like elements.

Brief Description of the Drawings

[0013]

Figure 1A

Figure 1B

Figure 1C

Figure 1D

Figure 1E

Figure 1F

Figure 1G

Figure 1H

Figure 2A

Figure 2B

Figure 3A

Figure 3B

Figure 4

Figure 5

Figure 6

Mode for Carrying Out the Invention

[0014] The detailed description set forth below in connection with the accompanying drawings or figures is intended to explain various configurations and is not intended to show only structures capable of implementing the concepts described herein. The detailed description includes specific details for the purpose of providing a thorough understanding of the various concepts. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known components are shown in block diagram form to avoid obscuring such concepts.

[0015] Figures 1A - 1H illustrate an example of a manufacturing process for creating traps by metallization of a formed glass substrate or a formed dielectric substrate, related to aspects of the present disclosure. The figures provide a schematic representation of the manufacturing process, and the sizes and thicknesses shown are for illustrative purposes only and are not intended to accurately represent the actual sizes and thicknesses of the trap features.

[0016] The type of metallization process used can be an electroplating process such as those used in the manufacture of micro - electromechanical systems (MEMS). It will be understood that other techniques than electroplating processes can be used for metallization as needed. For example, for at least some of the metallization steps required as part of the present disclosure, techniques such as sputtering and / or physical vapor deposition (PVD) or other similar techniques may be used instead of an electroplating process. The processes or methods described herein are applicable to traps having multiple metallization layers (e.g., traps where one or more of the metal layers can be used for routing and one of the metal layers can be used for the top electrode), but they can also be applicable to traps that use a single metallization layer, either in whole or in part.

[0017] FIG. 1A illustrates a substrate 100, also referred to as a wafer or die, made of a glass material or a dielectric material. An example of a material that can be used for the substrate 100 is fused silica (FuSi). Also shown are alignment patterns or marks 110 fabricated on the upper surface of the substrate 100 using standard manufacturing processes. These alignment marks 110 can be used to position subsequent processes performed on the surface of the substrate 100.

[0018] Next, as shown in FIG. 1B, to prepare the wafer for selective etching, the back surface of the substrate 100 is prepared by laser scribing, or a similar process. Optionally, as shown in FIG. 1B, partial etching 120 may be performed to create holes that go from the back surface of the substrate 100 to the upper surface of the substrate 100. Examples of types of selective etching include the techniques described in Andrius Marcinkevicius, Saulius Juodkazis, Mitsuru Watanabe, Masafumi Miwa, Shigeki Matsuo, Hiroaki Misawa, and Junji Nishii, “Femtosecond laser-assisted three-dimensional microfabrication in silica,” Opt. Lett. 26, 277-279 (2001). Exemplary manufacturers of this process are Translume (www.translume.com) and Femtoprint (www.femtoprint.ch). The partial etching 120 may include one or more steps of scribing or etching.

[0019] When partial etching is included (as shown in FIG. 1B), a meniscus or thin layer 130 can be generated from the partial etching. The meniscus 130 can be left to provide mechanical support for subsequent processes performed on the upper surface of the substrate 100. The thickness of the meniscus 130 can depend on how much partial etching 120 (if present) is performed. Additionally, or alternatively, for high aspect ratio (HAR) lithography used with an electroplating process, the meniscus 130 may be left to reduce topology. By leaving the meniscus 130 with a flat surface, better photoresist deposition and development may be possible. The meniscus 130 can also be created by a laser scribing process for selective etching in later steps. The meniscus 130 can be etched at a stage after the upper surface process is completed and the holes through the substrate 100 are completed.

[0020] Figure 1C illustrates the following process performed on the upper surface of substrate 100. These processes may include depositing or forming a dielectric layer 150 after depositing or forming a metallization layer 140, which may or may not be patterned, on the upper surface of substrate 100. The metallization layer 140 provides a protective etch stop for subsequent processing steps and can also function as an electrical routing layer. The metallization layer 140 may be referred to as the first metallization layer. Examples of metals used for the metallization layer 140 are chromium or titanium tungsten (Ti tungsten or TiW). This layer may be a stack of multiple metals that improves electrical conductivity or provides additional protective advantages. For example, to improve electrical conductivity, copper metallization may cover chromium or titanium tungsten metallization. The dielectric layer 150 may be patterned and filled with metal or other conductive material to form electrical vias 155 that penetrate the dielectric layer 150. Both the dielectric layer 150 and the vias 155 may be planarized using chemical mechanical polishing or other processes to provide a flat or nearly flat surface for further process steps. Since multiple layers of different materials are deposited or formed on a glass (or dielectric) substrate, the traps described herein may be referred to as multilayer traps on glass. Further, for example, since the glass is shaped by partial etching 120 (and subsequent full etching, optionally etching of other parts of substrate 100), the traps described herein may also be referred to as multilayer traps on shaped glass. When the substrate is a dielectric substrate or a glass ceramic substrate, the traps may be referred to as multilayer traps on shaped dielectric or shaped glass ceramic, respectively.

[0021] Next, as shown in FIG. 1D, a metallization 160 is applied over the dielectric layer 150 to form the upper electrode of the trap and / or the routing connection. As described above, the process used for metallization, such as the fabrication of the metallization 160, can be an electroplating process such as that used in the manufacture of MEMS. Further, an example of the metal used for the metallization 160 is gold (Au), however, other metals or combinations of metals can also be used. If the metallization 160 is the upper metal layer of a multilayer stack or multilayer structure built on the upper surface of the substrate 100, it can be referred to as the upper metallization or the upper electroplated metallization (when fabricated by such a process). In an exemplary aspect, the metallization 160 can include a metallization layer (not shown) between the upper metallization and the dielectric layer 150, which may or may not be patterned. An example of this metallization layer is an electroplating seed layer used when the metallization 160 is formed by electroplating a metal. This intermediate layer may be etched prior to the next (following) step, or left to be removed at a later stage of the process.

[0022] FIG. 1E illustrates the deposition of a temporary protective layer 170 over the metallization 160. The temporary protective layer 170 is over the structure formed by the metallization 160 and not under the structure. The temporary protective layer 170 can be formed by one or more protective layers. This temporary protective layer 170 enables a subsequent etching process to be performed on the back surface of the substrate 100 without affecting the upper multilayer stack.

[0023] Figure 1F illustrates a process of performing a partial etching 120 and then etching so as to penetrate the meniscus 130 (e.g., by placing the entire substrate 100 in an acid bath) to create a full etching 120' on the back surface of the substrate 100. If a partial etching has not been performed heretofore, this etching provides a full etching that penetrates the substrate 110. The metallization layer 140, also referred to as a protective metallization layer 140, can be mainly used for routing. However, the metallization layer 140 can also be used to include a backside etching that penetrates to reach the dielectric layer 150. As a variant, the metallization layer 140 may be patterned so that the etchant can reach the dielectric layer 150 in a specified area above the etching 120'. If the meniscus 130 or other areas of the substrate have been prepared for selective etching during the previous processing, the resulting etching shape can be controllable. If the meniscus 130 has not been prepared in such a way, the etching can be isotropic. The etchant or etching process used in this manufacturing stage may or may not be the same as the previous etchant or etching process used for any optional substrate shaping heretofore.

[0024] Optionally, the metallization layer 140 may then be etched from the back surface to expose the dielectric layer 150. The dielectric layer 150 may then be etched to complete a hole 120” that penetrates the entire substrate and deposition layer as shown in Figure 1G. In this method, there is a hole connecting the back surface and the top surface, and this hole is properly positioned using the alignment mark 110 (see Figure 1A) during the various processes described above. An example of such a hole is a hole that is used to fill the top surface of the trap with atomic species from the back of the substrate 100 for trapping atomic species and using them for qubits in quantum operations and quantum computing.

[0025] When the through - connection is achieved, the temporary protective layer 170 can be removed as shown in FIG. 1H. At this point, using an additional protective layer and etching from the front side, the holes in the dielectric layer 150 and the metallization layer 140 can be cut out. For example, if an optional back - side etching that penetrates the metallization layer 140 and the dielectric layer 150 is not performed, full etching through the device can be completed by front - side etching that includes a protective layer patterned to limit the etching to a specific region.

[0026] The manufacturing techniques described above address some of the incompatibilities related to using a glass - forming process or an etching process along with a process such as that used in MEMS manufacturing. To enable the creation of a multi - layer stack, it is useful but not necessarily required for the top surface of the substrate 100 to remain original and hole - free. If an etching process is applied up to the top surface, such a process may not function well either if the surface created by it has holes. Further, since the laser - scribing process may damage or destroy the multi - layer stack, after the multi - layer stack is built on the top surface of the substrate 100, a back - etching process cannot be executed entirely. Therefore, the techniques described herein include preparing the substrate (which may include partial etching), building a multi - layer stack on the top surface, and performing a final etching from the back side to the front side while protecting the front side from the acid (or other process) used to shape the substrate by removing the laser - scribed area of the substrate or the unprepared substrate (e.g., the meniscus 130) or a combination of the two.

[0027] FIG. 2A illustrates an example of using a dam or via 200 that penetrates the dielectric layer 150 to limit the range of etching that penetrates the region 210 from the dielectric layer 150. The dam or via 200 may surround the upper range of the etching 120” or may only surround a part of the etching. Without these protective dams or vias 200, the etching that penetrates the dielectric layer 150 may be limited only by the etching time when using an acid. This makes it possible to complete the etching that penetrates the dielectric layer 150 while imposing design limitations to prevent excessive undercutting of the metallization 160.

[0028] FIG. 2B illustrates an example of the trap structure shown in FIG. 2A after removal of its temporary protective layer (e.g., the temporary protective layer 170). This figure also illustrates full etching through the device (see, e.g., FIG. 1H).

[0029] FIGS. 1A - 2B illustrate examples of the use of substrates shaped to have holes in a glass substrate or a dielectric substrate (or a glass - ceramic substrate), but the techniques described above can be applied to multilayers on glass traps with additional or alternative shaping. FIGS. 3A - 3B illustrate other shaping examples of a glass substrate or a dielectric substrate according to aspects of the present disclosure.

[0030] For example, FIG. 3A shows a substrate 100 in which glass shaping is used such that narrowing of the trap 300 and / or the wing 310 occurs. The trap 300 is shown to have a narrowed center, and wings 310 are formed at both ends of the trap 300. These features make it possible to provide improved optical compatibility and system integration for the trap. Thus, a trap formed as shown in FIG. 3A can be created using a process that includes back - side preparation, construction of the upper - layer stack, and final back - side etching as described herein.

[0031] In another example, FIG. 3B shows a substrate 100 in which the narrowing of the trap 300, the wing 310, and / or the undercut 320 occurs by forming glass. Similar to FIG. 3A, the trap 300 is shown to have a narrowed center, wings 310 are formed at both ends of the trap 300, and undercuts 320 are added on both sides of the central portion of the trap 300. The form or geometry of the undercut 320 is provided by way of example and not limitation, and other forms or geometries may also be used. These features make it possible to provide improved optical compatibility (e.g., compatibility with the beam waist of an optical beam) and system integration for the trap. Thus, a trap formed as shown in FIG. 3B can be created using a process that includes backside preparation, construction of a multilayer stack on the top surface, and final backside etching as described herein.

[0032] FIG. 4 illustrates a flow diagram of a method 400 for fabricating a trap by metallization of a formed glass substrate or a formed dielectric substrate according to an aspect of the present disclosure.

[0033] When a glass substrate or a dielectric substrate is provided, method 400 may include, at 410, preparing the bulk of the glass substrate or the dielectric substrate (e.g., substrate 100). This preparation may include one or more of the steps described above in connection with FIGS. 1A and 1B.

[0034] Method 400 may include, at 420, constructing (e.g., disposing or depositing) a multilayer stack on the top surface of the glass substrate or the dielectric substrate. This construction may include one or more of the various steps described above in connection with FIGS. 1C - 1E.

[0035] Method 400 may include, at 430, performing or completing etching from the back side so as to penetrate a glass substrate or a dielectric substrate, and completing the ion trap. This may include etching through a part of the multilayer stack from the back side to create holes through the entire thickness of the substrate 100 and the multilayer stack. Completion of the etching may include the steps described above in connection with FIGS. 1F and 1G.

[0036] In addition, method 400 may include removing a temporary protective layer (e.g., temporary protective layer 170), and / or performing additional etching through the metallization layer 140 and the dielectric layer 150, as illustrated in FIGS. 1H and 2B.

[0037] In addition, method 400 may include forming dams or vias (e.g., dam 200) in the dielectric layer to limit the extent of etching through the dielectric layer.

[0038] Aspects of the present disclosure describe a method of manufacturing a trap (e.g., method 400) that includes preparing the back side of a substrate for subsequent processing; after preparing the back side of the substrate, constructing a stack of multiple layers on the top side of the substrate, the stack of multiple layers including at least one metal layer for routing and at least one metal layer for an upper electrode; and shaping the substrate by processing the back side of the substrate after constructing the stack of multiple layers on the top side of the substrate.

[0039] With respect to this method, the substrate may be made of a glass material or a dielectric material.

[0040] With respect to this method, the substrate may be made of fused silica.

[0041] With respect to this method, preparing the back side of the substrate includes applying at least one laser scribing process to prepare the back side of the substrate for selective etching.

[0042] With respect to this method, preparing the back surface of the substrate includes removing a portion of the substrate from the back surface of the substrate to partially shape the substrate. Further, removing a portion of the substrate includes applying one or more laser scribing processes and one or more etching processes. Additionally, or alternatively, by removing a portion of the substrate, a meniscus is left near the upper surface of the substrate. Additionally, or alternatively, preparing the back surface of the substrate includes applying one or more laser scribing processes to the meniscus, and the entire thickness of the meniscus can be prepared for subsequent selective etching, or only a portion of the thickness can be prepared for subsequent selective etching. Further, the method includes removing the meniscus at a later stage. For example, constructing a stack of multiple layers includes placing a protective layer on the stack of multiple layers and removing the meniscus after placing the protective layer on the stack of multiple layers.

[0043] With respect to this method, constructing a stack of multiple layers includes placing a first metallization on the upper surface of the substrate, placing a dielectric layer on the first metallization, and placing a second metallization on the dielectric layer, where the first metallization is part of at least one metal layer for routing and the second metallization is part of at least one metal layer for the upper electrode. Placing the dielectric layer includes forming vias in the dielectric layer to enable connection between the first metallization and the second metallization. Placing the first metallization includes patterning the first metallization to provide routing. Placing the second metallization includes patterning the second metallization to provide the upper electrode. Placing the first metallization, placing the second metallization, or both includes an electroplating process. Further, the second metallization may be made of gold. Placing the second metallization includes patterning the second metallization to provide the upper electrode.

[0044] Regarding this method, constructing a stack of multiple layers includes disposing a dielectric layer and disposing two or more metallization layers on the dielectric layer.

[0045] Regarding this method, constructing a stack of multiple layers includes disposing three or more metallization layers.

[0046] Regarding this method, constructing a stack of multiple layers includes disposing a protective layer on the stack of multiple layers, and shaping the substrate by processing the back surface of the substrate includes removing a portion of the substrate from the back surface of the substrate to form a hole that penetrates the thickness of the substrate. Further, for the holes that penetrate the substrate so as to extend through the stack of multiple layers, the stack of multiple layers is shaped by removing a portion of the stack of multiple layers. The stack of multiple layers includes a dielectric layer having a plurality of dams and holes that extend through the stack of multiple layers and extend between the dams of the dielectric layer. The method further includes removing the protective layer.

[0047] FIG. 5 shows a block diagram illustrating an example of a QIP system 500 according to an aspect of the present disclosure in which a multi-layer ion trap can be implemented on a formed glass substrate or dielectric substrate described herein. The QIP system 500 may also be referred to as a quantum computing system, a computer device, a trapped ion system, and the like.

[0048] The QIP system 500 can include a source 560 that provides a species of atoms (e.g., a plume or flux of neutral atoms) to a chamber 550 having an ion trap 570 that traps the species of atoms when ionized (e.g., photoionized). The source 560 may be implemented separately from the chamber 550. The ion trap 570 can be part of a processor or processing unit of the QIP system 500. The ion trap 570 can be an example of a multilayer ion trap on a shaped glass substrate or dielectric substrate described herein. For example, the ion trap 570 can be configured and formed according to the processes, methods, or techniques described above in connection with FIGS. 1A - 2B. Additionally, the ion trap 570 can be shaped to include some or all of the features described above in connection with FIGS. 3A and 3B, such as the trap 300.

[0049] The imaging system 530 can include a high - resolution imager (e.g., a CCD camera) to monitor the atomic ions while they are being supplied to the ion trap or after they have been supplied to the ion trap 570. In one aspect, the imaging system 530 can be implemented separately from the optical and trap controller 520, however, it may be necessary to use fluorescence to detect, identify, and label the atomic ions using image - processing algorithms in order to interface with the optical and trap controller 520.

[0050] The QIP system 500 can also include an algorithm component 510 that can be operated by other parts (not shown) of the QIP system 500 to execute quantum algorithms or quantum operations including a stack or sequence of single - qubit operations and / or a combination of multi - qubit operations (e.g., two - qubit operations), and extended quantum computations. Thus, the algorithm component 510 can give instructions to various components of the QIP system 500 (e.g., the optical and trap controller 520) so as to implement a quantum algorithm or quantum operation.

[0051] Referring now to FIG. 6, an exemplary computer system or device 600 according to an aspect of the present disclosure is illustrated. The computer device 600 may represent a single computing device, multiple computing devices, or, for example, a distributed computing system. The computer device 600 may be configured as a quantum computer (e.g., a QIP system), a classical computer, or a combination of quantum computing capabilities and classical computing capabilities. For example, the computer device 600 can be used to process information using quantum algorithms based on trapped ion technology, and thus can implement the multilayer ion traps on the shaped glass substrate or dielectric substrate described herein. An inclusive example of the computer device 600 as a QIP system is illustrated in the QIP system 500 shown in FIG. 5.

[0052] The computer device 600 may include a processor 610 for executing the processing of functions related to one or more of the features described herein. The processor 610 may include a single or multiple processors or a set of multi-core processors. Further, the processor 610 may be implemented as an integrated processing system and / or a distributed processing system. The processor 610 may include one or more central processing units (CPUs) 610a, one or more graphics processing units (GPUs) 610b, one or more quantum processing units (QPUs) 610c, one or more intelligence processing units (IPUs) 610d (e.g., artificial intelligence or AI processors), or a combination of some or all of these processor types. In one aspect, the processor 610 may refer to a general processor of the computer device 300 and may also include an additional processor 610 for executing more specific functions (e.g., including functions for controlling the operation of the computer device 600). The processor 610 may include an ion trap such as a multilayer ion trap on a formed glass substrate or a dielectric substrate described herein. For example, the ion trap may be used for one or more of the QPUs 610c.

[0053] In one example, the computer device 600 may include a memory 620 for storing instructions executable by the processor 610 for executing the functions described herein. In one implementation, for example, the memory 620 may correspond to a computer-readable storage medium for storing code or instructions for executing one or more of the functions or operations described herein. Similar to the processor 610, the memory 620 may refer to a general memory of the computer device 600 and may also include an additional memory 620 for storing instructions and / or data for more specific functions such as instructions and / or data for controlling individual beams.

[0054] Furthermore, computer device 600 may include a communication component 630 that utilizes hardware, software, and services to provide for the establishment and maintenance of communication with one or more parties. Communication component 630 can perform communication not only between components on computer device 600, but also between computer device 600 and external devices, such as devices located across a communication network and / or devices serially or locally connected to computer device 600. For example, communication component 630 may include one or more buses and may further include a transmit chain component and a receive chain component, each associated with a transmitter and a receiver operable to interact with external devices.

[0055] Additionally, computer device 600 may include a data store 640, which may be any suitable combination of hardware and / or software and which provides for mass storage information, databases, and programs employed in connection with the implementations described herein. For example, data store 640 may be a data repository for an operating system 660 (e.g., a classical OS or a quantum OS). In one implementation, data store 640 may include memory 620.

[0056] The computer device 600 may also be operable to receive input from a user of the computer device 600 and further include a user interface component 650 that is operable to generate output for presentation to the user (directly or indirectly) or for providing to a different system. The user interface component 650 may include one or more input devices including, but not limited to, a keyboard, numeric keypad, mouse, touch-sensitive display, digitizer, navigation keys, function keys, microphone, speech recognition component, any other mechanism capable of receiving input from a user, or any combination thereof. Further, the user interface component 650 may include one or more output devices including, but not limited to, a display, speaker, tactile feedback mechanism, printer, any other mechanism capable of presenting output to the user, or any combination thereof.

[0057] In one implementation, the user interface component 650 may send and / or receive messages corresponding to the operation of the operating system 660. Additionally, the operating system 660 and / or an application or program may be executed by the processor 610 and may be stored in the memory 620 or the data store 640.

[0058] If the computer device 600 is implemented as part of a cloud-based infrastructure, the user interface component 650 may be used to enable a user of the cloud-based infrastructure to interact remotely with the computer device 600.

[0059] In aspects of the present disclosure, a QIP system is described that includes an ion trap having a substrate made of a glass material or a dielectric material and a stack of multiple layers disposed on the substrate and including at least one metal layer for routing, at least one dielectric layer, and at least one metal layer for an upper electrode, wherein the substrate and the stack of multiple layers are shaped to form holes that penetrate the substrate and extend through the stack of multiple layers (e.g., QIP system 500). The QIP system also includes a source configured to provide atomic species from the back surface of the ion trap, through the holes in the substrate and the stack of multiple layers of the ion trap, to the top surface of the ion trap.

[0060] In aspects of the present disclosure, an ion trap is described that has a substrate made of a glass material or a dielectric material and a stack of multiple layers disposed on the substrate and including at least one metal layer for routing, at least one dielectric layer, and at least one metal layer for an upper electrode, wherein the substrate and the stack of multiple layers are shaped to form holes that penetrate the substrate and extend through the stack of multiple layers.

[0061] The foregoing description of the present disclosure is provided to enable a person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of the present disclosure. Further, elements of the described aspects may be described or claimed in the singular, but the plural is contemplated unless explicitly stated to be limited to the singular. Additionally, all or part of any aspect may be used in conjunction with all or part of any other aspect, unless otherwise specified. Accordingly, the present disclosure should not be limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of manufacturing a trap, comprising: preparing the back surface of a substrate for subsequent processing; after the step of preparing the back surface of the substrate, constructing a stack of multiple layers on the front surface of the substrate, the stack of multiple layers including at least one metal layer for routing and at least one metal layer for an upper electrode; after constructing the stack of multiple layers on the front surface of the substrate, shaping the substrate by processing the back surface of the substrate.

2. The method according to claim 1, wherein the substrate is made of a glass material or a dielectric material.

3. The method according to claim 1, wherein the substrate is made of fused silica.

4. The method according to claim 1, wherein the step of preparing the back surface of the substrate includes applying at least one laser scribing step to prepare the back surface of the substrate for selective etching.

5. The method according to claim 1, wherein the step of preparing the back surface of the substrate includes partially shaping the substrate by removing a part of the substrate from the back surface of the substrate.

6. The method according to claim 5, wherein the step of removing the part of the substrate includes applying one or more laser scribing steps and one or more etching steps.

7. The method according to claim 5, wherein a meniscus is left near the front surface of the substrate by the step of removing the part of the substrate.

8. The method according to claim 7, further comprising a step of removing the meniscus.

9. The method according to claim 8, wherein: the step of constructing the stack of multiple layers includes placing a protective layer on the stack of multiple layers; the step of removing the meniscus is performed after the protective layer is placed on the stack of multiple layers.

10. The method according to claim 1, wherein the step of constructing the stack of multiple layers includes: placing a first metallization on the front surface of the substrate; placing a dielectric layer on the first metallization; placing a second metallization on the dielectric layer, wherein the first metallization is part of at least one metal layer for routing and the second metallization is part of at least one metal layer for the upper electrode.

11. The method according to claim 10, wherein the step of disposing the dielectric layer includes forming vias in the dielectric layer to enable connection between the first metallization and the second metallization.

12. The method according to claim 10, wherein the step of disposing the first metallization includes patterning the first metallization to provide the routing.

13. The method according to claim 10, wherein the step of disposing the second metallization includes patterning the second metallization to provide the upper electrode.

14. The method according to claim 10, wherein the step of disposing the first metallization, the step of disposing the second metallization, or both include an electroplating process.

15. The method according to claim 1, wherein the step of constructing the stack of multiple layers includes disposing a protective layer on the stack of multiple layers, the step of shaping the substrate by processing the back surface of the substrate includes removing a part of the substrate from the back surface of the substrate to form a hole penetrating the thickness of the substrate.

16. The method according to claim 15, further including a step of shaping the stack of multiple layers by removing a part of the stack of multiple layers for the hole penetrating the substrate so as to extend through the stack of multiple layers.

17. The method according to claim 16, wherein the stack of multiple layers includes a dielectric layer having a plurality of dams and the hole extending through the stack of multiple layers extending between the dams of the dielectric layer.

18. The method according to claim 16, further including a step of removing the protective layer.

19. An ion trap, comprising a substrate made of a glass material or a dielectric material, a stack of multiple layers disposed on the substrate, including at least one metal layer for routing, at least one dielectric layer, and at least one metal layer for the upper electrode, wherein the substrate and the stack of multiple layers are shaped to form a hole penetrating the substrate and extending through the stack of multiple layers.

20. An ion trap, comprising a substrate made of a glass material or a dielectric material, It includes a stack of a plurality of layers disposed on the substrate, including at least one metal layer for routing, at least one dielectric layer, and at least one metal layer for the upper electrode. The substrate and the stack of the plurality of layers are shaped to form an ion trap that penetrates the substrate and extends through the stack of the plurality of layers. A quantum information processing system including a supply source configured to provide atomic species from the back surface of the ion trap, through the holes of the substrate and the stack of the plurality of layers of the ion trap, to the upper surface of the ion trap.

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