Pixel Circuit and Display Panel

Abstract

The present application discloses a pixel circuit and a display panel. The pixel circuit includes a driving module, a first reset module, a data writing module, a first light emission control module, a second light emission control module, and a memory module. The first reset module is connected to the driving module, the data writing module is connected to the driving module, the first light emission control module is connected in series between a light emitting element, a positive voltage power supply, and the driving module, the second light emission control module is connected between the driving module and a negative voltage power supply, and the memory module is electrically connected to the driving module.

Description

Technical Field

[0001] This application claims the priority of a Chinese patent application with an application number of 202310445544.8, filed with the Chinese Patent Office on April 21, 2023, and all the contents of the application are incorporated herein by reference.

[0002] Embodiments of the present application relate to the field of display technology, for example, pixel circuits and display panels.

Background Art

[0003] With the continuous development of display technology, the application scope of display panels is becoming increasingly wide, and the requirements of users for display panels are also increasing. Pixel circuits in display panels play a very important role in driving light-emitting elements to emit light stably. However, in the related art, in the display process, the gate electrode potential of the driving transistor in the pixel circuit is not stable, which affects the stable output of the driving current, affects the display brightness of the light-emitting element, and further affects the display uniformity of the display panel.

Summary of the Invention

Problems to be Solved by the Invention

[0004] This application provides a pixel circuit and a display panel, which can stabilize the potential of the control end of the driving module in the pixel circuit, output a stable driving current in the light-emitting stage of the pixel circuit, and is beneficial to improving the display uniformity of the display panel.

Means for Solving the Problems

[0005] On a first side, an embodiment of the present application provides a pixel circuit including: a driving module configured to generate a driving current based on the potential of its control terminal; a first reset module connected to the control terminal of the driving module and configured to transmit a first reset signal to the control terminal of the driving module in response to a first scanning signal; a data writing module connected to the driving module and configured to transmit a data voltage to the driving module in response to a second scanning signal; a first light-emitting control module connected in series between a light-emitting element, a positive voltage power supply, and a second terminal of the driving module, configured to be conducted in response to a light-emitting control signal, and configured to transmit a first power signal provided from the positive voltage power supply to the second terminal of the driving module through the cathode of the light-emitting element; a second light-emitting control module connected between a first terminal of the driving module and a negative voltage power supply and configured to be conducted in response to the light-emitting control signal; and a storage module electrically connected to the control terminal of the driving module and configured to store the potential of the control terminal of the driving module.

[0006] On a second side, an embodiment of the present application further provides a display panel including a plurality of pixel circuits according to any embodiment of the present application.

Advantages of the Invention

[0007] Based on the fact that the cathodes of a plurality of light-emitting elements are isolated and the cathode potential of the plurality of light-emitting elements can be individually controlled in the embodiments of the present application, a circuit structure is provided in which the cathode of the light-emitting element accesses the pixel circuit. By connecting the cathode of the light-emitting element directly or indirectly to the second end of the driving module, it is possible to connect the first end of the driving module to the negative voltage power supply by the second light-emitting control module. In the light-emitting stage, the second light-emitting control module is conducted, and a second power signal provided from the negative voltage power supply is stably accessed to the first end of the driving module, thereby maintaining the potential of the first end of the driving module unchanged. At the same time, by providing a memory module, the function of storing charges and preserving the potential is provided in the light-emitting stage, and the potential of the control end of the driving module can be maintained unchanged. Therefore, the pixel circuit according to the embodiments of the present application can control the potentials of the control end and the first end of the driving module not to change in the light-emitting stage. Compared with the related art in which the potentials of the gate electrode and the source electrode of the driving transistor both change in the light-emitting stage, the embodiments of the present application can more easily ensure that the potential difference between the control end and the first end of the driving module remains unchanged. As a result, since the driving current output from the driving module remains unchanged, the luminance in the light-emitting stage of the light-emitting element does not change, which is advantageous for improving the display uniformity of the display panel. And the memory module in the embodiments of the present application does not need to provide a coupling effect, and only needs to provide the function of potential holding, which can reduce the influence degree of the memory module on the emission luminance, has lower design requirements for the memory module, and can set the structure of the memory module and its layout in the display panel more flexibly.

Brief Description of the Drawings

[0008]

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Embodiments for Carrying Out the Invention

[0009] In the specification and claims of the present application, and in the above drawings, terms such as "first", "second", etc. are not necessarily used to explain a specific order or sequence, but are for distinguishing similar objects. Data used in this way can be replaced when appropriate, and it should be understood that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. Also, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0010] As described in the background art, in the related art, in the display process, the gate electrode potential of the driving transistor is not stable, which affects the display uniformity of the display panel. According to the applicant's research, the reasons for the above situation are as follows. The pixel circuits in related art small-size display products usually adopt an LTPS (Low Temperature Poly-Silicon) pixel circuit, that is, a structure in which all transistors in the pixel circuit are P-type transistors, or an LTPO (Low Temperature Polycrystalline and Oxide) pixel circuit, that is, a structure in which some transistors in the pixel circuit are P-type transistors and some transistors are N-type transistors. In the above pixel circuits, all driving transistors are P-type transistors. However, for medium-size / large-size products, due to the defect that the leakage current of P-type transistors is large and the long-distance uniformity is poor, the applicable degree of the above pixel circuits is low, and in medium-size / large-size products manufactured by adopting the above pixel circuits, the situation of poor luminance uniformity is likely to appear. Therefore, in the medium-size / large-size field, in order to improve the display uniformity by utilizing the advantages that the leakage current of N-type IGZO transistors is low and the long-distance uniformity is good, a pixel circuit based on IGZO (Indium Gallium Zinc Oxide), that is, a structure in which all transistors in the pixel circuit are N-type transistors, has been proposed.

[0011] FIG. 1 is a schematic circuit diagram of a pixel circuit in the related art. Referring to FIG. 1, the all-N-type pixel circuit in the related art includes a driving transistor M01 and switching transistors M02 to M06. The signals accessed by the transistors include a scanning signal S01, S02, and S03, an emission control signal EM01 and EM02, a first power supply signal VDD, a second power supply signal VSS, a data voltage Data, and a reset signal Vref0. FIG. 2 is a schematic film layer structure diagram of the pixel circuit in the related art. The structures of the switching transistors M05 and M06 are omitted in FIG. 2, and mainly the connection structure between the driving transistor M01 and the light-emitting element OLED is shown. In actual manufacturing, the driving transistor M01 can be connected to the light-emitting element OLED by the switching transistor M06. Combining FIGS. 1 and 2, the film layer structure of the all-N-type pixel circuit in the related art uses the film layer structure of the LTPS pixel circuit as it is, and includes an active layer 010, a first metal layer 011, a second metal layer 012, and a third metal layer 013, which are laminated and provided on a substrate 001. The light-emitting element OLED also has a common cathode structure, that is, the cathodes of a plurality of light-emitting elements OLED in the display panel are provided on the entire surface, and the same cathode voltage VSS is applied. The light-emitting element OLED includes an anode 021 laminated and provided on the side far from the substrate 001 of the third metal layer 013, a light-emitting functional layer 022, and a cathode 023. The anode of the light-emitting element OLED is connected to the pixel circuit, and the pixel circuit individually controls the anode potential of the corresponding light-emitting element OLED.

[0012] After adjusting the driving transistor M01 so that the N-type transistor is connected to the anode of the light-emitting element OLED, since the current flow direction during the light emission of the light-emitting element OLED is from the anode to the cathode, the source electrode of the driving transistor M01 is connected to the anode of the light-emitting element OLED. For example, ignoring the switching transistors M05 and M06, the current path in the light-emitting stage is: power supply line LVDD (used for transmitting the power supply signal VDD) → drain electrode M011 of the driving transistor M01 → channel region M012 of the driving transistor M01 → source electrode M013 of the driving transistor M01 → anode 021 of the light-emitting element OLED → light-emitting functional layer 022 → cathode 023 of the light-emitting element OLED. On the other hand, since the anode potential of the light-emitting element OLED changes during light emission, the gate-source voltage difference of the driving transistor M01 constantly changes during the light-emitting process, and the driving current output from the driving transistor M01 becomes unstable. To avoid the above situation, in the related art, a capacitor Cst0 is provided in the pixel circuit to be connected to the gate electrode of the driving transistor M01 and the anode of the light-emitting element OLED respectively. When the switching transistor M06 is turned on, the capacitor Cst0 corresponds to being connected between the gate electrode and the source electrode of the driving transistor M01. In the light-emitting stage, the capacitor Cst0 maintains the gate-source voltage difference of the driving transistor M01 based on its coupling effect. However, the coupling effect of the capacitor is affected by the size of the capacitor Cst0 and cannot maintain the gate-source voltage difference of the driving transistor M01 unchanged by 100%. Furthermore, in this design, the capacitor Cst0 not only affects the charging efficiency during the data writing process but also affects the gate electrode potential of the driving transistor M01 after coupling by the capacitor during the light-emitting stage, and the influence of the capacitance size on the driving current is large.

[0013] From the above, in the related art, since the light-emitting element OLED has a common cathode structure, the pixel circuit based on all N-type transistors can only be connected to the anode of the light-emitting element OLED, and individual control of the anode potentials of a plurality of light-emitting elements OLED has been realized. Due to the above limitations, in the light-emitting stage, the gate-source voltage difference of the driving transistor in the pixel circuit becomes unstable, so that the driving current output from the pixel circuit becomes unstable, affecting the display uniformity.

[0014] The applicant designs an element structure in which the cathodes of each light-emitting element are individually separated, and based on this, designs a pixel circuit structure in which the driving transistor is electrically connected to the cathode of the light-emitting element and the cathode potential of the light-emitting element can be individually controlled, thereby stabilizing the gate electrode potential of the driving transistor in the pixel circuit in the light-emitting stage. In the manufacturing process of the display panel, by providing an isolation structure to separate the cathodes of adjacent light-emitting elements, the cathodes of a plurality of light-emitting elements can be connected to the corresponding pixel circuits respectively, and individual control of the cathode potentials of a plurality of light-emitting elements by the pixel circuit can be realized. Hereinafter, first, the structure and operation principle of the pixel circuit, and the connection relationship between the light-emitting element and the pixel circuit will be described.

[0015] FIG. 3 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present application. Referring to FIG. 3, the pixel circuit includes a driving module 10, a first reset module 20, a data writing module 30, a first light-emitting control module 40, a second light-emitting control module 50, and a storage module 60.

[0016] Among them, the driving module 10 is configured to generate a driving current based on the potential of the control terminal G of the driving module 10. The first reset module 20 is connected to the control terminal G of the driving module 10 and is configured to transmit a first reset signal Vref1 to the control terminal G of the driving module 10 in response to a first scan signal Scan1. The data writing module 30 is connected to the driving module 10 and is configured to transmit a data voltage Data to the driving module 10 in response to a second scan signal Scan2. The first light emission control module 40 and the light emitting element OLED are connected in series between the positive voltage power supply and the second terminal D of the driving module 10. The first light emission control module 40 is configured to be conducted in response to a light emission control signal EM and transmit a first power supply signal ELVDD provided from the positive voltage power supply to the second terminal D of the driving module 10 through the cathode of the light emitting element OLED. The second light emission control module 50 is connected between the first terminal S of the driving module 10 and the negative voltage power supply and is configured to be conducted in response to the light emission control signal EM. The memory module 60 is electrically connected to the control terminal G of the driving module 10 and is configured to store the potential of the control terminal G of the driving module 10.

[0017] Exemplarily, the specific connection method of a plurality of functional modules in the pixel circuit may be as follows. The first reset module 20 has a first scan line connected to its control terminal, and accesses the first scan signal Scan1. A first reset signal line is connected to its first terminal, and accesses the first reset signal Vref1. The control terminal G of the driving module 10 is connected to its second terminal. The data writing module 30 has a second scan line connected to its control terminal, and accesses the second scan signal Scan2. A data line is connected to its first terminal, and inputs the data voltage Data. The first terminal S of the driving module 10 is connected to its second terminal, the control terminal G of the driving module 10 is connected to its third terminal, and the second terminal D of the driving module is connected to its fourth terminal. The data writing module 30 is configured to transmit a signal carrying the data voltage Data information and the threshold voltage information of the driving module 10 to the control terminal G of the driving module 10. The first light emission control module 40 has a light emission control signal line connected to its control terminal, and accesses the light emission control signal EM. A first power supply signal line is connected to its first terminal, and accesses the first power supply signal ELVDD output from the positive voltage power supply. The anode of the light emitting element OLED is connected to its second terminal. The second terminal D of the driving module 10 is connected to the cathode of the light emitting element OLED. The second light emission control module 50 has a light emission control signal line connected to its control terminal, and accesses the light emission control signal EM. The first terminal S of the driving module 10 is connected to its first terminal, a second power supply signal line is connected to its second terminal, and accesses the second power supply signal ELVSS output from the negative voltage power supply. The storage module 60 has the control terminal G of the driving module 10 connected to its first terminal, and a fixed potential signal line connected to its second terminal, and accesses the fixed potential signal V1, thereby realizing the potential holding for the control terminal G of the driving module 10.

[0018] Among them, the first scanning signal Scan1, the second scanning signal Scan2, and the light emission control signal EM are all scanning signals that alternately convert between a high potential and a low potential. The first power supply signal ELVDD, the second power supply signal ELVSS, the first reset signal Vref1, and the fixed potential signal V1 are all DC voltage signals with fixed potentials. Exemplarily, the first power supply signal ELVDD and the first reset signal Vref1 are at a high potential, and the second power supply signal ELVSS is at a low potential.

[0019] Figure 4 is a schematic diagram of the time sequence of driving a pixel circuit according to an embodiment of the present application. Referring to FIGS. 3 and 4, taking as an example that the conduction potentials of a plurality of functional modules are all at a high potential, the driving process of the pixel circuit includes the following. In the gate electrode reset stage T1, the first scanning signal Scan1 is at a high potential, and the second scanning signal Scan2 and the light emission control signal EM are both at a low potential. The first reset module 20 is conducted, and the first reset signal Vref1 is transmitted to the control terminal G of the driving module 10. In this stage, the first reset signal Vref1 resets the control terminal G of the driving module 10, prepares for the writing of the next data, and ensures that the driving module 10 can be surely conducted in the data writing stage T2.

[0020] In the data writing stage T2, the second scanning signal Scan2 is at a high potential, and the first scanning signal Scan1 and the light emission control signal EM are both at a low potential. The data writing module 30 is conducted, and the data voltage Data is written to the control terminal G of the driving module 10 through the first terminal S and the second terminal D of the driving module 10.

[0021] In the light-emitting stage TE, the light-emitting control signal EM is at a high level, and both the first scanning signal Scan1 and the second scanning signal Scan2 are at low levels. Both the first light-emitting control module 40 and the second light-emitting control module 50 are turned on, conducting the series path between the driving module 10 and the light-emitting element OLED between the positive voltage power supply and the negative voltage power supply. The driving module 10 generates a driving current to drive the light emission of the light-emitting element OLED. At this stage, based on the storage function of the storage module 60, the potential of the control terminal G of the driving module 10 is stably held at the potential written in the data writing stage T2. The second power supply signal ELVSS is transmitted to the first terminal S of the driving module 10 through the second light-emitting control module 50. Since the potential of the second power supply signal ELVSS does not change, the potential of the first terminal S of the driving module 10 also does not change. Therefore, the potential difference between the control terminal G and the first terminal S of the driving module 10 is held unchanged in the light-emitting stage TE. As a result, the driving module 10 can stably output a driving current with a constant magnitude corresponding to this potential difference in the light-emitting stage TE, and can drive the stable light emission of the light-emitting element OLED.

[0022] Based on the fact that the cathodes of a plurality of light-emitting elements OLED are isolated and the cathode potentials of the plurality of light-emitting elements OLED can be individually controlled, the embodiments of the present application provide a circuit structure in which the cathode of the light-emitting element OLED accesses the pixel circuit. By connecting the cathode of the light-emitting element OLED directly or indirectly to the second terminal D of the driving module 10, it is possible to connect the first terminal S of the driving module 10 to the negative voltage power supply by the second light-emitting control module 50. In the light-emitting stage, the second light-emitting control module 50 is turned on, and the second power signal ELVSS provided from the negative voltage power supply is stably accessed at the first terminal S of the driving module 10, whereby the potential of the first terminal S of the driving module 10 is maintained unchanged. At the same time, by providing the memory module 60, it is possible to provide the function of storing charges and preserving the potential in the light-emitting stage, and to maintain the potential of the control terminal G of the driving module 10 unchanged. Therefore, the pixel circuit according to the embodiments of the present application can control the potentials of the control terminal G and the first terminal S of the driving module 10 not to change in the light-emitting stage TE. Compared with the mode in the related art where the potentials of the gate electrode and the source electrode of the driving transistor both change in the light-emitting stage, the embodiments of the present application can more easily ensure that the potential difference between the control terminal G and the first terminal S of the driving module 10 does not change. As a result, the driving current output from the driving module 10 does not change, so the luminance in the light-emitting stage of the light-emitting element OLED does not change, which is advantageous for improving the display uniformity of the display panel. And the memory module 60 in the embodiments of the present application does not need to provide a coupling effect, and only needs to provide the function of potential holding, which can reduce the influence degree of the memory module 60 on the light-emitting luminance OLED, the design requirements for the memory module 60 are lower, and the structure of the memory module 60 and its layout in the display panel can be set more flexibly.

[0023] FIG. 5 is a schematic circuit diagram of another pixel circuit according to an embodiment of the present application. Referring to FIG. 5 and based on the above embodiment, for example, the driving module 10 includes a driving transistor DTFT whose gate electrode is connected to the control terminal G of the driving module 10, the first pole is connected to the first terminal S of the driving module 10, and the second pole is connected to the second terminal D of the driving module 10. In this embodiment, the driving module 10 is composed of one transistor, which simplifies the structure of the driving module 10 and makes it easy to implement. Exemplarily, for the driving transistor DTFT, the first pole is its source electrode and the second pole is its drain electrode.

[0024] Continuing to refer to FIG. 5 and based on the above embodiment, for example, the first reset module 20 includes a first transistor M1 whose gate electrode is connected to the first scanning line, the first pole is connected to the control terminal G of the driving module 10, and the second pole is connected to the first reset signal line. In this embodiment, the first reset module 20 is composed of one transistor, which simplifies the structure of the first reset module 20 and makes it easy to implement.

[0025] Continuing to refer to FIG. 5 and based on the above embodiment, for example, the data writing module 30 includes a data writing unit 301 and a threshold compensation unit 302. Among them, the data writing unit 301 is connected to the first terminal S of the driving module 10 and is configured to be conducted in response to the second scanning signal Scan2 and transmit the data voltage Data to the first terminal S of the driving module 10. The threshold compensation unit 302 is connected between the control terminal G and the second terminal D of the driving module 10 and is configured to be conducted in response to the second scanning signal Scan2 and perform threshold voltage compensation on the driving module 10.

[0026] For example, the data writing unit 301 includes a second transistor M2, and the threshold compensation unit 302 includes a third transistor M3. A second scanning line is connected to the gate electrodes of both the second transistor M2 and the third transistor M3. The second transistor M2 has a data line connected to its first pole and the first end S of the driving module 10 connected to its second pole. The third transistor M3 has a control end G of the driving module 10 connected to its first pole and the second end D of the driving module 10 connected to its second pole. In this embodiment, the second transistor M2 is connected between the gate electrode and the second pole of the driving transistor DTFT. When both the second transistor M2 and the third transistor M3 are turned on in response to the second scanning signal Scan2, the gate electrode and the second pole of the driving transistor DTFT are connected to form a diode connection form. After the data voltage Data is written to the first pole of the driving transistor DTFT by the second transistor M2, it can be written to the gate electrode of the driving transistor DTFT through the driving transistor DTFT and the third transistor M3. When the potential difference between the gate electrode and the first pole of the driving transistor DTFT is equal to the threshold voltage Vth of the driving transistor DTFT, the driving transistor DTFT is turned off. Therefore, the gate electrode potential of the driving transistor DTFT is maintained at the value of Data + Vth, which is equivalent to storing the information of the data voltage Data and the threshold voltage of the driving transistor DTFT at the same time. This is advantageous for eliminating the influence on the driving current due to the threshold voltage shift of the driving transistor DTFT in the subsequent light-emitting stage and compensating for the influence on the display effect due to the non-uniformity of the threshold voltage of the driving transistor DTFT.

[0027] Continuing to refer to FIG. 5, based on the above embodiment, for example, the first light emission control module 40 includes a fourth transistor M4 whose gate electrode is connected to a light emission control signal line and is connected in series between the light emitting element OLED, a positive voltage power supply, and the second terminal D of the driving module 10. For example, the fourth transistor M4 has a first power signal ELVDD accessed at its first pole, the anode of the light emitting element OLED connected to its second pole, and the second terminal D of the driving module 10 connected to the cathode of the light emitting element OLED. In this embodiment, the first light emission control module 40 is composed of one transistor, simplifying the structure of the first light emission control module 40 and making it easy to implement.

[0028] Continuing to refer to FIG. 5, based on the above embodiment, for example, the second light emission control module 50 includes a fifth transistor M5 whose gate electrode is connected to a light emission control signal line, whose first pole is connected to the first terminal S of the driving module 10, and whose second pole is connected to a negative voltage power supply. In this embodiment, the second light emission control module 50 is composed of one transistor, simplifying the structure of the second light emission control module 50 and making it easy to implement.

[0029] Based on the above embodiment, for example, the memory module 60 has its first terminal connected to the control terminal G of the driving module 10, and at least one fixed potential signal can be accessed at its second terminal, thereby providing the function of potential holding. As shown in FIG. 5, illustratively, one fixed potential signal is accessed by the memory module 60, and the memory module 60 includes one memory unit 610 whose first terminal is connected to the control terminal G of the driving module 10 and whose second terminal has the fixed potential signal V1 accessed. For example, the memory unit 610 may include a capacitor Cst whose first terminal is the first terminal of the memory unit 610 and whose second terminal is the second terminal of the memory unit 610. In this embodiment, the memory unit 610 is composed of a capacitor Cst, simplifying the structure of the memory unit 610 and making it easy to implement.

[0030] Continuing to refer to FIG. 5, based on the above embodiment, for example, in the pixel circuit, a second reset module 70 is further provided which is electrically connected to the cathode of the light-emitting element OLED, responds to the third scan signal Scan3, and is configured to transmit the second reset signal Vref2 to the cathode of the light-emitting element OLED. In this embodiment, by providing the second reset module 70, before the light-emitting stage, the second reset signal Vref2 is adopted to initialize the cathode of the light-emitting element OLED, and the residual charge in the previous frame of the light-emitting element OLED can be eliminated, which is advantageous for improving the contrast. Exemplarily, the second reset signal Vref2 may be a DC voltage signal having a low potential.

[0031] For example, the second reset module 70 may include a sixth transistor M6. The third scan line is connected to the gate electrode of the sixth transistor M6, the third scan signal Scan3 is accessed, the cathode of the light-emitting element OLED is connected to the first pole of the sixth transistor M6, the second reset signal line is connected to the second pole of the sixth transistor OLED, and the second reset signal Vref2 is accessed. In this embodiment, the second reset module 70 is provided with one transistor, simplifying the structure of the second reset module 70 and making it easy to implement.

[0032] Referring to FIG. 5, exemplarily, all of the plurality of transistors in the pixel circuit are N-type transistors, and an all-N-type pixel circuit may be formed. Based on the characteristic that the leakage current of the N-type transistor is low, it is advantageous to improve the display uniformity of the display panel and apply the pixel circuit to products of medium / large sizes in particular, and it is also advantageous for realizing low-frequency display of the display panel.

[0033] FIG. 6 is a schematic diagram of the time sequence of driving another pixel circuit according to an embodiment of the present application. Taking the pixel circuit being an all-N-type pixel circuit in connection with FIGS. 5 and 6 as an example, the driving process of the pixel circuit may include the following. In the cathode reset stage T0, the third scan signal Scan3 is at a high level, and the first scan signal Scan1, the second scan signal Scan2, and the emission control signal EM are all at a low level. The sixth transistor M6 is turned on, and the second reset signal Vref2 is transmitted to the cathode of the light-emitting element OLED via the sixth transistor M6, and the cathode of the light-emitting element OLED is reset to eliminate the residual charge in the previous frame, which is beneficial to improving the contrast. At the same time, since the gate electrode of the driving transistor DTFT maintains the potential of the previous frame, the driving transistor DTFT remains turned on in this stage, and the second reset signal Vref2 is transmitted to the second pole of the driving transistor DTFT via the sixth transistor M6, and then transmitted to the first pole of the driving transistor DTFT via the driving transistor DTFT, and the first pole and the second pole of the driving transistor DTFT are reset, which is beneficial to correcting the threshold voltage shift of the driving transistor DTFT and improving the phenomenon that the luminance of the first frame is low during tone change.

[0034] In the gate electrode reset stage T1, the first scan signal Scan1 is at a high level, and the second scan signal Scan2, the third scan signal Scan3, and the emission control signal EM are all at a low level. The first transistor M1 is turned on, and the first reset signal Vref1 is transmitted to the gate electrode of the driving transistor DTFT via the first transistor M1, and the gate electrode of the driving transistor DTFT is reset to change the gate electrode of the driving transistor DTFT to a high level.

[0035] In the data writing stage T2, the second scanning signal Scan2 is at a high level, and the first scanning signal Scan1, the third scanning signal Scan3, and the light emission control signal EM are all at low levels. The second transistor M2 and the third transistor M3 are turned on, and the data voltage Data is transmitted to the gate electrode of the driving transistor DTFT through the second transistor M2, the first and second electrodes of the driving transistor DTFT, and the third transistor M3. In the data writing process, the gate electrode potential Vg of the driving transistor DTFT continuously decreases from the high level of the first reset signal Vref1. When the potential difference Vgs = Vth between the gate electrode and the first electrode of the driving transistor DTFT is reached, the driving transistor DTFT is cut off. At this time, the gate electrode potential of the driving transistor DTFT stops changing and is maintained at Vg = Data + Vth, where Vth is the threshold voltage of the driving transistor DTFT.

[0036] In the cathode precharge stage T3, the third scanning signal Scan3 is at a high level, and the first scanning signal Scan1, the second scanning signal Scan2, and the light emission control signal EM are all at low levels. The sixth transistor M6 is turned on, and the second reset signal Vref2 precharges the cathode of the light-emitting element OLED through the sixth transistor M6. Thereby, the lighting speed of the light-emitting element OLED at low brightness is increased, the flicker caused by the too-slow lighting at low brightness due to the low mobility of the IGZO driving transistor is improved, and at the same time, the phenomenon of display non-uniformity at even lower brightness can be improved.

[0037] JPEG2025517049000002.jpg94169

[0038] The pixel circuit according to the embodiment of the present application provides the light-emitting element OLED between two light-emitting control modules, for example, by providing it between the first light-emitting control module 40 and the driving module 10. Therefore, in the time period when the light-emitting control signal EM is at a low potential, since both of the two light-emitting control modules are cut off and the power supply source of the light-emitting element OLED can be disconnected, the light-emitting element OLED can be controlled to be completely turned off, and the phenomenon of accidental lighting of the light-emitting element OLED caused by leakage of the sixth transistor M6 can be effectively avoided. At the same time, the range of the initialization voltage (i.e., the second reset signal Vref2) of the cathode of the light-emitting element OLED can be greatly expanded. Thereby, it is possible to enable the second reset signal Vref2 to provide a sufficiently low potential to the cathode of the light-emitting element OLED, and there is no need to worry about the situation where the light-emitting element OLED cannot be blocked by a black screen. Based on this, by setting the cathode reset stage T0, it is possible to achieve a complete reset of the state of the driving transistor DTFT before data is written, which is advantageous for improving situations such as a decrease in the luminance of the first frame, low-frequency flicker, and frequency-switching flicker. And by resetting the cathode potential of the light-emitting element OLED, the residual charge from the previous frame of the cathode of the light-emitting element OLED can be eliminated, and the contrast can be improved. And by setting the cathode pre-charge stage T3, the cathode of the light-emitting element OLED can be pre-charged before light emission. Especially when in a low-luminance section, by pre-charging the cathode of the light-emitting element OLED to a low potential in advance, the lighting speed of the light-emitting element OLED can be increased, and the low-frequency flicker caused by the slow lighting speed of the light-emitting element OLED due to the low mobility of the IGZO driving transistor can be improved. The phenomenon of non-uniform luminance caused by non-uniform lighting speed in the low-luminance section can be improved.

[0039] In the above embodiment, in connection with a specific pixel circuit, the circuit connection relationship and operating principle of the pixel circuit have been described. Hereinafter, the film layer structure of the pixel circuit will be specifically described.

[0040] FIG. 7 is a schematic diagram of the film layer structure of a pixel circuit according to an embodiment of the present application. FIG. 7 shows a specific arrangement method of film layers in a display panel of one pixel circuit. Also, FIG. 7 mainly shows a series structure between a driving transistor DTFT and a light-emitting element OLED between a positive voltage power supply and a negative voltage power supply, and the structures of the fourth transistor M4 and the fifth transistor M5 are omitted. At the same time, FIG. 7 shows the structure of a capacitor Cst.

[0041] Referring to FIG. 7, exemplarily, the display panel includes an active layer 82, a gate insulating layer 83, a first metal layer 84, a capacitor intermediate dielectric layer 85, a second metal layer 86, an interlayer insulating layer 87, an organic insulating layer 88, a third metal layer 89, a planarization layer 90, an anode layer, a light-emitting functional layer, a cathode layer, a first inorganic encapsulation layer 96, an organic encapsulation layer 97, and a second inorganic encapsulation layer 98, which are sequentially stacked on a substrate 81. Among them, the anode 91 of the light-emitting element OLED is provided in the anode layer, the light-emitting function-related film layer 93 is provided in the light-emitting functional layer, the cathode 94 is provided in the cathode layer, the anodes 91 of a plurality of light-emitting elements OLED are separated by a pixel definition layer 92, and the light-emitting function-related film layers 93 and the cathodes 94 of a plurality of light-emitting elements OLED are separated by an isolation structure 95.

[0042] Among them, the substrate 81 is configured to place a plurality of upper film layers and may be manufactured by adopting an organic material such as polyimide (PI) or an inorganic material such as glass. The active layer 82 is configured to form the channel portion, source, and drain regions of the transistor in the pixel circuit. Its material can be, for example, a-Si, P-Si, IGZO, etc. As long as a PN junction can be formed, the specific material is not limited. The gate insulating layer 83 is configured to isolate the active layer 82 from the first metal layer 84 and may be made of an inorganic material such as silicon nitride or silicon oxide. The capacitor intermediate dielectric layer 85 is configured to isolate the first metal layer 84 from the second metal layer 86 and may be made of an inorganic material such as silicon nitride. Both the interlayer insulating layer 87 and the organic insulating layer 88 are configured to isolate the second metal layer 86 from the third metal layer 89. The interlayer insulating layer 87 may include stacked silicon nitride and silicon oxide. The planarization layer 90 is configured to isolate the third metal layer 89 from the anode layer and planarize the surface film layer to optimize the light emission of the pixel and flatten the film layer of the subsequent light-emitting element OLED. It can be manufactured by adopting an organic material. The material of the metal layer may be a metal material such as molybdenum or titanium-aluminum-titanium. The pixel definition layer 92 is configured to define the size of the pixel opening and can be manufactured by adopting an inorganic material. The first inorganic encapsulation layer 96, the organic encapsulation layer 97 (for example, an inkjet printing layer), and the second inorganic encapsulation layer 98 are configured to form the encapsulation film layer of the display panel.

[0043] Among them, the isolation structure 95 may be manufactured on the side away from the substrate 81 of the pixel definition layer 92 before depositing the light-emitting functional layer. The isolation structure 95 corresponding to the light-emitting element OLED may be provided surrounding the pixel opening corresponding to the light-emitting element OLED. The isolation structure 95 has a certain height. Thereby, when depositing the light-emitting functional layer and the cathode layer, the protruding isolation structure 95 separates the light-emitting functional related film layers 93 between different light-emitting element OLEDs, blocks the electrical connection between the cathodes 94 of adjacent light-emitting element OLEDs, and ensures that the cathode potentials of the plurality of light-emitting element OLEDs can be individually controlled. Exemplarily, the isolation structure 95 may have a structure that is wide at the top and narrow at the bottom. For example, the cross-sectional shape is an inverted trapezoid, thereby ensuring that the cathodes 94 of adjacent light-emitting element OLEDs are blocked from each other during the manufacture of the cathode layer.

[0044] Hereinafter, in connection with FIG. 7, the main components of the pixel circuit after abbreviation related to the dashed frame and the arrangement method in the plurality of film layers of the display panel of the plurality of signal lines will be described. Among them, the configurations of the fourth transistor M4 and the fifth transistor M5 are omitted in FIG. 7. In actual manufacturing, the second power signal line LVSS can be connected to the first pole MS of the driving transistor DTFT by the fifth transistor M5. Also, the cathode 94 of the light-emitting element OLED may be directly connected to the second pole MD of the driving transistor DTFT, or the cathode 94 of the light-emitting element OLED may be connected by the fourth transistor M4.

[0045] In one embodiment, for example, the channel region, source region, and drain region of the driving transistor DTFT are all provided in the active layer 82, the gate electrode MG of the driving transistor DTFT is provided in the first metal layer 84, and the projection in the thickness direction of the display panel covers the channel region of the driving transistor DTFT. Both the first pole MS and the second pole MD of the driving transistor DTFT are provided in the third metal layer 89, and the projections of the first pole MS and the second pole MD of the driving transistor in the thickness direction of the display panel cover the source region and the drain region of the driving transistor DTFT respectively, and the source region and the drain region of the driving transistor DTFT can be respectively connected to the first pole MS and the second pole MD of the driving transistor through via holes.

[0046] The fixed potential signal is provided from the fixed potential signal line LV1. The fixed potential signal line LV1 may be provided in the second metal layer 86 as shown in FIG. 7, or may be provided in another conductive film layer, for example, the third metal layer 89. Among them, the projection of the fixed potential signal line LV1 in the thickness direction of the display panel and the gate electrode MG of the driving transistor DTFT overlap at least partially, and the gate electrode MG of the driving transistor DTFT can be used as the first electrode plate C1 of the capacitor Cst. The connection between the first end of the capacitor Cst and the gate electrode MG of the driving transistor DTFT is realized. The overlapping part of the fixed potential signal line LV1 and the gate electrode MG of the driving transistor DTFT can be used as the second electrode plate C2 of the capacitor Cst, and the connection between the second end of the capacitor Cst and the fixed potential signal line LV1 is realized. Among them, the first electrode plate C1 and the second electrode plate C2 face each other to form the capacitor Cst, and the facing area between the first electrode plate C1 and the second electrode plate C2 can be set according to actual needs.

[0047] The isolation structure 95 may include a conductive material layer. The cathode 94 of the light-emitting element OLED contacts the isolation structure 95 and is electrically connected to the corresponding pixel circuit by the isolation structure 95, for example, electrically connected to the second pole MD of the driving transistor DTFT. The pixel circuit and the light-emitting element OLED may both be arranged in an array in the display panel. When the isolation structure 95 includes a conductive material layer, one isolation structure 95 may surround the outer periphery of each light-emitting element OLED. In this way, two adjacent light-emitting elements OLED can be isolated by the two isolation structures 95, and the two isolation structures 95 are insulated from each other. For example, by being isolated by the organic encapsulation layer 97, the electrical connection between the cathodes 94 of adjacent light-emitting elements OLED can be surely blocked. Before manufacturing the isolation structure 95, first, through holes are provided in the pixel definition layer 92 and the planarization layer 90 to expose the surface of the second pole MD of the driving transistor DTFT so as to realize the electrical connection between the isolation structure 95 and the second pole MD of the driving transistor DTFT, and then the isolation structure 95 may be manufactured on the pixel definition layer 92. Among them, the upper surface of the isolation structure 95 may be a flat surface anywhere. Alternatively, if the isolation structure 95 can cut the cathodes 94 of adjacent light-emitting elements OLED, the height corresponding to the area of the through hole may be lower than the height of other areas, and the height difference of the top surface of the isolation structure 95 itself can be filled flat by the organic encapsulation layer 97. Further, the cross-sectional shape of the isolation structure 95 can be understood as the cross-sectional shape of the portion located above the through hole of the isolation structure 95. The cross-sectional shape itself does not include the portion of the through hole, and the shape and size of the through hole itself can be arbitrarily set according to the manufacturing process and actual needs.

[0048] Continuing to refer to FIG. 7, by way of example, the positive voltage power supply is connected to the pixel circuit by the first power signal line LVDD, and is connected to, for example, the anode 91 of the light-emitting element OLED. The first power signal line LVDD may be provided in a conductive film layer located below the light-emitting functional layer, for example, provided in the second metal layer 86, the third metal layer 89, or the anode layer. In FIG. 7, it is shown as an example that the first power signal line LVDD is provided in the third metal layer 89. Also, the negative voltage power supply is connected to the pixel circuit by the second power signal line LVSS, and is connected to, for example, the first electrode MS of the driving transistor DTFT. The second power signal line LVSS may be provided in a conductive film layer located below the light-emitting functional layer, for example, provided in the second metal layer 86, the third metal layer 89, or the anode layer. In FIG. 7, it is shown as an example that the second power signal line LVSS is provided in the third metal layer 89. And the overlapping portion of the second power signal line LVSS and the source region of the driving transistor DTFT can be used as the first electrode MS of the driving transistor DTFT.

[0049] Based on the film layer structure in FIG. 7, starting from the first power signal line LVDD, a current path of the first power signal line LVDD → the anode 91 of the light-emitting element OLED → the light-emitting functional layer 93 of the light-emitting element OLED → the cathode 94 of the light-emitting element OLED → the isolation structure 95 → the second electrode MD of the driving transistor DTFT → the channel region of the driving transistor DTFT → the first electrode MS of the driving transistor DTFT → the second power signal line LVSS can be provided.

[0050] As can be seen from the above, in the pixel circuit according to the embodiment of the present application, by dividing the cathodes 94 of a plurality of light-emitting elements OLED into an isolation structure 95 that is wide at the top and narrow at the bottom, it is possible to ensure that the potentials of the cathodes 94 of the plurality of light-emitting elements OLED can be individually controlled. Further, the cathode 94 of the light-emitting element OLED is connected to the second pole MD of the N-type driving transistor DTFT by the isolation structure 95, the second power signal line LVSS is connected to the first pole MS of the driving transistor DTFT, and the capacitor Cst is connected to the gate electrode MG of the driving transistor DTFT, so as to ensure that the potential difference Vgs (i.e., the gate-source voltage difference) between the gate electrode and the first pole of the driving transistor DTFT remains unchanged during the light-emitting stage, and it is possible to ensure that the light-emitting current remains unchanged. And since the cathodes 94 of the plurality of light-emitting elements OLED are separated from each other, only the current of a single pixel circuit is applied to the cathode 94 of each light-emitting element OLED, and the main current of the entire panel is carried by two power signal wirings, namely the first power signal line LVDD and the second power signal line LVSS. On the other hand, both the first power signal line LVDD and the second power signal line LVSS are metal wirings provided below the light-emitting functional layer, which do not block the light-emitting surface of the light-emitting element OLED, and the transparency of the two power signal wirings does not affect the light emission of the light-emitting element OLED. Therefore, compared with the fully transparent cathode structure in the related art, in the film layer structure according to the embodiment of the present application, the materials of the two power signal wirings are not limited by transparency, and a material with lower resistance can be selected and manufactured according to needs, thereby reducing the voltage drop (IR Drop) of the power signal line and reducing the power consumption.

[0051] Based on the above embodiments, for example, the film layer structures of a plurality of transistors not shown in FIG. 7 may be distributed as follows. The active layer 82 may further include the channel regions, source regions, and drain regions of the first transistor M1 to the sixth transistor M6. The first metal layer 84 may further include the first scanning line, the second scanning line, the third scanning line, and the emission control signal line. Among them, the overlapping portions of the plurality of scanning lines, emission control signal lines, and the active layer 82 constitute the corresponding transistors. The plurality of scanning lines and emission control signal lines are further used as the gate electrodes of the plurality of transistors. The portion of the active layer 82 covered by the scanning line or the emission control signal line is the channel region of the transistor, and both sides of the channel region are the source region and the drain region respectively. For the transistor, the source region corresponds to its first pole, the drain region corresponds to its second pole, or for the transistor, the source region corresponds to its second pole, and the drain region corresponds to its first pole. The second metal layer 86 may further include the first reset signal line and the second reset signal line. The third metal layer 89 may further include the data line.

[0052] Based on the pixel circuit in FIG. 5, the above embodiments have explained in detail the structure and operation process of the all-N-type pixel circuit, but it does not limit the present application. In other embodiments, the pixel circuit may have other circuit structures, and correspondingly, may have other film layer structures. Some of the adjustment methods will be described below.

[0053] FIG. 8 is a schematic circuit diagram of still another pixel circuit according to an embodiment of the present application. Referring to FIG. 8, in one embodiment, for example, the first power supply signal ELVDD may be used as the first reset signal Vref1. Correspondingly, the first power supply signal line LVDD may be used as the first reset signal line, and thus, there is no need to separately provide the first reset signal line in the film layer structure.

[0054] The first power supply signal ELVDD and the first reset signal Vref1 are both high-potential signals. When they are transmitted through different signal lines, the first reset signal Vref1 may be provided from an individual power supply. Therefore, the first reset signal Vref1 has an adjustable voltage, whereby the gate electrode potential of the driving transistor DTFT can be provided according to needs in the gate electrode reset stage, which is advantageous for optimizing the display effect of the product. When the first power supply signal ELVDD is also used as the first reset signal Vref1, the number of signal lines in the display panel can be reduced, which is advantageous for reducing the space required for the designed wiring of the pixel, for the design of products with a high pixel density, and for reducing the number of output channels required for the driving chip.

[0055] In the above embodiment, for example, at least one of the first power supply signal ELVDD, the second power supply signal ELVSS, the first reset signal Vref1, and the second reset signal Vref2 may also be used as the fixed potential signal V1. Correspondingly, at least one of the first power supply signal line LVDD, the second power supply signal line LVSS, the first reset signal line, and the second reset signal line may also be used as the fixed potential signal line LV1. Therefore, it is not necessary to separately provide the fixed potential signal line LV1 in the display panel, which is advantageous for reducing the space required for the designed wiring of the pixel. When other signal lines are used and also used as the fixed potential signal line LV1, a second electrode plate C2 of the capacitor Cst may be separately provided at a position facing the gate electrode MG of the driving transistor DTFT in the second metal layer 86, and the second electrode plate C2 may be connected to the corresponding signal line by means such as via holes or jumpers. Exemplarily, as shown in FIG. 8, the second power supply signal ELVSS can also be used as the fixed potential signal V1.

[0056] In the above embodiment, the memory module 60 is exemplarily shown as having one fixed potential signal accessed and including one memory unit 610. However, this does not limit the present application. In other embodiments, for example, as shown in FIG. 9, the memory module 60 may be configured to include at least two memory units (here, having two memory units is shown as an example). The plurality of memory units all have the control terminal G of the driving module 10 connected to the first end, and different fixed potential signals are accessed to the second ends respectively. For example, as shown in FIG. 9, the first memory unit 611 includes the first capacitor Cst1, and the second power supply signal ELVSS can be accessed to its second end, and the second memory unit 612 includes the second capacitor Cst2, and the first power supply signal ELVDD can be accessed to its second end. In this embodiment, by configuring the memory module 60 to include a plurality of memory units and connecting a plurality of fixed potential signals to the plurality of memory units, it is advantageous for flexibly realizing a larger capacity design and improving the potential holding ability of the memory module 60.

[0057] In the above embodiment, the structure in which a positive voltage power supply is connected to the first end of the first light emission control module 40 and the driving module 10 is connected to the cathode of the light emitting element OLED is exemplarily shown. However, this does not limit the present application. In other embodiments, for example, as shown in FIG. 9, a positive voltage power supply may be connected to the anode of the light emitting element OLED, the first end of the first light emission control module 40 is connected to the cathode, and the second end D of the driving module 10 is connected to the second end of the first light emission control module 40. The second reset module 70 remains electrically connected to the cathode of the light emitting element OLED.

[0058] FIG. 10 is a schematic diagram of the time sequence of driving another pixel circuit according to an embodiment of the present application. The pixel circuit shown in FIG. 9 can be driven by adopting the time sequence of driving as shown in FIG. 10. In connection with FIGS. 9 and 10, the driving process of the pixel circuit includes the following. In the gate electrode reset stage T1, the first scan signal Scan1 is at a high potential, and the second scan signal Scan2, the third scan signal Scan3, and the light emission control signal EM are all at low potentials. The first transistor M1 is turned on, and the first reset signal Vref1 is transmitted to the gate electrode of the driving transistor DTFT through the first transistor M1 to reset the gate electrode of the driving transistor DTFT.

[0059] In the data writing stage T2, the second scan signal Scan2 and the third scan signal Scan3 are at high potentials, and the first scan signal Scan1 and the light emission control signal EM are both at low potentials. The second transistor M2 and the third transistor M3 are turned on, and the data voltage Data is transmitted to the gate electrode of the driving transistor DTFT through the second transistor M2, the first and second poles of the driving transistor DTFT, and the third transistor M3. Moreover, the sixth transistor M6 is turned on, and the second reset signal Vref2 is used to reset the cathode of the light emitting element OLED through the sixth transistor M6.

[0060] In the light emission stage TE, the light emission control signal EM is at a high potential, and the first scan signal Scan1, the second scan signal Scan2, and the third scan signal Scan3 are all at low potentials. Both the fourth transistor M4 and the fifth transistor M5 are turned on, and the driving transistor DTFT generates a driving current to drive the light emission of the light emitting element OLED.

[0061] In the driving time sequence shown in FIG. 10, the pulses of the third scanning signal Scan3 and the second scanning signal Scan2 overlap, that is, the cathode reset of the light-emitting element OLED and the data writing process of the driving transistor DTFT are performed simultaneously. However, the above time sequence does not limit the present application. In other embodiments, for example, before the light-emitting stage TE, the first light-emitting control module 40 remains blocked, and the potential of the second reset signal Vref2 is not transmitted to the second pole of the driving transistor DTFT. Therefore, the cathode reset stage of the light-emitting element OLED may be performed at any time within the time period when the light-emitting control signal EM is at a low potential, for example, simultaneously with the gate electrode reset stage T1.

[0062] FIG. 11 is a circuit structure schematic diagram of still another pixel circuit according to an embodiment of the present application. Referring to FIG. 11, based on the above embodiment, for example, in order to simplify the wiring of the display panel, the second scanning signal Scan2 may be used as the third scanning signal Scan3, and the pixel circuit can still adopt the driving time sequence as shown in FIG. 4. Alternatively, in order to simplify the wiring of the display panel, the first scanning signal Scan1 may be used as the third scanning signal Scan3, and in this case, the pixel circuit can still adopt the driving time sequence as shown in FIG. 4.

[0063] From the above, the embodiments of the present application are applied to the isolation of the cathodes of a plurality of light-emitting elements OLED, and provide a pixel driving circuit of all N-type transistors capable of individually controlling the cathode potential. In order to verify the effect of improving the display uniformity by the pixel circuit, the applicant simulated the pixel circuit structure of the related technology in FIG. 1 and the pixel circuit structure according to the embodiment of the present application in FIG. 8 respectively, and collected the changes in the potential of the key nodes in the pixel circuit during the light-emitting process. The simulation results can be referred to in FIGS. 12 and 13.

[0064] Referring to FIG. 12, when simulating a pixel circuit in the related art, the gate electrode potential VG, the first electrode potential VS, and the second electrode potential VD of the driving transistor are respectively collected. Further, the anode potential VA of the light-emitting element is collected. As can be seen from the simulation results in FIG. 12, in the related art, since the potential difference is maintained by utilizing the coupling of the capacitor, in the long time after the start of the light-emitting stage TE, the gate electrode potential VG and the first electrode potential VS of the driving transistor DTFT rise synchronously. In the long time after the start of the light-emitting stage TE, both the gate electrode potential VG and the first electrode potential VS of the driving transistor DTFT are constantly changing, and the voltage difference of Vgs is maintained by the coupling of the capacitor so as not to change as much as possible, but the voltage difference cannot be completely stably maintained.

[0065] Referring to FIG. 13, when simulating a pixel circuit according to an embodiment of the present application, the gate electrode potential VG, the first electrode potential VS, and the second electrode potential VD of the driving transistor are respectively collected. Further, the cathode potential VC of the light-emitting element is collected. As can be seen from the simulation results in FIG. 13, from the light-emitting stage TE, the gate electrode potential VG and the first electrode potential VS of the driving transistor DTFT are maintained to be constant and unchanged. Therefore, the pixel circuit according to the embodiment of the present application can surely maintain the gate electrode potential VG and the first electrode potential VS of the driving transistor DTFT.

[0066] Referring to FIG. 14, in order to verify the compensation effect corresponding to the non-uniformity of the threshold voltage of the driving transistor DTFT of the pixel circuit according to the embodiment of the present application, the applicant further simulated the percentage of luminance change when the threshold voltage Vth of the driving transistor DTFT varied by ±0.5V on the screens of gradations W255, W128, and W64 based on the pixel circuit according to the embodiment of the present application. As can be seen from this, in the 64 gradations, even when Vth varies by ±0.5V, the pixel circuit structure can ensure that the luminance change is only within 3%. This shows that the pixel circuit can achieve effective compensation for the non-uniformity of the threshold voltage Vth of the driving transistor DTFT and can surely improve the display uniformity of the display panel.

[0067] The embodiments of the present application further provide a display panel including a plurality of pixel circuits according to any embodiment of the present application and having corresponding beneficial effects. Exemplarily, the plurality of pixel circuits may be arranged in an array in the display area of the display panel. The scanning signal and the light emission control signal required for the pixel circuit can be provided through corresponding signal lines by a corresponding gate electrode driving circuit provided in the non-display area of the display panel, and the data voltage required for the pixel circuit can be provided through a data line by a driving chip.

[0068] In the embodiment of the pixel circuit, although the film layer structures in the display panels of different pixel circuits have been specifically described, any of these film layer structures may be considered as the film layer structure of the display panel according to the embodiment of the present application. For overlapping content, it will not be repeatedly described here.

[0069] For example, the display panel may include an active layer, a first metal layer, a second metal layer, a third metal layer, an anode layer, a light-emitting functional layer, and a cathode layer that are sequentially stacked. Among them, the channel region, source region, and drain region of the driving transistor are all provided in the active layer, the gate electrode of the driving transistor is provided in the first metal layer, and the projection in the thickness direction of the display panel covers the channel region of the driving transistor. The first electrode and the second electrode of the driving transistor are both provided in the third metal layer, and the source region and the drain region of the driving transistor are respectively connected to the first electrode and the second electrode of the driving transistor. The fixed potential signal is provided from a fixed potential signal line provided in the second metal layer or the third metal layer, and the projection in the thickness direction of the display panel at least partially overlaps with the gate electrode of the driving transistor. The overlapping portion of the fixed potential signal line and the gate electrode of the driving transistor forms a memory module. The positive voltage power supply may be connected to the pixel circuit by the first power signal line, the negative voltage power supply may be connected to the pixel circuit by the second power signal line, and both the first power signal line and the second power signal line may be provided in the conductive film layer below the light-emitting functional layer, for example, provided in the second metal layer, the third metal layer, or the anode layer. The display panel further includes a plurality of isolation structures provided to surround a plurality of light-emitting elements and configured to isolate the cathodes of adjacent light-emitting elements. Exemplarily, the isolation structure may include a conductive material layer, the cathode of the light-emitting element contacts the isolation structure, and is electrically connected to the corresponding pixel circuit by the isolation structure. The cross-sectional shape of the isolation structure may be a trapezoid with the top base narrower than the bottom base.

[0070] It should be understood that the various forms of flows shown above can be used, and the steps can be rearranged, added, or deleted. For example, the multiple steps described in the present application may be executed in parallel, sequentially, or in a different order, and as long as the desired results of the technical aspects of the present application can be achieved, this specification is not limited herein.

Claims

1. A driving module configured to generate a driving current based on the potential of its own control terminal; A first reset module connected to the control terminal of the driving module, configured to respond to a first scanning signal and transmit a first reset signal to the control terminal of the driving module; A data writing module connected to the driving module, configured to respond to a second scanning signal and transmit a data voltage to the driving module; A first light emission control module connected in series between a light emitting element, a positive voltage power supply, and a second terminal of the driving module, configured to be conducted in response to a light emission control signal and transmit a first power supply signal provided from the positive voltage power supply to the second terminal of the driving module through the cathode of the light emitting element; A second light emission control module connected between a first terminal of the driving module and a negative voltage power supply, configured to be conducted in response to the light emission control signal; A memory module electrically connected to the control terminal of the driving module and configured to store the potential of the control terminal of the driving module, A pixel circuit.

2. In the first light emission control module, the positive voltage power supply is connected to the first terminal, the anode of the light emitting element is connected to the second terminal, and the second terminal of the driving module is connected to the cathode of the light emitting element; Or, the light emitting element has the positive voltage power supply connected to its anode, the first terminal of the first light emission control module connected to its cathode, and the second terminal of the driving module connected to the second terminal of the first light emission control module. The pixel circuit according to Claim 1.

3. The memory module includes one memory unit to which one fixed potential signal is accessed, with the control terminal of the driving module connected to the first terminal and the fixed potential signal accessed to the second terminal; Or, the memory module includes at least two memory units to which at least two fixed potential signals are accessed, with the control terminal of the driving module connected to each of the first terminals and different fixed potential signals accessed to each of the second terminals. The pixel circuit according to Claim 1.

4. The memory unit includes a capacitor with its first terminal being the first terminal of the memory unit and its second terminal being the second terminal of the memory unit. The pixel circuit according to Claim 3.

5. ​ ​ ​ At least one of the first power signal provided from the positive voltage power supply, the second power signal provided from the negative voltage power supply, and the first reset signal is also used as the fixed potential signal. The pixel circuit according to claim 3.

6. The driving module includes a driving transistor having a gate electrode connected to a control end of the driving module, a first pole connected to a first end of the driving module, and a second pole connected to a second end of the driving module. The first reset module includes a first transistor having a first scanning line connected to a gate electrode, a control end of the driving module connected to a first pole, and a first reset signal line connected to a second pole. The data writing module includes a data writing unit connected to a first end of the driving module, configured to be conducted in response to a second scanning signal, and transmit a data voltage to the first end of the driving module, and a threshold compensation unit connected between a control end and a second end of the driving module, configured to be conducted in response to the second scanning signal, and perform threshold voltage compensation on the driving module. The data writing unit includes a second transistor having a second scanning line connected to a gate electrode, a data line connected to a first pole, and a first end of the driving module connected to a second pole. The threshold compensation unit includes a third transistor having the second scanning line connected to a gate electrode, a control end of the driving module connected to a first pole, and a second end of the driving module connected to a second pole. The first light emission control module includes a fourth transistor having a light emission control signal line connected to a gate electrode, and connected in series between the light emitting element, the positive voltage power supply, and a second end of the driving module. The second light emission control module includes a fifth transistor having a light emission control signal line connected to a gate electrode, a first end of the driving module connected to a first pole, and a negative voltage power supply connected to a second pole. The pixel circuit according to claim 1.

7. The first power signal provided from the positive voltage power supply is also used as the first reset signal. The pixel circuit according to claim 6.

8. Further provided is a second reset module configured to be electrically connected to a cathode of the light emitting element, and transmit a second reset signal to the cathode of the light emitting element in response to a third scanning signal. The pixel circuit according to claim 1.

9. The second reset module includes a sixth transistor in which a third scanning line is connected to a gate electrode, a cathode of the light-emitting element is connected to a first electrode, and a second reset signal line is connected to a second electrode. The pixel circuit according to claim 8.

10. At least one fixed potential signal is accessed to the memory module, and the second reset signal is also used as one of the fixed potential signals. The pixel circuit according to claim 8.

11. The first light emission control module has a positive voltage power source connected to a first end, an anode of the light-emitting element connected to a second end, and a second end of the driving module connected to a cathode of the light-emitting element. The first reset module is configured to be turned on in response to the first scanning signal in a gate electrode reset stage and perform a reset on a control end of the driving module by using the first reset signal. The data writing module is configured to be turned on in response to the second scanning signal in a data writing stage and transmit the data voltage to the driving module. The second reset module is configured to be turned on in response to the third scanning signal in a cathode precharge stage and precharge a cathode of the light-emitting element by using the second reset signal. The first light emission control module and the second light emission control module are configured to be turned on in response to the light emission control signal so that in a light emission stage, the driving module generates a driving current based on a potential of its control end to drive the light emission of the light-emitting element. The pixel circuit according to claim 8.

12. The second reset module is further configured to be turned on in response to the third scanning signal before the gate electrode reset stage and perform a reset on the cathode of the light-emitting element, a first end and a second end of the driving module by using the second reset signal. The pixel circuit according to claim 11.

13. The light-emitting element has a positive voltage power source connected to an anode, a first end of the first light emission control module connected to a cathode, and a second end of the driving module connected to a second end of the first light emission control module. The first reset module is configured to be turned on in response to the first scanning signal in a gate electrode reset stage and perform a reset on a control end of the driving module by using the first reset signal. The data writing module is configured to be turned on in response to the second scanning signal in the data writing stage and transmit the data voltage to the driving module. The second reset module is configured to be turned on in response to the second scanning signal in at least one of the gate electrode reset stage and the data writing stage, and perform reset on the cathode of the light emitting element by using the second reset signal. The first light emission control module and the second light emission control module are configured to be turned on in response to the light emission control signal in the light emission stage so that the driving module generates a driving current based on the potential of its control terminal to drive the light emission of the light emitting element. The pixel circuit according to claim 8.

14. The second reset module is turned on in the data writing stage, and the second scanning signal is also used as the third scanning signal. The pixel circuit according to claim 13.

15. A display panel including a plurality of pixel circuits according to any one of claims 1 to 14. Display panel.

16. The driving module of the pixel circuit includes a driving transistor. The display panel includes an active layer, a first metal layer, a third metal layer, an anode layer, a light emitting functional layer, and a cathode layer provided in a stacked manner. The channel region, source region, and drain region of the driving transistor are all provided in the active layer. The gate electrode of the driving transistor is provided in the first metal layer, and the projection in the thickness direction of the display panel at least partially covers the channel region of the driving transistor. The first pole and the second pole of the driving transistor are both provided in the third metal layer, and the source region and the drain region of the driving transistor are respectively connected to the first pole and the second pole of the driving transistor. The display panel according to claim 15.

17. At least one fixed potential signal is accessed by the memory module. The display panel further includes a second metal layer provided between the first metal layer and the third metal layer. The fixed potential signal is provided from a fixed potential signal line provided in the second metal layer or the third metal layer, and the projection of which in the thickness direction of the display panel at least partially overlaps with the gate electrode of the driving transistor. A location where the fixed potential signal line and the gate electrode of the driving transistor overlap forms the memory module. The display panel according to claim 16.

18. The positive voltage power supply is connected to the pixel circuit by a first power signal line provided in the second metal layer, the third metal layer, or the anode layer. The display panel according to claim 17.

19. The negative voltage power supply is connected to the pixel circuit by a second power signal line provided in the second metal layer, the third metal layer, or the anode layer. The display panel according to claim 17.

20. The display panel further includes a plurality of isolation structures provided surrounding the light-emitting element and configured to isolate the cathodes of adjacent light-emitting elements. The isolation structure includes a conductive material layer, and the cathode of the light-emitting element contacts the isolation structure and is electrically connected to the corresponding pixel circuit by the isolation structure. The cross-sectional shape of the isolation structure is an inverted trapezoid. The display panel according to claim 15.

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