Semiconductor Package

Abstract

A semiconductor package according to an embodiment includes a circuit board and a connecting member embedded in the circuit board, the circuit board including a first insulating layer having no reinforcing member, the connecting member being embedded in the first insulating layer of the circuit board, and the connecting member including a second insulating layer including an organic material.

Description

[Technical field]

[0001] The embodiment relates to a semiconductor package. [Background technology]

[0002] As the performance of electrical / electronic products continues to improve, technologies for mounting more packages on a board of limited size are being proposed and researched. However, since a typical package is based on mounting one semiconductor chip, there is a limit to achieving the desired performance.

[0003] A typical semiconductor package has a processor package in which a processor chip is arranged and a memory package in which a memory chip is attached, which are connected together as one. This type of semiconductor package has the advantage that the chip mounting area is reduced by manufacturing the processor chip and the memory chip in one integrated package, and high-speed signal transmission is possible through a short path.

[0004] Due to these advantages, the above-mentioned semiconductor packages are widely used in mobile devices and the like.

[0005] Meanwhile, recently, the size of packages has increased due to the high specifications of electronic devices such as mobile devices and the adoption of HBM (High Bandwidth Memory), and therefore semiconductor packages including interposers are widely used. At this time, the interposer is made of a silicon substrate.

[0006] However, in the case of an interposer such as a silicon substrate, not only is the material cost for manufacturing the interposer high, but the formation of TSVs (Through Silicon Vias) is complicated and costly.

[0007] Conventionally, semiconductor packages have been provided that include silicon-based interconnect bridges, but the silicon-based interconnect bridges have reliability issues due to a mismatch in the coefficient of thermal expansion (CTE) between the silicon material of the bridge and the organic material of the substrate, resulting in reduced power integrity characteristics. Summary of the Invention [Problem to be solved by the invention]

[0008] The embodiment makes it possible to provide a semiconductor package with a new structure.

[0009] Also, the embodiment provides a semiconductor package in which multiple processor chips can be mounted side-by-side.

[0010] Moreover, the embodiment provides a semiconductor package in which memory chips can be mounted side by side together with a plurality of processor chips.

[0011] An embodiment also provides a semiconductor package including a processor chip and passive components embedded within the circuit board.

[0012] In the proposed embodiments, the technical problems to be solved are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the proposed embodiments pertain from the following description.

[0013] A semiconductor package according to an embodiment includes a circuit board and a connecting member embedded in the circuit board, the circuit board including a first insulating layer having no reinforcing member, the connecting member embedded in the first insulating layer of the circuit board, and the connecting member including a second insulating layer including an organic material.

[0014] The first insulating layer also includes a first layer, a second layer disposed on the first layer and having a cavity, and a third layer filling the cavity and disposed on the second layer, and the connecting member is disposed within the cavity.

[0015] The second insulating layer of the connecting member includes polyimide.

[0016] The circuit board further includes a third insulating layer disposed below the first insulating layer, the third insulating layer including a different insulating material than the first insulating layer.

[0017] The third insulating layer also includes a reinforcing member.

[0018] The circuit board further includes a fourth insulating layer disposed below the third insulating layer, the fourth insulating layer including the same insulating material as the first insulating layer.

[0019] The third insulating layer further includes a through hole and a semiconductor element disposed in the through hole.

[0020] The first insulating layer is disposed to fill the through hole and cover the semiconductor element.

[0021] The third insulating layer includes a plurality of through holes spaced apart from each other in the horizontal direction, and the semiconductor elements are disposed in the plurality of through holes, respectively.

[0022] Additionally, the plurality of through holes do not overlap the connecting member in the vertical direction.

[0023] A circuit board according to an embodiment includes a first substrate and a second substrate of a bridge substrate embedded in the first substrate, the first substrate including a first insulating layer, a first circuit layer disposed on the first insulating layer, and a first via penetrating the first insulating layer, the first insulating layer of the first substrate including a first layer, a second layer disposed on the first layer and including a first cavity in which the second substrate is disposed, and a third layer disposed on the second layer and embedding the second substrate, the first to third layers of the insulating layer of the first substrate do not include glass fiber, and the second substrate includes an insulating layer including an organic material.

[0024] Moreover, the first to third layers of the first insulating layer of the first substrate include ABF (Aginomoto Build-up Film).

[0025] The insulating layer of the second substrate includes polyimide.

[0026] The first substrate further includes a second insulating layer of the first substrate disposed below the first layer of the first insulating layer of the first substrate, the second insulating layer of the first substrate including fiberglass.

[0027] The first substrate further includes a third insulating layer of the first substrate disposed below the second insulating layer of the first substrate, the third insulating layer of the first substrate including the same insulating material as the first insulating layer of the first substrate.

[0028] Moreover, the first via of the first substrate includes a 1-1 via that penetrates the first layer of the first insulating layer, a 1-2 via that penetrates the second layer of the first insulating layer, and a 1-3 via that penetrates the third layer of the first insulating layer, and the first circuit layer of the first substrate includes a 1-1 circuit layer disposed on the first layer of the first insulating layer, a 1-2 circuit layer disposed on the second layer of the first insulating layer, and a 1-3 circuit layer disposed on the third layer of the first insulating layer.

[0029] It also includes a first element disposed in a second cavity penetrating the second insulating layer of the first substrate, the second cavity and the first element being covered by the first layer of the first insulating layer of the first substrate.

[0030] In addition, the 1-1 via of the first substrate includes a first sub-via that does not overlap the first element in the thickness direction and does not directly contact the terminal of the first element, and a second sub-via that is horizontally spaced apart from the first sub-via, overlaps the first element in the thickness direction, and is directly connected to the terminal of the first element, and at least one of a thickness and a width of the first sub-via is different from at least one of a thickness and a width of the second sub-via.

[0031] It also includes a second element disposed in a third cavity penetrating the second insulating layer of the first substrate, the third cavity and the second element being covered by the first layer of the first insulating layer of the first substrate, the second cavity and the third cavity being horizontally spaced apart within the second insulating layer of the first substrate, and the first cavity not overlapping with the second cavity and the third cavity in the thickness direction.

[0032] In addition, the 1-3 via of the first substrate includes a first sub-via that overlaps with the second substrate in the thickness direction and is directly connected to a pad layer of the second substrate, and a second sub-via of the 1-3 via that is horizontally separated from the first sub-via of the 1-3 via and is not directly connected to the pad layer of the second substrate, and at least one of a thickness and a width of the first sub-via of the 1-3 via is different from at least one of a thickness and a width of the second sub-via of the 1-3 via.

[0033] In addition, the 1-1 circuit layer of the first substrate overlaps with the first cavity in the thickness direction and includes a pad portion whose upper surface is exposed through the first cavity, and the second substrate is attached onto the pad portion by an adhesive layer arranged on the pad portion.

[0034] The second substrate further includes a first circuit layer of the second substrate arranged on an upper surface of an insulating layer of the second substrate, a second circuit layer of the second substrate arranged on a lower surface of the insulating layer of the second substrate, and a via of the second substrate penetrating the insulating layer of the second substrate, and the inclination of the side surface of the via of the second substrate is different from the inclination of the side surface of the 1-1 via of the first substrate.

[0035] The first circuit layer of the second substrate also includes a first metal layer including at least one of nickel and chromium, and a second metal layer disposed on the first metal layer and including copper.

[0036] Moreover, the inclination of the side surface of the via in the second substrate is closer to a right angle than the inclination of the side surface of the 1-1 via in the first substrate.

[0037] The second substrate also includes a first protective layer disposed on the insulating layer of the second substrate and including an opening that overlaps with the first circuit layer of the second substrate in a thickness direction.

[0038] The second substrate further includes a second protective layer disposed under the insulating layer of the second substrate and entirely covering the lower surface of the second circuit layer of the second substrate, and the adhesive layer is disposed on the lower surface of the second protective layer of the second substrate.

[0039] The second substrate further includes a pad layer directly connected to the 1-3 via of the first substrate, and the position of the top surface of the pad layer of the second substrate is different from the position of the top surface of the 1-2 circuit layer of the first substrate.

[0040] Furthermore, the thickness of each of the first to third layers of the first insulating layer of the first substrate has a first difference with respect to the thickness of the second insulating layer of the first substrate, and the height of the upper surface of the pad layer of the second substrate and the upper surface of the 1-2 circuit layer of the first substrate has a second difference, and the second difference is smaller than the first difference. Effect of the Invention

[0041] The circuit board of the embodiment includes a first insulating layer and a second insulating layer. The second insulating layer may include a prepreg. Through this, the embodiment may maintain the rigidity of the circuit board and improve warpage characteristics, thereby improving product reliability. Also, the first insulating layer includes ABF. As a result, the embodiment may reduce the size of the circuit layer and vias disposed in the first insulating layer. Specifically, the embodiment may form a fine pattern circuit layer and vias connected to the first processor chip and the second processor chip in the first insulating layer.

[0042] The first insulating layer includes a plurality of layers. A circuit layer and a via are disposed in each of the plurality of layers of the first insulating layer. In this case, the embodiment allows the circuit layer and the via formed in the first insulating layer to be gradually increased as they are adjacent to the second insulating layer. As a result, the embodiment can minimize signal transmission loss between the circuit layer and the via disposed in the first insulating layer and the circuit layer and the via disposed in the second insulating layer. As a result, the embodiment can improve the communication characteristics of the circuit board.

[0043] Also, the circuit board of the embodiment includes a bridge substrate embedded in the first insulating layer. The bridge substrate may be disposed in a first cavity formed in a second layer of the first insulating layer and covered by a third layer of the first insulating layer. In addition, the embodiment may directly connect a pad layer included in the bridge substrate to a via penetrating the first insulating layer. As a result, the embodiment may minimize the signal transmission distance and further minimize the signal transmission loss.

[0044] In addition, the insulating layer of the bridge substrate of the embodiment has a CTE similar to that of the first insulating layer. Furthermore, the insulating layer of the bridge substrate of the embodiment has a flexible characteristic. Specifically, the insulating layer of the bridge substrate can include polyimide (PI), which is an organic material. As a result, the embodiment can reduce the product unit cost compared to a conventional bridge substrate including silicon.

[0045] Further, the bridge substrate of the embodiment includes a pad layer. The pad layer is directly connected to a first via disposed in the first insulating layer. At this time, an alignment state between the pad layer of the bridge substrate and the first via has a significant effect on the product reliability of the circuit board and the semiconductor package. At this time, in the embodiment, transparent polyimide is applied as the insulating layer of the bridge substrate. As a result, the embodiment can improve the alignment between the pad layer of the bridge substrate and the first via disposed in the first insulating layer. As a result, the embodiment can improve the overall product reliability.

[0046] Furthermore, the embodiment can stably protect the bridge substrate from stresses that occur when the circuit substrate is thermally deformed.

[0047] That is, the insulating layer of the bridge substrate conventionally contains silicon. As a result, the conventional bridge substrate has rigid properties due to the silicon. As a result, in the conventional bridge substrate, stress generated when the circuit substrate is thermally deformed is directly transmitted to the bridge substrate. As a result, the conventional bridge substrate has reliability problems such as cracks.

[0048] In contrast, the insulating layer of the bridge substrate in the embodiment includes polyimide. This allows the bridge substrate to flow together with the first insulating layer when the circuit board is thermally deformed. This improves the physical and electrical reliability of the bridge substrate in the embodiment.

[0049] Furthermore, the embodiment allows the thickness of the bridge substrate to be easily adjusted. For example, in a conventional bridge substrate including silicon, a process of polishing a silicon substrate is required to adjust the thickness of the bridge substrate, and due to the difficulty of the process, it is difficult to adjust the thickness of the bridge substrate to a desired thickness.

[0050] In contrast, the embodiment can easily adjust the total thickness of the bridge substrate, and thus the thickness of the bridge substrate can be easily adjusted in response to the depth of the cavity formed in the first insulating layer. As a result, the embodiment can minimize the difference in thickness between the first sub-via that directly contacts the bridge substrate and the other sub-vias. As a result, the embodiment can improve the overall physical reliability and electrical reliability of the circuit board. [Brief description of the drawings]

[0051] [Figure 1] FIG. 11 is a cross-sectional view showing a semiconductor package according to a comparative example. [Diagram 2] FIG. 2 is a cross-sectional view showing a circuit board according to an embodiment of the present invention. [Diagram 3] 3 is an enlarged cross-sectional view of a partial region of the first insulating layer of FIG. 2. [Figure 4] FIG. 2 is a cross-sectional view showing a bridge substrate in accordance with the first embodiment. [Diagram 5] FIG. 11 is a cross-sectional view showing a bridge substrate according to a second embodiment. [Figure 6] FIG. 13 is a diagram showing a bridge substrate according to a third embodiment. [Figure 7] 4 is a cross-sectional view showing a layer structure of a redistribution layer in accordance with the first embodiment. FIG. [Figure 8] FIG. 13 is a diagram showing a layer structure of a redistribution layer according to a second embodiment. [Figure 9] 5 is a cross-sectional view for explaining a step between a 1-2 circuit layer and a pad layer of a bridge substrate in the first embodiment. FIG. [Figure 10] 13 is a diagram for explaining a step between the 1-2 circuit layer and the pad layer of the bridge substrate in the second embodiment. FIG. [Figure 11] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 12] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 13] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 14]3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 15] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 16] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 17] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 18] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 19] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 20] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 21] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 22] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Diagram 23] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 24] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Diagram 25] 3A to 3C are diagrams for explaining the process sequence of the circuit board in FIG. 2. [Figure 26] FIG. 1 is a diagram showing a semiconductor package according to a first embodiment. [Figure 27] FIG. 13 is a diagram showing a semiconductor package according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0052] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0053] However, the technical concept of the present invention is not limited to the embodiments described, but may be embodied in various different forms, and one or more of the components of the embodiments may be selectively combined or substituted within the scope of the technical concept of the present invention.

[0054] In addition, the terms (including technical and scientific terms) used in the embodiments of the present invention may be interpreted as meanings that may be commonly understood by a person having ordinary knowledge in the technical field to which the present invention belongs, unless otherwise clearly defined and described, and commonly used terms such as terms defined in a dictionary may be interpreted in consideration of the contextual meaning of the related art. In addition, the terms used in the embodiments of the present invention are intended to explain the embodiments, and are not intended to limit the present invention.

[0055] In this specification, unless otherwise specified in the phrase, the singular form can include the plural form, and when it is described as "A and (and) at least one (or more) of B and C," it can include one or more of all possible combinations of A, B, and C. In addition, terms such as first, second, A, B, (a), (b), etc. can be used to describe components of the embodiments of the present invention.

[0056] Such terms are used merely to distinguish the component from other components, and do not limit the nature, order, or sequence of the components. Furthermore, when a certain component is described as being "connected," "coupled," or "connected" to another component, it includes not only the case where the component is directly connected, coupled, or connected to the other component, but also the case where the component is "connected," "coupled," or "connected" between the other component and the other component or by another component.

[0057] In addition, when described as being formed or located "above or below" each component, "above" or "below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or located between the two components. In addition, when described as "above or below," it can include not only the upper direction based on one component, but also the lower direction.

[0058] -Comparative Example-

[0059] FIG. 1 is a cross-sectional view showing a semiconductor package according to a comparative example.

[0060] Referring to FIG. 1, in the comparative example, at least two packages are required to transmit signals to a main board of an electronic device.

[0061] The semiconductor package included in the electronic device in the comparative example may be in a state where at least two or more packages are combined.

[0062] The semiconductor package according to the comparative example includes a first package 10 and a second package 20.

[0063] The first package 10 is a processor package in which a processor chip 12 is mounted, and the second package 20 is a memory package in which a memory chip 23 is mounted.

[0064] The first package 10 includes a first substrate 11 on which a processor chip 12 is mounted. The first substrate 11 has a multi-layer structure and includes one side on which the processor chip 12 is disposed and the other side on which first adhesive balls 16 are disposed. The first package 10 has a fan-out structure and is attached to a main board (not shown) of an electronic device using the first adhesive balls 16 disposed on the other side.

[0065] A processor chip 12 is mounted on the first substrate 11. The processor chip 12 is an integrated processor chip in which various functions are integrated. Therefore, the size of the processor chip 12 increases in proportion to the number of functions it provides. That is, the first substrate 11 has the processor chip 12 mounted thereon and functions to connect the processor chip 12 to a main board of an electronic device.

[0066] Meanwhile, the first package 10 of the comparative example further includes a second substrate 15. The second substrate 15 is an interposer that connects the first package 10 and the second package 20 to each other.

[0067] That is, the semiconductor package of the comparative example essentially includes an interposer such as the second substrate 15. The semiconductor package of the comparative example has a problem in that the overall volume increases in proportion to the thickness of the interposer. As a result, the thickness of the electronic device increases in the semiconductor package of the comparative example, which limits how slim it can be made.

[0068] In addition, the semiconductor package of the comparative example has a problem that the length of the signal transmission line increases by interconnecting the first package 10 and the second package 20 using the second substrate 15. That is, in the semiconductor package of the comparative example, in order to mutually transmit signals between the processor chip 12 and the memory chip 23, the signals must pass through at least the second substrate 15, and thus the signal transmission distance between the processor chip 12 and the memory chip 23 increases in accordance with the length of the signal transmission line in the second substrate 15. As a result, the comparative example has a problem that high-speed communication between the processor chip 12 and the memory chip 23 is difficult due to the second substrate 15. Furthermore, the comparative example has a problem that the signal transmission distance increases due to the second substrate 15, which makes the comparative example vulnerable to noise and thus reduces communication performance.

[0069] Meanwhile, the first package 10 of the comparative example includes second adhesive balls 13 disposed on a first substrate 11, and a first molding layer 14 that molds the second adhesive balls 13 and the processor chip 12. At this time, the first molding layer 14 protects the processor chip 12 and the second adhesive balls 13. Thus, the thickness of the first molding layer 14 is determined by the heights of the processor chip 12 and the second adhesive balls 13. However, in the comparative example, the second substrate 15 is further disposed on the first molding layer 14, and therefore, the thickness of the first molding layer 14 must take into account the influence of the second substrate 15, resulting in an increase in thickness.

[0070] The second package 20 of the comparative example includes a third substrate 22, a memory chip 23 disposed on the third substrate 22, and a second molding layer 24.

[0071] As described above, in the comparative example, at least three substrates are required to electrically connect the processor chip 12 and the memory chip 23 to each other. In addition, in the comparative example, a process is required to bond at least three substrates to each other, which increases the number of manufacturing processes and reduces the yield due to the complexity. Specifically, in the comparative example, at least three substrates are required due to the difficulty of the process of arranging different chips on one substrate.

[0072] Also, in the comparative example, at least two adhesive balls are required to bond at least three substrates together.

[0073] That is, in the comparative example, second adhesive balls 13 for connecting the first substrate 11 and the second substrate 15 and third adhesive balls 21 for connecting the second substrate 15 and the third substrate 22 are required. As a result, the semiconductor package according to the comparative example requires at least two adhesive balls for mutually bonding a plurality of substrates, and thus has a problem that the reliability of the semiconductor package may be reduced due to poor connection of the adhesive balls. In addition, the semiconductor package has a structure in which the two or more adhesive balls are arranged in the thickness direction, and therefore has a problem that the thickness of the semiconductor package and the electronic device are increased by the thickness of the adhesive balls.

[0074] Specifically, the first substrate 11 has a first thickness t1 of 120 μm to 150 μm. The second thickness t2 including the first molding layer 14, the processor chip 12, and the second adhesive balls 13 is 145 μm to 160 μm. The third thickness t3 of the second substrate 15 is 90 μm to 110 μm. The fourth thickness t4 of the first adhesive balls 16 is 130 μm to 150 μm.

[0075] As a result, the total thickness t8 of the first package 10 including the first to fourth thicknesses t1, t2, t3, and t4 is 480 μm to 550 μm.

[0076] The fifth thickness t5 of the third adhesive ball 21 is 145 μm to 180 μm. The sixth thickness t6 of the third substrate 22 is 90 μm to 110 μm. The seventh thickness t7 including the memory chip 23 and the second molding layer 24 is 370 μm to 400 μm. As a result, the total thickness t9 of the second package 20 including the fifth to seventh thicknesses t5, t6, and t7 is 610 μm to 700 μm. Therefore, the total thickness of the semiconductor package of the comparative example is 1100 μm or more.

[0077] Meanwhile, due to the recent trend of slimming electronic devices, the required thickness of the semiconductor package is 1100 μm or less. Recently, electronic devices are mainly foldable products, and due to the characteristics of the foldable products, there are few restrictions in the longitudinal direction but many restrictions in the thickness direction. However, the semiconductor package of the comparative example has a structure in which multiple substrates are mutually bonded via multiple adhesive balls in the thickness direction, which causes a problem of not meeting the specifications required for electronic devices.

[0078] Recently, as the performance of electric / electronic products has improved, technology for attaching more packages to a substrate of limited size has been researched, which has led to a demand for finer circuit patterns. However, the semiconductor package of the comparative example has a limit to finer circuit patterns. The circuit patterns included in the semiconductor package of the comparative example have a line width of at least 10 μm and a spacing of at least 10 μm. Recently, the number of functions processed by an application processor (AP) has increased, making it difficult to realize this as a single chip. However, in the comparative example, it may be difficult to implement two application processors AP that perform different functions on the single first substrate 11.

[0079] The embodiment is intended to solve the problems of the comparative example, and makes it possible to provide a circuit board with a new structure on which multiple application processor chips can be mounted on a single board, and a semiconductor package including the same.

[0080] Furthermore, the embodiments are intended to solve the problems of the comparative examples, and provide a circuit board with a new structure in which an application processor chip and a memory chip can be mounted side by side, and a semiconductor package including the same.

[0081] -Electronic Devices-

[0082] Prior to describing the embodiment, an electronic device including a semiconductor package of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various chips may be mounted in the semiconductor package. Mainly, memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory, application processor chips such as a central processor (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller, and logic chips such as an analog-to-digital converter and an application-specific IC (ASIC), etc. may be mounted in the semiconductor package.

[0083] In addition, the present invention provides a semiconductor package that can mount at least two different types of chips on one substrate while reducing the thickness of the semiconductor package connected to the main board of the electronic device.

[0084] In this case, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, the electronic device is not limited to these, and may be any other electronic device that processes data.

[0085] Working Example

[0086] Hereinafter, a circuit board according to an embodiment and a semiconductor package including the circuit board will be specifically described.

[0087] FIG. 2 is a cross-sectional view showing a circuit board according to an embodiment, FIG. 3 is an enlarged cross-sectional view of a portion of the first insulating layer of FIG. 2, FIG. 4 is a cross-sectional view showing a bridge substrate according to a first embodiment, FIG. 5 is a cross-sectional view showing a bridge substrate according to a second embodiment, FIG. 6 is a diagram showing a bridge substrate according to a third embodiment, FIG. 7 is a cross-sectional view showing the layer structure of a redistribution layer according to the first embodiment, and FIG. 8 is a diagram showing the layer structure of a redistribution layer according to the second embodiment.

[0088] Hereinafter, the circuit board according to the embodiment will be described with reference to FIGS.

[0089] 2 to 8, the circuit board of the embodiment allows at least two different chips to be mounted thereon.

[0090] For example, an embodiment of a circuit board may include multiple chip mounting areas capable of mounting at least two processor chips.

[0091] For example, a circuit board of an embodiment may include multiple chip mounting areas capable of mounting one processor chip and one memory chip.

[0092] For example, an embodiment of a circuit board may include multiple chip mounting areas capable of mounting at least one processor chip and at least one memory chip.

[0093] In the circuit board of the embodiment, the configuration excluding the bridge substrate 200 can be called the “first substrate,” and the bridge substrate 200 can be called the “second substrate.” Preferably, the bridge substrate 200 can be called a connecting member that connects between a plurality of semiconductor elements, and the remaining configuration excluding the bridge substrate can be called a circuit board in which the connecting member is embedded.

[0094] The circuit board further includes elements 300 and 400 embedded in the bridge substrate 200. A plurality of the elements 300 and 400 may be embedded in the substrate. For example, a plurality of the elements 300 and 400 may be embedded in the substrate, spaced apart from each other in the horizontal direction.

[0095] On the other hand, in the circuit board of the embodiment, the first insulating layer 110, the second insulating layer 120, and the third insulating layer 121 can be regarded as substrate insulating layers. Furthermore, the first to third circuit layers arranged on the first insulating layer 110, the second insulating layer 120, and the third insulating layer 121 can be regarded as substrate circuit layers. Furthermore, the first to third vias arranged on the first insulating layer 110, the second insulating layer 120, and the third insulating layer 121 can be regarded as substrate vias. Furthermore, the first protective layer 151 arranged on the first insulating layer 110 can be regarded as a first substrate protective layer. Furthermore, the second protective layer 152 arranged under the third insulating layer 121 can be regarded as a second substrate protective layer.

[0096] Meanwhile, the bridge substrate also includes an insulating layer, a circuit layer, a via, and a protective layer. In order to distinguish between these, the insulating layer included in the bridge substrate can be referred to as a bridge insulating layer. Also, the circuit layer included in the bridge substrate can be referred to as a bridge circuit layer. Also, the via included in the bridge substrate can be referred to as a bridge via. Also, the protective layer included in the bridge substrate can be referred to as a bridge protective layer.

[0097] The circuit board may include multiple insulating layers.

[0098] For example, the circuit board can include a first insulating layer 110, a second insulating layer 120, and a third insulating layer 121.

[0099] The first insulating layer 110 may refer to an insulating layer region in which a processor chip is mounted among a plurality of insulating layers. The first insulating layer 110 may also refer to an insulating layer region in which a bridge substrate 200 is disposed. That is, the first insulating layer 110 may refer to an insulating layer in which a bridge substrate 200 is embedded to connect the plurality of processor chips while providing a mounting region in which a plurality of processor chips are mounted. The first insulating layer 110 may be composed of a plurality of layers. For example, the first insulating layer 110 may be composed of first to third layers 111, 112, and 113 from the bottom. However, the embodiment is not limited thereto, and the first insulating layer 110 may have a layer structure of two layers or less, or may have a layer structure of four layers or more.

[0100] The second insulating layer 120 may be disposed on one surface of the first insulating layer 110. The second insulating layer 120 may be disposed on a lower surface of the first insulating layer 110. The second insulating layer 120 may include an insulating material different from that of the first insulating layer 110. The second insulating layer 120 may include an insulating material having higher rigidity than the first insulating layer 110. The second insulating layer 120 may refer to an insulating layer region in which the elements 300 and 400 are embedded among the plurality of insulating layers.

[0101] The insulating layer 121 may be disposed under the second insulating layer 120. The third insulating layer 121 may have a symmetrical structure with the first insulating layer 110 based on the second insulating layer 120. The third insulating layer 121 may refer to an insulating layer region connected to a main board among a plurality of insulating layers. For example, the third insulating layer 121 may refer to an insulating layer region connected to an electronic device among a plurality of insulating layers. The number of layers of the third insulating layer 121 may be the same as the number of layers of the first insulating layer 110. Thus, the third insulating layer 121 may include first to third layers 122, 123, and 124. However, the embodiment is not limited thereto. For example, the third insulating layer 121 may have a greater number of layers than the first insulating layer 110, or may have a smaller number of layers than the first insulating layer 110.

[0102] The first insulating layer 110 may include a first insulating material, the second insulating layer 120 may include a second insulating material different from the first insulating material, and the third insulating layer 121 may include the same first insulating material as the first insulating layer 110.

[0103] The second insulating layer 120 may be a core layer. Thus, the circuit board of the embodiment may be a core board including a core layer. However, the embodiment is not limited thereto. For example, the second insulating layer 120 may refer to an insulating layer disposed in an inner layer among a plurality of insulating layers, rather than a core layer. Thus, the circuit board of the embodiment may be a coreless board.

[0104] The second insulating layer 120 may include a prepreg. The second insulating layer 120 may be a prepreg in which glass fibers are impregnated in a resin. The second insulating layer 120 may include a resin and glass fibers disposed in the resin. The glass fibers may be called a reinforcing member. The reinforcing member may be classified as a filler or the like. The resin may be, but is not limited to, an epoxy resin. In the following, the second insulating layer 120 will be described as a core layer.

[0105] The second insulating layer 120 may be a clad copper laminate (CCL) including prepreg (PPG), or may include materials such as silicon, sapphire, glass, and ceramic. However, the second insulating layer 120 of the embodiment may include transparent materials such as glass and sapphire. As a result, the overall warpage characteristics of the circuit board may be improved due to the modulus rigidity of the second insulating layer 120. The circuit board of the embodiment includes a plurality of insulating layers. The values ​​of the circuit layers and vias arranged in the plurality of insulating layers may be different from each other. For example, at least one circuit layer or via may have a value for connection to the bridge substrate 200 or the processor chip. At least another circuit layer or via may have a value for connection to the elements 300 and 400. At least another circuit layer or via may have a value for connection to the main board. As a result, the embodiment requires electrical connection reliability between the respective circuit layers and vias. Here, the electrical connection reliability may include alignment between the vias arranged in each layer.

[0106] At this time, the second insulating layer 120 of the embodiment is formed of a transparent material such as sapphire or glass. As a result, the embodiment is advantageous in adjusting the top and bottom alignment due to the transparent characteristics of the second insulating layer 120, and thus the processability and product quality can be improved. For example, the embodiment can improve the positional accuracy when forming a via in the second insulating layer 120, can improve the alignment characteristics in the exposure and development processes, and can easily check whether there is a defect in the circuit layer arranged on the surface.

[0107] The second insulating layer 120 may include a plurality of cavities. For example, the second insulating layer 120 may include a second cavity C2 and a third cavity C3. The second cavity C2 and the third cavity C3 may penetrate the second insulating layer 120. The second cavity C2 and the third cavity C3 may be spaced apart in a horizontal direction (e.g., a lengthwise direction or a widthwise direction) within the second insulating layer 120. The second cavity C2 and the third cavity C3 may provide a space in which the elements 300 and 400 are disposed.

[0108] For example, the second cavity C2 may provide a space in which the first element 300 is disposed. And the third cavity C3 may provide a space in which the second element 400 is disposed. The width of the second cavity C2 may be greater than the width of the first element 300. Thus, at least a portion of the second cavity C2 may be filled with the first insulating layer 110. For example, the second cavity C2 may include a first region in which the first element 300 is disposed, and a second region other than the first region that is filled with the first insulating layer 110.

[0109] Also, a width of the third cavity C3 may be greater than a width of the second element 400. Thus, at least a portion of the third cavity C3 may be filled with the first insulating layer 110. For example, the third cavity C3 may include a third region in which the second element 400 is disposed, and a fourth region other than the third region that is filled with the first insulating layer 110.

[0110] The second cavity C2 and the third cavity C3 may not overlap the first cavity C1 in the vertical direction (or thickness direction). The first cavity C1 is formed in the first insulating layer 110 and provides a space in which the bridge substrate 200 is disposed.

[0111] The embodiment can improve the overall warpage characteristics of the circuit board by preventing the first cavity C1, the second cavity C2, and the third cavity C3 from overlapping in the vertical direction. Furthermore, the embodiment can minimize signal interference between the bridge substrate 200 disposed in the first cavity C1 and the elements 300, 400 disposed in the second cavity C2 and the third cavity C3. Through this, the embodiment can improve the signal characteristics of the circuit board. That is, the embodiment can improve the electrical reliability and physical reliability of the circuit board through the above-mentioned cavity arrangement structure.

[0112] The first insulating layer 110 is disposed on the second insulating layer 120. The first insulating layer 110 may be composed of a plurality of layers.

[0113] The first insulating layer 110 may include a first layer 111, a second layer 112, and a third layer 113. For example, the first insulating layer 110 may have a three-layer structure. However, the embodiment is not limited thereto. The first layer 111, the second layer 112, and the third layer 113 of the first insulating layer 110 may include an insulating material different from that of the second insulating layer 120. For example, the first insulating layer 110 may not include glass fiber. As an example, the first insulating layer 110 may include a photocurable resin or a photosensitive resin. For example, the first insulating layer 110 may include an Aginomoto Build-up Film (ABF). However, the embodiment is not limited thereto. For example, the first insulating layer 110 may include a Photo Imageable Dielectic (PID).

[0114] The first insulating layer 110 may include a first cavity C1.

[0115] The first layer 111 of the first insulating layer 110 refers to a layer adjacent to the second insulating layer 120 in which the first cavity C1 is not formed. The second layer 112 of the first insulating layer 110 refers to a layer in which the first cavity C1 is formed. The third layer 113 of the first insulating layer 110 refers to a layer disposed on the second layer 112 to fill the first cavity C1.

[0116] The first insulating layer 110 may have four or more layers. When the first insulating layer 110 has four or more layers, the first layer 111 may have a greater number of layers than the third layer. This can minimize the distance between the area where the chip is mounted and the area where the bridge substrate is disposed. As a result, the embodiment can minimize signal transmission loss between chips and maximize the use of the fine circuit pattern of the bridge substrate.

[0117] Further, in the embodiment, the second layer 112 in which the first cavity C1 is formed may be formed of a plurality of layers, so that the embodiment can utilize the fine circuit of the bridge substrate to a greater extent, thereby minimizing signal transmission loss between chips connected through the bridge substrate and maximizing the use of the fine circuit pattern of the bridge substrate.

[0118] The first insulating layer 110 allows the formation of relatively fine circuit layers and vias compared to the second insulating layer 120. For example, when the first insulating layer 110 includes ABF, the width of the circuit layers and vias formed in the first insulating layer 110 may be smaller than the width of the circuit layers and vias formed in the second insulating layer 120.

[0119] Recently, the number of terminals of a processor chip has been increasing, and therefore, in this embodiment, the first insulating layer 110 includes an insulating material such as ABF or PID so that the pitch of the mounting pads on which the chip is mounted can be minimized.

[0120] However, in the embodiment, the first insulating layer 110 is formed using ABF, which has excellent processability and is advantageous in CTE matching with the insulating material forming the second insulating layer 120 .

[0121] Each of the first to third layers 111, 112, 113 of the first insulating layer 110 may have a thickness in the range of 8 μm to 35 μm. Each of the first to third layers 111, 112, 113 of the first insulating layer 110 may have a thickness in the range of 10 μm to 30 μm. Each of the first to third layers 111, 112, 113 of the first insulating layer 110 may have a thickness in the range of 11 μm to 20 μm. If each of the first to third layers 111, 112, 113 of the first insulating layer 110 has a thickness less than 8 μm, the circuit layer formed on the first insulating layer 110 may not be stably protected. If each of the first to third layers 111, 112, 113 of the first insulating layer 110 has a thickness more than 35 μm, it may be difficult to miniaturize the circuit layer and vias formed on the first insulating layer 110, and the thickness of the circuit board may be increased.

[0122] The first layer 111 of the first insulating layer 110 is disposed on the second insulating layer 120. The first layer 111 of the first insulating layer 110 may fill at least a portion of the second cavity C2 and the third cavity C3 of the second insulating layer 120.

[0123] The second layer 112 of the first insulating layer 110 is disposed on the first layer 111 of the first insulating layer 110. The second layer 112 of the first insulating layer 110 may include a first cavity C1. The first cavity C1 may penetrate the second layer 112 of the first insulating layer 110. The first cavity C1 may provide a space in which a bridge substrate 200 is disposed within the first insulating layer 110. For example, the first cavity C1 may provide a space for embedding the bridge substrate 200 within the first insulating layer 110.

[0124] The width of the first cavity C1 may be greater than the width of the bridge substrate 200. In this case, the first cavity C1 may have an upper width and a lower width that are different from each other. For example, the lower width of the first cavity C1 may be smaller than the upper width. And, the width of the first cavity C1 described below may refer to the lower width of the first cavity C1.

[0125] The width of the first cavity C1 may be 105% to 180% of the width of the bridge substrate 200. The width of the first cavity C1 may be 110% to 170% of the width of the bridge substrate 200. The width of the first cavity C1 may be 112% to 160% of the width of the bridge substrate 200. If the width of the first cavity C1 is smaller than 105% of the width of the bridge substrate 200, a problem may occur in that the bridge substrate 200 in the first cavity C1 is not stably protected due to a processing error in a process of forming the first cavity C1. In addition, if the width of the first cavity C1 is smaller than 105% of the width of the bridge substrate 200, a problem may occur in that stress may be concentrated at an edge region of an inner wall of the first cavity C1 in a process environment or a use environment of a circuit board, and the stress may be transferred to the bridge substrate 200. If the width of the first cavity C1 is greater than 180% of the width of the bridge substrate 200, the horizontal size of the circuit board can be increased.

[0126] The third layer 113 of the first insulating layer 110 may be disposed on the second layer 112 of the first insulating layer 110. The third layer 113 of the first insulating layer 110 may fill at least a portion of the first cavity C1 of the second layer 112 of the first insulating layer 110. For example, the third layer 113 of the first insulating layer 110 may be disposed on the second layer 112 of the first insulating layer 110 while surrounding the periphery of the bridge substrate 200 disposed in the first cavity C1.

[0127] A third insulating layer 121 may be disposed below the second insulating layer 120 .

[0128] The third insulating layer 121 may have a symmetrical structure with the first insulating layer 110 with respect to the second insulating layer 120 .

[0129] The third insulating layer 121 may include, but is not limited to, a first layer 122, a second layer 123, and a third layer .

[0130] Meanwhile, each layer of the first insulating layer 110 may have a thickness smaller than that of the second insulating layer 120 .

[0131] For example, the difference between the thickness of each layer of the first insulating layer 110 and the thickness of the second insulating layer 120 may be 15 μm or more, or 20 μm or 25 μm or more.

[0132] The circuit board of the embodiment includes a circuit layer. The circuit layer may be disposed on a surface of an insulating layer of the circuit board. For example, the circuit board of the embodiment may include multiple circuit layers disposed on multiple insulating layers.

[0133] The circuit layers include a first circuit layer disposed on a first insulating layer 110 .

[0134] For example, the first circuit layer includes a 1-1 circuit layer 131 disposed on a first layer 111 of a first insulating layer 110. The first circuit layer also includes a 1-2 circuit layer 132 disposed on a second layer 112 of the first insulating layer 110. The first circuit layer also includes a 1-3 circuit layer 133 disposed on a third layer 113 of the first insulating layer 110.

[0135] The circuit layers also include a second circuit layer disposed on the second insulating layer 120 .

[0136] For example, the second circuit layer includes a 2-1 circuit layer 134 disposed on the upper surface of the second insulating layer 120. The second circuit layer also includes a 2-2 insulating layer 135 disposed on the lower surface of the second insulating layer 120.

[0137] The circuit layers also include a third circuit layer disposed on a third insulating layer 121 .

[0138] For example, the third circuit layer includes a 3-1 circuit layer 136 disposed on a first layer 122 of the third insulating layer 121. The third circuit layer also includes a 3-2 circuit layer 137 disposed on a second layer 123 of the third insulating layer 121. The third circuit layer also includes a 3-3 circuit layer 138 disposed on a third layer 124 of the third insulating layer 121.

[0139] Meanwhile, the first circuit layer includes a pad portion 131a overlapping the first cavity C1 in a vertical direction. The pad portion 131a may be in direct contact with an inner wall of the first cavity C1. For example, the pad portion 131a may have an upper surface exposed through the first cavity C1. The pad portion 131a may be a part of the 1-1 circuit layer 131 of the first circuit layer. That is, the pad portion 131a may refer to a circuit layer of the 1-1 circuit layer 131 that overlaps the first cavity C1 in a vertical direction.

[0140] The pad portion 131a may be greater than the width of the first cavity C1, so that the pad portion 131a may be divided into a plurality of regions.

[0141] For example, the pad portion 131a may include a first portion 131a1 that does not overlap the first cavity C1 in a thickness direction (specifically, does not overlap a lower region of the first cavity in a thickness direction). The first portion 131a1 of the pad portion 131a may not have an upper surface exposed through the first cavity C1. Preferably, the first portion 131a1 of the pad portion 131a may be covered by the second layer 112 of the first insulating layer 110.

[0142] In addition, the pad portion 131a may include second portions 131a2 and 131a3 overlapping the first cavity C1 in a thickness direction. Top surfaces of the second portions 131a2 and 131a3 of the pad portion 131a may be exposed through the first cavity C1.

[0143] The pad portion 131a may function as a laser stopper during the process of forming the first cavity C1.

[0144] In addition, the pad portion 131 a can function as a mounting pad for placing the bridge substrate 200 .

[0145] In addition, the pad portion 131 a can function as a heat dissipation pad for transferring heat generated in the bridge substrate 200 .

[0146] Meanwhile, the second portions 131a2 and 131a3 of the pad portion 131a may be divided into a plurality of portions. The second portions 131a2 and 131a3 of the pad portion 131a may include a 2-1 portion 131a2 that does not overlap at least one of the adhesive layer 500 and the bridge substrate 200 in the thickness direction. In this case, the 2-1 portion 131a2 is shown as being entirely overlapped with the adhesive layer 500 in the vertical direction in the drawings, but is not limited thereto. Preferably, the 2-1 portion 131a2 refers to a portion of the second portion that does not overlap with the bridge substrate 200 in the thickness direction. The 2-1 portion 131a2 may overlap with the adhesive layer 500 in the thickness direction, or may not overlap with the adhesive layer 500 in the thickness direction.

[0147] Also, the second portion of the pad portion 131a includes a 2-2 portion 131a3 overlapping the adhesive layer 500 and the bridge substrate 200 in the thickness direction. That is, the 2-2 portion 131a3 of the second portion of the pad portion 131a provides a space in which the bridge substrate 200 is actually disposed. And, the 2-1 portion 131a2 can function as an extra space in a process of inserting or disposing the bridge substrate 200 in the first cavity C1.

[0148] Meanwhile, the first, second and third circuit layers may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu) and zinc (Zn). The first, second and third circuit layers may be formed of a paste or solder paste containing at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu) and zinc (Zn) having excellent bonding strength. Preferably, the first, second and third circuit layers may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0149] The first, second, and third circuit layers can be formed using typical printed circuit board manufacturing processes such as additive process, subtractive process, MSAP (Modified Semi Additive Process), and SAP (Semi Additive Process), and detailed description thereof will be omitted here.

[0150] The first, second and third circuit layers may have a thickness in the range of 7 μm to 20 μm. For example, the first, second and third circuit layers may have a thickness in the range of 9 μm to 17 μm. The first, second and third circuit layers may have a thickness in the range of 10 μm to 13 μm. If the thickness of the first, second and third circuit layers is less than 7 μm, the resistance may increase, and the electrical characteristics may decrease. If the thickness of the first, second and third circuit layers is less than 7 μm, the warpage characteristics of the circuit board may decrease. If the thickness of the first, second and third circuit layers is more than 20 μm, it may be difficult to miniaturize the circuit layers. This may decrease the circuit integration of the circuit board. This may increase the size of the circuit board.

[0151] The first, second and third circuit layers include pads and traces. The pads may include via pads connected to vias, core pads on which adhesive balls (described later) connected to a main board of an electronic device are disposed, or BGA pads. The traces may refer to long line-shaped wiring that transmits electrical signals while being connected to the pads. The pads (specifically, via pads) of the first, second and third circuit layers may have a width in the range of 20 μm to 50 μm. The pads of the first, second and third circuit layers may have a width in the range of 22 μm to 40 μm. The pads of the first, second and third circuit layers may have a width in the range of 25 μm to 35 μm.

[0152] Meanwhile, the traces of the first, second, and third circuit layers can have a specific line width and a specific spacing. For example, the line width of the traces of the first, second, and third circuit layers can have a range of 6 μm to 20 μm. For example, the line width of the traces of the first, second, and third circuit layers can have a range of 7 μm to 15 μm. For example, the line width of the traces of the first, second, and third circuit layers can have a range of 8 μm to 12 μm. Also, the spacing of the traces of the first, second, and third circuit layers can have a range of 6 μm to 20 μm. For example, the spacing of the traces of the first, second, and third circuit layers can have a range of 7 μm to 15 μm. For example, the spacing of the traces of the first, second, and third circuit layers can have a range of 8 μm to 12 μm.

[0153] Meanwhile, the first, second, and third circuit layers may have different thicknesses, widths, and intervals. For example, the first and third circuit layers are disposed on a first insulating layer 110 and a third insulating layer 121, which are made of a first insulating material. And the second circuit layer is disposed on a second insulating layer 120, which is made of a second insulating material. Thus, the thicknesses, widths, and intervals of the first and third circuit layers may be smaller than the thickness, width, and intervals of the second circuit layer, but are not limited thereto.

[0154] As an example, the first circuit layer may have a smaller thickness, width, and spacing as it moves away from the second circuit layer.

[0155] For example, the thickness, width, and spacing of the 1-3 circuit layer 133 among the first circuit layers may be the smallest. This is because the 1-3 circuit layer 133 functions as a pad connected to a processor chip, and therefore should have a standard corresponding to the terminal of the processor chip. Furthermore, the 1-3 circuit layer 133 is required to have a high degree of integration. Thus, in this embodiment, the thickness, width, and spacing of the 1-3 circuit layer 133 among the first circuit layers are made the smallest.

[0156] In addition, the thickness, width, and spacing of the 1-1 circuit layer 131 may be the largest among the first circuit layers. For example, the thickness, width, and spacing of the 1-1 circuit layer 131 may correspond to the thickness, width, and spacing of the second circuit layer.

[0157] Furthermore, the thickness, width, and spacing of the 1-2 circuit layer 132 of the first circuit layer may be smaller than those of the 1-1 circuit layer 131 and larger than those of the 1-3 circuit layer 133. As a result, the embodiment can minimize signal transmission loss caused by differences in specifications of the circuit layers through changes in thickness, width, and spacing for each layer of the first circuit layer.

[0158] Meanwhile, the third circuit layer is connected to a main board of an electronic device, so that the third circuit layer can have a specification corresponding to the specifications (e.g., the number of pads, the spacing between pads, etc.) of the main board of the electronic device.

[0159] On the other hand, the circuit board of the embodiment includes a via. The via penetrates at least one insulating layer. As a result, the via can be called a through electrode. The via can penetrate one insulating layer. In contrast, the via can penetrate at least two or more insulating layers in common.

[0160] The vias include a first via that penetrates the first insulating layer 110 .

[0161] The first vias include a 1-1 via 141 that penetrates a first layer 111 of the first insulating layer 110. The first vias include a 1-2 via 142 that penetrates a second layer 112 of the first insulating layer 110. The first vias include a 1-3 via 143 that penetrates a third layer 113 of the first insulating layer 110.

[0162] The vias include a second via 144 that penetrates the second insulating layer 120 .

[0163] The vias also include a third via that penetrates the third insulating layer 121.

[0164] The third vias include a 3-1 via 145 that penetrates a first layer 122 of the third insulating layer 121. The third vias include a 3-2 via 146 that penetrates a second layer 123 of the third insulating layer 121. The third vias include a 3-3 via 147 that penetrates a third layer 124 of the third insulating layer 121.

[0165] Each of the first to third vias may have a width in the range of 10 μm to 60 μm. Each of the first to third vias may have a width in the range of 15 μm to 50 μm. Each of the first to third vias may have a width in the range of 20 μm to 40 μm. In this case, each of the first to third vias includes a first surface and a second surface opposite to the first surface. The width of the first surface is different from the width of the second surface. In this case, the width of each of the first to third vias may refer to the width of the surface that is relatively wider among the first surface and the second surface.

[0166] In this case, the first to third vias may have different widths. For example, the second via 144 may have a width greater than the first and second vias. The second via 144 may have a cross-sectional shape different from the cross-sectional shapes of the first and second vias, but is not limited thereto.

[0167] Meanwhile, the first vias of the embodiment may include vias having different thicknesses or widths in the same layer.

[0168] For example, the 1-1 via 141 can include a first sub-via 141a and a second sub-via 141b depending on the location.

[0169] The first sub-via 141 a of the 1-1 via 141 refers to a via connected to the second circuit layer 134 disposed on the upper surface of the second insulating layer 120 .

[0170] The second sub-via 141b of the 1-1 via 141 is horizontally spaced apart from the first sub-via 141a of the 1-1 via 141. The second sub-via 141b of the 1-1 via 141 is connected to the elements 300 and 400 inserted in the second insulating layer 120. For example, the second sub-via 141b of the 1-1 via 141 is connected to the terminals 310 and 410 of the elements 300 and 400.

[0171] Therefore, the first sub-via 141a and the second sub-via 141b of the 1-1 via 141 may have different widths or thicknesses.

[0172] For example, the width of the first sub-via 141a of the 1-1 via 141 may be greater than the width of the second sub-via 141b of the 1-1 via 141. That is, the second sub-via 141b of the 1-1 via 141 is connected to the terminals 310, 410 of the elements 300, 400, and therefore must have a width or pitch corresponding to the specifications of the terminals 310, 410. However, the first sub-via 141a of the 1-1 via 141 is connected to the second circuit layer. And, the first sub-via 141a of the 1-1 via 141 may have a width corresponding to the width of the second via 144 in order to minimize signal transmission loss.

[0173] Meanwhile, a thickness of the first sub-via 141a of the 1-1 via 141 may correspond to a thickness of the first layer 111 of the first insulating layer 110. And, a thickness of the second sub-via 141b of the 1-1 via 141 may be different from a thickness of the first sub-via 141a of the 1-1 via 141. For example, a thickness of the second sub-via 141b of the 1-1 via 141 may be different from a thickness of the first layer 111 of the first insulating layer 110.

[0174] For example, the position of the upper surface of the terminals 310, 410 of the elements 300, 400 may be different from the position of the upper surface of the second circuit layer 134 disposed on the upper surface of the second insulating layer 120. For example, the position of the upper surface of the terminals 310, 410 of the elements 300, 400 may be higher than the position of the upper surface of the second circuit layer 134 disposed on the upper surface of the second insulating layer 120, or may be different and lower than the position of the upper surface of the second circuit layer 134 disposed on the upper surface of the second insulating layer 120.

[0175] Therefore, as an example, the thickness of the first sub-via 141a of the 1-1 via 141 may be greater than the thickness of the second sub-via 141b of the 1-1 via 141. In another example, the thickness of the first sub-via 141a of the 1-1 via 141 may be less than the thickness of the second sub-via 141b of the 1-1 via 141.

[0176] Meanwhile, the 1-3 via 143 may include 1-3 sub-vias 143a, 143b, and 143c depending on the position. The first sub-via 143a of the 1-3 via 143 may refer to a via that vertically overlaps with the bridge substrate 200. For example, the first sub-via 143a of the 1-3 via 143 refers to a via that is directly connected to the bridge substrate 200.

[0177] The second sub-via 143b of the 1-3 via 143 refers to a via connected to a mounting pad (not shown) connected to a processor chip.

[0178] The third sub-via 143c of the 1-3 via 143 refers to a via connected to a mounting pad (not shown) connected to a memory chip.

[0179] The first sub-via 143a of the 1-3 via 143 may have a thickness different from that of the second and third sub-vias 143b, 143c of the 1-3 via 143. The first sub-via 143a of the 1-3 via 143 may have a width different from that of the second and third sub-vias 143b, 143c of the 1-3 via 143.

[0180] The second sub-via 143b of the 1-3 via 143 is required to be miniaturized for connection to a processor chip mounted on a substrate, and therefore the second sub-via 143b of the 1-3 via 143 may have a width smaller than that of the third sub-via 143c of the 1-3 via 143.

[0181] Meanwhile, the third sub-via 143c of the 1-3 via 143 may have a width greater than the first and second sub-vias 143a and 143b of the 1-3 via 143.

[0182] In addition, the first sub-via 143a of the 1-3 via 143 may have a width smaller than that of the second sub-via 143b of the 1-3 via 143. This reduces the signal transmission length connecting process chips mounted on the substrate, thereby reducing signal loss during signal transmission between chips.

[0183] As described above, in the embodiment, the first vias disposed in the first insulating layer 110 have different thicknesses or widths depending on their positions or functions. In the embodiment, the signal transmission loss occurring in the circuit board connected to the processor chip, the elements 300, 400, and the bridge substrate 200 can be minimized, thereby improving communication performance.

[0184] Meanwhile, the vias may be formed by forming through holes penetrating the respective insulating layers and filling the insides of the formed through holes with a conductive material.

[0185] The through-holes may be formed by any one of mechanical, laser, and chemical processing methods. The through-holes may be formed by any one of mechanical processing methods, such as milling, drilling, and routing. The through-holes may also be formed by UV or CO 2 The through-holes can be formed by using any one of the laser processing methods mentioned above. Also, the through-holes can be formed by using a chemical processing method using a chemical containing aminosilane, ketones, and the like.

[0186] When the through holes are formed, the insides of the through holes can be filled with a conductive material to form the respective vias. The metal material forming the vias can be any one selected from the group consisting of copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). The conductive material can be filled by any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and de-fencing.

[0187] Meanwhile, the circuit board of the embodiment provides a mounting area in which at least two chips of different types are mounted. Also, the circuit board of the embodiment provides an embedding area in which at least one passive element is embedded. The mounting area may refer to a chip arrangement area on the outside of the circuit board. And, the embedding area may refer to a chip arrangement area on the inside of the circuit board.

[0188] The circuit board can transmit and receive signals acquired or processed by at least two processor chips or a processor chip and a memory chip, and in this case, the at least two processor chips or the processor chip and the memory chip are connected via the bridge substrate 200.

[0189] That is, the circuit board provides a chip mounting area on which a plurality of first and second chips of different types can be mounted, and the first and second chips may be first and second processor chips in which application processors are separated according to their functions.

[0190] For example, the circuit board of the embodiment provides a first mounting area in which a first processor chip is mounted. Also, the circuit board of the embodiment provides a second mounting area in which a second processor chip is mounted. In this case, the first processor chip may be any one of application processor (AP) chips such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. The second processor chip may be a processor chip of a different type from the first processor chip, among application processor (AP) chips such as a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. For example, the first processor chip may be a central processor chip, and the second processor chip may be a graphic processor chip. That is, the circuit board of the embodiment may be a circuit board for separating an application processor by function and die-splitting at least two processor chips separated by the function.

[0191] Meanwhile, as the number of functions required for application processors has increased recently, there has been a demand for a circuit board on which a separate processor chip can be mounted, with each function being configured as a separate processor chip. In this case, even if the application processor is separated into two processor chips for each function, the number of terminals (input / output) provided on each processor chip is increasing. In this case, unlike the comparative example in which one application processor chip processes all the functions, when the processor chip is separated into at least two, each processor chip must be electrically connected to each other to exchange signals between them.

[0192] In this case, if the distance between the processor chips is large, fine patterns as in the embodiment may not be required. However, if the distance between the processor chips is large, the communication speed for signal exchange between the processor chips may decrease. Furthermore, if the distance between the processor chips is large, the power consumption required for communication increases. Furthermore, if the distance between the processor chips is large, the length of the traces connecting the processor chips increases, which makes the processor chips vulnerable to noise and increases signal transmission loss.

[0193] That is, the spacing between the processor chips must be 150 μm or less for reliability. For example, the spacing between the processor chips must be 120 μm or less for reliability. For example, the spacing between the processor chips must be 100 μm or less for reliability.

[0194] Therefore, in order to connect both the wiring between the first processor chip and the second processor chip within the limited space as described above, it is necessary to miniaturize the circuit pattern to a specific line width and spacing or less, as described above.

[0195] Conventionally, the number of connecting wires between the first processor chip and the second processor chip was N. When the number of connecting wires is N, the miniaturization level of the circuit pattern may differ from that of the embodiment within the limited space described above.

[0196] Meanwhile, the number of terminals in the first processor chip and the second processor chip has been gradually increasing recently due to reasons such as 5G, Internet of Things (IOT), improved image quality, and increased communication speed, etc. As a result, the number of connecting wires between the first processor chip and the second processor chip may be more than twice (2N pieces), more than three times (3N pieces), or more than ten times (10N pieces) of the conventional number.

[0197] Therefore, in order to mount the first processor chip and the second processor chip on a single circuit board while minimizing the gap between them and to connect the first processor chip and the second processor chip within a limited space, ultra-fine circuit layers of the circuit board are required.

[0198] However, there is a limit to miniaturizing the circuit layer. Therefore, in the embodiment, a bridge substrate 200 is disposed on the first insulating layer 110. And, in the embodiment, at least two chips mounted on the circuit board are connected to each other through the bridge substrate 200.

[0199] As a result, as described above, the width or thickness of the first sub-via 143a of the 1-3 via 143 may be different from the width or thickness of the other sub-vias of the 1-3 via 143. This is because the thickness and width of the first sub-via 143a of the 1-3 via 143 are determined according to the height of the bridge substrate 200 and the width of the wiring layer included in the bridge substrate 200.

[0200] For example, the height of the top wiring layer of the bridge substrate 200 may be lower than the top surface of the 1-2 circuit layer 132. Alternatively, the height of the top wiring layer of the bridge substrate 200 may be higher than the top surface of the 1-2 circuit layer 132. Therefore, the thickness of the first sub-via 143a of the 1-3 via 143 may be greater than or smaller than the thickness of the other sub-vias. However, in the embodiment, the thickness difference between the first sub-via 143a of the 1-3 via 143 and the other sub-vias of the 1-3 via 143 is minimized. Through this, the embodiment may improve the reliability of the circuit substrate. In this case, the top wiring layer of the bridge substrate 200 may refer to the circuit layer of the bridge substrate, or may refer to a pad layer.

[0201] This can be achieved by structural features of the bridge substrate 200, which will be described below.

[0202] Meanwhile, the circuit board of the embodiment includes a first protective layer 151. The first protective layer 151 may be disposed on the first insulating layer 110.

[0203] The circuit board of the embodiment also includes a second protective layer 152. The second protective layer 152 may be disposed under the third insulating layer 121.

[0204] Each of the first protective layer 151 and the second protective layer 152 includes at least one opening.

[0205] Meanwhile, the bridge substrate 200 is disposed in the first cavity C1 of the first insulating layer 110. That is, the bridge substrate 200 is embedded in the first insulating layer 110. Specifically, the bridge substrate 200 may be covered with the third layer 113 of the first insulating layer 110 while being disposed in the first cavity C1 formed in the second layer 112 of the first insulating layer 110.

[0206] The bridge substrate 200 is electrically connected to a first circuit layer and a first via formed in the first insulating layer 110 .

[0207] For example, the bridge substrate 200 is connected to the 1-3 via 143 penetrating the third layer 113 of the first insulating layer 110. Preferably, the bridge substrate 200 is connected to the first sub-via 143a of the 1-3 via 143.

[0208] At this time, the first sub-vias 143a of the 1-3 vias 143 may be divided into a plurality of groups. For example, the first sub-vias 143a of the 1-3 vias 143 include at least one via of a first group connected to a first processor chip. Also, the first sub-vias 143a of the 1-3 vias 143 include at least one via of a second group connected to a second processor chip. And, the bridge substrate 200 is connected to the vias of the first group and the vias of the second group of the first sub-vias 143a of the 1-3 vias 143. For example, the bridge substrate 200 electrically connects the vias of the first group and the vias of the second group of the first sub-vias 143a. Through this, the bridge substrate 200 connects between the first processor chip and the second processor chip. Specifically, the first processor chip includes a plurality of first terminals. And, the second processor chip includes a plurality of second terminals. At this time, at least one of the first terminals must be electrically connected to at least one of the second terminals. In this embodiment, at least one of the first terminals is electrically connected to at least one of the second terminals using the bridge substrate 200.

[0209] The bridge substrate 200 can perform die-to-die interconnection that electrically connects a plurality of processor chips mounted on a circuit board to each other. The plurality of processor chips must be electrically connected to each other within a limited space. At this time, in order to connect the plurality of processor chips, a very dense connection circuit is required within the limited space. Therefore, in the embodiment, the bridge substrate 200 including a high-density circuit layer is disposed in the first cavity C1 of the first insulating layer 110. And, in the embodiment, the bridge substrate 200 can be used to electrically connect the plurality of processor chips mounted on the circuit board.

[0210] The bridge substrate 200 may include a micro-fine pattern.

[0211] The bridge substrate 200 includes an insulating layer 210 and a circuit layer disposed on the insulating layer 210 .

[0212] 6, the bridge substrate 200 may include, but is not limited to, one insulating layer. Exemplarily, the bridge substrate 200 may include an insulating layer having a multi-layer laminate structure.

[0213] Thus, the circuit layers of the bridge substrate 200 may include a first circuit layer 220 a disposed on the upper surface of the insulating layer 210 and a second circuit layer 220 b disposed on the lower surface of the insulating layer 210 .

[0214] The bridge substrate 200 further includes a via 230 penetrating the insulating layer 210. The via 230 of the bridge substrate 200 electrically connects the first circuit layer 220a and the second circuit layer 220b of the bridge substrate 200.

[0215] The bridge substrate 200 also includes a protective layer disposed on the insulating layer 210. For example, the bridge substrate 200 includes a first protective layer 240a disposed on an upper surface of the insulating layer 210. The bridge substrate 200 also includes a second protective layer 240b disposed on a lower surface of the insulating layer 210. The first protective layer 240a and the second protective layer 240b may be, but are not limited to, solder resist.

[0216] The first protective layer 240a is disposed on an upper surface of the insulating layer 210. The first protective layer 240a includes an opening overlapping at least a portion of an upper surface of the first circuit layer 220a in a thickness direction. For example, the first protective layer 240a may include a first opening overlapping the first circuit layer 220a connected to a first group of vias among the first sub-vias 143a in a thickness direction. The first protective layer 240a may also include a second opening overlapping the first circuit layer 220a connected to a second group of vias among the first sub-vias 143a in a thickness direction.

[0217] The first circuit layer 220a overlapping the first opening of the first protective layer 240a in the thickness direction may function as a first pad layer connected to the first group of vias of the first sub-via 143a, and the first circuit layer 220a overlapping the second opening of the first protective layer 240a in the thickness direction may function as a second pad layer connected to the second group of vias of the first sub-via 143a.

[0218] The second protective layer 240b is disposed on the lower surface of the insulating layer 210. At this time, the second protective layer 240b does not include an opening. For example, the second protective layer 240b is disposed to entirely cover the side and lower surface of the second circuit layer 220b of the bridge substrate 200.

[0219] In this case, the insulating layer 210, the first circuit layer 220a, and the second circuit layer 220b constituting the bridge substrate 200 can be said to be a redistribution layer RDL.

[0220] The redistribution layer RDL may include a first protective layer 240a and a second protective layer 240b.

[0221] The insulating layer 210 of the bridge substrate 200 may include an organic material. The insulating layer 210 of the bridge substrate 200 may include an insulating material different from the first insulating layer 110, the second insulating layer 120, and the third insulating layer 121. For example, the bridge substrate 200 may include an insulating material having excellent processability and elasticity. For example, the insulating layer 210 of the bridge substrate 200 may include polyimide (PI).

[0222] In this case, the insulating layer of a general bridge substrate is made of a silicon material, whereas the bridge substrate 200 of the embodiment includes polyimide (PI).

[0223] As a result, the embodiment allows the insulating layer 210 of the bridge substrate 200 to have a similar CTE to the first insulating layer 210 of the circuit board, thereby minimizing stress applied to the bridge substrate 200. Through this, the embodiment may improve the physical and electrical reliability of the bridge substrate 200.

[0224] In addition, in the embodiment, the material of the insulating layer 210 applied to the bridge substrate 200 is changed to polyimide, which is less expensive than a silicon substrate, so that the cost of the bridge substrate 200 can be reduced.

[0225] At this time, the alignment state between the first pad layer of the first circuit layer 220a of the bridge substrate 200 and the first group of vias of the first sub-via 143a of the 1-3 via 143 has a large effect on the product reliability of the circuit substrate and the semiconductor package. Also, the alignment state between the second pad layer of the first circuit layer 220a of the bridge substrate 200 and the second group of vias of the first sub-via 143a of the 1-3 via 143 has a large effect on the product reliability of the circuit substrate and the semiconductor package. Thus, in the embodiment, polyimide (PI) having transparent properties is used as the insulating layer of the bridge substrate 200. Thus, in the embodiment, the alignment between the first and second pad layers of the bridge substrate 200 and the first sub-via 143a of the 1-3 via 143 can be improved.

[0226] Furthermore, the embodiment may stably protect the bridge substrate 200 from stress generated during thermal deformation of the first insulating layer 110 through CTE matching. Thus, the embodiment may stably establish electrical connection between a plurality of semiconductor devices through the bridge substrate 200, thereby enabling the plurality of semiconductor devices to stably operate.

[0227] That is, conventionally, the insulating layer of the bridge substrate is made of silicon. At this time, the silicon has a large CTE difference from the insulating layer constituting the first insulating layer 110. Furthermore, the silicon has rigid properties. As a result, the conventional bridge substrate has a problem that the bridge substrate including the silicon cannot flow when the first insulating layer 110 is thermally deformed. As a result, the conventional bridge substrate has reliability problems such as cracks when thermally deformed.

[0228] In contrast, in the embodiment, the insulating layer 210 of the bridge substrate 200 has a similar CTE to the first insulating layer 110 and has a flexible characteristic. As a result, in the embodiment, the bridge substrate 200 flows when the first insulating layer 110 is thermally deformed, thereby solving reliability problems such as cracks in the bridge substrate 200.

[0229] Also, in the embodiment, the insulating layer 210 includes polyimide (PI), so that the thickness of the bridge substrate 200 can be easily adjusted. For example, in the conventional bridge substrate including a silicon substrate, a process of polishing the silicon substrate must be performed to adjust the thickness of the bridge substrate. As a result, it is difficult to adjust the thickness of the bridge substrate to a desired thickness due to the difficulty of the process. Furthermore, the conventional bridge substrate can connect pads provided on different layers using TSVs (Through Silicon Vias), but there is a problem in that the TSVs are difficult to process, which increases the manufacturing cost.

[0230] In contrast, in the embodiment, the insulating layer 210 of the bridge substrate 200 includes polyimide (PI), so that the thickness of the bridge substrate 200 can be easily adjusted. Furthermore, in the embodiment, the total thickness of the bridge substrate 200 can be easily controlled in response to the depth of the first cavity C1 formed in the first insulating layer 110. As a result, the embodiment can minimize the height difference between the first circuit layer 220a of the bridge substrate 200 and the first-2 circuit layer 132 disposed on the second layer 112 of the first insulating layer 110. As a result, the embodiment can improve the reliability of the product.

[0231] Furthermore, in the embodiment, since the insulating layer 210 of the bridge substrate 200 includes an organic material, it is possible to easily electrically connect the pad layers provided on different layers. Exemplarily, in the embodiment, a via is formed penetrating the insulating layer 210 of the bridge substrate 200, and the pad layers provided on different layers can be electrically connected therethrough. Thus, in the embodiment, power can be stably supplied to the semiconductor device using the pad layers provided on the upper and lower sides of the bridge substrate 200.

[0232] In particular, the number of power terminals and communication terminals of semiconductor packages applied to servers and / or HPCs (High Performance Computers), etc., is increasing. As a result, in the case of a conventional bridge substrate including an inorganic substance, it may be difficult to stably supply power to the bridge substrate and semiconductor elements due to a shortage of the number of power supply lines and / or limitations on power intensity, and the semiconductor package may not operate stably due to a shortage of power for the bridge substrate and / or semiconductor elements.

[0233] In contrast, the embodiment may provide a bridge substrate 200 including an organic insulating layer, thereby increasing the number of power supply lines or increasing the power intensity. Therefore, the embodiment may provide a stable power supply to the bridge substrate 200 and / or the semiconductor device, and may prevent a drop in power supplied to the bridge substrate and / or the semiconductor device through decoupling of the capacitor function.

[0234] Meanwhile, referring to FIG. 5, the bridge substrate 200 of the second embodiment may further include a first pad layer 250a and a second pad layer 250b. The first pad layer 250a of the bridge substrate 200 is disposed on a first circuit layer 220a of the bridge substrate 200 that is vertically overlapped with the first opening of the first protective layer 240a. Also, the second pad layer 250b of the bridge substrate 200 is disposed on a first circuit layer 220a of the bridge substrate 200 that is vertically overlapped with the second opening of the first protective layer 240a. Thus, the bridge substrate of the second embodiment may further ensure alignment between the first sub-via 143a of the 1-3 via 143 and the pad layer compared to the first embodiment. Meanwhile, the first pad layer 250a and the second pad layer 250b may be called bumps.

[0235] Meanwhile, referring to FIG. 6, the bridge substrate 200 of the third embodiment may have a multi-layer structure. For example, the bridge substrate 200 may include a first insulating layer 210a, a second insulating layer 210b, and a third insulating layer 210c. The bridge substrate 200 may also include a first circuit layer 220a disposed on the first insulating layer 210a. The bridge substrate 200 may also include a second circuit layer 220b disposed between the lower surface of the first insulating layer 210a and the upper surface of the second insulating layer 210b. The bridge substrate 200 may also include a third circuit layer 220c disposed between the lower surface of the second insulating layer 210b and the upper surface of the third insulating layer 210c. The bridge substrate 200 may also include a fourth circuit layer 220d disposed on the lower surface of the third insulating layer 210c. The bridge substrate 200 of the third embodiment may also include a first protective layer 240a disposed on the upper surface of the first insulating layer 210a. The bridge substrate 200 of the third embodiment also includes a second protective layer 240b disposed on the lower surface of the third insulating layer 210c. The bridge substrate 200 of the third embodiment also includes a first via 230a penetrating the first insulating layer 210a. The bridge substrate 200 of the third embodiment also includes a second via 230b penetrating the second insulating layer 210b. The bridge substrate 200 of the third embodiment also includes a third via 230c penetrating the third insulating layer 210c.

[0236] The following description will focus on the bridge substrate 200 of the first embodiment. However, the bridge substrate 200 may have a structure as shown in FIGS.

[0237] The slope of the side surface of the via 230 penetrating the insulating layer 210 of the bridge substrate 200 may be different from the slope of the side surface of the first via penetrating the first insulating layer 110 .

[0238] Preferably, the inclination of the side surface of the via 230 penetrating the insulating layer 210 of the bridge substrate 200 may be closer to vertical than the inclination of the side surface of the first via penetrating the first insulating layer 110 .

[0239] Specifically, the difference between the top and bottom widths of the via 230 penetrating the insulating layer 210 of the bridge substrate 200 of the embodiment may be smaller than the difference between the top and bottom widths of the first via penetrating the first insulating layer 110.

[0240] For example, the lower width of the via 230 penetrating the insulating layer 210 of the bridge substrate 200 may be in the range of 95% to 105% of the upper width. For example, the lower width of the via 230 penetrating the insulating layer 210 of the bridge substrate 200 may be in the range of 96% to 104% of the upper width. For example, the lower width of the via 230 penetrating the insulating layer 210 of the bridge substrate 200 may be in the range of 97% to 103% of the upper width. As a result, the embodiment may improve the electrical characteristics of the bridge substrate 200.

[0241] Meanwhile, the reason why the inclination of the side of the via 230 of the bridge substrate 200 can approach a substantially vertical angle is because the insulating layer 210 of the bridge substrate 200 includes polyimide (PI). That is, in the embodiment, the insulating layer 210 of the bridge substrate 200 includes polyimide (PI), and a via hole penetrating the insulating layer 210 can be formed using a UV laser. As a result, the inclination of the inner wall of the via 230 penetrating the insulating layer 210 can approach a right angle with respect to the upper or lower surface of the insulating layer 210.

[0242] Meanwhile, referring to FIGS. 7 and 8, the first circuit layer 220a, the second circuit layer 220b, and the vias 230a of the bridge substrate 200 of the embodiment may have a multi-layer structure.

[0243] Specifically, the first circuit layer 220a of the bridge substrate 200 may include a first metal layer 220a1 and a second metal layer 220a2. The second circuit layer 220b of the bridge substrate 200 may also include a first metal layer 220b1 and a second metal layer 220b2 corresponding to the first circuit layer 220a. The via 230a of the bridge substrate 200 may also include a first metal layer 230a1 and a second metal layer 230a2 corresponding to the first circuit layer 220a and the second circuit layer 220b.

[0244] The following description will focus on the first metal layer 220a1 and the second metal layer 220a2 of the first circuit layer 220a. The first metal layers 220b1, 230a1 and the second metal layers 220b2, 230a2 of the second circuit layer 220b and the via 230a may be formed corresponding to the first metal layer 220a1 and the second metal layer 220a2 of the first circuit layer 220a described below.

[0245] The first metal layer 220a1 of the first circuit layer 220a may be a metal layer formed through sputtering. The first metal layer 220a1 may be a seed layer. The first metal layer 220a1 may have a one-layer structure, or alternatively, may have a two-layer structure.

[0246] When the first metal layer 220a1 has a one-layer structure, the first metal layer 220a1 may include only a first layer including at least one of nickel (Ni) and chromium (Cr). When the first metal layer 220a1 has a two-layer structure, the first metal layer 220a1 may further include a second layer including copper (Cu) on the first layer. Hereinafter, the first metal layer 220a1 will be described as including a first layer and a second layer. However, the embodiment is not limited thereto.

[0247] The first layer of the first metal layer 220a includes at least one of nickel (Ni) and chromium (Cr) formed through a sputtering process, and the second layer of the first metal layer 220a may be formed by sputtering a metal including copper (Cu) on the first layer of the first metal layer 220a.

[0248] The first layer of the first metal layer 220a may have a thickness of 0.01 μm to 0.15 μm. For example, the first layer of the first metal layer 220a may have a thickness of 0.03 μm to 0.14 μm. For example, the first layer of the first metal layer 220a may have a thickness of 0.05 μm to 0.12 μm. If the first layer of the first metal layer 220a has a thickness smaller than 0.01 μm, the first metal layer 220a may not function as a seed layer. Also, if the first layer of the first metal layer 220a has a thickness smaller than 0.01 μm, the adhesion between the first metal layer 220a and the second metal layer 220b may not be ensured.

[0249] Furthermore, if the thickness of the first metal layer 220a1 is greater than 0.15 μm, the line width and spacing of the first circuit layer 220a of the bridge substrate 200 can be increased. For example, if the thickness of the first metal layer 220a1 is greater than 0.15 μm, it may be difficult to ultra-fine the first circuit layer 220a of the bridge substrate 200.

[0250] The second layer of the first metal layer 220a1 may have a thickness of 0.1 μm to 0.35 μm. For example, the second layer of the first metal layer 220a1 may have a thickness of 0.12 μm to 0.34 μm. For example, the second layer of the first metal layer 220a1 may have a thickness of 0.15 μm to 0.33 μm.

[0251] Meanwhile, the total thickness of the first metal layer 220a1 including the first and second layers may be 0.5 μm or less. Preferably, the total thickness of the first metal layer 220a1 including the first and second layers may be 0.4 μm or less. More preferably, the total thickness of the first metal layer 220a1 including the first and second layers may be 0.3 μm or less. If the total thickness of the first metal layer 220a1 including the first and second layers exceeds 0.5 μm, it may be difficult to fine-tune the first circuit layer 220a. Specifically, the formation process of the first circuit layer 220a of the bridge substrate 200 includes a seed layer removal process of removing the first metal layer 220a1. At this time, as the thickness of the first metal layer 220a1 increases, the amount of etching in the seed layer process increases, which makes it difficult to fine-tune the first circuit layer 220a of the bridge substrate 200.

[0252] In the embodiment, the first metal layer 220a1 is formed by a sputtering process, which allows the first circuit layer 220a of the bridge substrate 200 to be miniaturized.

[0253] The second metal layer 220a2 may be an electrolytic plating layer formed by electrolytic plating using the first metal layer 220a1 as a seed layer. The second metal layer 220a2 may have a thickness in the range of 2 μm to 12 μm. The second metal layer 220a2 may have a thickness in the range of 3 μm to 11 μm. The second metal layer 220a2 may have a thickness in the range of 4 μm to 10 μm.

[0254] If the thickness of the second metal layer 220a2 is less than 2 μm, the second metal layer 220a2 is also etched during the etching process of the seed layer, which may make it difficult to properly realize the first circuit layer 220a of the bridge substrate 200. If the thickness of the second metal layer 220a2 is more than 12 μm, it may be difficult to miniaturize the first circuit layer 220a of the bridge substrate 200.

[0255] In addition, the first metal layer 230a1 of the via 230a may be formed of a metal layer different from the first metal layers 220a1, 220b1 of the first circuit layer 200a or the second circuit layer 220b. The first metal layer 230a1 of the via 230a may include palladium Pd, which is a metal different from the first metal layers 220a1, 220b1 of the first circuit layer 220a or the second circuit layer 220b.

[0256] The first circuit layer 220a having the above-mentioned layer structure may have a total thickness in the range of 3 μm to 13 μm. The first circuit layer 220a having the above-mentioned layer structure may have a total thickness in the range of 4 μm to 12 μm. The first circuit layer 220a having the above-mentioned layer structure may have a total thickness in the range of 5 μm to 11 μm. If the thickness of the first circuit layer 220a is less than 5 μm, the resistance of the first circuit layer 220a increases, and the reliability of the connection with the first and second processor chips may decrease. If the thickness of the first circuit layer 220a exceeds 11 μm, it may be difficult to realize a fine pattern required for the bridge substrate 200.

[0257] Thus, the first circuit layer 220a may have an ultra-fine pattern. For example, the first circuit layer 220a may have a line width of 5 μm or less. For example, the first circuit layer 220a may have a line width of 3 μm or less. For example, the first circuit layer 220a may have a line width of 2 μm or less. The first circuit layer 220a may have a spacing of 5 μm or less. The spacing may refer to a separation distance between traces of the first circuit layer 220a arranged on the same layer. For example, the first circuit layer 220a may have a spacing of 3 μm or less. For example, the first circuit layer 220a may have a spacing of 2 μm or less.

[0258] Preferably, the first circuit layer 220a may have a line width of 1 μm to 5 μm. The first circuit layer 220a may have a line width in the range of 1.2 μm to 3 μm. The first circuit layer 220a may have a line width in the range of 1.5 μm to 2 μm. If the line width of the first circuit layer 220a is smaller than 1 μm, the resistance of the first circuit layer 220a increases, which may make it difficult to properly communicate with the processor chip. If the line width of the first circuit layer 220a is larger than 5 μm, it may be difficult to realize a bridge substrate 200 for connecting a plurality of processor chips in a limited space. For example, if the line width of the first circuit layer 220a is larger than 6 μm, it may be difficult to arrange the bridge substrate 200 including traces for connecting a plurality of processor chips in the first cavity C1 formed in a limited space.

[0259] Meanwhile, the second circuit layer 220b of the bridge substrate 200 may also include a first metal layer 220b1 and a second metal layer 220b2 having a structure corresponding to that of the first circuit layer 220a.

[0260] In addition, the via 230a of the bridge substrate 200 may also include a first metal layer 230a1 and a second metal layer 230a2 having a structure corresponding to the first circuit layer 220a and the second circuit layer 220b.

[0261] Meanwhile, the second metal layer 230a2 of the via 230a may have different structures depending on the embodiment.

[0262] For example, as shown in FIG. 7, the second metal layer 230a2 of the via 230a may be disposed to entirely fill a through hole penetrating the insulating layer 210 of the bridge substrate 200. As shown in FIG.

[0263] As another example, as shown in FIG. 8, the second metal layer 220a2 of the via 230a may be disposed to fill a portion of a through hole penetrating the insulating layer 210 of the bridge substrate 200. In the example shown in FIG.

[0264] Meanwhile, the circuit board of the embodiment includes an adhesive layer 500 disposed on the lower surface of the second protective layer 240b of the bridge substrate 200. The adhesive layer 500 may be disposed on the pad portion 131a exposed through the first cavity C1.

[0265] The adhesive layer 500 may provide a bonding force such that the bridge substrate 200 is stably fixed or mounted in the first cavity C1.

[0266] Meanwhile, the circuit board of the embodiment may further include elements 300, 400 disposed in the second cavity C2 and the third cavity C3 of the second insulating layer 120. The elements 300, 400 may be, but are not limited to, passive elements. For example, active elements may be embedded in the circuit board of the embodiment.

[0267] For example, the circuit board may include a first element 300 disposed in the second cavity C2. The first element 300 may be an integrated passive device (IPD). The first element 300 includes a terminal 310. The terminal 310 of the first element 300 may be electrically connected to a second sub-via 141b of a 1-1 via 141 penetrating a first layer 111 of a first insulating layer 110.

[0268] For example, the circuit board may include a second element 400 disposed in a third cavity C3. The second element 400 may be, but is not limited to, a multi-layer ceramic capacitor (MLCC). The second element 400 includes a terminal 410. For example, when the second element 400 is a multi-layer ceramic capacitor, the terminal of the second element 400 may include a plurality of terminals 411, 412, and 413. For example, the second element 400 may be a three-terminal MLCC.

[0269] FIG. 9 is a cross-sectional view for explaining the step between the 1-2 circuit layer and the pad layer of the bridge substrate in the first embodiment, and FIG. 10 is a diagram for explaining the step between the 1-2 circuit layer and the pad layer of the bridge substrate in the second embodiment.

[0270] Referring to FIG. 9, the bridge substrate 200a in the first embodiment is disposed in the first cavity C1 of the second layer 112 of the first insulating layer 110. As shown in FIG.

[0271] At this time, it may be difficult to accurately match the thickness of the second layer 112 of the first insulating layer 110, which corresponds to the depth of the first cavity C1, with the thickness of the bridge substrate 200a.

[0272] Therefore, in the embodiment, the insulating layer 210 constituting the bridge substrate 200a is made of polyimide (PI), which makes it possible to easily control the thickness of the bridge substrate 200a.

[0273] Therefore, in the embodiment, the height difference H1 between the upper surface of the pad layer of the bridge substrate 200a and the first-second circuit layer 132 can be minimized.

[0274] The pad layer of the bridge substrate 200a may refer to the first circuit layer 220a of the bridge substrate 200a in the first embodiment, and the pad layer of the bridge substrate 200a may refer to the first and second pad layers 250a and 250b protruding on the first circuit layer 220a in the second embodiment.

[0275] For example, an upper surface of the pad layer of the bridge substrate 200a may be located lower than an upper surface of the 1-2 circuit layer 132. For example, an upper surface of the pad layer of the bridge substrate 200a may be located lower than an upper surface of the 1-2 circuit layer 132 by a first height H1.

[0276] In this case, in the embodiment, the first height H1 can be easily controlled compared to a conventional bridge substrate including silicon, and thus the first height H1 can be set to 25 μm or less. For example, in the embodiment, the first height H1 is set to 20 μm or less. For example, in the embodiment, the first height H1 is set to 15 μm or less.

[0277] Preferably, in this embodiment, the first height H1 is smaller than the difference between the thickness of each layer of the first insulating layer 110 and the thickness of the second insulating layer 120.

[0278] At this time, a difference in thickness or height occurs between the first sub-via 143a and the second sub-via 143b of the 1-3 via 143 penetrating the third layer 113 of the first insulating layer 110 by the difference in the first height H1. At this time, the first sub-via 143a and the second sub-via 143b of the 1-3 via 143 are formed by filling the inside of the via hole with a metal material. At this time, if the first height H1 is large, the difference in size between the via hole constituting the first sub-via 143a and the via hole constituting the second sub-via 143b becomes large, and thus a problem may occur in the plating property of the plating layer filling the inside. Then, the reliability of plating property decreases due to the difference in the size of the via holes, and thus the first sub-via 143a and the second sub-via 143b may be misaligned. Then, the misalignment may act as a factor that reduces the reliability of the electrical contact between the circuit board of the embodiment and the bridge board 200a.

[0279] Accordingly, in the embodiment, the insulating layer 210 of the bridge substrate 200a includes polyimide (PI), which facilitates thickness control of the bridge substrate 200a. As a result, in the embodiment, the first height H1 can be minimized, and thus the difference in height or thickness between the first sub-via 143a of the 1-3 via 143 and the second sub-via 200 can be minimized. As a result, in the embodiment, the contact reliability between the circuit board and the bridge substrate 200a can be improved, and further the product reliability can be improved.

[0280] Meanwhile, referring to FIG. 10, the bridge substrate 200b in the second embodiment is disposed in the first cavity C1 of the second layer 112 of the first insulating layer 110. As shown in FIG.

[0281] In the second embodiment, the upper surface of the pad layer of the bridge substrate 200b may be positioned higher than the upper surface of the 1-2 circuit layer 132. For example, the upper surface of the pad layer of the bridge substrate 200b may be positioned higher than the upper surface of the 1-2 circuit layer 132 by a second height H2. In the embodiment, the second height H2 is 25 μm or less, 20 μm or less, or 15 μm or less.

[0282] In the embodiment, the first height H1 and the second height H2 are set to be smaller than the difference between the thickness of each layer of the first insulating layer 110 and the thickness of the second insulating layer 120. Through this, the embodiment can maintain the strength of the circuit board.

[0283] For example, in the case of the first embodiment of Fig. 9, the thickness of the substrate in the area where the bridge substrate is disposed can be secured, thereby improving the rigidity of the substrate, and in the case of the second embodiment of Fig. 10, it is possible to realize a fine circuit in the pad portion in contact with the chip mounting area.

[0284] Moreover, the embodiment can improve chip mountability.

[0285] For example, when the first height H1 and the second height H2 are greater than the difference between the thickness of each layer of the first insulating layer 110 and the thickness of the second insulating layer 120, the height of the top surface of the third layer 113 of the first insulating layer 110 may vary greatly from region to region, which may result in a large difference in height of the mounting pads connected to the chip, which may cause defects when mounting the chip.

[0286] In contrast, in the embodiment, the deviation in height of the top surface of the third layer 113 of the first insulating layer 110 can be reduced, so that mounting defects can be minimized when mounting chips.

[0287] The circuit board of the embodiment includes a first insulating layer and a second insulating layer. The second insulating layer may include a prepreg. Through this, the embodiment may maintain the rigidity of the circuit board and improve warpage characteristics, thereby improving product reliability. Also, the first insulating layer includes ABF. As a result, the embodiment may reduce the size of the circuit layer and vias disposed in the first insulating layer. Specifically, the embodiment may form a fine pattern circuit layer and vias connected to the first processor chip and the second processor chip in the first insulating layer.

[0288] The first insulating layer includes a plurality of layers. A circuit layer and a via are disposed in each of the plurality of layers of the first insulating layer. In this case, the embodiment allows the circuit layer and the via formed in the first insulating layer to be gradually increased as they are adjacent to the second insulating layer. As a result, the embodiment can minimize signal transmission loss between the circuit layer and the via disposed in the first insulating layer and the circuit layer and the via disposed in the second insulating layer. As a result, the embodiment can improve the communication characteristics of the circuit board.

[0289] Also, the circuit board of the embodiment includes a bridge substrate embedded in the first insulating layer. The bridge substrate may be disposed in a first cavity formed in a second layer of the first insulating layer and covered by a third layer of the first insulating layer. In addition, the embodiment may directly connect a pad layer included in the bridge substrate to a via penetrating the first insulating layer. As a result, the embodiment may minimize the signal transmission distance and further minimize the signal transmission loss.

[0290] In addition, the insulating layer of the bridge substrate of the embodiment has a CTE similar to that of the first insulating layer. Furthermore, the insulating layer of the bridge substrate of the embodiment has a flexible characteristic. Specifically, the insulating layer of the bridge substrate can include polyimide (PI), which is an organic material. As a result, the embodiment can reduce the product unit cost compared to a conventional bridge substrate including silicon.

[0291] Further, the bridge substrate of the embodiment includes a pad layer. The pad layer is directly connected to a first via disposed in the first insulating layer. At this time, an alignment state between the pad layer of the bridge substrate and the first via has a significant effect on the product reliability of the circuit board and the semiconductor package. At this time, in the embodiment, transparent polyimide is applied as the insulating layer of the bridge substrate. As a result, the embodiment can improve the alignment between the pad layer of the bridge substrate and the first via disposed in the first insulating layer. As a result, the embodiment can improve the overall product reliability.

[0292] Furthermore, the embodiment can stably protect the bridge substrate from stresses that occur when the circuit substrate is thermally deformed.

[0293] That is, the insulating layer of the bridge substrate conventionally contains silicon. As a result, the conventional bridge substrate has rigid properties due to the silicon. As a result, in the conventional bridge substrate, stress generated when the circuit substrate is thermally deformed is directly transmitted to the bridge substrate. As a result, the conventional bridge substrate has reliability problems such as cracks.

[0294] In contrast, the insulating layer of the bridge substrate in the embodiment includes polyimide. This allows the bridge substrate to flow together with the first insulating layer when the circuit board is thermally deformed. This improves the physical and electrical reliability of the bridge substrate in the embodiment.

[0295] Furthermore, the embodiment allows the thickness of the bridge substrate to be easily adjusted. For example, in a conventional bridge substrate including silicon, a process of polishing a silicon substrate is required to adjust the thickness of the bridge substrate, and due to the difficulty of the process, it is difficult to adjust the thickness of the bridge substrate to a desired thickness.

[0296] In contrast, the embodiment can easily adjust the total thickness of the bridge substrate, and thus the thickness of the bridge substrate can be easily adjusted in response to the depth of the cavity formed in the first insulating layer. As a result, the embodiment can minimize the difference in thickness between the first sub-via that directly contacts the bridge substrate and the other sub-vias. As a result, the embodiment can improve the overall physical reliability and electrical reliability of the circuit board.

[0297] A method for manufacturing a circuit board according to an embodiment will be described below.

[0298] 11 to 25 are diagrams for explaining the process of the circuit board of FIG. 2 in order.

[0299] 11, an embodiment may perform a process of manufacturing an inner layer of a circuit board. To this end, the embodiment may prepare a second insulating layer 120. Then, the embodiment may form a via hole penetrating the prepared second insulating layer 120. Then, the embodiment may form a second via 144 filling the via hole of the second insulating layer 120. Also, the embodiment may perform a process of forming second circuit layers 134 and 135 on the upper and lower surfaces of the second insulating layer 120, respectively.

[0300] 12, in an embodiment, a process may be performed to form a second cavity C2 and a third cavity C3 in the second insulating layer 120. The second cavity C2 and the third cavity C3 may penetrate an upper surface and a lower surface of the second insulating layer 120, respectively. The second cavity C2 and the third cavity C3 may be formed in the second insulating layer 120 to be spaced apart in the horizontal direction.

[0301] 13, in an embodiment, a process of disposing a carrier board on the lower surface of the second insulating layer 120 may be performed. The carrier board may include a carrier insulating layer CB1 and a carrier adhesive layer CB2.

[0302] 14, in an embodiment, a process of mounting a first element 300 in the second cavity C2 of the second insulating layer 120 may be performed using the carrier adhesive layer CB2 of the carrier board. In addition, in an embodiment, a process of mounting a second element 400 in the third cavity C3 of the second insulating layer 120 may be performed using the carrier adhesive layer CB2 of the carrier board.

[0303] 15, in the embodiment, a process of stacking a first layer 111 of the first insulating layer 110 on the second insulating layer 120 may be performed. At this time, at least a portion of the first layer 111 of the first insulating layer 110 may be located in the second cavity C2 and the third cavity C3 of the second insulating layer 120. For example, the first layer 111 of the first insulating layer 110 may be disposed to cover the first element 300 disposed in the second cavity C2. Also, the first layer 111 of the first insulating layer 110 may be disposed to cover the second element 400 disposed in the third cavity C3.

[0304] 16 , in an embodiment, a process of removing the carrier board disposed on the lower surface of the second insulating layer 120 may be performed. As a result, the lower surface of the second insulating layer 120, the lower surface of the second circuit layer 135, the lower surface of the first element 300, and the lower surface of the second element 400 may be exposed.

[0305] Referring to FIG. 17, in this embodiment, a process of laminating a first layer 122 of a third insulating layer 121 on a lower surface of the second insulating layer 120 may be performed.

[0306] Referring to FIG. 18, an embodiment may perform a process of forming a 1-1 via 141 penetrating the first layer 111 of the first insulating layer 110 and a 1-1 circuit layer 131 on the upper surface of the first layer 111 of the first insulating layer 110.

[0307] In addition, in the embodiment, a process of forming a 3-1 via 145 penetrating the first layer 122 of the third insulating layer 121 and a 3-1 circuit layer 136 on the lower surface of the first layer 122 of the third insulating layer 121 may be performed.

[0308] 19, in the embodiment, a process of laminating a second layer 112 of the first insulating layer 110 on a first layer 111 of the first insulating layer 110 may be performed. In addition, in the embodiment, a process of laminating a second layer 123 of the third insulating layer 121 under a first layer 122 of the third insulating layer 121 may be performed.

[0309] Referring to FIG. 20, an embodiment may include a process of forming a 1-2 via 142 penetrating the second layer 112 of the first insulating layer 110 and a 1-2 circuit layer 132 on the upper surface of the second layer 112 of the first insulating layer 110.

[0310] In addition, in the embodiment, a process of forming a 3-2 via 146 penetrating the second layer 123 of the third insulating layer 121 and a 3-2 circuit layer 137 on the lower surface of the second layer 123 of the third insulating layer 121 may be performed.

[0311] In this embodiment, when forming a via hole corresponding to the 1-2 via 142, a process of forming a first cavity C1 at a position corresponding to the pad portion 131a of the 1-1 circuit layer 131 may be performed.

[0312] Referring to FIG. 21, in this embodiment, a process of disposing an adhesive layer 500 on the pad portion 131a exposed through the first cavity C1 may be performed.

[0313] Referring to FIG. 22, an embodiment may perform a process of attaching a bridge substrate 200 onto the adhesive layer 500.

[0314] 23 , in the embodiment, a process of forming a third layer 113 of the first insulating layer 110 on the second layer 112 of the first insulating layer 110 may be performed. The third layer 113 of the first insulating layer 110 may be formed by filling a first cavity C1 formed in the second layer 112 of the first insulating layer 110. Thus, the bridge substrate 200 disposed in the first cavity C1 may be covered by the third layer 113 of the first insulating layer 110. Thus, the bridge substrate 200 may be embedded in the first insulating layer 110.

[0315] In addition, in the embodiment, a process of forming a third layer 124 of the third insulating layer 121 under the second layer 123 of the third insulating layer 121 may be performed.

[0316] Referring to FIG. 24, an embodiment may include a process of forming a 1-3 via 143 penetrating the third layer 113 of the first insulating layer 110 and a 1-3 circuit layer 133 on the upper surface of the third layer 113 of the first insulating layer 110.

[0317] In addition, in this embodiment, a process of forming a 3-3 via 147 penetrating the third layer 124 of the third insulating layer 121 and a 3-3 circuit layer 138 on the lower surface of the third layer 124 of the third insulating layer 121 may be performed.

[0318] Referring to FIG. 25, in this embodiment, a process of forming a first protective layer 151 on the third layer 113 of the first insulating layer 110 may be performed.

[0319] In addition, in the embodiment, a process of forming a second protective layer 152 under the third layer 124 of the third insulating layer 121 may be performed.

[0320] FIG. 26 is a diagram showing a semiconductor package according to the first embodiment.

[0321] Referring to FIG. 26, in an embodiment, a structure may be provided in which multiple chips are mounted on the circuit board of FIG.

[0322] To this end, the circuit board includes a first pad and a second pad. The first pad may be a part of a 1-3 circuit layer 133 disposed on the uppermost side of the first circuit layers of the circuit board. For example, the first pad may be a circuit layer of the 1-3 circuit layer 133 that overlaps with a first opening of a first protective layer 151 in the thickness direction. Also, the second pad may be a circuit layer of the -3 circuit layer 133 that overlaps with a second opening of the protective layer 151 in the thickness direction.

[0323] The semiconductor package may include a first adhesive part 610 disposed on a first pad of the circuit board, and a second adhesive part 640 disposed on a second pad.

[0324] The first adhesive portion 610 and the second adhesive portion 640 may have the same shape, or may have different shapes.

[0325] For example, the first adhesive portion 610 and the second adhesive portion 640 may have a hexahedral shape. For example, the cross section of the first adhesive portion 610 and the second adhesive portion 640 may include a quadrilateral shape. The cross section of the first adhesive portion 610 and the second adhesive portion 640 may include a rectangular or square shape. For example, the first adhesive portion 610 and the second adhesive portion 640 may include a spherical shape. For example, the cross section of the first adhesive portion 610 and the second adhesive portion 640 may include a circular or semicircular shape. For example, the cross section of the first adhesive portion 610 and the second adhesive portion 640 may include a partially or entirely rounded shape. The cross section of the first adhesive portion 610 and the second adhesive portion 640 may be flat on one side and curved on the other side. The first adhesive portion 610 and the second adhesive portion 640 may be, but is not limited to, a solder ball.

[0326] In an embodiment, the semiconductor device may include a first chip 620 disposed on the first adhesive portion 610. The first chip 620 may be a first processor chip. For example, the first chip 620 may be an application processor (AP) chip among a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, and a microcontroller. A terminal 625 of the first chip 620 may be electrically connected to the first pad via the first adhesive portion 610.

[0327] In addition, in an embodiment, the first chip 620 may include a second chip 650 disposed on the second adhesive part 640. The second chip 650 may be a second processor chip. For example, the second chip 650 may be an application processor (AP) chip of a different type from the first chip 620, among a central processor (e.g., CPU), a graphic processor (e.g., GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller. A terminal 655 of the second chip 650 may be electrically connected to the second pad via the second adhesive part 640.

[0328] As an example, the first chip 620 may be a central processor chip, and the second chip 650 may be a graphic processor chip, but is not limited thereto.

[0329] Meanwhile, the first chip 620 and the second chip 650 may be arranged on the circuit board with a first gap therebetween. The first gap may be 150 μm or less. For example, the first gap may be 120 μm or less. For example, the first gap may be 100 μm or less.

[0330] Preferably, the first separation width may be in the range of 60 μm to 150 μm. Preferably, the first separation width may be in the range of 70 μm to 120 μm. Preferably, the first separation width may be in the range of 80 μm to 110 μm. If the first separation width is smaller than 60 μm, interference between the first chip 620 and the second chip 650 may cause a problem in the reliability of the operation of the first chip 620 or the second chip 650. If the first separation width is smaller than 60 μm, the bridge substrate 200 may not be disposed in a region corresponding to the first cavity C1 that overlaps in the thickness direction with a space corresponding to the first separation width. If the first separation width is larger than 150 μm, the distance between the first chip 620 and the second chip 650 may be increased, thereby increasing signal transmission loss. If the first gap is greater than 150 μm, the volume of the bridge substrate 200 may become large, which may further increase the volume of the semiconductor package.

[0331] The semiconductor package may include a molding layer 630. The molding layer 630 may be disposed to cover the first chip 620 and the second chip 650. For example, the molding layer 630 may be, but is not limited to, an epoxy mold compound (EMC) formed to protect the mounted first chip 620 and second chip 650.

[0332] At this time, the molding layer 630 may have a low dielectric constant to enhance heat dissipation characteristics. For example, the dielectric constant (Dk) of the molding layer 630 may be 0.2 to 10. For example, the dielectric constant (Dk) of the molding layer 630 may be 0.5 to 8. For example, the dielectric constant (Dk) of the molding layer 630 may be 0.8 to 5. Thus, in an embodiment, the molding layer 630 has a low dielectric constant, thereby enhancing heat dissipation characteristics with respect to heat generated in the first chip 620 and / or the second chip 650.

[0333] Meanwhile, the semiconductor package may include a third adhesive portion 660 disposed on the lowermost side of the circuit board. The third adhesive portion 660 may be disposed on the lower surface of the 3-3 circuit layer 138 exposed through the opening of the second protective layer 152.

[0334] FIG. 27 is a diagram showing a semiconductor package according to the second embodiment.

[0335] Referring to FIG. 27, the semiconductor package according to the second embodiment further includes a memory chip mounting unit compared to the semiconductor package according to the first embodiment.

[0336] Specifically, the semiconductor package includes a memory chip 670 disposed side by side with the first chip 620 or the second chip 650 at a certain distance from the first chip 620 or the second chip 650. In this case, the memory chip 670 may have a multi-layer structure with an adhesive layer 672 sandwiched therebetween. The semiconductor package may also include a connecting member 674 connected to the memory chip 670. The connecting member 674 may be, but is not limited to, a wire.

[0337] Meanwhile, the semiconductor package according to the third embodiment may further include a second package disposed on the semiconductor package according to the first embodiment. The second package may be a memory package including a memory chip.

[0338] For this purpose, a memory package including an interposer may be disposed on the semiconductor package of the first embodiment. Alternatively, a memory package may be disposed directly on the semiconductor package of the first embodiment.

[0339] The features, structures, effects, etc. described in the above-mentioned embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person having ordinary skill in the art to which the embodiment belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiment.

[0340] In addition, although the above description focuses on the embodiments, these are merely illustrative and do not limit the embodiments, and a person having ordinary skill in the art to which the embodiments pertain will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be interpreted as being included in the scope of the embodiments defined in the appended claims.

Claims

1. A circuit board; a connecting member embedded in the circuit board; The circuit board includes a first insulating layer that does not include a strength member; the connecting member is embedded in the first insulating layer of the circuit board; The connecting member includes a second insulating layer including an organic material. Semiconductor package.

2. the first insulating layer includes a first layer, a second layer disposed on the first layer and having a cavity, and a third layer filling the cavity and disposed on the second layer; The semiconductor package of claim 1 , wherein the connecting member is disposed within the cavity.

3. The semiconductor package of claim 1 , wherein the second insulating layer of the connecting member comprises polyimide.

4. The circuit board further includes a third insulating layer disposed below the first insulating layer. The semiconductor package of claim 1 , wherein the third insulating layer comprises a different insulating material than the first insulating layer.

5. The semiconductor package of claim 4 , wherein the third insulating layer comprises a strength member.

6. the circuit board further includes a fourth insulating layer disposed below the third insulating layer; The semiconductor package of claim 4 , wherein the fourth insulating layer comprises the same insulating material as the first insulating layer.

7. the third insulating layer has a through hole; The semiconductor package according to claim 4 , further comprising a semiconductor element disposed in the through hole.

8. The semiconductor package according to claim 7 , wherein the first insulating layer fills the through hole and is disposed to cover the semiconductor element.

9. The through holes are provided in the third insulating layer and spaced apart from each other in a horizontal direction, The semiconductor package according to claim 7 , wherein the semiconductor elements are disposed in the plurality of through holes, respectively.

10. The semiconductor package of claim 9 , wherein the plurality of through holes do not overlap the connecting member in a vertical direction.

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