Hard Mask for High Aspect Ratio Dielectric Etching at Ultra-Low Temperatures and during Temperature Rise

Abstract

Various embodiments of the present specification relate to a method, apparatus, and system for etching high aspect ratio features in a dielectric material. The dielectric material is etched using a multi-layer or graded hard mask having at least two different compositions. Different etching conditions are used while different portions of the hard mask are exposed. For example, while the upper portion of the hard mask is exposed, the feature may be etched to a first depth at a first temperature, and then while the lower portion of the hard mask is exposed, the feature may be etched to a final depth at a second temperature higher than the first temperature.

Description

Technical Field

[0001] Incorporation by Reference: As part of this application, a PCT application form is filed simultaneously with this specification. Each application specified in the simultaneously filed PCT application form and for which this application claims benefit or priority is hereby incorporated by reference in its entirety for all purposes into this specification.

Background Art

[0002] One of the processes frequently employed during the manufacture of semiconductor devices is a process of etching a dielectric material to form concave features therein. Examples of situations where such a process is performed include, but are not limited to, memory applications such as DRAM and 3D NAND structures. With the progress of the semiconductor industry and the reduction of device dimensions, etching such features has become increasingly difficult.

[0003] The description of the background art provided herein is intended to generally present the content of the present disclosure. Research by the inventors named at the present time within the scope described in this background art section, as well as aspects of the description that cannot be separately regarded as prior art at the time of filing the application, are not recognized as prior art against the present disclosure, whether explicitly or implicitly.

Summary of the Invention

[0004] Various embodiments of this specification relate to a method, apparatus, and system for etching features into a substrate. The substrate is typically a semiconductor substrate, and the features are etched into a dielectric material.

[0005] In one aspect of an embodiment of the present disclosure, a method of etching features into a substrate is provided. The method includes receiving a substrate within a process chamber, the substrate including a dielectric material and a hard mask including an upper portion and a lower portion, the upper portion including carbon, the lower portion including at least one material selected from the group consisting of doped carbon, silicon, metal, metal-containing material, and combinations thereof, the upper and lower portions of the hard mask having different compositions, the hard mask being patterned to define a location where the feature is to be etched into the dielectric material, the hard mask being positioned above the dielectric material, etching the feature into the substrate to a first depth while the substrate is at a first temperature and the upper portion of the hard mask is exposed, and etching the feature to a final depth while the substrate is at a second temperature higher than the first temperature and the lower portion of the hard mask is exposed.

[0006] Certain temperatures may be used in various embodiments. In some cases, the first temperature is between about -100 °C and about 0 °C, and the second temperature is between about 0 °C and about 100 °C. In some such cases, the first temperature is between about -60 °C and about -20 °C, and the second temperature is between about 20 °C and about 60 °C.

[0007] The hard mask may include a material having a specific composition. For example, in some embodiments, the lower portion of the hard mask includes one or more metals selected from the group consisting of aluminum, boron, chromium, cobalt, hafnium, molybdenum, niobium, ruthenium, tantalum, titanium, tungsten, vanadium, zirconium, and combinations thereof. In various embodiments, the lower portion of the hard mask has a composition that is at least about 5 at% metal.

[0008] The method may include one or more additional steps. For example, the method may further include exposing the substrate to an oxygen-containing plasma to ashing any remaining upper portion of the hard mask after etching the feature into the substrate to a first depth and before etching the feature to a final depth. In these or other embodiments, the method may further include depositing a liner on the sidewalls of the feature after etching the feature into the substrate to a first depth and before etching the feature to a final depth. In these or other embodiments, the method may further include depositing additional mask material on the hard mask after etching the feature into the substrate to a first depth and before etching the feature to a final depth.

[0009] The hard mask may include a plurality of distinct layers or may be graded. In some embodiments, the upper and lower portions of the hard mask are distinct layers. In other embodiments, the hard mask has a graded composition such that the composition of the upper portion of the hard mask transitions gradually to the composition of the lower portion of the hard mask.

[0010] In another aspect of embodiments of the present disclosure, an apparatus for etching a substrate is provided. The apparatus includes a process chamber, a substrate support configured to support a substrate within the process chamber, an inlet to the process chamber for introducing one or more reactants into the process chamber, an outlet of the process chamber for removing material from the process chamber, and a controller including a memory and a processor. The controller is configured to receive a substrate within the process chamber, the substrate including a dielectric material and a hard mask including an upper portion and a lower portion, the upper portion including carbon, the lower portion including at least one material selected from the group consisting of doped carbon, silicon, metal, metal-containing material, and combinations thereof, the upper and lower portions of the hard mask having different compositions, the hard mask being patterned to define locations where features are etched into the dielectric material, the hard mask being positioned above the dielectric material, and configured to etch the features into the substrate to a first depth while the substrate is at a first temperature and the upper portion of the hard mask is exposed, and to etch the features to a final depth while the substrate is at a second temperature higher than the first temperature and the lower portion of the hard mask is exposed.

[0011] The controller may be configured to etch under specific process conditions. For example, in some embodiments, the first temperature is between about -100°C and about 0°C, and the second temperature is between about 0°C and about 100°C. In some such embodiments, the first temperature is between about -60°C and about -20°C, and the second temperature is between about 20°C and about 60°C.

[0012] The hard mask may include a material having a specific composition. In some embodiments, the lower portion of the hard mask includes one or more metals selected from the group consisting of aluminum, boron, chromium, cobalt, hafnium, molybdenum, niobium, ruthenium, tantalum, titanium, tungsten, vanadium, zirconium, and combinations thereof. In some such embodiments, the lower portion of the hard mask has a composition that is at least about 5 at% metal.

[0013] The controller may be further configured to cause additional operations. For example, in some embodiments, the controller is further configured to expose the substrate to an oxygen-containing plasma and ashing any remaining upper portion of the hard mask after etching the feature into the substrate to a first depth and before etching the feature to a final depth. In these or other embodiments, the controller may be further configured to deposit a liner on the sidewalls of the feature after etching the feature into the substrate to a first depth and before etching the feature to a final depth. In these or other embodiments, the controller may be further configured to deposit additional mask material on the hard mask after etching the feature into the substrate to a first depth and before etching the feature to a final depth.

[0014] The hard mask may include a plurality of distinct layers or may be graded. In some embodiments, the upper and lower portions of the hard mask are distinct layers. In other embodiments, the hard mask may have a graded composition such that the composition of the upper portion of the hard mask transitions gradually to the composition of the lower portion of the hard mask.

[0015] These and other aspects are described in further detail below with reference to the drawings.

Brief Description of the Drawings

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[0029] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. Embodiments of the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure embodiments of the present disclosure. Embodiments of the present disclosure are described in conjunction with specific embodiments, but it is understood that the embodiments of the present disclosure are not intended to be limiting. Summary and Use

[0030] In various embodiments of the present specification, features are etched into a substrate (usually a semiconductor wafer) having a dielectric material on its surface. The etching process is generally a plasma-based etching process such as a reactive ion etching process. The feature is a recess in the surface of the substrate. The feature can have many different shapes, such as cylinders, ellipses, rectangles, squares, other polygonal recesses, grooves, etc., but is not limited thereto.

[0031] The aspect ratio is a comparison of the depth of the feature to the critical dimension of the feature (often its width / diameter). For example, a cylinder with a depth of 2 μm and a width of 50 nm has an aspect ratio of 40:1 and is often more simply denoted as 40. As used herein, unless otherwise specified, the aspect ratio is measured based on the critical dimension proximate to the opening of the feature.

[0032] The features formed by the methods of the present disclosure may be high aspect ratio features. In some applications, a high aspect ratio feature is a feature having an aspect ratio of at least about 5, at least about 10, at least about 20, at least about 30, at least about 40, at least about 50, at least about 60, at least about 80, or at least about 100. The critical dimension of the features formed by the methods of the present disclosure may be, for example, about 200 nm or less, about 100 nm or less, about 50 nm or less, or about 20 nm or less.

[0033] The material into which the features are etched may, in various cases, be a dielectric material. Examples of materials include silicon oxide, silicon nitride, silicon carbide, oxynitride, oxycarbide, carbonitride, doped versions of these materials (e.g., doped with boron, phosphorus, etc.), and laminates of any combination of these materials, but are not limited thereto. Specific exemplary materials include SiO 2Examples include stoichiometric and non-stoichiometric compounds such as SiN, SiON, SiOC, and SiCN. In various embodiments, the material in which the feature is etched includes a stack of alternating materials such as silicon oxide and silicon nitride. One or more of the materials to be etched may include other elements, for example, hydrogen in various cases. In some embodiments, the nitride material and / or oxide material being etched has a composition that includes hydrogen. As used herein, silicon oxide materials, silicon nitride materials, etc. include both stoichiometric and non-stoichiometric versions of such materials, and it is understood that such materials may have other elements as described above.

[0034] One use of the method of the present disclosure is related to the formation of DRAM devices. In this case, the feature may be etched primarily into silicon oxide. Also, the substrate may include, for example, one, two, or more layers of silicon nitride. In one example, the substrate includes a silicon oxide layer sandwiched between two layers of silicon nitride, the silicon oxide layer having a thickness between about 800 and 200 nm, and one or more of the silicon nitride layers having a thickness between about 300 and 400 nm. The etched feature may be a cylinder having a final depth between about 1 and 3 μm, for example, between about 1.5 and 2 μm. The cylinder may have a width between about 20 and 50 nm, for example, between about 25 and 30 nm. After the cylinder is etched, a capacitor memory cell may be formed therein.

[0035] Another use of the method of the present disclosure is related to the formation of vertical NAND (also referred to as VNAND or 3D NAND) devices. In this case, the material in which the feature is etched may have a repeating layered structure. For example, the material may be an alternating layer of oxide (e.g., SiO 2 ) and nitride (e.g., SiN), or an alternating layer of oxide (e.g., SiO 2) may include alternating layers of [material] and polysilicon. The alternating layers form pairs of materials. In some cases, the number of pairs may be at least about 20, at least about 30, at least about 40, at least about 60, or at least about 70. The oxide layer may have a thickness between about 20 and 50 nm, for example, between about 30 and 40 nm. The nitride layer or polysilicon layer may have a thickness between about 20 and 50 nm, for example, between about 30 and 40 nm. Features etched within the alternating layers may have a depth between about 2 and 8 μm, for example, between about 3 and 5 μm. The features may have a width between about 50 and 150 nm, for example, between about 50 and 100 nm. Problem

[0036] There are multiple problems that can occur when etching concave features. These problems include, for example, non-vertical etching profiles, warping, twisting, ellipticity, and selectivity. In many etching applications, concave features are etched more extensively near the top of the feature compared to the bottom of the feature. This non-vertical etching profile (e.g., a feature with slanted sidewalls) is at least undesirable because it limits the ways in which adjacent features can be placed in close proximity without compromising the integrity of the semiconductor device.

[0037] In various etching applications, concave features are etched more extensively near the middle of the feature compared to the top and bottom of the feature. As a result, warping occurs near the middle of the feature where it is widest. Similar to the non-vertical etching profile described above, such warping is at least undesirable because it limits the ways in which features can be positioned adjacent to and close to each other without compromising the integrity of the semiconductor device.

[0038] Twist is another problem that can occur during etching. Twist refers to a feature that shifts from its intended position as it is further etched into the dielectric material. Another factor to consider during etching is the ellipticity. Ellipticity relates to the shape of the concave feature. In many cases, the concave feature is cylindrical. The cross-sectional shape of such a feature is circular when viewed from above. During etching, this circle may distort into an ellipse with a major axis and a minor axis. Ellipticity is a measure for comparing the major axis and the minor axis (e.g., ellipticity = (B - A) / B, where A is the length of the minor axis and B is the length of the major axis), and provides a measurement of the ellipticity with respect to the circularity of the feature. An ellipticity of 0 means that the feature has a perfectly circular cross-section, which is desirable.

[0039] Another important issue related to etching is selectivity. Selectivity relates to the degree to which an etching process removes a first material relative to a second material. Typically, the dielectric material being etched is positioned between a lower layer (e.g., an etch stop layer or another type of layer) and an upper mask layer. The mask layer is patterned by photolithography and related processes, and defines where features are formed in the dielectric material. A high selectivity between the mask layer and the dielectric material allows features to be etched deeply into the dielectric material. In contrast, if the selectivity between the mask layer and the dielectric material is not high enough, the mask layer may be removed by etching before the features reach the desired depth within the dielectric material. Another type of selectivity to consider is the selectivity between the dielectric material and the lower layer material. It is desirable to have a high selectivity between these materials to ensure that the dielectric material can be completely removed without significantly removing the lower layer material.

[0040] To address these challenges, various etching strategies have been developed. Often, the strategies employed to address the first challenge will perform poorly with respect to the second challenge. Therefore, it can be difficult to design a process that appropriately balances all of the related issues. Method

[0041] One strategy that can be used to address the above problems is to combine two different etching techniques to form features in a dielectric material. In various embodiments herein, the etching is performed through a two-step process that includes (1) a first reactive ion etching process performed at an extremely low etching temperature and (2) a second reactive ion etching process performed at a conventional etching temperature. The first etching process may be used to etch most of the feature depth. The second etching process may be used to etch the remaining portion of the feature. A multilayer hard mask is provided above the dielectric material being etched. The multilayer hard mask includes (1) an upper layer designed to be used during the first reactive ion etching process performed at an extremely low temperature and (2) a lower layer designed to be used during the second reactive ion etching process performed at a conventional temperature. Examples of the materials for each layer of the multilayer hard mask are described below. By using the multilayer hard mask, each part of the etching process can be optimized and better etching performance can be achieved.

[0042] As used herein, the term "conventional etching" is intended to refer to a reactive ion etching process performed at a conventional temperature that is not an extremely low temperature. The extremely low temperature etching process may be performed at a temperature between about -100°C and about 0°C. The conventional etching process may be performed at a temperature between about 0°C and about 100°C. More detailed temperature ranges are described below.

[0043] Figures 1A and 1B show available high aspect ratio features and different etching mechanisms. Figure 1A shows an etching process at extremely low temperature, and Figure 1B shows an etching process at conventional temperature. Each of Figures 1A and 1B shows a substrate having a feature formed in a dielectric material 101. The feature is formed in an opening in a mask 102. As shown in Figure 1A, in many cases where etching is performed at extremely low temperature, the etching depends on the transfer of fluorine neutral species to the bottom of the feature, which is caused by the surface diffusion of physically adsorbed molecules containing fluorine 103. Activation is caused by ion bombardment. In contrast, as shown in Figure 1B, in many cases where etching is performed at conventional temperature, x F y etching is performed by chemical sputtering by ions 104.

[0044] Figures 2A and 2B show the mechanisms available for etching various mask materials when etching at either extremely low temperature (Figure 2A) or conventional temperature (Figure 2B). Each of Figures 2A and 2B shows four substrates, each having a different material used for the mask layer. The first mask layer 201 is silicon oxide (e.g., SiO 2 ), the second mask layer 202 is silicon nitride (e.g., Si 3 N 4 ), the third mask layer 203 is carbon (e.g., amorphous carbon), and the fourth mask layer 204 is a metal (e.g., boron, tungsten, molybdenum, etc.). As shown in Figure 2A, when etching is performed at extremely low temperature, when the substrate is exposed to the etching reactants and plasma, a thin fluorinated layer 205 grows on the surfaces of the mask layers 201 to 204. The fluorinated layer 205 may be about 1 nm thick. The etching rate of the mask is promoted by the chemical intermolecular bonds between the fluoride in the etching reactants and the materials of the mask layers 201 to 204. In this example, the etching reactants are CH 2 F 2 , H 2 , NF 3 , Cl 2and a mixture of HBr. However, as will be further described below, in various embodiments, other chemicals and combinations of chemicals may be used.

[0045] As shown in FIG. 2B, when etching is performed at a conventional temperature, when the substrate is exposed to the etching reactant and plasma, C is formed on the surfaces of the mask layers 201 to 204. x F y salvage layer 206 grows. C x F y The salvage layer 206 may have a thickness of about 5 to 10 nm, which is substantially thicker than the fluorinated layer 205 formed when etching at extremely low temperatures. The etching rate of the mask in this example is carbon consumption (e.g., C x F y inside the salvage layer 206) and C x F y promoted by diffusion by the salvage layer 206. In this example, the etching reactant is C 4 F 8 、C 4 F 6 、and O 2 and a mixture of. However, as will be further described below, in various embodiments, other chemicals and combinations of chemicals may be used.

[0046] Due to the etching mechanisms described in FIGS. 1A - 1B and FIGS. 2A - 2B, different performance advantages and disadvantages are brought about for each mechanism. For example, the cryogenic etching method described in relation to FIGS. 1A and 2A provides relatively fast etching with excellent profile control, high selectivity between the dielectric material and the mask material, low ellipticity, low twist, and low warp. Due to these factors, cryogenic etching is well - suited for etching most of the feature depth. On the other hand, the conventional etching method described in relation to FIGS. 1B and 2B provides excellent selectivity performance with respect to etching the underlying material with respect to the dielectric material. Due to this factor, conventional etching is well - suited for etching to the final depth of the feature after partially etching the feature at cryogenic temperature (e.g., to a first depth).

[0047] As described above, in the embodiments of this specification, a multi - layer hard mask is used. The hard mask includes an upper layer used during etching at cryogenic temperature and a lower layer used during etching at conventional temperature. The upper layer of the hard mask may be substantially consumed during etching at cryogenic temperature, thereby exposing the lower layer of the hard mask. By using a multi - layer hard mask, each layer of the hard mask can be optimized according to the type of etching process used while that particular layer of the hard mask is exposed. Thereby, high - speed and high - quality etching results can be achieved while minimizing material costs and operating costs. For example, the required mask thickness may be thinner than the thickness required for a single homogeneous mask layer, thus minimizing material costs. Similarly, since features can be etched quickly, only less energy is required compared to slower methods, and higher throughput can be achieved, thus also minimizing operating costs.

[0048] To maximize the advantages of the embodiments of the present disclosure, the materials of the upper and lower layers of the multilayer hard mask may be selected to optimize each part of the etching process. Generally, the upper layer of the multilayer hard mask is carbon (e.g., amorphous carbon), and the lower layer of the multilayer hard mask is a different material such as doped carbon, silicon, metal, or a metal-containing material (e.g., metal oxide, metal nitride, metal silicide, metal carbide, metal alloy, etc.). These materials will be further described below.

[0049] Figures 3A - 3D show the etching mechanisms that can occur during reactive ion etching using different etching temperature situations and different types of mask layers. Figure 3A shows etching at extremely low temperature using a carbon mask 302, Figure 3B shows etching at extremely low temperature using a doped carbon mask 303, Figure 3C shows etching at a conventional temperature using a carbon mask 302, and Figure 3D shows etching at a conventional temperature using a doped carbon mask 303. When using the doped carbon mask 303, the carbon is doped with a metal. In Figures 3B and 3D, only the metal in the mask layer is shown (e.g., carbon in the mask layer is excluded), but it is understood that this metal may be provided in a form mixed with doped carbon or other related metal(s).

[0050] Each of Figures 3A - 3D shows a substrate having features formed in a layer of a dielectric material 301. The location of the features is defined by an opening in a mask layer (e.g., carbon mask 302 or doped carbon mask 303). As shown in Figure 3A, when etching is performed at an extremely low temperature using a carbon mask 302, a sidewall film 310 is formed on the sidewalls of the features. The sidewall film 310 is an ammonium fluoride film containing silicon and can protect the sidewalls from being over-etched. Thereby, a vertical etching profile with slight warping, tilt, twist, and ellipticity is obtained. These results are highly desirable. As previously described in connection with Figure 2A, during etching at an extremely low temperature, a thin fluorinated layer 305 is formed on the surface of the carbon mask 302.

[0051] As shown in FIG. 3B, when etching is performed at an extremely low temperature using a doped carbon mask 303, a sidewall film 311 is formed on the sidewalls of the feature. The sidewall film 311 is a silicon-containing ammonium fluoride film having metal and / or metal fluoride therein. The metal can originate from the doped carbon mask 303. The metal originating from the doped carbon mask 303 in the sidewall film 311 may form a non-vertical, tapered etching profile. These results are not ideal. As previously described in connection with FIG. 2A, during extremely low temperature etching, a thin fluorinated layer 305 is formed on the surface of the carbon doped mask 303.

[0052] As shown in FIG. 3C, when etching is performed at a conventional temperature using a carbon mask 302, a sidewall film 312 is formed on the sidewalls of the feature. The sidewall film 312 is a C x F y salvage layer 306 and the same C x F y film. This sidewall film 312 is deposited in a non-conformal manner, and the deposition may be thicker near the top of the feature and may be little or no deposition near the bottom of the feature. This can lead to the formation of warping and other undesirable etching profile characteristics.

[0053] As shown in FIG. 3D, when etching is performed at a conventional temperature using a doped carbon mask 303, a sidewall film 313 is formed on the sidewalls of the feature. The sidewall film 313 is a C x F y film and may partially contain metal and / or metal fluoride. The metal in the sidewall film can originate from the metal in the doped carbon mask 303. During etching at a conventional temperature, as described above in connection with FIG. 2B, on the doped carbon mask 303, C x F yA salvage layer 306 may be formed. Similar to the mechanism shown in FIG. 3C, the mechanism shown in FIG. 3D forms the sidewall film 313 in a non-conformal manner, which may result in the formation of warping, twisting, and other undesirable etching profile characteristics. Generally, the sidewall film 313 formed during etching at conventional temperatures has a lower metal content than the sidewall film 311 formed during etching at cryogenic temperatures. Therefore, a tapered profile is less likely to be formed with the sidewall film 313 compared to the sidewall film 311.

[0054] Since the etching mechanisms at conventional temperatures shown in FIGS. 3C and 3D often lead to undesirable etching profiles, these techniques should not be used for etching most of the feature depth. Instead, use the techniques described in connection with FIG. 3A, including cryogenic etching using a carbon mask, to etch most of the feature depth. The final portion of the feature depth can be etched using the mechanism shown in FIG. 3D, which offers a distinct advantage in terms of selectivity (especially the selectivity to the underlying layer located directly beneath the dielectric material).

[0055] FIG. 4 is a flowchart related to a method of etching features according to various embodiments of the present specification into a dielectric material. The method of FIG. 4 is described in relation to FIGS. 5A-5C, which show a semiconductor substrate undergoing the various processing operations of FIG. 4. The method of FIG. 4 begins at operation 401, where a substrate is received within a process chamber. As shown in FIG. 5A, the substrate includes one or more layers of a dielectric material 501 into which features are to be etched. Below the dielectric material 501 is an etch stop layer 508. Above the dielectric material 501 is a patterned multilayer hard mask 520 that includes an upper layer 520a and a lower layer 520b. The upper layer 520a of the multilayer hard mask 520 is carbon (e.g., amorphous carbon). The upper layer 520a may have a specific thickness in various embodiments. For example, the upper layer 520a may have a thickness of at least about 1500 nm, or about 1250 nm, or about 1000 nm. In these or other embodiments, the upper layer 520a may have a thickness of at most about 2500 nm, or about 3000 nm, or about 3500 nm.

[0056] The lower layer 520b of the multilayer hard mask 520 is a material such as doped carbon, silicon, metal, or a metal-containing material (e.g., metal oxide, metal nitride, metal silicide, metal carbide, metal alloy, etc.). Examples of metals and other materials for the lower layer 520b are further described below. The lower layer 520b may have a specific thickness in various embodiments. For example, the lower layer 520b may have a thickness of at least about 1000 nm, or about 500 nm, or about 200 nm. In these or other embodiments, the lower layer 520b may have a thickness of at most about 2000 nm, or about 1500 nm, or about 1250 nm.

[0057] The multi-layer hard mask 520 may have a specific total thickness. This total thickness includes the thicknesses of both the upper layer 520a and the lower layer 520b before etching the dielectric material 501. The total thickness may be at least about 2500 nm, or about 2000 nm, or about 1500 nm. In these or other embodiments, the total thickness may be at most about 4000 nm, or about 3500 nm, or about 3000 nm. The multi-layer hard mask 520 is patterned to include openings therein. The openings define where the features are etched into the dielectric material 501. The openings can be formed by photolithography and related processes. The openings may have dimensions as described herein.

[0058] Returning to the embodiment of FIG. 4, the method continues with operation 403 and uses an ultra-low temperature etching temperature to etch the features into the dielectric material to a first depth. As shown in FIG. 5B, this ultra-low temperature etching process is used to etch most of the feature depth. In various embodiments, the ultra-low temperature etching temperature may be used to etch a particular portion of the feature (e.g., the top of the feature). For example, this portion may be at least about 50% of the final etching depth, at least about 75% of the final etching depth, at least about 90% of the final etching depth, at least about 95% of the final etching depth, at least about 98% of the final etching depth, or at least about 99% of the final etching depth.

[0059] During etching at ultra-low temperature, the substrate is cooled to a relatively low temperature. For example, the substrate support may be cooled to maintain the substrate at a low temperature. Examples of the minimum temperature of the substrate support may be about -100 °C, about -80 °C, about -60 °C, or about -40 °C. Examples of the maximum temperature of the substrate support may be about -50 °C, about -20 °C, or about 0 °C.

[0060] An etching reactant and plasma are supplied to a process chamber, and a substrate is exposed to the etching reactant and plasma. During the etching operation (or its equivalent), the upper layer 520a of the multilayer hard mask 520 is exposed to the process conditions, and the lower layer 520b of the multilayer hard mask 520 is protected by the upper layer 520a. In some embodiments, the upper layer 520a may be consumed to expose the lower layer 520b at a point near the end of operation 403 or at the start of operation 411. In some embodiments, the upper layer 520a is only partially consumed during etching, and a separate optional step may be taken to remove any remaining upper layer 520a, as described in connection with FIGS. 6 and 7A-7D. In various embodiments, the dielectric material 501 may be etched by the mechanism shown in FIG. 3A (showing cryogenic etching using a carbon mask) during operation 403.

[0061] The etching reactant used during operation 403 typically includes a mixture of reactants. An example of the mixture is shown in FIGS. 2A, 3A, and 3B and includes CH 2 F 2 , H 2 , NF 3 , Cl 2 , and HBr. However, as further described below, in various embodiments, other chemicals and combinations of chemicals may be used. Such chemicals include, for example, fluorocarbons and hydrofluorocarbons (e.g., trifluoromethane (CHF 3 ), tetrafluoromethane (CF 4 ), hexafluoroethane (C 2 F 6 ), octafluoropropane (C 3 F 8 ), etc.), iodine-containing fluorocarbons (e.g., trifluoromethyl iodide (CF 3 I), iodopentafluoroethane (C 2 IF 5 ), diiodotetrafluoroethane (C 2 I 2 F 4), Pentafluoroethyl iodide (C 2 F 5 I), etc.), Iodine-containing fluorides (e.g., Iodine monofluoride (IF), Iodine trifluoride (IF 3 ), Iodine pentafluoride (IF 5 ), Iodine heptafluoride (IF 7 ), etc.), Hydrogen iodide (HI), Bromine-containing fluorocarbons (e.g., Tribromotrifluoroethane (C 2 Br 3 F 3 ), Dibromotetrafluoroethane (C 2 Br 2 F 4 ), Bromopentafluoroethane (C 2 BrF 5 ), Bromotrifluoromethane (CF 3 Br), etc.), Other bromine-containing reactants (e.g., Iodine monobromide (IBr), Hydrogen bromide (HBr), etc.), Sulfur-containing reactants (e.g., Sulfur hexafluoride (SF 6 ), Hydrogen sulfide (H 2 S), Sulfur dioxide (SO 2 ), Carbon disulfide (CS 2 ), Carbonyl sulfide (COS), and other sulfur-containing reactants) may be included. In these or other embodiments, the chemical substance is Nitrogen trifluoride (NF 3 ), Difluoromethane (CH 2 F 2 ), Fluoromethane (CH 3 F), Octafluorocyclobutane (C 4 F 8 ), 1,3-Hexafluorobutadiene (C 4 F 6 ), Pentafluoroethane (C 2 HF 5 ), Tetrafluoroethane (C 2 H 2 F 4 , both isomers: 1,1,1,2-Tetrafluoroethane, and 1,1,2,2-Tetrafluoroethane), etc. One or more etchants may be included. Further, in these or other embodiments, the chemical substance is Methane (CH 4 ), Nitrogen (N 2 ), Oxygen (O2 ) and / or one or more co-reactants such as hydrogen (H 2 ) may be included. Noble gases (helium, neon, argon, krypton, xenon) may also be added as diluents and / or carrier gases. These chemical substances may be combined as desired according to specific applications.

[0062] In operation 403, specific process conditions may be used during cryogenic etching. For example, the pressure in the processing chamber may be at least about 10 mTorr, or about 20 mTorr. In these or other embodiments, the pressure in the processing chamber may be at most about 100 mTorr, or about 50 mTorr. The flow rate of the etching reactant (excluding any noble gas or other non-reactive gas) may be at least about 200 sccm, or about 300 sccm. This flow rate may be at most about 500 sccm, or about 1000 sccm. The flow rate of the non-reactive gas (e.g., Ar, He, Kr, etc.) may be at least about 200 sccm, or about 100 sccm. In these or other embodiments, the flow rate of the non-reactive gas may be at most about 500 sccm, or about 300 sccm. The plasma may be generated at one or more frequencies. Examples of frequencies include 60 MHz, 27 MHz, 13.65 MHz, 2 MHz, 1 MHz, and 400 kHz. The plasma may be generated at a specific power level. For example, this source power level may be at least about 10 kW, or about 15 kW. In these or other cases, this power level may be at most about 20 kW, or about 30 kW. These power levels may be appropriately adjusted according to an additional substrate or other substrate sizes with respect to a single semiconductor substrate with a diameter of 300 mm. During etching, a bias may be applied to the substrate, and the bias power (e.g., at about 400 kHz) ranges from at least about 30 W, or about 50 W to at most about 75 W, or about 100 W. For example, various plasmas such as inductively coupled plasma, capacitively coupled plasma, transformer coupled plasma, and microwave induced plasma may be used. The plasma may be a direct plasma generated in the process chamber.

[0063] Next, in operation 411, the features are further etched into the dielectric material by etching at a conventional temperature. Operation 411 may be used to etch the features to their final depth, as shown in FIG. 5C. In some cases, operation 411 may be performed in a single step. In some other cases, operation 411 may be performed in multiple steps, for example, a first portion for etching the features and a second portion for over-etching the features.

[0064] In various embodiments, the upper layer 520a is carbon and the lower layer 520b is carbon doped with one or more metals. The metal doped in the lower layer 520b slows down the rate at which the lower layer 520b is consumed. Since the rate at which the dielectric is etched does not essentially change (for example, compared to the case of using a single carbon hard mask), the decrease in the mask etching rate results in higher etching selectivity. This improvement in selectivity is particularly advantageous at the end of the etching process. Various other possible materials that can be mentioned as the lower layer 520b are expected to provide advantages similar to those of doped carbon.

[0065] During etching at a conventional temperature, the substrate may or may not be temperature controlled, for example, by heating and / or cooling. For example, the substrate support may be heated and / or cooled to maintain a desired temperature on the substrate. Exemplary minimum temperatures of the substrate support may be about 20°C, or about 40°C, or about 60°C. Exemplary maximum temperatures of the substrate support may be about 60°C, or about 80°C, or about 100°C. In some cases, higher temperatures may be used.

[0066] During operation 411, an etching reactant and a plasma are supplied to the process chamber, and the substrate is exposed to the etching reactant and the plasma. During this etching operation (or its equivalent), the lower layer 520a of the multilayer hard mask 520 is exposed to the process conditions. As described above, the upper layer 520a may be consumed to expose the lower layer 520b at some point near the end of operation 403 or at the start of operation 411. Alternatively, any remaining upper layer 520a can be removed in a separate step. In various embodiments, the dielectric material 501 may be etched during operation 411 by the mechanism shown in FIG. 3D (showing etching at conventional temperatures using a doped carbon mask).

[0067] The etching reactant used during operation 411 typically includes a mixture of reactants. An example of the mixture is shown in FIGS. 2B, 3C, and 3D and includes C 4 F 8 , C 4 F 6 , and O 2 . However, in various embodiments, other chemicals and combinations of chemicals may be used. Generally, any of the chemicals described in connection with the cryogenic etching in operation 403 may be used for the conventional temperature etching in operation 411. Such chemicals can be combined as desired depending on the particular application.

[0068] During operation 411, certain process conditions may be used while performing etching at a conventional temperature. For example, the pressure within the processing chamber may be at a minimum of about 10 mTorr, or about 20 mTorr. In these or other embodiments, the pressure within the processing chamber may be at a maximum of about 50 mTorr, or about 100 mTorr. The flow rate of the etching reactant (excluding any noble gas or other non-reactive gas) may be at a minimum of about 200 sccm, or about 300 sccm. This flow rate may be at a maximum of about 500 sccm, or about 1000 sccm. The flow rate of the non-reactive gas (e.g., Ar, He, Kr, etc.) may be at a minimum of about 200 sccm, or about 100 sccm. In these or other embodiments, the flow rate of the non-reactive gas may be at a maximum of about 500 sccm, or about 300 sccm. The plasma may be generated at one or more frequencies. Examples of frequencies include 60 MHz, 27 MHz, 13.65 MHz, 2 MHz, 1 MHz, and 400 kHz. The plasma may be generated at a specific power level. For example, this source power level may be at a minimum of about 10 kW, or about 15 kW. In these or other cases, this power level may be at a maximum of about 20 kW, or about 30 kW. These power levels may be appropriately adjusted according to an additional substrate or substrates of other sizes, with respect to a single 300 mm diameter semiconductor substrate. During etching, a bias may be applied to the substrate, and the bias ranges from a power of about 30 kW, or about 50 kW at a minimum of 400 kHz to a power of a maximum of about 75 kW, or about 100 kW. For example, various plasmas such as inductively coupled plasma, capacitively coupled plasma, transformer coupled plasma, and microwave induced plasma may be used. Capacitively coupled plasma is preferred in various embodiments.

[0069] FIG. 6 is a flowchart relating to a method of etching features according to various embodiments of the present specification into a dielectric material. The method of FIG. 6 is described in relation to FIGS. 7A-7D, which show a semiconductor substrate undergoing the various processing operations of FIG. 6. The method of FIG. 6 is similar to the method of FIG. 4. For example, operations 601, 603, and 611 of FIG. 6 are similar to operations 401, 403, and 411 of FIG. 4, respectively. For the sake of brevity, the details related to operations 601, 603, and 611 are mostly excluded. However, it is understood that the details provided for operations 401, 403, and 411 are applicable to operations 601, 603, and 611, respectively.

[0070] FIG. 7A shows a substrate received within a process chamber during operation 601. The substrate includes a dielectric material 701 positioned between an etch stop layer 708 and a multilayer hard mask 720 including an upper layer 720a and a lower layer 720b. FIG. 7B shows the substrate after etching a feature into the dielectric material 701 to a first depth at an ultra-low temperature etch temperature during operation 603. Returning to the embodiment of FIG. 6, the method continues at operation 605 and, as shown in FIG. 7C, removes any remaining portions of the upper layer 720a of the multilayer hard mask 720. This removal may be performed in a separate step. In many embodiments, the upper layer 720a is removed by ashing. Ashing includes exposing the substrate to an oxygen plasma. The oxygen in the oxygen plasma reacts with the carbon in the upper layer 720a of the multilayer hard mask 720, thereby removing the upper layer 720a.

[0071] One advantage of removing the remaining portion of the upper layer 720a is that it provides a substantially uniform mask height for subsequent processing. This eliminates any non-uniformities that may occur during etching at cryogenic temperatures during operation 703. Such non-uniformities in mask height are seen in FIG. 7B. These non-uniformities are typically due to non-uniformities in the layout / density of features, referred to as isolated / dense fill. By providing a uniform mask height for subsequent process steps, such subsequent process steps may be performed in a more uniform manner. Another advantage of removing the remaining portion of the upper layer 720a is to remove any necks that may develop during etching at cryogenic temperatures during operation 703.

[0072] The process conditions used to ashing the remaining upper layer 720a may depend on a plurality of factors, such as for example the amount of material to be removed. Oxygen plasma may be generated at one or more frequencies of, for example, 13.65 MHz, 27 MHz, 40 MHz, and 60 MHz. Oxygen plasma may be generated at a specific power level. This power level may be at least about 200 W, or about 500 W. In these or other embodiments, this power level may be at most about 3000 W, or about 6000 W. The substrate may be controlled to a specific temperature, for example by controlling the temperature of the substrate support. Exemplary minimum temperatures of the substrate support may be about 20 °C, or about 50 °C. Exemplary maximum temperatures of the substrate support may be about 200 °C, or about 250 °C. The pressure within the process chamber may be controlled. Exemplary minimum chamber pressures may be about 500 mTorr, or about 750 mTorr. Exemplary maximum chamber pressures may be about 2 Torr, or about 4 Torr. The flow rate of oxygen into the process chamber may be controlled. Examples of minimum flow rates of oxygen include about 500 sccm, or about 1000 sccm. Examples of maximum flow rates of oxygen include about 2000 sccm, or about 4000 sccm. Also, a carrier gas may be supplied. Also, to promote the dissociation of oxygen and supply fluorine for the removal of silicon-containing etching products, CF4 can be added.

[0073] In operation 605, after removing any remaining portions of the upper layer 720a, the method of FIG. 6 continues with operation 611 and further etches the features into the dielectric material 701 using a conventional etching temperature as described in connection with operation 411 of FIG. 4. After etching in operation 611, as shown in FIG. 7D, the features are at their final depth (e.g., reaching the etch stop layer 708).

[0074] FIG. 6 is presented in the context of an embodiment in which all of the remaining portions of the upper layer 720a are removed, but it should be understood that this removal may be partial. In such an embodiment, operation 605 includes removing only a portion, rather than all, of the remaining portions of the upper layer 720a. A partial removal may be sufficient to obtain one or more of the advantages described above, such as providing a uniform mask height and / or removing the necking.

[0075] FIG. 8 is a flowchart of a method of etching features into a dielectric material according to various embodiments of the present specification. The method of FIG. 8 is described in connection with FIGS. 9A - 9E, which show a semiconductor substrate undergoing the various processing operations of FIG. 8. The method of FIG. 8 is similar to the methods of FIGS. 4 and 6. For example, operation 801 of FIG. 8 is similar to operation 401 of FIG. 4 and operation 601 of FIG. 6, operation 803 of FIG. 8 is similar to operation 403 of FIG. 4 and operation 603 of FIG. 6, operation 805 of FIG. 8 is similar to operation 605 of FIG. 6, and operation 811 of FIG. 8 is similar to operation 411 of FIG. 4 and operation 611 of FIG. 6. For the sake of brevity, the details related to operations 801, 803, 805, and 811 are mostly excluded. However, it is understood that the details related to operations 401 / 601, 403 / 603, 605, and 411 / 611 are also applicable to operations 801, 803, 805, and 811, respectively.

[0076] In this example, as shown in FIG. 9A, the feature is etched into the dielectric material 901 and positioned between the etch stop layer 908 and the multilayer hard mask 920 having an upper layer 920a and a lower layer 920b. FIG. 9B shows the substrate after operation 803. FIG. 9C shows the substrate after operation 805. Generally, in a separate step such as operation 805, removing the upper layer 920a of the multilayer hard mask is optional, and in some embodiments, the method of FIG. 8 may be implemented without performing operation 805.

[0077] The method of FIG. 8 continues with operation 807 and deposits a liner 930 along the sidewalls of the partially etched feature as shown in FIG. 9D. In many embodiments, this deposition is performed by chemical vapor deposition (CVD) and may or may not involve exposure to plasma. However, other deposition methods such as atomic layer deposition (ALD), self-assembled monolayers (SAM), etc. can also be used. The liner 930 is often a carbon liner. Depending on the specific application, other types of liners such as metal-doped carbon, metal nitride, or metal oxide can also be used as desired.

[0078] The process conditions used to form the liner may be controlled. In various examples of depositing a carbon liner using CVD, the following conditions may be used. The pressure in the processing chamber may be at least about 1 Torr, or about 5 Torr. This pressure may be at most about 10 Torr, or about 15 Torr. The substrate may be temperature-controlled, for example, by heating and / or cooling the substrate support. The substrate support may be controlled to a minimum temperature of about 200 °C, or about 300 °C. The substrate support may be controlled to a maximum temperature of about 500 °C, or about 700 °C. The reactants supplied to the process chamber are C x H y (e.g., CH 4 、C 2 H 2 、C 3 H 6 、C 4 H 8It may include (etc.). A carrier gas may be supplied. An exemplary minimum flow rate of the reactants (excluding the carrier gas) may be about 20 sccm, or about 100 sccm. An exemplary maximum flow rate of the reactants (excluding the carrier gas) may be about 5 slm, or about 10 slm. The plasma can be capacitively coupled or inductively coupled at various frequencies.

[0079] As described above, for forming the liner, other types of deposition can also be used. In this case, the process conditions need to be adjusted according to the type of process being used and the type of material being deposited.

[0080] In operation 807, after depositing the liner 930 on the sidewalls, the method of FIG. 8 continues with operation 811 and further etches the feature into the dielectric material 901 using a conventional etching temperature as shown in FIG. 9E.

[0081] In various embodiments, depositing the liner 930 in operation 807 and etching the feature at a conventional temperature in operation 911 may be performed periodically with respect to each other. By performing it periodically in this way, if all other conditions are the same, the feature may be etched further into the dielectric material compared to the depth achievable by other methods.

[0082] FIG. 10 is a flowchart relating to a method of etching features according to various embodiments of the present specification into a dielectric material. The method of FIG. 10 is described in relation to FIGS. 11A-11E, which show a semiconductor substrate undergoing the various processing operations of FIG. 10. The method of FIG. 10 is similar to the methods of FIGS. 4, 6, and 8. For example, operation 1001 of FIG. 10 is similar to operations 401, 601, and 801, operation 1003 of FIG. 10 is similar to operations 403, 603, and 803, operation 1005 of FIG. 10 is similar to operations 605 and 805, operation 1007 of FIG. 10 is similar to operation 807, and operation 1011 of FIG. 10 is similar to operations 411, 611, and 811. For the sake of brevity, details regarding operations 1001, 1003, 1005, 1007, and 1011 are mostly excluded. However, the details regarding operations 401 / 601 / 801, 403 / 603 / 803, 605 / 805, 807, and 411 / 611 / 811 are also applicable to the operations of 1001, 1003, 1005, 1007, and 1011, respectively.

[0083] In the method of FIG. 10, as shown in FIG. 11A, a feature is etched into a substrate having a dielectric material 1101 positioned between a lower etching stop layer 1108 and an upper multilayer hard mask 1120 having an upper layer 1120a and a lower layer 1120b. FIG. 11B shows the substrate after etching at extremely low temperature in operation 1003. FIG. 11C shows the substrate after removing the remaining upper layer 1120a of the multilayer hard mask 1120 in operation 1005. The method of FIG. 10 continues with operation 1007, depositing a liner 1130 along the sidewalls of the partially etched feature, and continues with operation 1009, depositing additional mask material 1135 on the remaining portion of the multilayer hard mask 1120. These operations may be performed simultaneously or one after the other. In various embodiments, operations 1007 and / or 1009 are performed by chemical vapor deposition and may or may not involve exposure to plasma.

[0084] In various embodiments, the additional mask material 1135 is carbon. The additional mask material 1135 may have the same composition as the carbon forming the upper layer 1120a of the multilayer hard mask 1120, or may have the same composition as the doped carbon or other material forming the lower layer 1120b of the multilayer hard mask 1120, or may have a composition different from both of these materials.

[0085] The process conditions used to form the liner and / or the additional mask material may be controlled. In various examples where CVD is used, the following conditions may be employed. The pressure in the processing chamber may be at least about 1 Torr, or about 5 Torr. This pressure may be at most about 10 Torr, or about 15 Torr. The substrate may be temperature-controlled, for example, by heating and / or cooling a substrate support. The substrate support may be controlled to a minimum temperature of about 200 °C, or about 300 °C. The substrate support may be controlled to a maximum temperature of about 500 °C or about 700 °C. The reactants supplied to the process chamber may include C x H y (CH 4 , C 2 H 2 , C 3 H 6 , C 4 H 8 etc.). A carrier gas may be supplied. An exemplary minimum flow rate of the reactants (excluding the carrier gas) may be about 20 sccm, or about 100 sccm. An exemplary maximum flow rate of the reactants (excluding the carrier gas) may be about 5 slm, or about 10 slm. The plasma may be capacitively or inductively coupled at various frequencies.

[0086] Other types of deposition can also be used to form the liner and / or the additional mask material. In this case, the process conditions need to be adjusted according to the type of process being used and the type of material being deposited.

[0087] Any of the methods described in this specification may be modified to be repeatable for one or more steps. For example, referring to FIG. 6, in operation 605, removal of a portion of the multilayer hard mask may be repeated. In some embodiments, partial mask removal in operation 605 and etching at a conventional temperature in operation 611 may be performed periodically. Referring to FIG. 8, certain additional steps may be repeated. For example, removal of a portion of the multilayer hard mask in operation 805, deposition of a liner in operation 807, and / or etching of features at a conventional etching temperature in operation 811 may be repeated. In various embodiments, two or more of these operations may be performed periodically with respect to each other. Similarly, FIG. 10 represents additional steps that may be repeated in some embodiments. For example, removal of a portion of the multilayer hard mask in operation 1005, deposition of a liner in operation 1007, deposition of additional mask material in operation 1009, and / or etching at a conventional etching temperature in operation 1011 may be repeated. In various embodiments, two or more of these operations may be performed periodically with respect to each other. By performing them periodically in this way, it may be possible to etch features deeper than can be achieved by other means. Material for Multilayer Hard Mask

[0088] The multilayer hard mask includes at least an upper layer and a lower layer. Additional layers may be provided as desired depending on the particular application. Generally, the upper layer is carbon, and the lower layer is a different material such as doped carbon, silicon, metal, or a metal-containing material (e.g., metal oxide, metal nitride, metal silicide, metal carbide, metal alloy, etc.).

[0089] Carbon in the upper layer of the multilayer hard mask may be relatively pure, for example, at least about 85% carbon, at least about 90% carbon, at least about 95% carbon, at least about 99% carbon, or at least about 99.9% carbon. These measurements are based on at%. In various embodiments, the upper layer contains only carbon and trace impurities. In some embodiments, the upper layer may be lightly doped carbon as described below. Such carbon may be doped with one or more of the metals as described below. The lightly doped upper layer may be combined with a more extensively doped lower layer or a lower layer composed of a different material. The upper layer may be amorphous or polycrystalline with a grain size of less than 2 nm.

[0090] The upper layer of the multilayer hard mask can be formed by any suitable deposition method. In some embodiments, the upper layer of the multilayer hard mask may be formed by CVD.

[0091] The lower layer 520b of the multilayer hard mask 520 is a material such as doped carbon, silicon, metal, or a metal-containing material (e.g., metal oxide, metal nitride, metal silicide, metal carbide, metal alloy, etc.). Generally, when the lower layer 520b contains a metal, the metal may be present at a minimum concentration of about 0.1%, or about 0.5%, or about 1%, or about 2%, or about 5%, or about 10%, or about 20%, or about 30%, or about 50%. In these or other embodiments, the metal may be present in the lower layer 520b at a maximum concentration of about 5%, about 10%, about 20%, about 50%, or even up to about 100% (e.g., a pure metal, or a metal containing only trace impurities, or a metal alloy). These measurements are based on at%.

[0092] In some embodiments, the lower layer is carbon lightly doped with one or more metals. For example, the carbon lightly doped with a metal may have up to about 10% metal. In some embodiments, the lower layer is carbon moderately doped with one or more metals. For example, the carbon moderately doped with a metal may have between about 15 - 35% metal. In some embodiments, the lower layer is carbon heavily doped with one or more metals. For example, the carbon heavily doped with a metal may have between about 40 - 50% metal. These measurements are based on at%.

[0093] In some embodiments, the lower layer is silicon. The silicon may be relatively pure, containing, for example, only trace amounts of impurities.

[0094] In some embodiments, the lower layer is a metal or a metal-containing material. Metal-doped carbon has been described above. Metal-doped oxides, metal-doped nitrides, metal-doped carbides, and / or metal-doped silicides can also be used. Other metal-containing materials that can be used for the lower layer include, for example, metal oxides, metal nitrides, metal carbides, and metal silicides. In such embodiments, the metal may be present at a stoichiometric level, a sub-stoichiometric level, or a super-stoichiometric level.

[0095] A variety of different metals may be used. For example, the lower layer may include one or more metals selected from the group consisting of aluminum, boron, chromium, cobalt, hafnium, molybdenum, niobium, ruthenium, tantalum, titanium, tungsten, vanadium, zirconium, and combinations thereof. In some embodiments, other metals may be used.

[0096] In multiple embodiments, the metal included in the lower layer (e.g., in the form of a pure metal, metal-doped carbon, metal oxide, metal nitride, metal carbide, metal silicide, or other metal-doped layer described herein) is a metal that has a relatively high boiling point when combined with fluorine. For example, the relevant metal fluoride may have a boiling point that is approximately equal to or higher than that of tungsten fluoride at the relevant etching temperature, and in some cases, may have a boiling point higher than that of molybdenum fluoride, or chromium fluoride, or tantalum fluoride. Since the metal in the lower layer reacts with fluorine in the etching chemical (e.g., C x F y chemicals and related chemical sputtering), this leads to the formation of metal fluorides. When these metal fluorides are relatively more stable (e.g., have a higher boiling point and lower volatility), more energy is required to remove them. Therefore, metals with high-boiling metal fluorides are well-suited to be included in the lower layer. Among them, tantalum fluoride (TaF 5 ), niobium fluoride (NbF 5 ), titanium fluoride (TiF 4 ), and hafnium fluoride (HfF 4 ) are known to have relatively high boiling points.

[0097] In some embodiments, the metal included in the lower layer is a metal that has relatively low reactivity with fluorine. For example, the relevant metal may have reactivity with fluorine that is comparable to or lower than that of ruthenium. Since the metal in the lower layer reacts with fluorine in the etching chemical (e.g., C x F y chemicals), selecting a metal with relatively low reactivity with fluorine will result in a relatively lower mask etching rate when etching the lower layer of the multilayer hard mask. As a result, as described above, the etching selectivity is improved.

[0098] The lower layer of the multilayer hard mask can be formed by any suitable deposition method. In some embodiments, the lower layer of the multilayer hard mask may be formed by CVD. The lower layer may be amorphous or polycrystalline with a grain size of less than 2 nm.

[0099] In addition to compositional differences, the upper and lower layers may also have differences in other material properties. For example, the lower layer may be denser than the upper layer. Tilted Multilayer Hard Mask

[0100] In various embodiments, the multilayer hard mask described herein can be replaced with a graded layer hard mask or a multilayer hard mask having at least one graded layer. Referring to the multilayer hard mask 520 of FIG. 5A, the graded layer may include a first end or portion similar to the upper layer 520a, a second end or portion similar to the lower layer 520b, and a graded composition therebetween (e.g., one composition that transitions stepwise to the next composition along the thickness of the layer). Generally, any details provided herein regarding the multilayer hard mask are also applicable to embodiments where the multilayer hard mask (or a layer therein) is replaced with a graded layer hard mask. For example, in the context of the methods described in FIGS. 4, 6, 8, and 10, a graded layer hard mask may be used instead of the multilayer hard mask. Device

[0101] Figures 12A - 12C show an embodiment of a capacitively coupled confinement RF plasma reactor 1200 having an adjustable gap that can be used to perform the etching operations described herein. As shown, the vacuum chamber 1202 includes a chamber housing 1204 that surrounds an internal space containing a lower electrode 1206. At the top of the chamber 1202, an upper electrode 1208 is disposed vertically spaced from the lower electrode 1206. The planes of the upper and lower electrodes 1208, 1206 are substantially parallel and orthogonal to the vertical direction between the electrodes. Preferably, the upper and lower electrodes 1208, 1206 are circular and coaxial with respect to a vertical axis. The lower surface of the upper electrode 1208 faces the upper surface of the lower electrode 1206. The spaced opposing electrode surfaces define an adjustable gap 1210 therebetween. During operation, the lower electrode 1206 is supplied with RF power by an RF power source (matcher) 1220. The RF power is supplied to the lower electrode 1206 through an RF supply conduit 1222, an RF strap 1224, and an RF power member 1226. A ground shield 1236 may surround the RF power member 1226 to provide a uniform RF field by the lower electrode 1206. As described in commonly owned U.S. Patent No. 7,732,728, the entire contents of which are incorporated herein by reference, a wafer is inserted through a wafer port 1282, supported in the gap 1210 on the lower electrode 1206 for processing, a process gas is supplied to the gap 1210 (e.g., through one or more inlets), and excited to a plasma state by RF power. The upper electrode 1208 may be powered or grounded.

[0102] In the embodiment shown in FIGS. 12A - 12C, the lower electrode 1206 is supported on a lower electrode support plate 1216. An insulator ring 1214 intervening between the lower electrode 1206 and the lower electrode support plate 1216 insulates the lower electrode 1206 from the support plate 1216.

[0103] The RF bias housing 1230 supports the lower electrode 1206 on the RF bias housing bowl 1232. The bowl 1232 is connected to the conduit support plate 1238 through an opening in the chamber wall plate 1218 by the arm 1234 of the RF bias housing 1230. In a preferred embodiment, the RF bias housing bowl 1232 and the RF bias housing arm 1234 are one integrally formed component, but the arm 1234 and the bowl 1232 can also be two separate components bolted or joined together.

[0104] The RF bias housing arm 1234 includes one or more hollow passages for passing RF power and equipment, such as a gas coolant, a liquid coolant, RF energy, a lift pin control cable from the outside of the vacuum chamber 1202 to the inside of the vacuum chamber 1202, an electrical monitoring cable, and an actuation signal cable, through the space behind the lower electrode 1206. The RF supply conduit 1222 is insulated from the RF bias housing arm 1234, and the RF bias housing arm 1234 provides a return path for RF power to the RF power supply 1220. The equipment conduit 1240 provides a passage for components of the equipment. Further details of the components of the equipment are described in U.S. Pat. Nos. 5,948,704 and 7,732,728 and are not shown herein for the sake of brevity. The gap 1210 is preferably surrounded by a confinement ring assembly or a shroud (not shown), the details of which can be found in commonly owned U.S. Pat. No. 7,740,736, which is incorporated herein by reference. The interior of the vacuum chamber 1202 is maintained at a low pressure by connecting it to a vacuum pump through a vacuum portal 1280 (also called an outlet).

[0105] The conduit support plate 1238 is attached to the actuating mechanism 1242. Details of the actuating mechanism are described in commonly-owned U.S. Patent No. 7,732,728, which is incorporated herein by reference above. The actuating mechanism 1242, such as a servo motor, a stepping motor, etc., is attached to the vertical linear bearing 1244 by, for example, a screw gear 1246 such as a ball screw and a motor for rotating the ball screw. During the operation of adjusting the size of the gap 1210, the actuating mechanism 1242 moves along the vertical linear bearing 1244. FIG. 12A shows the arrangement when the actuating mechanism 1242 is in a high position on the linear bearing 1244, resulting in a small gap 1210a. FIG. 12B shows the arrangement when the actuating mechanism 1242 is in an intermediate position on the linear bearing 1244. As shown in the figure, the lower electrode 1206, the RF bias housing 1230, the conduit support plate 1238, and the RF power supply 1220 all move downward relative to the chamber housing 1204 and the upper electrode 1208, resulting in a medium-sized gap 1210b.

[0106] FIG. 12C shows the large gap 1210c when the actuating mechanism 1242 is in a low position on the linear bearing. Preferably, during the gap adjustment, the upper and lower electrodes 1208, 1206 remain coaxial, and the opposing surfaces of the upper and lower electrodes sandwiching the gap remain parallel.

[0107] According to this embodiment, during a multi-step process recipe (such as BARC, HARC, and STRIP, etc.), the gap 1210 between the lower electrode 1206 and the upper electrode 1208 in the CCP chamber 1202 is adjusted to maintain uniform etching over the entire large-diameter substrate, such as a 300 mm wafer or a flat panel display. In particular, this chamber is suitable for a mechanical arrangement that enables the linear motion necessary to provide an adjustable gap between the lower electrode 1206 and the upper electrode 1208.

[0108] FIG. 12A shows a laterally deflected bellows 1250 that is sealed at its proximal end to the conduit support plate 1238 and at its distal end to the stepped flange 1228 of the chamber wall plate 1218. The inner diameter of the stepped flange defines an opening 1212 within the chamber wall plate 1218 through which the RF bias housing arm 1234 passes. The distal end of the bellows 1250 is clamped by a clamp ring 1252.

[0109] The laterally deflected bellows 1250 provides a vacuum seal while allowing vertical movement of the RF bias housing 1230, the conduit support plate 1238, and the actuating mechanism 1242. The RF bias housing 1230, the conduit support plate 1238, and the actuating mechanism 1242 may be referred to as a cantilever assembly. Preferably, the RF power supply 1220 moves with the cantilever assembly and is attachable to the conduit support plate 1238. FIG. 12B shows the bellows 1250 in a neutral position when the cantilever assembly is in an intermediate position. FIG. 12C shows the laterally deflected bellows 1250 when the cantilever assembly is in a low position.

[0110] The labyrinth seal 1248 provides a particle barrier between the bellows 1250 and the interior of the plasma processing chamber housing 1204. A fixed shield 1256 is immovably attached to the inner wall inside the chamber housing 1204 at the chamber wall plate 1218 such that the movable shield plate 1258 moves vertically to provide a labyrinth groove 1260 (slot) corresponding to the vertical movement of the cantilever assembly. The outer portion of the movable shield plate 1258 remains within the slot at all vertical positions of the lower electrode 1206.

[0111] In the illustrated embodiment, the labyrinth seal 1248 includes a fixed shield 1256 attached to the inner surface of the chamber wall plate 1218 at the periphery of the opening 1212 in the chamber wall plate 1218 that defines the labyrinth groove 1260. The movable shield plate 1258 is attached to the RF bias housing arm 1234 and extends radially from the RF bias housing arm 1234, and the arm 1234 passes through the opening 1212 in the chamber wall plate 1218. When the movable shield plate 1258 extends into the labyrinth groove 1260, it is disposed at a first gap separation from the fixed shield 1256 and at a second gap separation from the inner surface of the chamber wall plate 1218. This allows the cantilever assembly to move in the vertical direction. The labyrinth seal 1248 prevents particles peeled off from the bellows 1250 from moving and entering the interior 1205 of the vacuum chamber, and prevents radicals generated from the process gas plasma from moving to the bellows 1250 where deposits can be formed and then the deposits from peeling off.

[0112] FIG. 12A shows that when the cantilever assembly is in a high position (small gap 1210a), the movable shield plate 1258 is in a higher position within the labyrinth groove 1260 above the RF bias housing arm 1234. FIG. 12C shows that when the cantilever assembly is in a low position (large gap 1210c), the movable shield plate 1258 is in a lower position within the labyrinth groove 1260 above the RF bias housing arm 1234. FIG. 12B shows the movable shield plate 1258 in a neutral or intermediate position within the labyrinth groove 1260 when the cantilever assembly is in an intermediate position (intermediate gap 1210b). The labyrinth seal 1248 is shown to be symmetric about the RF bias housing arm 1234, but in other embodiments, the labyrinth seal 1248 may be asymmetric about the RF bias arm 1234.

[0113] FIG. 13 shows a semiconductor process cluster architecture with various modules coupled by interface to a vacuum transfer module 1338 (VTM). The arrangement of transfer modules that "transfer" substrates between multiple storage facilities and processing modules may be referred to as a "cluster tool architecture" system. The airlock 1330, also known as a load lock or transfer module, is shown with four processing modules 1320a - 1320d in the VTM 1338, and these may be individually optimized to perform various manufacturing processes. For example, the processing modules 1320a - 1320d may be implemented to perform substrate etching, deposition, ion implantation, substrate cleaning, sputtering, and / or other semiconductor processes, as well as laser measurement and other defect detection and defect identification methods. One or more of the processing modules (any of 1320a - 1320d) may be implemented to etch concave features into a substrate using a multi-step etching process having a multi-layer hard mask as disclosed herein. The airlock 1330 and the process modules 1320a - 1320d may be referred to as "stations". Each station has a facet 1336 that interfaces the station to the VTM 1338. Inside the facet, sensors 1 - 18 are used to detect the passage of the substrate 1326 as it moves between the respective stations.

[0114] Robot 1322 transports substrates between stations. In one embodiment, the robot has one arm, and in another embodiment, the robot has two arms, and each arm has an end effector 1324 for picking up the substrate for transfer. A front-end robot 1332 within an atmospheric transfer module (ATM) 1340 may be used to transfer the substrate from a cassette or a front opening unified pod (FOUP) 1334 within a load port module (LPM) 1342 to an air lock 1330. A module center 1328 within process modules 1320a - 1320d may be one place for placing the substrate. An aligner 1344 within the ATM 1340 may be used to align the substrate.

[0115] In an exemplary processing method, the substrate is placed in one of the FOUPs 1334 within the LPM 1342. By the front-end robot 1332 transporting the substrate from the FOUP 1334 to the aligner 1344, the substrate 1326 can be properly centered before etching, or deposition, or other processing of the substrate 1326. After aligning the substrate, the substrate is moved into the air lock 1330 by the front-end robot 1332. Since the air lock module has the ability to match the environment between the ATM and the VTM, the substrate can move between the two pressure environments without being damaged. From the air lock module 1330, the substrate is moved through the VTM 1338 by the robot 1322 into one of the process modules 1320a - 1320d, for example, into the process module 1320a. To achieve this movement of the substrate, the robot 1322 uses the end effector 1324 on each of its arms. In the process module 1320a, the substrate is etched as described above. Next, the robot 1322 moves the substrate from the process module 1320a to its next desired position.

[0116] A computer that controls the movement of the substrate can be locally connected to the cluster architecture, or can be placed outside the cluster architecture within the manufacturing floor, or can be located remotely and connected to the cluster architecture via a network. Conclusion

[0117] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. Note that there are many alternative ways to implement the processes, systems, and apparatuses of this embodiment. Therefore, this embodiment should be regarded as illustrative and not restrictive, and this embodiment is not limited to the details described herein.

Claims

1. A method of etching features into a substrate, comprising: Receiving a substrate in a process chamber, the substrate comprising: A dielectric material; A hard mask having an upper portion and a lower portion; Wherein the upper portion contains carbon and the lower portion contains at least one material selected from the group consisting of doped carbon, silicon, metal, metal-containing material, and combinations thereof; The upper and lower portions of the hard mask have different compositions; The hard mask is patterned to define a location where the feature is etched into the dielectric material; The hard mask is positioned above the dielectric material; Etching the feature into the substrate to a first depth while the substrate is at a first temperature and the upper portion of the hard mask is exposed; Etching the feature to a final depth while the substrate is at a second temperature higher than the first temperature and the lower portion of the hard mask is exposed. A method comprising the above steps.

2. The method according to claim 1, wherein: The first temperature is between about -100°C and about 0°C, and the second temperature is between about 0°C and about 100°C.

3. The method according to claim 2, wherein: The first temperature is between about -60°C and about -20°C, and the second temperature is between about 20°C and about 60°C.

4. The method according to claim 1, wherein: The lower portion of the hard mask contains one or more metals selected from the group consisting of aluminum, boron, chromium, cobalt, hafnium, molybdenum, niobium, ruthenium, tantalum, titanium, tungsten, vanadium, zirconium, and combinations thereof.

5. The method according to claim 4, wherein: The lower portion of the hard mask has a composition that is at least about 5 at% metal.

6. The method according to claim 1, further comprising: After etching the feature into the substrate to the first depth and before etching the feature to the final depth, exposing the substrate to an oxygen-containing plasma to ash any remaining upper portion of the hard mask.

7. The method according to claim 1, wherein: A method further comprising depositing a liner on sidewalls of the feature after etching the feature into the substrate to the first depth and before etching the feature to the final depth.

8. The method according to claim 1, A method further comprising depositing additional mask material on the hard mask after etching the feature into the substrate to the first depth and before etching the feature to the final depth.

9. The method according to claim 1, A method wherein the upper and lower portions of the hard mask are separate layers.

10. The method according to claim 1, A method wherein the hard mask has a graded composition such that the composition of the upper portion of the hard mask transitions gradually to the composition of the lower portion of the hard mask.

11. An apparatus for etching a substrate, comprising: A process chamber; A substrate support configured to support the substrate within the process chamber; An inlet to the process chamber for introducing one or more reactants into the process chamber; An outlet of the process chamber for removing material from the process chamber; A controller including a memory and a processor, wherein the controller is configured to: Receive the substrate within the process chamber, the substrate including: A dielectric material; A hard mask including an upper portion and a lower portion, wherein the upper portion includes carbon and the lower portion includes at least one material selected from the group consisting of doped carbon, silicon, metal, metal-containing materials, and combinations thereof; The upper and lower portions of the hard mask having different compositions; The hard mask being patterned to define a location where the feature is etched into the dielectric material; The hard mask being positioned above the dielectric material; Etch the feature into the substrate to a first depth while the substrate is at a first temperature and the upper portion of the hard mask is exposed; Etch the feature to a final depth while the substrate is at a second temperature higher than the first temperature and the lower portion of the hard mask is exposed.

12. The apparatus according to claim 11, An apparatus, wherein the first temperature is between about -100°C and about 0°C, and the second temperature is between about 0°C and about 100°C.

13. The apparatus according to claim 12, wherein the first temperature is between about -60°C and about -20°C, and the second temperature is between about 20°C and about 60°C.

14. The apparatus according to claim 11, wherein the lower portion of the hard mask comprises one or more metals selected from the group consisting of aluminum, boron, chromium, cobalt, hafnium, molybdenum, niobium, ruthenium, tantalum, titanium, tungsten, vanadium, zirconium, and combinations thereof.

15. The apparatus according to claim 14, wherein the lower portion of the hard mask has a composition that is at least about 5 at% metal.

16. The apparatus according to claim 11, wherein the controller is further configured to expose the substrate to an oxygen-containing plasma after etching the feature into the substrate to the first depth and before etching the feature to the final depth, to ash any remaining upper portion of the hard mask.

17. The apparatus according to claim 11, wherein the controller is further configured to deposit a liner on the sidewalls of the feature after etching the feature into the substrate to the first depth and before etching the feature to the final depth.

18. The apparatus according to claim 11, wherein the controller is further configured to deposit additional mask material on the hard mask after etching the feature into the substrate to the first depth and before etching the feature to the final depth.

19. The apparatus according to claim 11, wherein the upper and lower portions of the hard mask are separate layers.

20. The apparatus according to claim 11, wherein the hard mask has a graded composition such that the composition of the upper portion of the hard mask transitions stepwise to the composition of the lower portion of the hard mask.

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