Method for transferring a layer from a source substrate to a target substrate

Abstract

This specification relates to a method of transferring a layer (15) from a source substrate (13) to a target substrate (17), the method comprising: a) placing a masking disk at a central portion of a bonding surface of the layer and / or the target substrate (17); b) performing ion etching to form steps (29, 30) facing a peripheral portion of the bonding surface of the layer and / or the target substrate that is not covered by the masking disk; c) removing the masking disk; d) activating the bonding surface of the layer and the bonding surface of the target substrate; and e) bringing the bonding surface of the layer into contact with the bonding surface of the target substrate (17).

Description

Technical Field

[0001] The present disclosure generally relates to a method for manufacturing microelectronic components based on semiconductor materials. More specifically, the present disclosure aims at a method for transferring a semiconductor layer from a source substrate to a target substrate.

Background Art

[0002] In the method of manufacturing microelectronic components, currently, layer transfer is used to transfer a relatively thin semiconductor layer with high crystal quality onto a thicker target substrate formed of a material with lower crystal quality or lower cost.

[0003] After transfer, the transferred layer may be used as a base for an epitaxial process. Thereafter, microelectronic components can be formed inside and on the epitaxial layer.

Summary of the Invention

Problems to be Solved by the Invention

[0004] It is desirable to at least partially overcome certain disadvantages of known methods for transferring a semiconductor layer from a source substrate to a target substrate.

[0005] Improvement in the quality of the edges of the layer to be transferred is more specifically considered herein.

Means for Solving the Problems

[0006] An embodiment is a method for transferring a layer from a source substrate to a target substrate, comprising: a) disposing a masking disk at a central portion of a bonding surface of the layer and / or the target substrate; b) performing ion etching to form a step facing a peripheral portion of the bonding surface of the layer and / or the target substrate that is not covered by the masking disk; c) removing the masking disk; d) Activating the bonding surface of the layer and the bonding surface of the target substrate by ion etching or ion deposition of a bonding material, and e) After step d), bringing the bonding surface of the layer into contact with the bonding surface of the target substrate having, Performing steps b) and d) continuously within the same ion processing chamber, Performing steps d) and e) under vacuum and maintaining the vacuum between steps d) and e), a method is provided.

[0007] According to an embodiment, the target substrate and / or the source substrate has a tapered edge extending over a first width.

[0008] According to an embodiment, after step b), the step extends over a width greater than or equal to the first width from the edge of the layer and / or the edge of the target substrate.

[0009] According to an embodiment, the masking disk has a diameter smaller than the diameter of the source substrate and / or the diameter of the target substrate.

[0010] According to an embodiment, the method has a step f) of removing the source substrate after step e).

[0011] According to an embodiment, step f) has an annealing step of decomposing the assembly obtained at the end of step e) at the surface of the implanted buried layer that separates the layer from the source substrate.

[0012] According to an embodiment, the layer is a semiconductor layer.

[0013] According to an embodiment, the method has a step of performing epitaxy in contact with the surface of the layer on the surface of the layer on the opposite side of the target substrate after step f).

[0014] According to an embodiment, after step b), the step extends to a depth exceeding 700 nm from the bonding surface of the layer and / or the bonding surface of the target substrate.

[0015] According to an embodiment, in step d), a bonding layer is deposited on the bonding surface of the layer and / or the bonding surface of the target substrate.

[0016] According to an embodiment, the thickness of the bonding layer is in the range of 0.2 nm to 100 nm, for example, in the range of 1 nm to 20 nm.

Brief Description of the Drawings

[0017] The foregoing and other features and advantages are described in detail in the remainder of the present disclosure of specific embodiments given by way of illustration and not limitation with reference to the accompanying drawings.

[0018]

Figure 1A

Figure 1B

Figure 1C

Figure 1D

Figure 1E

Figure 1F

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 2E

Figure 2F

Embodiments for Carrying Out the Invention

[0019] In various figures, similar features are denoted by similar reference numerals. In particular, structural features and / or functional features common to various embodiments may have the same reference numerals and may have the same structural properties, dimensional properties, and material properties.

[0020] For clarity, only the steps and elements useful for understanding the embodiments described herein are illustrated and described in detail. In particular, a method for manufacturing a microelectronic component based on the transferred semiconductor layer is not detailed, and the described transfer methods are compatible with all or most ordinary microelectronic component manufacturing methods.

[0021] In the following disclosure, when referring to absolute positions such as "front", "rear", "top", "bottom", "left", "right", or relative positions such as "above", "below", "upper side", "lower side", or words limiting directions such as "horizontal direction", "vertical direction", etc., unless otherwise specified, this language refers to the orientation of the drawing.

[0022] The expressions "about", "substantially", "essentially" and "degree" represent within the range of 10% of the corresponding value, preferably within the range of 5%, unless otherwise specified.

[0023] FIGS. 1A, 1B, 1C, 1D, 1E and 1F are cross-sectional views schematically showing in part successive steps of an example of a method of transferring a semiconductor layer from a source substrate to a target substrate according to a first embodiment.

[0024] FIG. 1A shows, in the left part, a structure 110 having a source substrate 13 and a semiconductor layer 15 to be transferred, and in the right part shows a target substrate 17.

[0025] The semiconductor layer 15 to be transferred is disposed, for example, in contact with the upper surface of the source substrate 13 on the upper surface of the source substrate 13. The semiconductor layer 15 extends continuously, for example, with a substantially constant thickness over the entire upper surface of the source substrate 13. The semiconductor layer 15 is, for example, a single crystal layer. By way of example, the semiconductor layer 15 is, for example, a single crystal layer of silicon carbide (SiC) of the 4H-SiC type. As a variant, the semiconductor layer 15 is formed of, for example, single crystal germanium (Ge). The described embodiments are not limited to these specific examples.

[0026] The source substrate 13 is formed of, for example, a semiconductor material. By way of example, the source substrate 13 is formed of the same material as the material of the semiconductor layer 15. However, the described embodiments are not limited to this particular case.

[0027] The thickness of the layer 15 to be transferred is, for example, in the range of 100 nm to 10 μm, for example, in the range of 300 nm to 2 μm.

[0028] The thickness of the source substrate 13 is, for example, in the range of 100 μm to 1 mm, for example, in the range of 250 μm to 800 μm, for example, about 350 μm.

[0029] The target substrate 17 may be formed of a semiconductor material or a dielectric material. The target substrate 17 is, for example, a semiconductor wafer formed of silicon or polysilicon carbide of the 3C-SiC type, for example.

[0030] As an example, the target substrate 17 and the source substrate 13 have substantially the same shape and the same dimensions in plan view. As an example, both the target substrate 17 and the source substrate 13 have a circular shape in plan view and, for example, have the same diameter.

[0031] To limit the risk of breakage, the target substrate 17 and / or the source substrate 13 preferably have a tapered or rounded edge and lip region extending over a surrounding annular strip having a width in the range of, for example, 0.1 mm to 5 mm, for example, 0.2 mm to 3 mm. In other words, the target substrate 17 and / or the source substrate 13 have a peripheral portion with a thickness that decreases as the distance to the center of the substrate increases, extending over a surrounding annular strip having a width in the range of, for example, 0.1 mm to 5 mm, for example, 0.2 mm to 3 mm.

[0032] While bonding the transferred layer 15 onto the target substrate 17, the upper surface of the transferred layer 15 is in contact with the upper surface of the target substrate 17 in the orientation of FIG. 1A.

[0033] In fact, more specifically, when the target substrate 17 and / or the source substrate 13 have a tapered edge, it may be observed that the bonding between the layer 15 and the target substrate 17 is incomplete at the periphery of the assembly. In fact, when bonding the layer 15 to the target substrate 17, the layer 15 and the target substrate 17 are in good contact at the central part of the assembly, but are not in contact or are only partially in contact at the edges of the assembly, particularly due to the tapered portions around the substrate and / or possible unevenness of the surface of the substrate.

[0034] At the end of the step of removing the source substrate 13, the peripheral portion of the layer 15 that is not bonded to the target substrate 17 or is insufficiently bonded to the target substrate 17 breaks. Thus, the surrounding annular strip of the target substrate 17 is not covered or is only partially covered by the layer 15.

[0035] In the absence of specific preventive measures, at the end of the transfer, the edges of layer 15 at the periphery of the assembly are irregular. This is because the bonding boundary between layer 15 and the target substrate 17 is irregular. Due to this irregularity of the edges of layer 15, during subsequent microelectronic component manufacturing processes, for example, during an epitaxy process from the upper surface of layer 15, defects may propagate towards the center of layer 15. The defects may particularly propagate to the epitaxial layer on layer 15.

[0036] In this regard, it is desirable to improve the regularity or sharpness of the edges of layer 15 at the end of the transfer.

[0037] FIG. 1B shows a process of etching a step 29 at the periphery of the upper surface referred to as the bonding surface of layer 15 and etching a step 30 at the periphery of the upper surface referred to as the bonding surface of the target substrate 17.

[0038] The step 29 extends from the upper surface of layer 15, for example, to a part of layer 15. As a variant, the step 29 extends from the upper surface of layer 15 to the substrate 13, for example, to a part of the substrate 13.

[0039] The steps 29 and 30 are formed by, for example, an etching method or an ion ablation method in which a beam of neutral ions 19 or atoms is irradiated onto the area to be etched. This process is carried out under vacuum, that is, at a pressure lower than atmospheric pressure, for example, under ultra-high vacuum, for example, lower than 10 -7 mbar, for example, lower than 10 -8 mbar.

[0040] During the etching process, only the free portions of the upper surfaces of the target substrate 17 and layer 15, that is, the portions of the upper surfaces of layer 15 and the target substrate 17 that are not covered by a mask, are etched.

[0041] In the example of FIG. 1B, in order to form the step 29 only at the peripheral portion of the bonding surface of the layer 15 and the step 30 only at the peripheral portion of the bonding surface of the target substrate 17, the central portions of the bonding surfaces are respectively covered with masking disks. Therefore, during the etching process, the masking disk 31 covers the central portion of the bonding surface of the layer 15, and the masking disk 33 covers the central portion of the bonding surface of the target substrate 17.

[0042] As an example, in a vertical projection, the center of the masking disk 31 coincides with the center of the source substrate 13, and the center of the masking disk 33 coincides with the center of the target substrate 17. As an example, the diameter of the masking disk 31 is smaller than the diameter of the source substrate 13, and the diameter of the masking disk 33 is smaller than the diameter of the target substrate 17. The difference between the diameter of the source substrate 13 and the diameter of the masking disk 31 is, for example, within the range of 0.1 mm to 5 mm, for example, within the range of 0.5 mm to 3 mm, and for example, about 1 mm. The difference between the diameter of the target substrate 17 and the diameter of the masking disk 33 is, for example, within the range of 0.1 mm to 5 mm, for example, within the range of 0.5 mm to 3 mm, and for example, about 1 mm. As an example, the masking disk 31 and the masking disk 33 are identical within the range of manufacturing variations.

[0043] The masking disks 31, 33 are, for example, made of metal and / or formed of a semiconductor material or an insulating material. As an example, during the process of etching the steps 29 and 30, the masking disk 31 is disposed in contact with the upper surface of the semiconductor layer 15 on the upper surface of the semiconductor layer 15, and the masking disk 33 is disposed in contact with the upper surface of the target substrate 17 on the upper surface of the target substrate 17.

[0044] In the illustrated example, the etching of the step 29 of the layer 15 and the etching of the step 30 of the target substrate 17 are performed simultaneously. As a modification, the etching of the step 29 of the layer 15 and the etching of the step 30 of the target substrate 17 are performed continuously.

[0045] As an example, the depth of step 29 from the upper surface of layer 15 is greater than approximately 700 nm, for example greater than approximately 1 μm. As an example, the depth of step 30 from the upper surface of substrate 17 is greater than approximately 700 nm, for example greater than approximately 1 μm. As an example, since the properties of layer 15 and substrate 17 are different, the depths of step 29 and step 30 are not the same.

[0046] At the end of this process, masking disks 31, 33 are removed.

[0047] FIG. 1C shows the process of activating the bonding surface of layer 15 and target substrate 17.

[0048] The method executed during this process is the same etching method or ion ablation method as the method executed during the formation of steps 29 and 30. In particular, according to the aspects of the embodiments of FIGS. 1A - 1F, the activation of the bonding surface by etching or ion ablation is performed in the same ion processing chamber as the etching of steps 29, 30. However, the etching energy and / or etching time are lower than and / or shorter than the etching energy used during the formation of steps 29 and 30 so as to activate the exposed surface without etching a significant thickness of layer 15 and substrate 17.

[0049] During this process, by irradiating the surface to be activated, preferably with a beam of neutral ions 19 or atoms, the dangling bonds used to generate covalent bonds while the activated surface is in contact in a subsequent process are left intact, for example, it is possible to remove oxides that may be present on the surface within the surface to be activated. Such a bonding method enables a bond generally referred to as surface activated bonding (SAB). As an example, during this process, material is removed from the surface to be activated that is less than a few nanometers, for example less than 5 nm. In any case, the thickness of the material removed during this activation process is less than the thickness of the material removed during the formation of steps 29, 30.

[0050] As an example, during the process shown in FIG. 1C, the surface exposure time, for example, decreases, and / or the power of the ion beam 19 decreases with respect to the process shown in FIG. 1B, for example.

[0051] In the illustrated example, the activation of the bonding surface of layer 15 and the activation of the bonding surface of the target substrate 17 are performed simultaneously. The activation of the bonding surface of layer 15 and the activation of the bonding surface of the target substrate 17 are performed continuously while maintaining a vacuum.

[0052] As an example, during this process, the entire surface of the bonding surface of the target substrate 17 and the entire surface of the bonding surface of layer 15 are activated.

[0053] FIG. 1D shows the structure 110 at the end of the process of activating the upper surface of the target substrate 17 and the upper surface of layer 15 and the target substrate 17.

[0054] At this stage, the surface 15' corresponding to the bonding surface of layer 15 that further extends to step 29 and the surface 17' corresponding to the bonding surface of the target substrate 17 that further extends to step 30 are activated in the same manner as the central portions of layer 15 and the target substrate 17.

[0055] FIG. 1E shows the process of bonding the structure 110 to the target substrate 17. During this process, the bonding surface 15' of layer 15 is in contact with the bonding surface 17' of the target substrate 17. Due to the geometric structures of the structure 110 and the target substrate 17, only the central region of the bonding surface of layer 15 defined at step 29 is in contact with the central region of the bonding surface of the target substrate 17 defined at step 30 during this process.

[0056] The dangling bonds generated on the bonding surface of layer 15 and the dangling bonds generated on the bonding surface of substrate 17 form covalent bonds when the bonding surfaces are in contact, securely bonding layer 15 to substrate 17. Since the depths of steps 29 and 30 are large enough, the dangling bonds generated at the peripheral portions of layer 15 in step 29 and the dangling bonds generated at the peripheral portions of substrate 17 in step 30 face each other but do not form covalent bonds.

[0057] As an example, the bonding step is performed at a temperature in the range of 10°C to 400°C, for example 10°C to 40°C, for example at room temperature.

[0058] FIG. 1F shows the structure obtained at the end of the step of removing the source substrate 13 from the structure shown in FIG. 1E.

[0059] As an example, the source substrate 13 is formed of the same semiconductor material as the semiconductor material of layer 15, and for example, an implanted layer (not shown in the drawing) into which hydrogen ions (H+) are implanted separates layer 15 from the source substrate 13. As an example, the structure 110 is initially a single-crystalline semiconductor wafer into which, for example, hydrogen ions are implanted from the upper surface in order to form an implanted layer that separates the transferred layer 15 from the source substrate 13. As an example, when removing the source substrate 13, a thermal annealing step may be performed to decompose the structure 110 at the surface of the implanted layer and remove the source substrate 13, enabling only layer 15 to be retained on the target substrate 17.

[0060] More generally, the source substrate 13 may be removed by any other known method of removing the source substrate while transferring the semiconductor layer from the source substrate to the target substrate, for example, by grinding or laser lift-off.

[0061] While removing the source substrate 13, only the central region of the transferred layer 15 that does not face steps 29, 30 remains bonded to the target substrate 17. However, the peripheral portions of the target substrate 17 that face steps 29 and 30 remain free, that is, are not covered by layer 15.

[0062] Therefore, at the end of the method shown in FIGS. 1A - 1F, the transferred layer 15 has a clear and regular edge that substantially corresponds to the edge of step 29 and / or step 30.

[0063] The activation step of the bonding surface (FIG. 1C) and the bonding step (FIG. 1E) are performed while maintaining a vacuum, for example, in the same apparatus equipped with an activation chamber in which the etching step of FIG. 1B and the activation step of FIG. 1C are performed and a bonding chamber in which the bonding step of FIG. 1E is performed.

[0064] Actually, during the bonding process (FIG. 1E), it is desirable to align the structure such that the central region of the bonding surface of layer 15 defined by step 29 coincides with the central region of the bonding surface of substrate 17 defined by step 30. However, even if the alignment is not perfect, the given solution allows only the portions of the contacting bonding surfaces to adhere to each other, making it possible to obtain a sharp edge of the transferred layer.

[0065] In the example shown in FIG. 1B, for forming step 29 in layer 15, the etching of layer 15 is performed through masking disk 31, and for forming step 30 in target substrate 17, the etching of target substrate 17 is performed through masking disk 33. As a variant, the masking disk may be provided only on layer 15 or only on target substrate 17 for forming a step on one of the two bonding surfaces.

[0066] FIGS. 2A, 2B, 2C, 2D, 2E and 2F are cross-sectional views showing in part and schematically successive steps of an example of a method of transferring a semiconductor layer from a source substrate to a target substrate according to a second embodiment.

[0067] The second embodiment is the same as the first embodiment shown in FIGS. 1A - 1F except that in the second embodiment, the activation of the bonding surface is performed by depositing a thin layer of a bonding material that generates dangling bonds to enable the generation of covalent bonds while the active surfaces are in contact. Elements common to the method of FIGS. 1A - 1F are not described in detail again below. Only the differences from the method of FIGS. 1A - 1F are emphasized.

[0068] FIG. 2A shows, similar to FIG. 1A, on the left side, a structure 110 having a source substrate 13 and a semiconductor layer 15 to be transferred, and on the right side, a target substrate 17.

[0069] FIG. 2B shows, similar to FIG. 1B, the step of etching step 30 at the peripheral portion of the upper surface of target substrate 17 and etching step 29 at the peripheral portion of the upper surface of layer 15.

[0070] FIG. 2C shows the step of activating the bonding surface of layer 15 and the bonding surface of the target substrate 17.

[0071] In this activation step, a thin activation layer, also referred to as a bonding layer, is deposited on the surface to be activated. Thus, in subsequent steps, while the activation surfaces are in contact, it is possible to generate dangling bonds that are used to form covalent bonds. This bonding technique is referred to as atomic diffusion bonding or ADB.

[0072] As an example, during this step, a beam of ions or atoms, such as a neutral gas, such as argon, irradiates a target 24 formed of a material that separates atoms 25 and uniformly deposits them in a thin layer on one or more surfaces to be activated. As an example, the target is made of metal and is formed of, for example, tungsten or titanium. As a variant, the target 24 is formed of a semiconductor material such as, for example, silicon or germanium.

[0073] This step is performed under vacuum, i.e., at a pressure below atmospheric pressure, for example, under ultra-high vacuum, for example, lower than 10 -7 mbar, for example, lower than 10 -8 mbar.

[0074] In the embodiments of FIGS. 2A-2F, the activation of the bonding surface by sputtering of the bonding material is performed in the same ion processing chamber as the etching in steps 29, 30.

[0075] In the example shown, the activation of the bonding surface of layer 15 and the activation of the bonding surface of the target substrate 17 are performed simultaneously. As a variant, the activation of the bonding surface of layer 15 and the activation of the bonding surface of the target substrate 17 are performed continuously while maintaining a vacuum.

[0076] FIG. 2D shows the structure 110 at the end of the step of activating the upper surface of the target substrate 17 and the upper surface of layer 15 and the target substrate 17.

[0077] At this stage, the bonding surfaces of layer 15 and the target substrate 17 are activated, that is, they are covered with layer 27 formed of the material of target 24. As an example, the thicknesses of layer 27 are each greater than 0.2 nm and less than, for example, 100 nm. As an example, the thickness of one or more layers 27 is in the range of 1 nm to 20 nm. In this embodiment, layer 27 further extends to steps 29 and 30 and is thus activated in the same way as the central portions of layer 15 and the target substrate 17.

[0078] FIG. 2E shows the step of bonding the structure 110 of FIG. 2D onto the target substrate 17 of FIG. 2D. During this step, the central portion of the bonding surface of layer 15 defined by step 29 is in contact with the central portion of the bonding surface of the target substrate 17 defined by step 30. More specifically, layer 27 formed on layer 15 is in contact with layer 27 formed on the target substrate 17. Due to the geometric structures of the structure 110 and the target substrate 17, only the central region of the bonding surface of layer 15 defined by step 29 is in contact with the central region of the bonding surface of the target substrate 17 defined by step 30 during this step.

[0079] The dangling bonds of layer 27 deposited on layer 15 and the dangling bonds of layer 27 deposited on the substrate 17 form covalent bonds when layer 27 is in contact, securely bonding layer 15 to the substrate 17. Since the depths of steps 29 and 30 are large enough, the dangling bonds generated at the peripheral portions of layer 15 in step 29 and the dangling bonds generated at the peripheral portions of the substrate 17 in step 30 face each other but do not form covalent bonds.

[0080] As an example, the bonding step is performed at a temperature in the range of 10 °C to 400 °C, for example 10 °C to 40 °C, for example at room temperature.

[0081] As an example, the interfacial resistivity between layer 15 and the target substrate 17 is -3 Ω·cm -2 lower, for example -5 Ω·cm -2 lower. Therefore, an electrically transparent bond can be achieved.

[0082] FIG. 2F shows the structure obtained at the end of the process of removing the source substrate 13 from the structure shown in FIG. 2E.

[0083] As an example, the source substrate 13 is formed of the same semiconductor material as the semiconductor material of layer 15, and an implanted layer (not shown in the drawing) into which, for example, hydrogen ions (H+) are implanted separates layer 15 from the source substrate 13. As an example, the structure 110 is initially a single-crystalline semiconductor wafer into which, for example, hydrogen ions are implanted from above to form an implanted layer that separates the layer 15 to be transferred from the source substrate 13. As an example, when removing the source substrate 13, a thermal annealing process may be performed to disassemble the structure 110 at the plane of the implanted layer and remove the source substrate 13, making it possible to hold only layer 15 on the target substrate 17.

[0084] More generally, the source substrate 13 may be removed by any other known method of removing the source substrate while transferring a semiconductor layer from the source substrate to the target substrate, such as grinding or laser lift-off.

[0085] As described above, during the removal of the source substrate 13, only the central region of the transferred layer 15 that does not face steps 29, 30 remains bonded to the target substrate 17. However, the peripheral portions of the target substrate 17 facing steps 29 and 30 remain free, i.e., are not covered by layer 15.

[0086] Therefore, at the end of the method shown in FIGS. 2A - 2F, the transferred layer 15 has a clear and regular edge that substantially corresponds to the edges of steps 29 and / or 30.

[0087] The activation process of the bonding surface (FIG. 2C) and the bonding process (FIG. 2E) are performed while maintaining a vacuum, for example, within the same apparatus having an activation chamber in which the activation process of FIG. 2C is performed and a bonding chamber in which the bonding process of FIG. 2E is performed.

[0088] In the example shown in FIG. 2B, the etching of layer 15 to form step 29 is performed through masking disk 31, and the etching of target substrate 17 to form step 30 is performed through masking disk 33. As a variant, the masking disk may be provided only on layer 15 or only on target substrate 17 to form a step on one of the two bonding surfaces.

[0089] In fact, during the bonding process, it is desirable to align the structure to match the central region of layer 27 defined by steps 29 and 30. However, even if the alignment is not perfect, with the given solution, only the contacting portions of adjacent layers 27 adhere to each other, making it possible to obtain a sharp edge of the transferred layer.

[0090] The advantage of the methods of FIGS. 1A - 1F and FIGS. 2A - 2F is that it is possible to enhance the sharpness of the boundary between the bonded central region and the unbonded peripheral region of layer 15 by etching steps 29 and / or 30.

[0091] Various embodiments and variants have been described. Those skilled in the art will understand that they can combine certain features of these various embodiments and variants, and other variants will be recalled by those skilled in the art. In particular, the described embodiments are not limited to the examples of materials and dimensions described in this disclosure.

[0092] Furthermore, although the embodiments are described for circular source and target substrates, the source and target substrates may have different shapes.

[0093] Furthermore, the described methods are advantageous for transferring a semiconductor layer from a source substrate to a target substrate, but these methods may also be performed for transferring layers of different properties, such as a metal layer or a dielectric layer, from a source substrate to a target substrate.

[0094] Finally, the actual implementation of the described embodiments and variants is within the scope of the skills of those skilled in the art based on the functional representations described above.

[0095] This application is based on French Patent Application No. 2204713, filed on May 18, 2022, under the title "Procede de transfert d'une couche depuis un substrat source vers un substrat destination", which is considered an essential part of this specification to the extent defined by law, and claims the priority of French Patent Application No. 2204713.

Claims

1. A method of transferring a layer (15) from a source substrate (13) to a target substrate (17), comprising: a) disposing masking disks (31, 33) at a central portion of a bonding surface of the layer (15) and / or the target substrate (17); b) performing ion etching to form steps (29, 30) facing a peripheral portion of the bonding surface of the layer (15) and / or the target substrate (17) that is not covered by the masking disks (31, 33); c) removing the masking disks (31, 33); d) activating the bonding surface of the layer (15) and the bonding surface of the target substrate (17) by ion etching or ion deposition of a bonding material; and e) after step d), bringing the bonding surface of the layer (15) into contact with the bonding surface of the target substrate (17). The method further comprises: continuously performing steps b) and d) in the same ion processing chamber; performing steps d) and e) under vacuum and maintaining the vacuum between steps d) and e).

2. The method according to claim 1, wherein the target substrate (17) and / or the source substrate (13) has a tapered edge over a first width.

3. The method according to claim 2, wherein after step b), the steps (29, 30) extend over a width greater than the first width from an edge of the layer (15) and / or an edge of the target substrate (17).

4. The method according to any one of claims 1 to 3, wherein the masking disks (31, 33) have a diameter smaller than the diameter of the source substrate (13) and / or the diameter of the target substrate (17).

5. The method according to any one of claims 1 to 4, further comprising a step f) of removing the source substrate (13) after step e).

6. The method according to claim 5, wherein step f) comprises an annealing step of decomposing the assembly obtained at the end of step e) at a surface of an implanted buried layer that separates the layer (15) from the source substrate (13).

7. The method according to any one of claims 1 to 6, wherein the layer (15) is a semiconductor layer.

8. The method according to claim 7, further comprising a step of performing epitaxy in contact with the surface of the layer (15) on a surface of the layer (15) on the opposite side of the target substrate (17) after step f).

9. After step b), the said steps (31, 33) extend to a depth exceeding 700 nm from the bonding surface of the said layer (15) and / or the bonding surface of the said target substrate (17), the method according to any one of claims 1 to 8.

10. In step d), a bonding layer (27) is deposited on the bonding surface of the said layer (15) and / or the bonding surface of the said target substrate (17), the method according to any one of claims 1 to 9.

11. The thickness of the said bonding layer (27) is in the range of 0.2 nm to 100 nm, for example in the range of 1 nm to 20 nm, the method according to claim 10.

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