Method for transferring a layer from a source substrate to a target substrate

Abstract

This specification relates to a method of transferring a layer (15) from a source substrate (13) to a target substrate (17), the method comprising: a) activating the bonding surface of the layer (15) and the bonding surface of the target substrate (17) by ion etching of these bonding surfaces or sputtering of a bonding material onto these bonding surfaces; and b) after step a), bringing the bonding surface of the layer (15) into contact with the bonding surface of the target substrate (17), wherein in step a), a masking ring (21) covers the peripheral portion of the bonding surface of the layer (15) and / or a masking ring (23) covers the peripheral portion of the bonding surface of the target substrate, steps a) and b) are carried out under vacuum, and the vacuum is maintained between steps a) and b).

Description

Technical Field

[0001] The present disclosure generally relates to a method of manufacturing microelectronic components based on semiconductor materials. More specifically, the present disclosure aims at a method of transferring a semiconductor layer from a source substrate to a target substrate.

Background Art

[0002] In the method of manufacturing microelectronic components, currently, layer transfer is used to transfer a relatively thin semiconductor layer with high crystal quality onto a thicker target substrate made of a material with lower crystal quality or lower cost.

[0003] After the transfer, the transferred layer may be used as a base for an epitaxial process. Thereafter, microelectronic components can be formed inside and on the epitaxial layer.

Summary of the Invention

Problems to be Solved by the Invention

[0004] It is desirable to at least partially overcome certain disadvantages of known methods for transferring a semiconductor layer from a source substrate to a target substrate.

[0005] Improvement in the quality of the edges of the layer to be transferred is more specifically considered herein.

Means for Solving the Problems

[0006] An embodiment is a method of transferring a layer from a source substrate to a target substrate, comprising: a) activating the bonding surface of the layer and the bonding surface of the target substrate by ion etching of the bonding surface or sputtering of a bonding material onto the bonding surface; and b) after step a), bringing the bonding surface of the layer into contact with the bonding surface of the target substrate having, during step a), a masking ring covering a peripheral portion of the bonding surface of the layer and / or a masking ring covering a peripheral portion of the bonding surface of the target substrate, There is provided a method in which step a) and step b) are carried out under vacuum and the vacuum is maintained between step a) and step b).

[0007] According to an embodiment, the target substrate and / or the source substrate have a tapered edge over a first width.

[0008] According to an embodiment, the masking ring has a width greater than or equal to the first width.

[0009] According to an embodiment, the method has a step c) of removing the source substrate after step b).

[0010] According to an embodiment, step c) has an annealing step of decomposing the assembly obtained at the end of step b) at the surface of the implanted buried layer that separates the layer from the source substrate.

[0011] According to an embodiment, the layer is a semiconductor layer.

[0012] According to an embodiment, the method has a step of performing epitaxy in contact with the surface of the layer on the surface of the layer on the opposite side of the target substrate after step c).

[0013] According to an embodiment, the method has a step of forming a step at the peripheral edge of the layer and / or at the peripheral edge of the target substrate before step a).

[0014] According to an embodiment, the step is formed by ion etching while protecting the central portion of the bonding surface using a masking disk.

[0015] According to an embodiment, the ion etching for forming the step is carried out using the same apparatus as that used in step a) for activating the bonding surface.

[0016] According to an embodiment, the method has a waiting time of at least 10 minutes and / or a cycle of applying a reactive gas between the formation of the step and the activation of the bonding surface.

Brief Description of the Drawings

[0017] The foregoing and other features and advantages are described in detail in the remainder of the disclosure of specific embodiments given by way of example and not limiting the invention with reference to the accompanying drawings.

[0018]

Figure 1A

Figure 1B

Figure 1C

Figure 1D

Figure 1E

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 2E

Figure 3A

Figure 3B

Figure 3C

Figure 3D

Figure 3E

Figure 3F

[0019] In the various figures, like features are denoted by like reference numerals. In particular, structural and / or functional features common to the various embodiments may have the same reference numerals and may have the same structural properties, dimensional properties and material properties.

[0020] For clarity, only the steps and elements useful for understanding the embodiments described herein are illustrated and described in detail. In particular, a method of manufacturing a microelectronic component based on the transferred semiconductor layer is not detailed, and the described transfer methods are compatible with all or most conventional microelectronic component manufacturing methods.

[0021] In the following disclosure, when referring to absolute positions such as "front", "rear", "top", "bottom", "left", "right", etc., or words that limit relative positions such as "above", "below", "upper side", "lower side", etc., or words that limit directions such as "horizontal direction", "vertical direction", etc., unless otherwise specified, this language refers to the orientation of the drawing.

[0022] Expressions such as "about", "substantially", "substantially", and "degree" represent within a range of 10% of the corresponding value, preferably within a range of 5%, unless otherwise specified.

[0023] Figures 1A, 1B, 1C, 1D, and 1E are perspective views that partially and schematically show successive steps of an example method of transferring a semiconductor layer from a source substrate to a target substrate according to a first embodiment.

[0024] Figure 1A shows, in the left part, a structure 110 having a source substrate 13 and a semiconductor layer 15 to be transferred, and shows a target substrate 17 in the right part.

[0025] The semiconductor layer 15 to be transferred is disposed, for example, in contact with the upper surface of the source substrate 13, on the upper surface of the source substrate 13. The semiconductor layer 15 extends continuously with a substantially constant thickness, for example, over the entire upper surface of the source substrate 13. The semiconductor layer 15 is, for example, a single crystal layer. By way of example, the semiconductor layer 15 is a layer of single crystal, for example 4H-SiC type silicon carbide (SiC). As a modification, the semiconductor layer 15 is formed of, for example, single crystal germanium (Ge). The described embodiments are not limited to these specific examples.

[0026] The source substrate 13 is formed of, for example, a semiconductor material. By way of example, the source substrate 13 is formed of the same material as the material of the semiconductor layer 15. However, the described embodiments are not limited to this specific case.

[0027] The thickness of the layer 15 to be transferred is, for example, in the range of 100 nm to 10 μm, and for example, in the range of 300 nm to 2 μm.

[0028] The thickness of the source substrate 13 is, for example, within the range of 100 μm to 1 mm, for example, within the range of 250 μm to 800 μm, and for example, about 350 μm.

[0029] The target substrate 17 may be formed of a semiconductor material or a dielectric material. The target substrate 17 is, for example, a semiconductor wafer formed of silicon or, for example, polysilicon carbide of the 3C - SiC type.

[0030] As an example, the target substrate 17 and the source substrate 13 have substantially the same shape and the same dimensions in plan view. As an example, both the target substrate 17 and the source substrate 13 have a circular shape in plan view and, for example, have the same diameter.

[0031] To limit the risk of breakage, the target substrate 17 and / or the source substrate 13 preferably have a tapered or rounded edge and lip region extending over a peripheral annular strip having a width within the range of, for example, 0.1 mm to 5 mm, for example, 0.2 mm to 3 mm. In other words, the target substrate 17 and / or the source substrate 13 have a thickness at the peripheral edge that decreases as the distance to the center of the substrate increases, over a peripheral annular strip having a width within the range of, for example, 0.1 mm to 5 mm, for example, 0.2 mm to 3 mm.

[0032] When transferring the layer 15 onto the target substrate 17, the layer 15 is in contact with the upper surface of the target substrate 17 with its upper surface in the orientation of FIG. 1A.

[0033] In fact, more specifically, when the target substrate 17 and / or the source substrate 13 have a tapered edge, it can be observed that the bonding between the layer 15 and the target substrate 17 is incomplete at the periphery of the assembly. In fact, when transferring the layer 15 onto the target substrate 17, the layer 15 and the target substrate 17 are in good contact at the central part of the assembly, but are not in contact or only partially in contact at the edges of the assembly, especially due to the tapered part around the substrate and / or possible unevenness on the surface of the substrate.

[0034] At the end of the step of removing the source substrate 13, the peripheral portion of the layer 15 that is not bonded to the target substrate 17 or is insufficiently bonded to the target substrate 17 is damaged. Therefore, the annular strips around the target substrate 17 are not covered by the layer 15 or are only partially covered.

[0035] In the absence of specific preventive measures, after transfer, the edges of the layer 15 at the peripheral portion of the assembly are irregular. This is because the bonding boundary between the layer 15 and the target substrate 17 is irregular. Due to this irregularity of the edge of the layer 15, during subsequent microelectronic component manufacturing processes, for example, during an epitaxy process from the upper surface of the layer 15, defects may propagate towards the center of the layer 15. The defects may particularly propagate to the epitaxial layer on the layer 15.

[0036] In this regard, it is desirable to improve the regularity or sharpness of the edge of the layer 15 at the end of the transfer.

[0037] FIG. 1B shows the activation process of the upper surface referred to as the bonding surface of the layer 15 and the upper surface referred to as the bonding surface of the target substrate 17.

[0038] This activation process is carried out, for example, by an etching method or an ion ablation method in which a beam 19 of neutral ions or atoms is irradiated onto the surface to be activated. By the beam 19, for example, oxides that may be present on the surface within the surface to be activated can be removed, and in subsequent steps, it is possible to generate dangling bonds used to form covalent bonds while the activated surfaces are in contact. Such a bonding method is generally referred to as surface activated bonding (SAB).

[0039] This process is carried out under vacuum, that is, at a pressure lower than atmospheric pressure, for example, under ultra-high vacuum, for example, lower than 10 -7 mbar, for example, lower than 10 -8 mbar.

[0040] In the example of FIG. 1B, during the activation process of the bonding surface, the masking ring 21 covers the peripheral portion of the bonding surface of the layer 15, and the masking ring 23 covers the peripheral portion of the bonding surface of the target substrate 17. As an example, the masking ring 21 has an outer diameter corresponding to the diameter of the source substrate 13. The masking ring 23 has an outer diameter corresponding to the diameter of the target substrate 17, for example. As an example, in a vertical projection, the center of the masking ring 21 coincides with the center of the source substrate 13, and the center of the masking ring 23 coincides with the center of the target substrate 17. The width of the annular strip around the layer 15 covered by the masking ring 21 is within a range of, for example, 0.2 mm to 5.1 mm, within a range of, for example, 0.3 mm to 3.1 mm, and is about 0.5 mm, for example. The width of the annular strip around the target substrate 17 covered by the masking ring 23 is within a range of, for example, 0.2 mm to 5.1 mm, within a range of, for example, 0.3 mm to 3.1 mm, and is about 0.5 mm, for example. As an example, the masking ring 21 and the masking ring 23 are identical within the range of manufacturing variations.

[0041] The masking rings 21 and 23 are made of, for example, metal, and / or are formed of a semiconductor material or an insulating material. As an example, during the activation process of the bonding surface by ion etching, the masking ring 21 is disposed in contact with the bonding surface of the semiconductor layer 15, and the masking ring 23 is disposed in contact with the bonding surface of the target substrate 17.

[0042] In the illustrated example, the activation of the bonding surface of the layer 15 and the activation of the bonding surface of the target substrate 17 are performed simultaneously. As a modification, the activation of the bonding surface of the layer 15 and the activation of the bonding surface of the target substrate 17 are performed continuously while maintaining a vacuum.

[0043] During the activation process, only the free portions of the bonding surfaces of the target substrate 17 and the layer 15 to be transferred, that is, the portions of the bonding surfaces of the layer 15 and the target substrate 17 not covered by the masking rings 21, 23, are activated. In particular, surface dangling bonds configured to generate covalent bonds for later bonding the layer 15 onto the target substrate 17 are generated only in the central portion not covered by the masking rings 21, 23 of the bonding surfaces of the layer 15 and the target substrate 17. However, activation, and in particular the generation of dangling bonds, does not occur at the peripheral portions of the bonding surfaces of the layer 15 and the target substrate 17 covered by the masking rings 21, 23.

[0044] Figure 1C shows the structure 110 and the target substrate 17 after removal of the masking rings 21, 23 at the end of the activation process of the bonding surfaces of the target substrate 17 and the layer 15.

[0045] At this stage, the central portion 15' of the bonding surface of the layer 15 is activated, and the central portion 17' of the bonding surface of the target substrate 17 is activated. However, the peripheral portion 15'' of the bonding surface of the layer 15 and the peripheral portion 17'' of the bonding surface of the target substrate 17 remain inactive and do not contain dangling bonds that would enable the generation of covalent bonds.

[0046] Figure 1D shows the process of bonding the structure 110 of Figure 1C onto the target substrate 17 of Figure 1C. During this process, the bonding surface of the layer 15 is in contact with the bonding surface of the target substrate 17.

[0047] The dangling bonds generated in the activated portion 15' of the bonding surface of the layer 15 and the dangling bonds generated in the activated portion 17' of the bonding surface of the substrate 17 generate covalent bonds when the bonding surfaces are in contact, and securely bond the layer 15 onto the substrate 17.

[0048] As an example, the bonding process is carried out at a temperature in the range of 10°C to 400°C, for example 10°C to 40°C, for example at room temperature.

[0049] FIG. 1E shows the structure obtained at the end of the step of removing the source substrate 13 so as to hold only the layer 15 to be transferred on the bonding surface of the target substrate 17.

[0050] As an example, the source substrate 13 is formed of the same semiconductor material as the semiconductor material of the layer 15. For example, an implanted layer (not shown in the drawing) into which hydrogen ions (H+) are implanted separates the layer 15 from the source substrate 13. As an example, the structure 110 is initially a single-crystalline semiconductor wafer into which, for example, hydrogen ions are implanted from above to form an implanted layer that separates the layer 15 to be transferred from the source substrate 13. As an example, when removing the source substrate 13, a thermal annealing process may be performed to decompose the structure 110 at the surface of the implanted layer and remove the source substrate 13, thereby enabling only the layer 15 to be held on the target substrate 17.

[0051] More generally, the source substrate 13 may be removed by any other known method of removing the source substrate while transferring the semiconductor layer from the source substrate to the target substrate, such as grinding or laser lift-off.

[0052] During the removal of the source substrate 13, only the central region of the layer 15 facing the activated portion 15' of the bonding surface remains bonded to the activated portion 17' of the bonding surface of the target substrate 17. However, the non-activated peripheral portion 17'' of the bonding surface of the target substrate 17 remains free, that is, it is not covered by the layer 15.

[0053] Therefore, at the end of the method shown in FIGS. 1A - 1E, the transferred layer 15 has a clear and regular edge that substantially corresponds to the inner edge of the masking ring 21 attached during the activation step of FIG. 1B.

[0054] The surface activation step and the bonding step are performed while maintaining a vacuum. As an example, the surface activation step (FIG. 1B) and the bonding step (FIG. 1D) are performed in the same apparatus including, for example, an activation chamber in which the activation step of FIG. 1B is performed and a bonding chamber in which the bonding step of FIG. 1D is performed.

[0055] In fact, during the bonding process (Figure 1D), it is desirable to align the structures so that the activation surface 15' of layer 15 coincides with the activation surface 17' of substrate 17. However, even if the alignment is not perfect, with the given solution, only the portions of the contacting activation surfaces 15' and 17' adhere to each other, making it possible to obtain a sharp edge of the transferred layer.

[0056] In the example shown in Figure 1B, it should be noted that the bonding surface of layer 15 is activated through masking ring 21, and the bonding surface of target substrate 17 is activated through masking ring 23. As a variant, the masking ring may be provided only on the bonding surface of layer 15, or only on the bonding surface of target substrate 17. In this case, while the bonding surfaces are in contact, dangling bonds are generated only on one of the two bonding surfaces, so the bonding of layer 15 to target substrate 17 does not occur at the periphery of the assembly. The advantage of this variant is that the required alignment accuracy is lower.

[0057] Figures 2A, 2B, 2C, 2D, and 2E are cross-sectional views partially and schematically showing successive steps of an example of a method for transferring a semiconductor layer from a source substrate to a target substrate according to a second embodiment.

[0058] The second embodiment is the same as the first embodiment shown in Figures 1A - 1E, except that in the second embodiment, the activation of the bonding surface is performed by depositing a thin layer of bonding material that generates dangling bonds, enabling the formation of covalent bonds while the activation surfaces are in contact. Elements common to the method of Figures 1A - 1E will not be detailed again below. Only the differences from the method of Figures 1A - 1E are emphasized.

[0059] Figure 2A shows, as in Figure 1A, a structure 110 having a source substrate 13 and a semiconductor layer 15 to be transferred on the left side, and a target substrate 17 on the right side.

[0060] Figure 2B shows the activation process of the upper surface, referred to as the bonding surface of layer 15, and the upper surface, referred to as the bonding surface of target substrate 17.

[0061] In this activation process, a thin activation layer is deposited on the surface to be activated. Therefore, in subsequent processes, while the activation layer is in contact, it is possible to generate dangling bonds that are used to form covalent bonds. This bonding technique is referred to as atomic diffusion bonding or ADB.

[0062] As an example, during this process, a beam of ions or atoms, such as a neutral gas, such as argon, separates atoms 25 and irradiates a target 24 formed of a material that is uniformly deposited in a thin layer on one or more surfaces to be activated. As an example, the target is made of metal and is formed of, for example, tungsten or titanium. As a variant, the target 24 is formed of a semiconductor material such as, for example, silicon or germanium.

[0063] This process is carried out under vacuum, that is, at a pressure lower than atmospheric pressure, for example, under ultra-high vacuum, for example, lower than 10 -7 mbar, for example, lower than 10 -8 mbar.

[0064] Similar to the method described above, during activation, the masking ring 21 covers the bonding surface of the layer 15, and the masking ring 23 covers the bonding surface of the target substrate 17.

[0065] In the illustrated example, the activation of the bonding surface of the layer 15 and the activation of the bonding surface of the target substrate 17 are carried out simultaneously. As a variant, the activation of the bonding surface of the layer 15 and the activation of the bonding surface of the target substrate 17 are carried out continuously while maintaining the vacuum.

[0066] Similar to the method described above, during the activation process, only the free portions of the bonding surfaces of the target substrate 17 and the layer 15, that is, the portions of the bonding surfaces of the layer 15 and the target substrate 17 that are not covered by the masking rings 21, 23, are activated.

[0067] Figure 2C shows the structure 110 and the target substrate 17 at the end of the activation process of the bonding surfaces of the target substrate 17 and the layer 15 after the masking rings 21, 23 have been removed.

[0068] At this stage, the central portion of the bonding surface of layer 15 and the central portion of the bonding surface of the target substrate 17 are active, that is, they are covered with layer 27 formed of the material of target 24. As an example, the thicknesses of layer 27 are each greater than 0.2 nm and, for example, less than 100 nm. As an example, the thickness of one or more layers 27 is in the range of 1 nm to 20 nm.

[0069] In this example, the peripheral portion 15'' of the bonding surface of layer 15 and the peripheral portion 17'' of the bonding surface of the target substrate 17 are not activated, that is, they are not covered with layer 27, and thus do not include dangling bonds that can form covalent bonds to bond layer 15 to the target substrate 17.

[0070] FIG. 2D shows the process of bonding the structure 110 of FIG. 2C onto the target substrate 17 of FIG. 2C. During this process, the bonding surface of layer 15 is in contact with the bonding surface of the target substrate 17. More specifically, layer 27 formed on layer 15 and layer 27 formed on the target substrate 17 are in contact.

[0071] The dangling bonds of layer 27 deposited on layer 15 and the dangling bonds of layer 27 deposited on substrate 17 form covalent bonds when layer 27 is in contact, securely bonding layer 15 to substrate 17.

[0072] As an example, the bonding process is carried out at a temperature in the range of 10 °C to 400 °C, for example 10 °C to 40 °C, for example at room temperature.

[0073] As an example, the interfacial resistivity between layer 15 and the target substrate 17 is lower than 10 -3 Ω·cm -2 and, for example, lower than 10 -5 Ω·cm -2 Thus, an electrically transparent bond becomes possible.

[0074] FIG. 2E shows the structure obtained at the end of the process of removing the source substrate 13 from the structure shown in FIG. 2D.

[0075] As described above, while removing the source substrate 13, only the central region of the transferred layer 15 facing the activated portion of the bonding surface remains bonded to the target substrate 17. However, the peripheral portion 17'' of the target substrate 17 facing the non-activated portion of the bonding surface remains free, i.e., it is not covered by the layer 15.

[0076] Here too, the bonding surface activation step (Fig. 2B) and the bonding step (Fig. 2D) are carried out while maintaining a vacuum, for example, within the same apparatus having, for example, an activation chamber in which the activation step of Fig. 2B is carried out and a bonding chamber in which the bonding step of Fig. 2D is carried out.

[0077] In the example shown in Fig. 2B, the bonding surface of the layer 15 is activated through the masking ring 21, and the bonding surface of the target substrate 17 is activated through the masking ring 23. As a variant, the masking ring may be provided only on the bonding surface of the layer 15 or only on the bonding surface of the target substrate 17. In this case, while the bonding surfaces are in contact, only dangling bonds are generated on one of the two bonding surfaces, so that the bonding of the layer 15 to the target substrate 17 does not occur at the periphery of the assembly.

[0078] In fact, during the bonding step, it is desirable to align the structures so that the activated surfaces of the two structures coincide. However, even if the alignment is not perfect, with the given solution, only the portions of the contacting activated surfaces adhere to each other, making it possible to obtain a sharp edge of the transferred layer.

[0079] Figs. 3A, 3B, 3C, 3D, 3E and 3F are cross-sectional views partially and schematically showing successive steps of an example of a method for transferring a semiconductor layer from a source substrate 13 to a target substrate 17 according to a third embodiment.

[0080] The third embodiment is the same as the first embodiment shown in FIGS. 1A to 1E, except that it has a step of etching steps on the peripheral edge of the target substrate 17 and the peripheral edge of the layer 15 before the step of bonding the layer 15 onto the target substrate 17. Regarding the elements common to the method of FIGS. 1A to 1E, they will not be described in detail again below. Only the differences from the method of FIGS. 1A to 1E are emphasized.

[0081] FIG. 3A shows, similar to FIG. 1A, a structure 110 having a source substrate 13 and a semiconductor layer 15 to be transferred on the left side, and a target substrate 17 on the right side.

[0082] FIG. 3B shows the step of etching a step 30 on the peripheral edge of the upper surface of the target substrate 17 and a step 29 on the peripheral edge of the upper surface of the layer 15.

[0083] The steps 29 and 30 are formed, for example, by an etching method or an ion ablation method in which a neutral ion 19 or an atomic beam is irradiated onto the area to be etched. This step is performed under vacuum, that is, at a pressure lower than atmospheric pressure, for example, under ultra-high vacuum, for example, lower than 10 -7 mbar, for example, lower than 10 -8 mbar.

[0084] During the etching process, only the free portions of the upper surfaces of the target substrate 17 and the layer 15, that is, the portions of the upper surfaces of the layer 15 and the target substrate 17 not covered by the mask, are etched.

[0085] In the example of FIG. 3B, in order to form the step 29 only on the peripheral edge of the bonding surface of the layer 15 and the step 30 only on the peripheral edge of the bonding surface of the target substrate 17, the central portions of the bonding surfaces are each covered with a masking disk. Therefore, during the etching process, the masking disk 31 covers the central portion of the bonding surface of the layer 15, and the masking disk 33 covers the central portion of the bonding surface of the target substrate 17.

[0086] As an example, in the vertical projection, the center of the masking disk 31 coincides with the center of the source substrate 13, and the center of the masking disk 33 coincides with the center of the target substrate 17. As an example, the diameter of the masking disk 31 is smaller than the diameter of the source substrate 13, and the diameter of the masking disk 33 is smaller than the diameter of the target substrate 17. The difference between the diameter of the source substrate 13 and the diameter of the masking disk 31 is, for example, within the range of 0.2 mm to 5 mm, for example, within the range of 0.5 mm to 3 mm, and for example, about 1 mm. The difference between the diameter of the target substrate 17 and the diameter of the masking disk 33 is, for example, within the range of 0.2 mm to 5 mm, for example, within the range of 0.5 mm to 3 mm, and for example, about 1 mm. As an example, the masking disk 31 and the masking disk 33 are identical within the range of manufacturing variations.

[0087] The masking disks 31, 33 are, for example, made of metal and / or formed of a semiconductor material or an insulating material. As an example, during the process of etching the steps 29 and 30, the masking disk 31 is disposed in contact with the upper surface of the semiconductor layer 15, and the masking disk 33 is disposed in contact with the upper surface of the target substrate 17.

[0088] In the illustrated example, the etching of the step 29 of the layer 15 and the etching of the step 30 of the target substrate 17 are performed simultaneously. As a modification, the etching of the step 29 of the layer 15 and the etching of the step 30 of the target substrate 17 are performed continuously.

[0089] As an example, the depth of the step 29 from the upper surface of the layer 15 is greater than approximately 10 nm, for example, greater than approximately 50 nm. As an example, the depth of the step 30 from the upper surface of the substrate 17 is greater than approximately 10 nm, for example, greater than approximately 50 nm. As an example, since the properties of the layer 15 and the substrate 17 are different, the depths of the steps 29 and 30 are not the same.

[0090] At the end of this process, the masking disks 31, 33 are removed.

[0091] Figure 3C shows the process of activating the bonding surface of the layer 15 and the target substrate 17.

[0092] The method executed during this step is the same etching method or ion ablation method as the method executed during the formation of steps 29 and 30. However, the etching energy and / or etching time are lower than and / or shorter than the etching energy used during the formation of steps 29 and 30 in order to activate the exposed surface without etching a significant thickness of layer 15 and substrate 17. During this step, by irradiating the activated surface with, for example, a beam of neutral ions 19 or atoms, while the activated surface is being contacted in a subsequent step, the dangling bonds used to form covalent bonds are left intact while, for example, removing oxides that may be present on the surface within the activated surface. As an example, during this step, the material removed from the activated surface is less than a few nanometers, for example less than 5 nm. In any case, the thickness of the material removed during this activation step is less than the thickness of the material removed during the formation of steps 29 and 30.

[0093] As an example, during the step shown in Figure 3C, the surface exposure time decreases, for example, and / or the power of the ion beam 19 decreases relative to the step shown in Figure 3B, for example.

[0094] Similar to the method described above with respect to Figure 1B, during activation, masking ring 21 covers the bonding surface of layer 15 and masking ring 23 covers the bonding surface of target substrate 17.

[0095] In the example shown, the activation of the bonding surface of layer 15 and the activation of the bonding surface of target substrate 17 are performed simultaneously. The activation of the bonding surface of layer 15 and the activation of the bonding surface of target substrate 17 are performed continuously while maintaining a vacuum.

[0096] Similar to the method described above, during the activation step, only the free portions of the bonding surfaces of target substrate 17 and layer 15, i.e., the portions of the bonding surfaces of layer 15 and target substrate 17 not covered by masking rings 21, 23, are activated.

[0097] As an example, the inner diameter of the masking ring 21 is equal to or greater than the diameter of the masking disk 31. Similarly, the inner diameter of the masking ring 23 is equal to or greater than the diameter of the masking disk 33. Therefore, the layer 15 has a free portion at the step 29, and the substrate 17 has a free portion at the step 30. Thus, these free portions of the steps 29 and 30 are activated during this process.

[0098] As an example, the step of etching the steps 29, 30 (FIG. 3B) and the step of activating the bonding surface through the masking ring (FIG. 3C) are spaced apart by several minutes, for example, at least about 15 minutes, in order to reduce the activation of the ring etched in the step of FIG. 3B. This waiting time may be provided while maintaining a vacuum between the two steps. As a modification, this waiting time may be replaced, for example, by using a load port, with a cycle of returning the chamber or a part of the chamber to an atmosphere containing a higher pressure, for example, atmospheric pressure, for example, a reactive gas such as nitrogen or oxygen. Again, for this reason, the activation of the etched ring can be reduced, that is, the dangling bonds on the surface of the etched ring can be invalidated.

[0099] FIG. 3D shows the structure 110 and the target substrate 17 at the end of the activation step of the upper surfaces of the target substrate 17 and the layer 15 after removing the masking rings 21, 23.

[0100] At this stage, the central portion 15' of the bonding surface of the layer 15 that further extends to the step 29 and the central portion 17' of the bonding surface of the target substrate 17 that further extends to the step 30 are activated. However, the peripheral portion 15'' of the bonding surface of the layer 15 and the peripheral portion 17'' of the bonding surface of the target substrate 17 remain inactive and do not contain dangling bonds that enable the formation of covalent bonds. As an example, the peripheral portion 15'' and the peripheral portion 17'' are respectively arranged at the steps 29 and 30. As an example, the peripheral portion 15'' extends over a width smaller than the width of the step 29, and similarly, the peripheral portion 17'' extends over a width smaller than the width of the step 30.

[0101] FIG. 3E shows the step of bonding the structure 110 to the target substrate 17. During this step, the bonding surface of layer 15 is in contact with the bonding surface of the target substrate 17. Different from the bonding step shown in FIG. 1D, in FIG. 3E, only the central region of the bonding surface of layer 15 defined by step 29 is in contact with the central region of the bonding surface of the target substrate 17 defined by step 30.

[0102] The dangling bonds generated in the activated portion 15' of the bonding surface of layer 15 and the dangling bonds generated in the activated portion 17' of the bonding surface of substrate 17 form covalent bonds when the bonding surfaces are in contact, securely bonding layer 15 to substrate 17.

[0103] As an example, the bonding step is performed at a temperature in the range of 10 °C to 400 °C, for example, 10 °C to 40 °C, for example, at ambient temperature.

[0104] FIG. 3F shows the structure obtained at the end of the step of removing the source substrate 13 from the structure shown in FIG. 3E.

[0105] During the removal of the source substrate 13, only the central region of layer 15 that is transferred other than steps 29 and 30, which faces the activated portion of the bonding surface, remains bonded to the target substrate 17. However, the peripheral portions of the target substrate 17 facing steps 29 and 30 remain free, that is, not covered by layer 15.

[0106] Here too, the activation step (FIG. 3C) and the bonding step (FIG. 3E) of the bonding surface are performed while maintaining a vacuum, for example, in the same apparatus equipped with an activation chamber where the etching step of FIG. 3B and the activation step of FIG. 3C are performed and a bonding chamber where the bonding step of FIG. 3E is performed.

[0107] In the example shown in FIG. 3B, the etching of layer 15 to form step 29 is performed through masking disk 31, and the etching of target substrate 17 to form step 30 is performed through masking disk 33. As a modification, the masking disk may be provided only on layer 15 or only on target substrate 17 to form a step on one of the two bonding surfaces.

[0108] Furthermore, in the example shown in FIG. 3C, the bonding surface of layer 15 is activated through masking ring 21, and the bonding surface of target substrate 17 is activated through masking ring 23. As a modification, the masking ring may be provided only on the bonding surface of layer 15 or only on the bonding surface of target substrate 17. In this case, while the bonding surfaces are in contact, since the dangling bonds are generated only on one of the two bonding surfaces, the bonding of layer 15 to target substrate 17 is not performed at the peripheral portion of the assembly.

[0109] The advantage of the method of FIGS. 3A to 3F is that it is possible to enhance the sharpness of the boundary between the bonded central region and the unbonded peripheral region of layer 15 by etching step 29 and / or step 30. However, since the bonding surfaces are defined by masking ring 21 and / or masking ring 23, step 29 and / or step 30 may be relatively shallow, for example, having a depth less than 500 nm, preferably less than 100 nm.

[0110] A more detailed example of the implementation of the method of FIGS. 2A to 2E is described. In this example, the single crystal layer of 4H-SiC of a 4H-SiC source substrate is transferred onto a target substrate corresponding to a polycrystalline 3C-SiC wafer. In this example, hydrogen ions are implanted into the 4H-SiC wafer to form an implanted layer, and the implanted layer defines the layer to be transferred onto the target substrate. The implantation process is, for example, 5×10 16 at / cm 2It is carried out with an amount of about and an energy of about 95 keV. Further, in this example, after the implantation process, a cleaning process can be performed on the 4H-SiC wafer and the 3C-SiC wafer to remove surface contaminants. After the cleaning process, the two wafers are introduced into the film deposition chamber of the ADB apparatus. In the film deposition chamber, the upper surfaces of the two wafers are each covered with a silicon film deposited through an annular mask that covers the peripheral portion over a width of about 1 mm. In this example, the annular mask is formed of fused silica. This process is carried out at ambient temperature under an ultra-high vacuum corresponding to a pressure of 10 -6 Pa (i.e., 10 -8 mbar). At the end of this process, the upper surface of each of the two 4H-SiC wafers and 3C-SiC wafers is covered with a silicon film having a thickness greater than 1 nm and less than 20 nm over the entire upper surface except for a ring having a width of about 1 mm at the edge of the wafer. While maintaining the vacuum, in another bonding chamber, the two wafers are bonded with care so that the silicon films formed on each of the two 4H-SiC wafers and 3C-SiC wafers are in contact. Thereafter, the bonded assembly is heat-treated to decompose the 4H-SiC wafer at the level of the implanted layer between the transferred layer and the source substrate, and thus remove the source substrate. The heat treatment is carried out, for example, at approximately 900 °C for about 30 minutes. A polishing process and / or a cleaning process may be performed, and then a new annealing may be carried out on the structure formed by the target substrate and the transferred layer at about 1,700 °C for about 30 minutes.

[0111] A more detailed example of the implementation of the method of FIGS. 3A to 3F is described. In this example, a germanium film is transferred from a source substrate corresponding to a germanium wafer to a target substrate corresponding to a silicon wafer. In this example, hydrogen ions are implanted into the germanium wafer to form an implanted layer, and the implanted layer defines the layer to be transferred to the target substrate. The implantation process is carried out with an amount of 5.5 × 10 16 at / cm 2 and an energy of approximately 100 keV. Further, in this example, after the implantation process, the silicon wafer and the germanium wafer are placed under ultra-high vacuum (i.e., 10 -7It is introduced into the activation chamber of the SAB device (less than mbar). In the activation chamber, the upper surfaces of the silicon wafer and the germanium wafer are etched respectively through a disk made of silicon and having a diameter about 3 mm smaller than the diameter of the wafer. The etching is performed while the wafer is rotating at a speed of, for example, about 70 rpm. The etching is performed for about 10 minutes under an argon flow having an energy of about 200 eV and an intensity of about 150 mA. At the end of the etching process, the two wafers are transferred to a load port where the pressure is increased to 500 mbar by a nitrogen flow, and then returned to ultra-high vacuum by purging with an argon flow at 500 mbar. Next, the wafers are returned to the activation chamber under ultra-high vacuum. Thereafter, the upper surfaces of the two wafers are activated respectively for 1 minute with argon atoms having an energy of about 200 eV and an intensity of about 150 mA through an annular mask made of silicon covering the peripheral portion over a width of about 2.5 mm. While maintaining the vacuum, in another bonding chamber, the two wafers are bonded carefully so that the activated surfaces of each of the two germanium wafers and the silicon wafer are in contact. The bonding process is performed at a temperature of about 250 °C under ultra-high vacuum. Thereafter, the bonded assembly is heat-treated to decompose the germanium wafer between the transferred layer and the source substrate at the level of the implanted layer, and thus remove the source substrate. The heat treatment is performed, for example, at approximately 330 °C for about 10 hours. In this example, a germanium film of about 800 nm is transferred onto silicon.

[0112] Various embodiments and variations are described. Those skilled in the art will understand that they can combine certain features of these various embodiments and variations, and other variations will be envisioned by those skilled in the art. In particular, the described embodiments are not limited to the examples of materials and dimensions described in this disclosure.

[0113] Furthermore, the embodiments of FIGS. 2A-2E and the embodiments of FIGS. 3A-3F may be combined. More precisely, the surface activation during the process shown in FIG. 3C may be performed according to the activation method described in connection with FIG. 2B.

[0114] Furthermore, although the embodiments have been described with respect to circular source and target substrates, the source and target substrates may have different shapes.

[0115] Furthermore, while the methods described are advantageous for transferring a semiconductor layer from a source substrate to a target substrate, these methods may further be performed for transferring layers of different properties, such as a metal layer or a dielectric layer, from a source substrate to a target substrate.

[0116] Furthermore, in the described embodiments, the masking ring may be replaced by a frame or an oval ring. Further, the edge of the masking ring may be wavy and may not have a circular shape.

[0117] Finally, the actual implementation of the described embodiments and variations is within the skill of one of ordinary skill in the art based on the functional descriptions provided above.

[0118] This application is based on French Patent Application No. 2204711, filed on May 18, 2022, under the title "Procede de transfert d'une couche depuis un substrat source vers un substrat destination", which is considered an essential part of this specification to the extent defined by law, and claims the priority of French Patent Application No. 2204711.

Claims

1. A method of transferring a layer (15) from a source substrate (13) to a target substrate (17), comprising: a) activating the bonding surface of the layer (15) and the bonding surface of the target substrate (17) by ion etching of the bonding surface or sputtering of a bonding material (27) onto the bonding surface; and b) after step a), bringing the bonding surface of the layer (15) into contact with the bonding surface of the target substrate (17). The method further comprises: During step a), a masking ring (21) covers the peripheral portion (15'') of the bonding surface of the layer (15) and / or a masking ring (23) covers the peripheral portion (17'') of the bonding surface of the target substrate (17); Steps a) and b) are performed under vacuum, and the vacuum is maintained between steps a) and b).

2. The method according to claim 1, wherein the target substrate (17) and / or the source substrate (13) has a tapered edge over a first width.

3. The method according to claim 2, wherein the masking ring has a width greater than or equal to the first width.

4. The method according to any one of claims 1 to 3, further comprising step c) of removing the source substrate (13) after step b).

5. The method according to claim 4, wherein step c) comprises an annealing step of decomposing the assembly obtained in step b) at the surface of an implanted buried layer that separates the layer (15) from the source substrate (13).

6. The method according to any one of claims 1 to 5, wherein the layer (15) is a semiconductor layer.

7. The method according to claim 6, which depends on claim 4, further comprising, after step c), an epitaxy step of contacting the surface of the layer (15) with the surface of the layer (15) on the opposite side of the target substrate (17).

8. The method according to any one of claims 1 to 7, further comprising, before step a), a step of forming steps (29, 30) on the peripheral portion of the layer (15) and / or the peripheral portion of the target substrate (17).

9. The method according to claim 8, wherein the steps (29, 30) are formed by ion etching by protecting the central portion of the bonding surface using a masking disk.

10. The method according to claim 9, wherein the ion etching for forming the steps (29, 30) is performed using the same apparatus as that used in step a) for activating the bonding surface.

11. The method according to claim 10, having a waiting time of at least 10 minutes and / or a cycle of applying a reactive gas between the formation of the segments (29, 30) and the activation of the bonding surface.

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