Neuron Circuit for Spiking Neural Network

Abstract

A neuron circuit is provided for a spiking neural network device having a plurality of such neuron circuits interconnected by links each associated with a respective weight for transmission of signals between the neuron circuits. The neuron circuit includes a digital transmitter for generating a trigger signal indicative of the state of the neuron circuit on an output link of the circuit. The state is encoded in time intervals defined by these trigger signals. The neuron circuit includes a digital receiver for detecting such trigger signals on an input link of the circuit and digital accumulator logic. In response to detecting a trigger signal on the input link, the digital accumulator logic is adapted to generate a weighted signal corresponding to the time interval and accumulate the weighted signals generated from the trigger signals on the input link to determine the state of the neuron circuit.

Description

Technical Field

[0001] The present invention generally relates to neuron circuits of spiking neural networks. A digital neuron circuit and a spiking neural network device using such a circuit are provided.

Background Art

[0002] A spiking neural network (SNN) is an efficient class of artificial neural networks. In an SNN, a network of interconnected neurons communicates via a sequence of spikes, thus approximating biological neural networks. Spike trains convey information about the state of individual neurons and are generally interpreted as all-or-none signals corresponding to binary communication with 1 and 0. Spikes (1) are sparse and asynchronous, leading to highly efficient operation.

[0003] Neural encoding relates to the manner in which information is communicated via electrical signals (often called "action potentials") at the level of individual neurons in an SNN. The goal of neural encoding methods is to enable fast and reliable processing of neural information. Rate encoding, in which information is encoded in the spiking rate of neurons, has been the dominant paradigm for many years. However, estimating the firing rate of neurons reliably requires transmitting a large number of spikes, resulting in significant delays. Time encoding methods, which base neural communication on the precise timing of action potentials, enable significantly faster information processing.

[0004] A neuron circuit for efficiently implementing a time-encoded SNN is highly desired.

Summary of the Invention

[0005] A first aspect of the present invention provides a neuron circuit for use in a spiking neural network device having a plurality of such neuron circuits interconnected by links each associated with a respective weight for the transmission of signals between neuron circuits. The neuron circuit includes a digital transmitter for generating a trigger signal indicative of the state of the neuron circuit on an output link of the circuit. The state is encoded in time intervals defined by these trigger signals. The neuron circuit further includes a digital receiver having a signal detector for detecting such trigger signals on an input link of the circuit and digital accumulator logic. The digital accumulator logic is adapted to generate a weighted signal according to the time interval defined by the trigger signal and the weight associated with the input link in response to the detection of the trigger signal on the input link, and to accumulate the weighted signals generated from the trigger signals on the input link to determine the state of the neuron circuit.

[0006] Embodiments of the present invention provide a digital neuron circuit for efficiently implementing a time-encoded SNN in a full digital implementation. As will be described in detail below, the embodiments can easily implement the TTS (Time-to-Spike) or TTFS (Time-to-First-Spike) encoding techniques, and particularly advantageous embodiments provide selective operation in both of these encoding modes.

[0007] To implement TTS encoding, the digital accumulator logic can be adapted to determine the state of the neuron circuit at the end of each period T by periodically accumulating the weighted signal at period T. The transmitter then generates a trigger signal indicating that state during the next period T. The transmitter can be adapted such that the trigger signal defines a time interval with reference to the end of the next period T. This provides an implementation with minimal delay. Alternatively, the transmitter can be adapted such that the trigger signal defines a time interval with reference to the start of the next period T. This provides a robust implementation that does not require link skew calibration.

[0008] The digital accumulator logic of the TTS encoding embodiment can be conveniently implemented by counter logic. The counter logic is adapted to generate a thermomotor encoding output value corresponding to the time interval defined by the trigger signal on that link for each input link, and the graphical multiplication logic is adapted to multiply the thermomotor encoding output value by the weight associated with that link for each input link to obtain a component of the weighted signal for that link. The accumulator logic further includes summation logic adapted to generate a weighted signal for each input link by summing the aforementioned components and to create an accumulated signal indicating the neuron state by summing the weighted signals generated during each period T. Since the trigger signal is processed purely in the digital domain by the graphical multiplication approach, an ADC (Analog-to-Digital Converter) is not required for the receiver here. The summation logic can be implemented very efficiently using a carry-save adder and a ripple-carry adder.

[0009] To implement TTFS encoding, digital accumulator logic can be adapted to determine the state of the neuron circuit during a period T' by accumulating weighted signals between each of successive periods T' to create an accumulated signal, and progressively comparing the accumulated signal with a threshold. The transmitter then generates a trigger signal in response to the accumulated signal exceeding the threshold during that period T'. In some embodiments herein, the digital accumulator logic is adapted to generate the weighted signal for each input link by starting the integration of a value corresponding to the weight associated with that link in response to detection of the trigger signal for that link, and includes a digital integrator adapted to generate an accumulated signal by summing the weighted signals generated during each period T'. Again, since all trigger signals are processed in the digital domain, no ADC is required at the receiver. These embodiments also provide a low complexity and low area implementation where the weights can be stored in simple registers. The digital integrator can efficiently implement the summing logic using carry-save adders and ripple-carry adders and can be implemented in a straightforward manner by a concatenated counter.

[0010] Advantageously, in embodiments of TTFS, the digital accumulator logic includes weighted logic adapted to generate a weighted signal for each input link by outputting a weighted value corresponding to the weight associated with that link in response to detection of the trigger signal on that link, and a digital integrator adapted to generate an accumulated signal by integrating the weighted values output by the weighted logic of the input links during the period T'. Thus, by having a global integrator for all input links, a particularly simple and low area implementation is provided. Further, a simple and efficient global integrator can be implemented by using carry-save adders and ripple-carry adders.

[0011] In a particularly advantageous embodiment, the digital accumulator logic is adapted to accumulate weighted signals during successive periods T' to generate an accumulated signal, and the neuron circuit is selectively operable in a first mode and a second mode. In the first mode, the digital accumulator logic is adapted to determine the state of the neuron circuit during that period T' by progressively comparing a threshold value with the accumulated signal during each period T', and the transmitter is adapted to generate a trigger signal during that period T' in response to the accumulated signal exceeding the threshold value. In the second mode, the digital accumulator logic is adapted to determine the state of the neuron circuit in response to the accumulated signal at the end of each period T', and the transmitter is adapted to generate a trigger signal indicating that state during the next period T'. Thus, in these embodiments, it is selectively operable in both the TTS and TTFS encoding modes. Further, the digital accumulator logic can be efficiently implemented using a digital integrator as described above.

[0012] The transmitter of the neuron circuit embodying the present invention is operable to encode, for each output link, the weight associated with that link into a pulse signal embedded in the trigger signal generated on that link. The receiver is then operable to decode the pulse signal embedded in the trigger signal on the input link to obtain the weight associated with that link. Various other features and advantages of the neuron circuit embodying the present invention will be described in connection with the following exemplary embodiments.

[0013] A further aspect of the present invention provides an SNN device including a plurality of neuron circuits according to the foregoing embodiments, the neuron circuits being interconnected by links, each link being associated with a respective weight for the transmission of signals between the neuron circuits.

[0014] Hereinafter, embodiments of the present invention will be described in more detail by way of illustrative and non-limiting examples with reference to the accompanying drawings.

[0015] Next, preferred embodiments of the present invention will be described by way of example only with reference to the following drawings.

Brief Description of the Drawings

[0016]

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[0017] FIG. 1 is a schematic diagram showing the basic configuration of an SNN device embodying the present invention. SNN1 includes a network of neuron circuits (represented by circles) interconnected by links (represented by arrows) for transmitting signals between the neuron circuits. A typical SNN includes a plurality of neurons (often a large number such as hundreds or thousands) that can be arranged and interconnected in various ways for signal communication in the SNN, but three neuron circuits ("neurons") are labeled as n i , n j , n k in this simple diagram. The neurons are arranged, for example, in the form of a series of layers, and each neuron in one layer is connected to neurons (some or all) in the next layer, and signals can be relayed across multiple neuron layers from the input to the output neuron layer. In other SNNs, the neurons may be arranged in the form of one or more aggregates in which the neurons can be interconnected in various ways to transmit signals within and between the neuron aggregates. Many other SNN architectures are also known, and the neuron circuits described hereinafter can be advantageously applied to any SNN architecture.

[0018] By associating each link between neuron pairs with its respective weight, the synaptic weights associated with the synapses of a biological neural network are emulated. Thus, in Figure 1, across the entire network, the input link from neuron n k to neuron n i has a weight indicated by w ik , and the input link from neuron n j has the corresponding weight w ij , and so on. In the operation of SNN1, a neuron receives signals from other neurons on its input links, and these signals are weighted by the corresponding link weights, thereby updating the state of the receiving neuron (often called the "membrane potential"). Subsequently, the receiving neuron generates output signals according to the state of that neuron, and these signals are transmitted to other neurons via its output links.

[0019] Figure 2 shows the components of the neuron circuit embodying the present invention used in SNN1. Neuron 2 includes a digital transmitter 3 for generating output signals ("trigger signals") on the output links of the circuit. These trigger signals indicate the aforementioned state of the neuron circuit. In particular, transmitter 3 is adapted such that the state of this neuron is encoded at time intervals defined by the trigger signals it generates. Neuron 2 further comprises a digital receiver 4 for receiving trigger signals from other neurons on the input links of the circuit. Receiver 4 comprises a signal detector 5 for detecting the trigger signals on the input link and a digital accumulator logic 6. This digital accumulator logic is adapted to generate a weighted signal according to the time interval defined by the trigger signal and the weight associated with that input link in response to the detection of the trigger signal on the input link. And accumulator logic 6 accumulates the weighted signals generated from the trigger signals on the input link and determines the state of the neuron circuit. The state of the neuron is supplied to the digital transmitter 3 for generating trigger signals as described above.

[0020] Figure 3 shows a TTS encoding scheme implemented by a first embodiment of the neuron circuit 2. In TTS encoding, at time t p neuron n that receives a spike train i has a membrane potential V i given by Equation 1 shown below:

Equation

[0021] The membrane potential V of the neuron n at time t = T i is shown in the lower timeline of FIG. 3 for the input signals from n i and n shown in the upper timeline. The shaded intervals here indicate the assigned ranges ΔT for transmitting the weight signals s k and n j and s. In embodiments where the weights are known at the receiving neuron, these signals are reduced to single pulses at times X k or X j respectively. In this example, the weight signal is a 4-bit binary pulse train and encodes the weights as in the following equations 2 and 3: k Equation 2: w j = Σ Equation 2: w ik = Σ m w ik,m 2 m = 2, whereby w ik,1 = 1, and Equation 3: w ij = Σ m w ij,m 2 m = 5, whereby w ij,2 = 1, and w ij,0 = 1. As shown by the thick line in the figure, the state of the neuron n at the end of the period T = 1024ΔT is determined by the equation represented by Equation 4: i

Number

[0022] ​Figure 4 shows the implementation of the digital transmitter 3 of neuron 2 of the TTS encoding scheme. In this embodiment, it is assumed that in the neuron receiver 4, all the weights of the input links are known. The transmitter 3 includes a synchronous counter 8 and spike logic 9 that receive a 5 GHz master clock signal. The spike logic 9 receives the state of the neuron from the digital receiver 4 and controls the generation of a trigger signal by the signal generator 10. In this embodiment, the transmitter 3 can use spike signaling or PWM (pulse width modulation) signaling as shown in FIGS. 5(a) and 5(b), respectively. At the start of each period T, a reference spike (FIG. 5(a)) or the falling edge of the PWM signal (FIG. 5(b)) is generated by the signal generator 10 under the control of the spike logic 9. The synchronous counter 8 counts such that an appropriate time interval Δt, here Δt = 179, that defines the current state of the neuron, is defined by the end of the period T. When the appropriate number is reached, the spike logic 9 controls the signal generator 10 to generate a spike (the data spike in FIG. 5(a)) or the rising edge of the PWM signal (FIG. 5(b)). The timing of the spike / edge here can be triggered by either the rising or falling edge of the master clock signal. Here x j The resulting trigger signal, indicated by, is thus transmitted via the output link of the neuron (here via the buffer 11).

[0023] In the signaling schemes of FIGS. 5(a) and 5(b), the trigger signal x j defines a time interval Δt in relation to the end of the period T, whereby the cumulative phase of the receiver (described later) can be started immediately after signal detection. Thus, the delay in operation is minimized, but pre-skew removal of the input link, i.e., calibration of the skew, is required. FIGS. 6(a) and 6(b) show the trigger signal x jAn alternative implementation is shown that defines a time interval Δt with reference to the start of a period T. Here, the shaded intervals in FIG. 6(b) indicate that there is a guard band relative to the master clock edge. If the guard band sufficiently covers the spread of the maximum delay, link skew calibration is not necessary. This provides a robust implementation in the presence of a spread of delays.

[0024] The start / stop spike signaling approach has the advantage that the evaluation occurs at the same clock edge (rising or falling), as opposed to PWM where both edges are evaluated. The single clock edge solution is less prone to two-mode jitter. However, PWM signaling may be more efficient in some embodiments due to a 50% reduction in edge density. In particular, the dynamic power loss in a CMOS (Complementary Metal-Oxide-Semiconductor) circuit is directly related to the number of signaling edges.

[0025] In the receiver 4 of this embodiment, the digital accumulator logic 6 is adapted to generate weighted signals from the trigger signals received on the input link, accumulate these weighted signals periodically at a period T, and determine the state of the neuron at the end of each period T. Thereafter, the transmitter 3 transmits a trigger signal x indicating the state in the next period T. jGenerate. FIG. 7 shows the implementation of the receiver 4 of this embodiment. The signal detector 5 is implemented here by a spike detector 15 that, for each input link, detects the received trigger signal (here, the spike signal of the scheme in FIG. 6(a)) and closes the switch over the time interval Δt defined by that signal. The digital accumulator logic 6 generally includes a counter logic 16 denoted by 16, a graphical multiplication logic 17 denoted by 17, and a summation logic 18 denoted by 18. The counter logic 16 is implemented by an 8-bit thermocouple encoder counter 20 for each input link, and the counter 20 is connected to the output of the switch of the signal detector 5 of that link. In this way, the counter 20 generates a thermocouple encoder output value that depends on the time interval Δt defined by the input trigger signal and during which the switch is closed and the counter is connected to the master clock. The graphical multiplication logic 17 includes, for each input link, a graphical multiplier 21 that receives a 256-bit thermocouple encoder output value from the counter 20 for that link. The graphical multiplier 21 is adapted to multiply the counter output value by a weight w j (w j is assumed to be known here and can be pre-stored in a register (not shown) of the receiver) and is adapted to perform the multiplication. Through the graphical multiplication operation, as will be described in detail below, a set of components of the weighted signal of the link is generated in the form of partial products. The summation logic 18 sums these components to generate a weighted signal for each input link, sums the weighted signals generated during each period T, and represents the neuron state, here generating an accumulated signal denoted by S ACC . The accumulated signal S ACC passes through an activation device 22 that includes a non-linear element, here a rectified linear unit (ReLU), so that a non-linear activation function is applied to S ACC to obtain the state of the neuron supplied to the transmitter 3.

[0026] In this embodiment, the graphical multiplier 21 uses a LUT (look-up table)-based graphical multiplication technique that uses a plurality of look-up tables storing the values of the aforementioned components (partial products) for possible (potential) values of the thermocouple encoder output value from the counter 20. Here, the graphical multiplier uses three look-up tables labeled LUT#1, LUT#2, and LUT#3. LUT#1 receives a thermocouple encoder output value of (256 = 2^8) bits (hereinafter referred to as x j ), and determines the partial product obtained when x j is overlaid with a coarse grid of 32-bit step sizes. Thereafter, the residual vector is processed in LUT#2 with an 8-bit step size, and finally LUT#3 determines the final residue with a 1-bit step size. The graphical multiplication operation is shown in detail in FIGS. 8 to 10 for the example of x j = 179 and w j = 43.

[0027] FIG. 8 illustrates the operation of LUT#1 having 10 addressable entries (the outputs corresponding to the last entry are two as shown). The thermocouple encoder value x j is received by the LUT address logic. This LUT address logic identifies the address in this LUT containing the partial product pr1 and the residual vector r j resulting from the first multiplication step of x j = 179 and w LUT#1 = 43. Thus, LUT#1 generates the following two outputs represented by Equations 5 and 6: Equation 5: Output_A of LUT#1: pr1 = Truncate(p j , 32), and Equation 6: Output_B of LUT#1: r LUT#1 = Mod(p j , 32), where p j = x j * w j and * represents multiplication. In this example, xj = 179, w j = 43, and the LUT entries of the results are shown shaded in the figure. That is, LUT address = 00000100, pr1 = (43 * 160) = 6880 (where 160 corresponds to five 32-bit binary values that are fully-populated), r LUT#1 is a 32-bit residual vector in which 13 logic 0s follow 19 logic 1s. The partial product pr1 from Output_A is supplied to the total logic 18, and the residual vector r LUT#1 from Output_B is passed to LUT #2. Note that for simplicity of representation in the figure, the LUT entries of Output_A are given in decimal. However, in hardware implementation, as will be described below, for the processing at the total logic 18, the numerical values are stored in two's complement format of binary. Also, for Output_B, only the range of the bit positions of the residual vector r LUT#1 is shown. In hardware implementation, instead of the bit positions, the bit values at those positions are passed to LUT #2.

[0028] Figure 9 illustrates the operation of LUT #2 with six addressable entries. The residual vector r LUT#1 from LUT #1 is received by the LUT address logic that identifies the address including the partial product pr2 and the residual vector r LUT#2 resulting from the second multiplication step represented in FIGS. 7 and 8: Equation 7: Output_A of LUT #2: pr2 = Truncate(pr LUT#1 , 8), and Equation 8: Output_B of LUT #2: r LUT#2 = Mod(pr LUT#1 , 8), where pr LUT#1 = r LUT#1 * w j , r LUT#1 = 19, w jLet it be 43. Therefore, Output_A = (43 * 16) = 688 (where 16 corresponds to two 8-bit binary values that are fully populated), and Output_B is an 8-bit residual vector having three logical 1s followed by five logical 0s. The partial product pr2 of Output_A is supplied to a total of logical 18, and the residual vector r of Output_B LUT#2 is passed to LUT#3. As shown in FIG. 10, LUT#3 has seven addressable entries. This LUT has r LUT#2 = 3, w j = 43, and the partial product pr LUT#3 = r LUT#2 * w j is determined, and the result is provided as Output_A to a total of logical 18. Therefore, in this example, Output_A = (43 * 3) = 129. As will be apparent to those skilled in the art, reducing the number of partial product values (a total of 23) stored in this implementation can be easily achieved at the cost of more LUTs and data processing overhead.

[0029] Returning to FIG. 7, the total logical 18 includes a 14-bit carry-save adder (CSA) that receives the partial product (Output_A) from three LUTs of the graphical multiplier 21 for each input link. In the foregoing example, the output of the CSA is equal to 6880 + 688 + 129 = 7697, and x j * w j = 179 * 43 = 7697 (where x j is 8-bit resolution and w j is 6-bit resolution) is correctly calculated. Thus, the CSA output for each input link is the weighted signal x j * w jis provided, which depends on the time intervals encoded in the input trigger signal and the weights associated with its input links. Note that the LUT directly provides the output (Output_A) in two's complement format required for CSA operation. As is well known in the art, a basic CSA stage can sum three binary input strings and generate two bit strings corresponding to the sum bit and the carry bit due to addition respectively. When more than three numbers are summed, by implementing the CSA adder as an adder tree with basic CSA adder stages cascaded, the final sum and the carry bit string can be obtained after all additions. In this example, the CSA adder sums three partial products in two's complement format from the LUT and obtains a 14-bit sum and a carry output due to addition (represented as a single output in Figure 7).

[0030] By providing the CSA outputs of all input links (e.g., 250 or 780 links) to the final ripple carry adder (RCA) of the sum logic 18, the final sum of all weighted signals x j *w j is calculated to obtain the cumulative signal S ACC . Thus, by deferring the resolution of the carry bits for individual sums until the final RCA stage, the calculation can be made highly efficient and the power consumption due to the calculation ripple of addition can be reduced. The RCA can be efficiently implemented by a 14-bit Kogge-Stone adder. After the application of the ReLU function to S ACC in the activation device 22, the resulting 8-bit neuron state is passed to the transmitter 3.

[0031] According to the foregoing embodiments, neurons are provided in which the transmitted neuron state information is encoded by the length of a time interval, and it can be seen that this time interval is measured by digital-counter logic in a neuron receiver. The neurons operate entirely in the digital domain, avoiding the need for analog-to-digital converters or calibration of analog components. A pure CMOS implementation is possible, and the circuit components are easy to describe in VHDL (Very High-Speed Integrated Circuit Hardware Description Language) and can be integrated. The circuit is modular and scalable according to the concept of reference / data spikes (such as PWM signaling), and synchronous operation can be easily achieved with a local frequency-multiplied PLL (Phase-Locked Loop) for spike / PWM generation / detection in the transmitter and receiver. Since the receiver output directly provides two's complement data by LUT-based multiplication, data format conversion is unnecessary. Therefore, this embodiment provides an efficient and fully digital implementation of a TTS-encoded SNN. Performance close to that provided by non-spiking artificial neural networks can be easily achieved.

[0032] FIG. 11 shows a TTFS encoding scheme implemented by a further embodiment of the neuron of FIG. 2. In TTFS encoding, a neuron spikes (generates an output signal) when its membrane potential reaches a given threshold and then remains silent. For neuron n i the spike time is t i and when receiving a spike train at time t p the following equation 9 is satisfied: Equation 9: TH = Σ p w ip (t i - t p ) H (t i - t p ), 0 ≦ t < T’, where TH is the firing threshold, w ip is the synaptic weight of the input link, and H(t) is the Heaviside function. When there is no solution for t i the neuron spikes at time t = T’ with a probability P ∈ [0, 1]. For neuron nk , n j、 n i Depending on the time when the state of each neuron reaches the threshold TH, the corresponding time intervals (X k , X j、 X i where T' represents the maximum (non-leaky) integration time to complete one iteration of neuron operation. Thus, as shown in the timeline at the top of the figure, the integration time of neuron n k is the time interval X k After that, the membrane potential V k exceeds the threshold TH at time t k Similarly, neuron n j is the time interval X j After that, the membrane potential V j crosses the threshold at time t j As already mentioned, the synaptic weights w ik and w ij The value of i Even if these values ​​are not known, they can be calculated by k and s j Each receiving neuron n i The state of a neuron is determined by the signals received on its input links during time period T'. This neuron produces an output signal during that period, which occurs over the time interval X i After that, the membrane potential V i When exceeds TH, the neuron n i The weights w associated with the output links of pi is the receiving neuron n p Even if it is not known, the spike train s i It can be communicated by.

[0033] Neuron n during period T' i Membrane potential V i The calculation of n shown in the upper timeline k and n jThe input signal from k is shown in the lower timeline of FIG. 11. (As before, the shaded intervals indicate the assigned ranges ΔT for transmitting the weight signals s j and s k . The weights are encoded in these signals, similar to the TTS scheme of FIG. 3. If the weights are known at the receiving neuron, these signals are each reduced to a single pulse at time X j or X i .) The state of neuron n during the period T' = 1024ΔT is given by: i Equation 10: V j =(t - X j )H(t - X ij )w k +(t - X k )H(t - X ik as represented by the thick line in the figure. If V i reaches TH, the neuron fires during T'. Otherwise, it fires with probability P at t = T'. If P = 0, the neuron remains silent.

[0034] For neuron 2 implementing the TTFS encoding scheme, it will be described later with reference to FIGS. 12 to 14. In these embodiments, the digital accumulator logic 6 generates weighted signals from the trigger signals received at the input link during each of the successive periods T', accumulates these weighted signals to produce an accumulated signal S ACC , and is adapted to gradually compare the accumulated signal with a threshold TH to determine the state of the neuron during that period T'. The transmitter is then adapted to generate a trigger signal in response to the accumulated signal exceeding the threshold TH during that period T'.

[0035] Figure 12 shows a first neuron implementation of TTFS encoding. The signal detector 5 is implemented in the same manner as in the aforementioned embodiment of FIG. 7, and includes, for each input link, a spike detector 15 that detects the received trigger signal and closes a switch. The digital accumulator logic of this embodiment includes a digital integrator 30 for each input link, a summing logic 31, and a comparator 32. The digital integrator 30 is adapted to start integrating a value corresponding to (dependent on) the weight w ij associated with that link in response to the detection of the trigger signal on the input link, and to generate a weighted signal for that link. Thus, the weighted signal depends on the link weight w ij and the time when the transmitting neuron n j fires (i.e., the end time of the time interval Δt encoded in the input trigger signal x j ). Next, the summing logic 31 sums all the weighted signals generated during each period T’ for all the input links to generate an accumulated signal S ACC . Assume that the weight w ij of the input link is known and pre-stored in a register (not shown) of the receiver.

[0036] In this embodiment, the digital integrator 30 includes a connected counter, namely a weight counter 35 and an integration counter 36. The link weight w ij in this implementation is stored in the form of a 6-bit value W j =(w max -w ij ). Here, w max is a predefined maximum value, in sign-magnitude form, i.e., W jIt is represented by (sign bit, w[0, 5]). When a spike is detected on the input link, the spike detector 15 closes the switch and the master clock edge is supplied to the weight counter 35. (Since TTFS depends on a single spike, the difference in propagation delay between input links can be mitigated by an adjustable timing offset, shown in the figure as the analog fine timing offset 37 and the digital coarse timing offset 38.) The weight counter 35 includes a 6-bit counter 40 that provides output bits c[0] to c[5] to the combinational logic 41 that also receives the weight bits w[0, 5]. The combinational logic 41 generates an output pulse each time the count c[0] to c[5] reaches the weight value w[0, 5]. This pulse is supplied to the integration counter 36, resets the counter 40, and resumes the count. The pulse from the weight counter 35 thus defines the update rate of the integration counter 36.

[0037] The integration counter 36 includes a 10-bit counter 43, and as this counter 43 is incremented progressively, the integration, i.e., p j (t) = w j *(t - X j ), t > X j is calculated. The integrator count value p j (t) becomes positive or negative according to the sign bit of W j supplied to the combinational logic 44 of the integration counter 36. The combinational logic 44 provides the integrator count value in CSA format as the sum vector (sum[0, 10]) and the carry vector (carry[0, 10]). Negative values are generated by adding a logical 1 to the carry vector and inverting the bits of the output of the counter 43. An optional coarse timing adjustment is applied in the CSA adder block 38, and the resulting weighted signal w j *(t - X j ), t > X j is output to the sum logic 31 in CSA format.

[0038] The total logic 31 includes a carry-save adder tree followed by a ripple-carry adder (e.g., a Kogge-Stone adder), sums the integrator outputs from all input links, and accumulates the resulting signal S ACC to the comparator 32. When S ACC exceeds the threshold TH, the comparator outputs a global reset signal to reset all the counters of the integrator 30. The comparator output is also supplied to the transmitter in the form of a spike generator 33, so that spike signals will be generated on the output links of the neurons.

[0039] The integration operation in the embodiment of FIG. 12 is schematically shown in FIG. 13. The lower trace shows the operation of the weight counter 35 of the link with W j =6. The count at the link integration counter 36 is shown in the upper adjacent trace, and it can be seen that the weight counter controls the steepness of the integrator. In this implementation, the higher the link weight W ij (and thus the lower the weight value W j as previously defined), the steeper the integrator. The top trace here shows the output signal accumulated over all neuron integrators, and when S ACC reaches the firing threshold TH, the neuron spikes and a global reset occurs.

[0040] FIG. 14 shows another neuron implementation of the TTFS encoding. The signal detector includes a spike detector 15 for each input link. The digital accumulator logic of this embodiment includes weighted logic 40, a digital integrator 41, and a comparator 42 for each input link. The weighted logic 40 is adapted to generate a weighted signal for a link by outputting a weight value in response to the detection of a trigger signal on that link and according to the weight associated with that link. In particular, the weight logic 40 includes a register 44 for storing the weight value w ij of the link and a switch controlled by the spike detector 15 of the link. When an input spike is detected, the switch is closed and the weight w ijis supplied to one input of the CSA adder tree 45 of the digital integrator 41 in CSA format. In this way, the CSA 45 accumulates the weights at the output of the weight logic 40 of the input link to generate a total value. This total value is supplied to one input of the ripple carry adder 46, and its output is fed back to the second input. A timer device 47, which is timed by the master clock signal, provides the current CSA total value to the RCA 46, whereby the RCA gradually accumulates the total value during the period T'. The resulting accumulated signal S ACC is compared with TH by the comparator 42. S ACC If S

[0041] The embodiments of FIGS. 12 and 14 provide a digital neuron implementation for realizing a full-digital TTFS-encoded SNN. In addition to the advantages described above for the TTS embodiments, these implementations have low weight programming complexity and are conceptually simple. The low-area implementation is possible because the weights are stored in simple registers and no LUT is required. The switching activity is higher than that of the multiplier approach using an LUT, but this results in a smaller overall area and thus fewer local interconnections. The embodiment of FIG. 14 provides a very efficient implementation by provisioning a global digital integrator 41 for all input links of the neuron.

[0042] The described TTS embodiments are also easily reconfigurable for TTS encoding, as shown in FIG. 15. Illustrated is the digital accumulator logic 6 implemented as a digital integrator in a reconfigurable neuron 50 to generate the accumulated signal S ACC as a component. The mode control logic 51 controls the selective operation of the circuit in the first TTFS encoding mode and the second TTS encoding mode. In the TTFS mode, the accumulated signal S ACCis supplied, via switch 52, to a comparator 53 that operates like comparators 32 and 42 of the aforementioned TTFS embodiments. Thus, S ACC is progressively compared with a threshold TH, and transmitter 54 outputs a spike signal when the threshold is exceeded during each successive period T’. In TTS mode, digital accumulator logic outputs, at the end of each period T’, an accumulated signal S ACC . This signal is supplied, via switch 52, to an activation device 55 that outputs the state of the neuron to transmitter 54. The transmitter then generates a trigger signal indicating its state during the next period T’.

[0043] The selective operation in both TTFS and TTS modes is a very attractive option for SNN implementations. TTS embodiments are suitable for efficient implementation of iterative algorithms that use non-local timing references, such as message-passing algorithms, or classification algorithms, for example, that need to process a continuous stream of input data, such as images. TTFS embodiments are suitable for low-latency classification algorithms, where, among the output layer neurons, the neuron corresponding to the correct class fires first. Providing both options in a single SNN implementation is thus highly beneficial.

[0044] The detailed operation has been described assuming that the weights are known at the receiver, but the aforementioned embodiments can be easily adapted to the transmission of the value of the weights by the weight signals shown in FIGS. 3 and 11. FIG. 16 is a diagram of a neuron circuit having such a function, and the aforementioned components are designated by similar reference symbols in this figure. For each input link of receiver 4, the signal detector includes weight decoder logic 60, and the weight w j encoded in the weight signal s jDecode this and dynamically supply it to the digital accumulator logic 6. In the transmitter 3, the signal generator 61 receives the neuron state for controlling the generation of the trigger signal on the output link. The transmitter also receives and stores the current value 62 of the weight of each output link. The weight of the output link can be updated periodically during operation, for example, during the network training operation. The signal generator 61 embeds the weight w p associated with that link into the pulse signal s p embedded in the trigger signal generated on that link. In some embodiments, the neuron may be operable in both the training mode and the inference mode. In the training mode, since the weights are updated periodically, they are transmitted by the output trigger signal. In the inference mode, the weights are no longer updated and the fixed weights are stored in the receiver.

[0045] Embodiments can also be adapted to implement a so-called "leaky neuron" circuit, whereby the neuron membrane potential decays over time according to a certain function. This is shown schematically in FIG. 17 for the example based on the neuron of FIG. 14. The cumulative signal S ACC (t) output by the RCA device 46 in FIG. 14 is supplied to the decay device 70 that implements the desired leaky neuron function. Add the output S’ ACC (t + 1) to the output of the timer device 47 to obtain S ACC (t + 1).

[0046] Of course, various other changes and modifications can be made to the above-described embodiments. Also, when features are described herein with reference to the neurons embodying the present invention, the corresponding features can be provided in an SNN device using such neurons.

[0047] The descriptions of the various embodiments of the present invention are presented for illustrative purposes, but are not intended to be exhaustive and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, the practical application, or the technical improvements seen in the marketplace, or to enable other skilled artisans to understand the embodiments disclosed herein.

[0048] FIG. 18 is a block diagram of an example of a system according to an embodiment of the present invention. Specifically, FIG. 18 discloses a computer system or a system 1800 including a computer shown in the form of a general computer device (e.g., computer system 1810). The method of the present invention can be embodied, for example, in a program 1860 embodied in a computer-readable storage device generally called a memory 1830 and more specifically called a computer-readable storage medium 1850. For example, the memory 1830 can include a storage medium 1834 such as RAM (Random Access Memory) or ROM (Read Only Memory), and a cache memory 1838. The program 1860 is executable by a processing device or processor 1820 of the computer system 1810 (to execute program steps, code, or program code). Additional data storage can also be embodied as a database that can include data 1914. The computer system 1810 and the program 1860 can be local to the user or provided as a remote service (e.g., as a cloud-based service), and in a further example, can be provided using a website accessible using a communication network 2000 (e.g., that interacts with a network, the Internet, or cloud services), which is a general representation of a computer and a program. Also, in this specification, the computer system 1810 is understood to generally represent a computer device or a computer included in a device, such as a notebook PC or a desktop computer, or one or more servers, alone or as part of a data center. The computer system can include a network adapter / interface 1826 and an input / output (I / O) interface 1822. The input / output interface 1822 enables input and output of data with an external device 1874 that can be connectable to the computer system.Network adapter / interface 1826 can provide communication between a computer system network generally shown as communication network 2000.

[0049] Computer 1810 can be described in the general context of computer system executable instructions such as program modules executed by a computer system. Generally, program modules can include routines, programs, objects, components, logic, data structures, etc. that perform specific tasks or implement specific abstract data types. Method steps and system components and techniques can be embodied in modules of program 1860 for performing the tasks of each step of the method and system. The modules are generally represented as program modules 1864. Program 1860 and program module 1864 can execute specific steps, routines, subroutines, instructions, or code of the program.

[0050] Embodiments of the present disclosure can be run locally on a device such as a mobile device, or, for example, on server 1900 that can be remotely accessed using communication network 2000 to run services. The program or executable instructions can also be provided as a service by a provider. Computer 1810 can be practiced in a distributed cloud computing environment where tasks are executed by remote processing devices linked via communication network 2000. In a distributed cloud computing environment, program modules can be located on both local and remote computer system storage media including memory storage devices.

[0051] More specifically, system 1800 includes a computer system 1810 shown in the form of a general-purpose computing device having exemplary peripheral devices. The components of computer system 1810 can include, but are not limited to, one or more processors or processing units 1820, a system memory 1830, and a bus 1814 that couples various system components including system memory 1830 to the processor 1820.

[0052] Bus 1814 represents one or more of several types of bus structures including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus that uses any of a variety of bus architectures. By way of example and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0053] Computer 1810 can include various computer-readable media. Such media can be any media that is accessible and usable by computer 1810 (e.g., a computer system, or a server), and can include both volatile and non-volatile media, as well as both removable and non-removable media. Computer memory 1830 can include additional computer-readable media 1834 in the form of volatile memory, such as random access memory (RAM), or cache memory 1838, or both. Computer 1810 can further include other removable / non-removable, volatile / non-volatile computer storage media, such as, by way of example, portable computer-readable storage media 1872. In one embodiment, computer-readable storage media 1850 can be provided for reading from and writing to a non-removable non-volatile magnetic medium. Computer-readable storage media 1850 can be embodied, for example, as a hard drive. Additional memory and data storage can be provided, for example, as a storage system 1910 (e.g., a database) for storing data 1914 and communicating with processing device 1820. The database can be stored on server 1900 or can be part of it. Although not shown, a magnetic disk drive for reading from and writing to a removable non-volatile magnetic disk (e.g., a “floppy disk”) or an optical disk drive for reading from and writing to a removable non-volatile optical disk such as a CD-ROM, DVD-ROM, or other optical media can also be provided. In such cases, each can be connected to bus 1014 by one or more data media interfaces. As further illustrated and described below, memory 1030 can include at least one program product that can include one or more program modules configured to implement the functions of embodiments of the present invention.

[0054] The method of the present invention can be embodied, for example, in one or more computer programs generally referred to as program 1860 and stored in memory 1830 within computer-readable storage medium 1850. Program 1860 can include program modules 1864. Program modules 1864 can generally implement the functions and / or methodologies of the embodiments of the present invention described herein. Program 1860 can be a keyword system or a natural language processing system. One or more programs 1860 are stored in memory 1830 and are executable by processing device 1820. By way of example, memory 1830 can store operating system 1852, one or more application programs 1854, other program modules, and program data in computer-readable storage medium 1850. It is understood that program 1060, operating system 1852, and application program 1854 stored in computer-readable storage medium 1850 are likewise executable by processing device 1820.

[0055] Computer 1810 can also communicate with one or more external devices 1874 such as a keyboard, a pointing device, a display 1880, one or more devices that enable the computer 1810 to interact with a user, or any device (e.g., a network card, a modem, etc.) or a combination thereof that enables the computer 1810 to communicate with one or more other computer devices. Such communication can be performed via an input / output (I / O) interface 1822. Nevertheless, computer 1810 can communicate with one or more networks 2000 such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet) or a combination thereof via a network adapter / interface 1826. As depicted, network adapter 1826 communicates with other components of computer 1810 via bus 1814. Although not shown, it should be understood that other hardware or software or both components can be used in conjunction with computer 1810. Examples include, but are not limited to, microcode, device drivers 1824, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0056] It is understood that a computer or a program 1810 executed by a computer can communicate with a server embodied as server 1100 via one or more communication networks embodied as communication network 2000. The communication network 2000 can include, for example, wireless, wired, or optical fiber, and transmission media and network links including routers, firewalls, switches, and gateway computers. The communication network can include connections such as wires, wireless communication links, or optical fiber cables. The communication network can represent a worldwide collection of networks and gateways, such as the Internet, that communicate with each other using various protocols such as LDAP (Lightweight Directory Access Protocol), TCP / IP (Transport Control Protocol / Internet Protocol), HTTP (Hypertext Transport Protocol), WAP (Wireless Application Protocol), and the like. The network can also include several different types of networks, such as, for example, intranets, local area networks (LANs), wide area networks (WANs), and the like.

[0057] As an example, a computer can utilize a network that enables access to websites (World Wide Web) on the web using the Internet. In one embodiment, a computer 1810, including a mobile device, can use a communication system or network 2000 that can include the Internet, or a public switched telephone network (PSTN), such as a cellular network. The PSTN can include telephone lines, fiber optic cables, microwave transmission links, cellular networks, and communication satellites. The Internet can facilitate a number of search and texting techniques, such as sending text messages (SMS), multimedia messaging service (MMS) (SMS-related), e-mail, and querying a search engine via a web browser, for example, using a mobile phone or a laptop computer. The search engine can obtain search results, i.e., links to websites, documents, or other downloadable data corresponding to the query, and similarly provide the search results to the user via the device, for example, as a web page of the search results.

[0058] The present invention can be, at an integration of any possible technical detail level, a system, a method, or a computer program product, or a combination thereof. The computer program product may include a computer-readable storage medium (or multiple computer-readable storage media) having computer-readable program instructions for causing a processor to implement aspects of the present invention.

[0059] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction-executing device. The computer-readable storage medium can be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof, but is not limited thereto. A non-exhaustive listing of more specific examples of computer-readable storage media includes the following: portable computer diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded devices such as punch cards or structures engraved in grooves in which instructions are recorded, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium shall not be construed to be a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or an electrical signal transmitted through an electrical wire.

[0060] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, or a wireless network or a combination thereof. The network may include copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, or edge servers or a combination thereof. The network adapter card or network interface of each computing / processing device receives the computer-readable program instructions from the network and transfers the computer-readable program instructions for storage on a computer-readable storage medium within the individual computing / processing device.

[0061] The computer-readable program instructions for carrying out the operations of the present invention may be written in any combination of one or more programming languages, including assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuits, or object-oriented programming languages such as Smalltalk(R), C++, and procedural programming languages such as the "C" programming language or similar programming languages, and may be either source code or object code. The computer-readable program instructions may be executed entirely on the user's computer, partly on the user's computer as a stand-alone software package, partly on the user's computer and partly on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA) may execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to customize the electronic circuit in order to carry out aspects of the present invention.

[0062] Aspects of the present invention will be described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer-readable program instructions.

[0063] These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of a flowchart, a block diagram, or both. These computer-readable program instructions may also be stored in a computer-readable storage medium that includes a product comprising instructions for implementing the mode of function / act specified in one or more blocks of a flowchart, a block diagram, or both, and the computer-readable storage medium may be capable of instructing a computer, a programmable data processing apparatus, or other devices, or a combination thereof, to function in a particular manner.

[0064] The computer-readable program instructions may also be loaded onto a computer, other programmable apparatus, or other device to produce a computer-implemented process such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of a flowchart, a block diagram, or both by causing a series of operational steps to be executed on the computer, other programmable apparatus, or other device.

[0065] The flowcharts and block diagrams in the drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, segment, or portion of instructions that include one or more executable instructions for implementing the specified logical function. In some alternative implementations, the functions noted in the blocks may occur out of the order shown in the drawings. For example, depending on the functionality involved, two blocks shown in succession may actually be executed simultaneously, or the blocks may sometimes be executed in the reverse order. It should also be noted that each block of the block diagrams or flowchart diagrams, or combinations of blocks of the block diagrams or flowchart diagrams or both, can be implemented by a special purpose hardware-based system that performs the specified function or activity or implements a combination of special purpose hardware and computer instructions.

Claims

1. A circuit including a plurality of neuron circuits interconnected by links of a spiking neural network device, each link being associated with respective weights for transmission of signals between respective neuron circuits, and a certain neuron circuit among the plurality of neuron circuits being A digital transmitter that generates on an output link of the circuit a trigger signal indicating a state of the neuron circuit, the state being encoded in a time interval defined by the generated trigger signal, the digital transmitter, and A signal detector for detecting such a trigger signal on an input link of the circuit, and in response to detection of the trigger signal on the input link, generating a weighted signal according to the time interval defined by the trigger signal and the weight associated with the input link, and accumulating the weighted signal generated from the trigger signal on the input link to determine the state of the neuron circuit, and a digital accumulator logic adapted to do so, a digital receiver including.

2. In the neuron circuit, the transmitter is operable to encode, for each output link, the weight associated with the link into a pulse signal embedded in the trigger signal generated on the link, the receiver is operable to decode the pulse signal embedded in the trigger signal on the input link to obtain the weight associated with the link The circuit according to claim 1.

3. In the neuron circuit, the digital accumulator logic is adapted to determine the state of the neuron circuit at the end of each period T by periodically accumulating the weighted signal at a period T, the digital transmitter is adapted to generate a trigger signal indicating the state during the next period T The circuit according to claim 1, comprising.

4. The circuit according to claim 3, wherein the digital transmitter is adapted such that the trigger signal defines the time interval with reference to the end of the next period T.

5. The circuit according to claim 3, wherein the digital transmitter is adapted such that the trigger signal defines the time interval with reference to the start of the next period T.

6. The circuit according to claim 3, wherein the trigger signal includes one of a spike signal and a pulse width modulation signal.

7. The digital accumulator logic includes, for each input link, a counter logic adapted to generate a thermomotor encoded output value corresponding to the time interval defined by the trigger signal on that link, for each input link, a graphical multiplication logic adapted to multiply the output value by the weight associated with that link to obtain a component of the weighted signal, and a summation logic adapted to generate the weighted signal for each input link by summing the components and to generate an accumulated signal indicative of the neuron state by summing the weighted signals generated during each period T The circuit according to claim 3.

8. The circuit according to claim 7, wherein the graphical multiplication logic includes a plurality of look-up tables storing values of the components of possible values of the thermomotor encoded output value.

9. The circuit according to claim 7, wherein the summation logic includes a carry save adder that sums the components to generate the weighted signal for each input link and a ripple carry adder that sums the weighted signals to generate the accumulated signal.

10. The circuit according to claim 7, wherein the digital accumulator logic is further adapted to apply a non-linear activation function to the accumulated signal to determine the neuron state.

11. The digital accumulator logic is adapted to accumulate the weighted signal to generate an accumulated signal during each of successive periods T', and to gradually compare the accumulated signal with a threshold value to determine the state of the neuron circuit during the period T'. The digital transmitter is adapted to generate a trigger signal during the period T' in response to the accumulated signal exceeding the threshold value. The circuit according to claim 1.

12. The circuit according to claim 11, wherein the trigger signal includes a spike signal.

13. The digital accumulator logic is For each input link, adapted to generate the weighted signal of the link by starting to integrate a value corresponding to the weight associated with the link in response to the detection of a trigger signal on the link, a digital integrator, Adapted to sum the weighted signals generated during each period T' to generate the accumulated signal, a summing logic The circuit according to claim 11, comprising.

14. The circuit according to claim 13, wherein the digital integrator includes a connected counter, and the summing logic includes a carry-save adder and a ripple-carry adder.

15. The digital accumulator logic is For each input link, a weighting logic adapted to generate the weighted signal by outputting a weight value corresponding to the weight associated with the link in response to the detection of a trigger signal on the link, A digital integrator adapted to generate the accumulated signal by integrating the weight value output by the weighting logic of the input link during the period T'. The circuit according to claim 11, comprising.

16. The circuit according to claim 15, wherein the digital integrator includes a carry-save adder that generates a sum value by summing the values of the weights output by the weighted logic of the input link, and a ripple-carry adder adapted to generate the accumulation signal by gradually accumulating the sum value during the period T'.

17. The circuit according to claim 11, wherein the digital accumulator logic is adapted to apply a leaky neuron function to the accumulation signal to implement a leaky neuron circuit.

18. The circuit according to claim 11, wherein the receiver is adapted to apply a timing offset to a trigger signal on an input link to mitigate a propagation delay difference between input links.

19. The digital accumulator logic is adapted to accumulate the weighted signal during each successive period T' to generate an accumulation signal, and the neuron circuit is selectively operable in a first mode and a second mode. In the first mode, the digital accumulator logic is adapted to gradually compare a threshold value with the accumulation signal during each period T' to determine the state of the neuron circuit during the period T', and the transmitter is adapted to generate a trigger signal during the period T' in response to the accumulation signal exceeding the threshold value. In the second mode, the digital accumulator logic is adapted to determine the state of the neuron circuit according to the accumulation signal at the end of each period T', and the transmitter is adapted to generate a trigger signal indicating the state during the next period T'. The circuit according to claim 1.

20. The digital accumulator logic is For each input link, a digital integrator adapted to generate the weighted signal of the link by starting to integrate a value corresponding to the weight associated with the link in response to detection of a trigger signal on the link. Summing logic adapted to sum the weighted signals generated during each period T' to generate the cumulative signal, and The circuit according to claim 19, comprising: **Claim 21** The digital accumulator logic is For each input link, adapted to generate the weighted signal by outputting a weighted value corresponding to the weight associated with the link in response to detection of a trigger signal on the link, and A digital integrator adapted to generate the cumulative signal by integrating the weighted values output by the weighted logic of the input link during the period T'. The circuit according to claim 19, comprising: **Claim 22** A spiking neural network device, comprising: A plurality of neuron circuits interconnected by links, each link connecting the neuron circuits being associated with a respective weight for transmission of signals between the neuron circuits. The spiking neural network device. **Claim 23** A certain neuron circuit among the plurality of neuron circuits is A digital transmitter that generates a trigger signal indicating the state of the neuron circuit on the output link of the circuit, the state being encoded in a time interval defined by the generated trigger signal, and A signal detector for detecting such a trigger signal on the input link of the circuit, and in response to detection of the trigger signal on the input link, generating a weighted signal corresponding to the time interval defined by the trigger signal and the weight associated with the input link, and accumulating the weighted signal generated from the trigger signal on the input link to determine the state of the neuron circuit. A digital receiver comprising digital accumulator logic adapted to The spiking neural network device according to claim 22, comprising **Claim 24** A method executed by a computer, comprising generating a trigger signal on an output link of a neuron circuit of a spiking neural network including a plurality of neuron circuits respectively connected by links, the generated trigger signal indicating a state of the neuron circuit, the state being encoded at time intervals defined by the generated trigger signal, wherein the method further comprises generating a weighted signal of the input link corresponding to the time interval defined by the detected trigger signal in response to detection of a certain trigger signal among the generated trigger signals on the input link of the neuron circuit; and encoding the weighted signal related to the input link into a pulse signal embedded in the trigger signal generated on the input link The method comprising. **Claim 25** A computer system, comprising one or more computer processors; one or more computer-readable storage media; program instructions stored on the one or more computer-readable storage media and executed by at least one of the one or more computer processors wherein the program instructions include program instructions for generating a trigger signal on an output link of a neuron circuit of a spiking neural network including a plurality of neuron circuits respectively connected by links, the generated trigger signal indicating a state of the neuron circuit, the state being encoded at time intervals defined by the generated trigger signal, wherein the stored program instructions further include Program instructions for generating a weighted signal of the input link according to the time interval defined by the detected trigger signal in response to the detection of a certain trigger signal among the generated trigger signals on the input link of the neuron circuit; Program instructions for encoding the weighted signal associated with the input link into a pulse signal embedded in the trigger signal generated on the input link; A computer system comprising the above.

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