Self-Aligned Vertical Bitlines for 3D (Three-Dimensional) Dynamic Random Access Memory (DRAM) Devices

Abstract

The semiconductor structure includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer, a word line metal layer, and an interface on a cross-section of the semiconductor layer, a plurality of memory levels, a spacer between adjacent memory levels among the plurality of memory levels in the first direction, and a bit line in contact with each interface of the plurality of memory levels, the bit line extending in the first direction. The bit line includes a metal material, and the interface includes a silicon compound.

Description

Background Art

[0001] Technical Field Embodiments described herein generally relate to semiconductor device manufacturing, and more particularly, to systems and methods for forming vertical bit lines in three-dimensional dynamic random access memory devices.

[0002] Description of Related Art Three-dimensional (3D) dynamic random access memory (DRAM) devices present challenges in manufacturability due to their three-dimensional (3D) design and small size. Each individual memory cell, which includes a field effect transistor (FET) device, needs to be connected to a bit line at the source / drain region of the FET device. The manufacture of such bit lines generally requires a through-hole process and multiple process steps, including a high aspect ratio (HAR) etching process to form slots for the bit lines. For example, a 3D DRAM device may include alternating layers of silicon (Si) and silicon germanium (SiGe), with the silicon germanium (SiGe) layer being selectively recessed. Vertical bit lines can be formed by filling the HAR slots with polycrystalline silicon (poly-Si) through the silicon (Si) layer. This conventional approach for forming vertical bit lines in 3D DRAM devices results in voids in the resulting vertical bit lines, leading to relatively high parasitic resistance.

[0003] Accordingly, there is a need for systems and methods capable of manufacturing vertical bit lines in 3D DRAM devices with reduced parasitic resistance minimized by reduced processing steps.

Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure. The semiconductor structure includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer, a word line metal layer, and an interface on a cross-section of the semiconductor layer; a spacer between adjacent memory levels among the plurality of memory levels in the first direction; and a bit line in contact with the interface of each of the plurality of memory levels, the bit line extending in the first direction. The bit line includes a metal material, and the interface includes a silicon compound.

[0005] Embodiments of the present disclosure also provide a method of forming a metal bit line in a semiconductor device. The method includes performing a first selective deposition process to selectively form a metal silicon compound layer on sidewalls of a trench, the sidewalls of the trench including a first cross-section of each of a plurality of semiconductor layers stacked in a first direction and a second cross-section of a spacer disposed between adjacent semiconductor layers among the plurality of semiconductor layers; performing a second selective deposition process to selectively form a metal layer on the sidewalls of the trench; and performing a filling process including depositing a dielectric material in the trench. The metal layer on the sidewalls of the trench is continuous across the plurality of semiconductor layers and forms a metal bit line.

[0006] Embodiments of the present disclosure further provide a three-dimensional (3D) dynamic random access memory (DRAM) device. The 3D DRAM device includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer having a first end and a second end in a second direction orthogonal to the first direction, a word line metal layer, and an interface on a cross-section at the first end of the semiconductor layer; a plurality of memory levels; a spacer between adjacent memory levels among the plurality of memory levels in the first direction; and bit lines in contact with interfaces of each of the plurality of memory levels, the bit lines extending in the first direction. The bit lines include a metal material, and the interfaces include a silicon compound.

[0007] To better understand the above-described features of the present disclosure, a more detailed description of the present disclosure, briefly summarized above, may be made by reference to embodiments shown in part in the accompanying drawings. However, it should be noted that the present disclosure may admit other equally effective embodiments, so the accompanying drawings merely illustrate typical embodiments of the present disclosure and should not be regarded as limiting its scope.

Brief Description of the Drawings

[0008]

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DETAILED DESCRIPTION OF THE INVENTION

[0009] For ease of understanding, where possible, the same reference numbers are used to designate the same elements common to the figures. It is contemplated that the elements and features of one embodiment may be beneficially incorporated into other embodiments without further elaboration. In the figures and the following description, an orthogonal coordinate system including the X-axis, Y-axis, and Z-axis is used. The directions represented by the arrows in the drawings are assumed to be positive directions for convenience.

[0010] The embodiments described in this specification provide systems and methods for forming transistor devices for extreme scale process nodes, such as 3D DRAM devices, having vertical metal bit lines and an interface between the vertical bit lines and FET devices forming memory cells. The vertical bit lines are formed from a metal such as molybdenum (Mo) and reduce the resistance of the bit lines as compared to polycrystalline silicon bit lines. The interface is formed from a metal silicon compound such as a molybdenum silicon compound (MoSi2, MoSi, Mo2Si) by a selective self-aligned deposition process, provides an ohmic contact between the FET device and the vertical bit line, and reduces contact parasitic resistance.

[0011] FIG. 1 is a schematic plan view of an example of a multi-chamber processing system 100 according to some examples of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 having respective transfer robots 112, 114, hold chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, wafers in the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the wafers to the ambient environment outside the processing system 100 (e.g., an atmospheric ambient environment such as may exist in a fab). For example, the wafers can be processed in various chambers and transferred between various chambers in a low pressure (e.g., about 300 Torr or less) or vacuum environment without breaking the low pressure or vacuum environment during various processes performed on the wafers in the processing system 100. Thus, the processing system 100 can provide an integrated solution for some processing of the wafers.

[0012] Examples of processing systems that can be suitably modified in accordance with the teachings provided herein include Endura®, Producer® or Centura® integrated processing systems commercially available from Applied Materials, Inc., located in Santa Clara, California, or other suitable processing systems (including those from other manufacturers). It is contemplated that other processing systems (including those from other manufacturers) can be adapted to benefit from the aspects described herein.

[0013] In the illustrated example of FIG. 1, the factory interface 102 includes a docking station 140 and a factory interface robot 142 to facilitate the transfer of wafers. The docking station 140 is configured to receive one or more front-opening unified pods (FOUPs) 144. In some examples, each factory interface robot 142 generally includes a blade 148 disposed on one end of each factory interface robot 142 configured to transfer wafers from the factory interface 102 to the load lock chambers 104, 106.

[0014] The load lock chambers 104, 106 have respective ports 150, 152 coupled to the factory interface 102 and respective ports 154, 156 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 158, 160 coupled to the holding chambers 116, 118 and respective ports 162, 164 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 166, 168 coupled to the holding chambers 116, 118 and respective ports 170, 172, 174, 176 coupled to the processing chambers 124, 126, 128, 130. The ports 154, 156, 158, 160, 162, 164, 166, 168, 170, 172, 174, 176 can be slit valve openings having slit valves, for example, for passing a wafer therethrough by the transfer robots 112, 114 and for providing a seal between respective chambers to prevent gas from passing between the respective chambers. Generally, any port is open to transfer a wafer therethrough. In some cases, the port is closed.

[0015] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not shown in detail). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo pumps, roughing pumps), a gas source, various valves, and conduits fluidly coupled to the various chambers. During operation, the factory interface robot 142 transfers wafers from the FOUP 144 through port 150 or 152 to the load lock chamber 104 or 106. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 in an internal low pressure or vacuum environment (which may include an inert gas). Thus, pumping down the load lock chamber 104 or 106 facilitates passing wafers, for example, between the ambient environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0016] For wafers in the pumped-down load lock chambers 104 or 106, transfer robot 112 transfers the wafers from the load lock chambers 104 or 106 into the transfer chamber 108 through ports 154 or 156. The transfer robot 112 can then transfer the wafers to any one of and / or between the processing chambers 120, 122 through respective ports 162, 164 for processing, and / or to any one of and / or between the holding chambers 116, 118 through respective ports 158, 160 to hold for further transfer. Similarly, transfer robot 114 can access wafers in the holding chambers 116 or 118 through ports 166 or 168, and transfer the wafers to any one of and / or between the processing chambers 124, 126, 128, 130 through respective ports 170, 172, 174, 176 for processing, and / or to any one of and / or between the holding chambers 116, 118 through respective ports 166, 168 to hold for further transfer. The transfer and holding of wafers within and between the various chambers can be in a low pressure or vacuum environment provided by the gas and pressure control system.

[0017] The processing chambers 120, 122, 124, 126, 128, 130 can be any suitable chambers for processing wafers. In some examples, processing chamber 122 may be capable of performing a cleaning process, processing chamber 120 may be capable of performing an etching process, and processing chambers 124, 126, 128, 130 may be capable of performing respective epitaxial growth processes. Processing chamber 122 can be a SiCoNi (trademark) Preclean chamber available from Applied Materials of Santa Clara, California. Processing chamber 120 can be a Selectra (trademark) Etch chamber available from Applied Materials of Santa Clara, California.

[0018] The system controller 190 is coupled to the processing system 100 to control the processing system 100 or its components. For example, the system controller 190 may control the operation of the processing system 100 using direct control of chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with chambers 104, 106, 108, 116, 118, 110, 120, 122, 124, 126, 128, 130. During operation, the system controller 190 enables data collection and feedback from each chamber to coordinate the performance of the processing system 100.

[0019] The system controller 190 generally includes a central processing unit (CPU) 192, a memory 194, and support circuitry 196. The CPU 192 can be one of any form of general-purpose processor that can be used in an industrial setting. The memory 194, or non-transitory computer-readable medium, is accessible by the CPU 192 and can be one or more of memories such as random access memory (RAM), read-only memory (ROM), floppy disks, hard disks, or any other form of local or remote digital storage. The support circuitry 196 is coupled to the CPU 192 and can include a cache, clock circuitry, input / output subsystems, power supplies, and the like. The various methods disclosed herein can generally be implemented under the control of the CPU 192 by the CPU 192 executing computer instruction codes stored in the memory 194 (or in the memory of a particular process chamber), for example, as software routines. When the computer instruction codes are executed by the CPU 192, the CPU 192 controls the chambers to perform processes according to various methods.

[0020] Other processing systems can be of other configurations. For example, more or fewer processing chambers can be coupled to the transfer device. In the illustrated example, the transfer device includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) can be implemented as the transfer device in the processing system.

[0021] FIG. 2A is a schematic diagram of a portion of a three-dimensional (3D) memory cell array 200 of dynamic random access memory (DRAM) cells M (also referred to as “memory cells”) according to one or more embodiments of the present disclosure.

[0022] As shown in FIG. 2B, a single memory cell M includes an access transistor Q and a storage capacitor C. The memory cell M stores a data bit by storing a packet of charge (i.e., binary 1) or no charge (i.e., binary 0) on the storage capacitor C. The data bit is input and output by a bit line BL connected to the source / drain of the access transistor Q, and the input is controlled by a word line WL connected to the gate of the access transistor Q.

[0023] The memory cell array 200 includes memory levels L n (n = 1, 2, 3,...) (the first memory level L1 and the second memory level L2 are shown) stacked in the Z direction. Each memory level L n includes a two-dimensional (2D) array of memory cells M. Although only two memory levels are shown in FIG. 2A, the memory cell array 200 can include more memory levels L n (n = 3, 4,...) stacked above the second memory level L2 in the Z direction.

[0024] In the memory cell array 200, the bit lines BL extend vertically in the Z direction, and the word lines WL extend horizontally in the Y direction. Each of the bit lines BL is linked to the source / drain of an access transistor Q aligned vertically in the Z direction. Each of the word lines WL is linked to the gate of an access transistor Q aligned horizontally in the Y direction.

[0025] FIG. 3A is an isometric view of a portion of a semiconductor structure 300 that can form a 3D memory cell array, such as a portion of the memory cell array 200, according to one or more embodiments of the present disclosure. FIG. 3B is a cross-sectional view of a portion of the semiconductor structure 300 along line B-B' shown in FIG. 3A. FIG. 3C is a cross-sectional view of a portion of the semiconductor structure 300 along line C-C' shown in FIG. 3A. FIG. 3D is a cross-sectional view of a portion of the semiconductor structure 300 along line D-D' shown in FIG. 3A. FIG. 3E is a cross-sectional view of a portion of the semiconductor structure 300 along line E-E' shown in FIG. 3A. As shown, two memory levels L1 and L2 are stacked in the Z direction on the substrate 302. The semiconductor structure 300 includes more memory levels L n (n = 3, 4,...) (not shown).

[0026] The semiconductor structure 300 includes a left field effect transistor (FET) module TR L and a right FET module TR separated from the left FET module TR in the X direction by a trench 304 L >. The semiconductor structure 300 further includes a left capacitor module C adjacent to the left FET module TR in the X direction R and a right capacitor module C adjacent to the right FET module TR in the X direction L . The left FET module TR L and the left capacitor module C R are divided into a plurality of sections S in the Y direction R (m = 1, 2, 3,...) (S L , S L , and S Lm ). L1 , S L2 , and SL3 is shown in FIG. 3A). The right FET module TR R and the right capacitor module C R are divided into a plurality of sections S Rm (m = 1, 2, 3,...) in the Y direction (S R1 , S R2 , and S R3 are shown in FIGS. 3A, 3C, and 3D). Each section S Lm (m = 1, 2, 3) at each memory level L n (n = 1, 2,...) in the left FET module TR L and the left capacitor module C L together form a memory cell M. Similarly, each section S Rm (m = 1, 2, 3) at each memory level L n (n = 1, 2,...) in the right FET module TR R and the left capacitor module C R together form a memory cell M. Only three sections S Lm (m = 1, 2, 3) and S Rm (m = 1, 2, 3) are shown, but more sections can be arranged along the Y direction.

[0027] As used herein, the term "substrate" refers to a layer of material that serves as a basis for subsequent processing operations and includes a surface to be cleaned. Substrate 302 can be a silicon-based material or any suitable insulating or conductive material, as needed. Substrate 302 can include materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0028] Memory level L n (n = 1, 2,...) FET module TR L and TR R each include a semiconductor layer 306 and a word line metal layer 308a. In some embodiments, memory level L n (n = 1, 2,...) FET module TR L and TR R each further include a word line metal layer 308b. Cross-section 306S of semiconductor layer 306 serves as the source / drain of the corresponding access transistor Q, respectively. Memory level L n (n = 1, 2,...) The word line metal layer 308a and the word line metal layer 308b extend in the Y direction and can be electrically connected to each other within memory level L n (connection points are not shown). Semiconductor layer 306 has gate oxide 310 above and below in the Z direction in a dual-gate configuration. Each of word line metal layers 308a and 308b has gate oxide 310 around word line metal layers 308a, 308b and is embedded in spacer 312. Memory level L n (n = 1, 2,...) FET module TR L and TR R are separated from adjacent memory levels L by spacer 312 n+1FET module TR in L and TR R are separated. The spacer 312 also separates the memory level L n (n = 1, 2,...) of adjacent sections (e.g., S shown in FIG. 3C R1 , S R2 , and S R3 ) to separate the semiconductor layer 306. The FET module TR at the memory level L1 L and TR R can be separated from the substrate 302 by the spacer 312. The semiconductor layer 306 can each have a width in the Y direction of between about 20 nm and about 60 nm, e.g., about 40 nm, and a thickness in the Z direction of between about 10 nm and about 30 nm, e.g., about 20 nm. The horizontal spacing between adjacent semiconductor layers 306 in the Y direction can be between about 140 nm and about 180 nm, e.g., 160 nm, and the vertical spacing between adjacent semiconductor layers 306 in the Z direction can be between about 50 nm and about 100 nm, e.g., about 80 nm. The bit line BL can have a width in the Y direction of between about 40 nm and about 120 nm, e.g., about 80 nm, and a thickness in the X direction of between about 40 nm and about 120 nm, e.g., about 80 nm. In some memory array designs, the BL is common to the left FET module TR L and the right FET module TR R , and thus the width of the bit line BL in the X direction is the width of the trench 304. In these designs, the word line WL on the left FET module TR L and the word line WL on the right FET module TR R can address two logical word line addresses and be controlled separately. In some other memory array designs, two separate bit lines BL, one on the left FET module TR L and the right FET module TR ROn the other hand, the upper one is formed. These bit lines BL are insulated from each other and can be separately connected to different global bit lines. Enabling a single word line connection to be used for the left word line WL and the right word line WL significantly reduces the number, and thus the area, required for deep word line "staircase" contacts.

[0029] The semiconductor layer 306 can be formed from silicon (Si) or silicon germanium (SiGe). The word line metal layers 308a, 308b can be formed from copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt), or a conductive oxide or nitride thereof, or any combination thereof. The gate oxide 310 can be formed from a high-k dielectric material such as silicon dioxide (SiO2), silicon oxynitride (SiON), hafnium oxide (HfO2), zirconium oxide (ZrO2), vanadium oxide (VO2), titanium oxide (TiO2), aluminum oxide (Al2O3), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO), niobium pentoxide (Nb2O5), tantalum pentoxide (Ta2O5), etc., or any combination thereof. The spacer 312 can be formed from a dielectric material such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon oxycarbide (SiOCN), boron-doped silicon oxycarbide (SiOCBN), etc., or any combination thereof.

[0030] Memory level L n (n = 1, 2,...) the left capacitor module C L and the right capacitor module C R are each at the memory level L nIt includes a first plate metal layer 314 electrically connected to the semiconductor layer 306 therein, a second plate metal layer 316 (not shown) grounded, and a dielectric layer 318 between the first plate metal layer 314 and the second plate metal layer 316. The first plate metal layer 314 is surrounded by a dielectric layer 320. The dielectric layer 320 is also arranged to separate the first plate metal layer 314, the second plate metal layer 316, and the dielectric layer 320 between adjacent sections (for example, S R1 shown in FIG. 3D R2 , S R3 ). A diffusion barrier layer (not shown) may be inserted between the first plate metal layer 314 and the semiconductor layer 306. The first plate metal layer 314 and the second plate metal layer 316 can act as two plates of the capacitor C. The first plate metal layer 314 and the second plate metal layer 316 can be formed from cobalt (Co), tungsten (W), aluminum (Al), ruthenium (Ru), iridium (Ir), molybdenum (Mo), platinum (Pt), tantalum (Ta), titanium (Ti), rhodium (Rh), or a conductive metal nitride, or any combination thereof. The dielectric layer 318 can be formed from a high-k dielectric material such as hafnium oxide (HfO2), zirconium oxide (ZrO2), vanadium oxide (VO2), titanium oxide (TiO2), tin oxide (SnO2), aluminum oxide (Al2O3), zinc oxide (ZnO), hafnium silicon oxide (HfSiO), zirconium silicon oxide (ZrSiO), niobium pentoxide (Nb2O5), tantalum pentoxide (Ta2O5), or any combination thereof.

[0031] The semiconductor structure 300 is between adjacent sections S L of the left FET module TR Lm (m = 1, 2, 3,...) and adjacent sections S R of the right FET module TR Rm (m = 1, 2, 3,...) (for example, between section S L1 and section S R1 as shown in FIGS. 3A and 3E, between section S L2 and section SR2 and between and section S L3 and section S R3 and further includes bit lines BL extending in the Z direction within the trench 304 between. Section S Lm and section S Rm (m = 1, 2, 3,...) The bit lines BL between are in direct contact with the interface 322 on the cross-section 306S of the semiconductor layer 306, and all memory levels L n (n = 1, 2,...) at section S Lm at the left FET module TR in L is electrically connected to the semiconductor layer 306 through the interface 322 at. Section S Lm and section S Rm (m = 1, 2, 3,...) The bit lines BL between are further in direct contact with the interface 322 on the cross-section 306S of the silicon layer 306, and all memory levels L n (n = 1, 2,...) at section S Rm at the right FET module TR in R is electrically connected to the semiconductor layer 306 through the interface 322 at.

[0032] Conventionally, the bit lines BL are formed either by filling the trench 304 with doped polysilicon or other conductive material and etching away the vertical insulating gaps between the bit lines BL to leave the conductive material as the completed bit lines BL, or by depositing a dielectric material in the trench 304 and etching the vertical contact holes that are each to be connected to the source-drain regions under the vertical contact holes. In either case, a common bit line BL for the left FET module TR L and the right FET module TR R is formed.

[0033] In the embodiments described herein, the bit lines BL are formed using selective deposition, which also includes the left FET module TR L and the right FET module TR RIt is possible to enable two separate bit lines BL above it. First, doped source / drain regions are formed on the exposed cross-section 306S of the semiconductor layer 306 using a suitable doping method. These doped source / drain regions may or may not bridge to vertically connect the bit lines BL. Thereafter, another selective deposition of metal is performed to form a metal silicon compound interface 322, and then deposition of the same metal or even a different metal follows to form a metal interconnect layer (referred to as 502 in FIG. 5C). The metal silicon compound is a molybdenum silicon compound (Mo x Si y ), a titanium silicon compound (Ti x Si y ), a cobalt silicon compound (Co x Si y ), nickel (Ni x Si y ), a tantalum silicon compound (Ta x Si y) or any combination thereof. Interface 322 provides an ohmic contact between semiconductor layer 306 and bit line BL. The bit line BL can be formed from a metal such as molybdenum (Mo), titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), or any combination thereof. The selectively deposited materials can be a silicon layer, a silicon compound layer, a metal layer, or any combination thereof, as long as they bridge and form a continuous vertical succession to form the bit line BL. The trench 304 and the bit line BL are ultimately provided with a dielectric layer 324 to insulate the bit line BL, which can also partially or completely fill the trench 304. The trench 304 can have voids buried below the surface to reduce the parasitic capacitance of the bit line BL, but is sealed at the top surface to enable the processing of the upper interconnect lines for the individual vertical bit lines BL. The dielectric layer 324 is formed from a dielectric material such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), boron nitride (BN), silicon oxycarbide nitride (SiOCN), boron-doped silicon oxycarbide nitride (SiOCBN), aluminum oxide (Al2O3), or hafnium oxide (HfO2), or any combination thereof.

[0034] FIG. 4 shows the FET module TR in the semiconductor structure 300 according to one or more implementations of the present disclosure L and the FET module TR RFIG. 400 shows a process flow diagram of a method 400 for forming bit lines BL between them. FIGS. 5A and 5C are cross-sectional views of a portion of the semiconductor structure 300 along line B-B' shown in FIG. 3A corresponding to various states of the method 400, and FIGS. 5B, 5D, and 5E are cross-sectional views of a portion of the semiconductor structure 300 along line E-E' shown in FIG. 3A corresponding to various states of the method 400. FIGS. 5A, 5B, 5C, 5D, and 5E show only partial schematic views of the semiconductor structure 300, and it should be understood that the semiconductor structure 300 may include any number of transistor sections and additional materials having the aspects shown in the figures. Also, although the method shown in FIG. 4 is described continuously, it should be noted that other process sequences including one or more operations that are omitted and / or added and / or rearranged in another desirable order are within the scope of the embodiments of the present disclosure provided herein.

[0035] FET modules TR in the semiconductor structure 300 including a semiconductor layer 306, a word line metal layer 308a, a word line metal layer 308b, a gate oxide 310, a spacer 312, a first plate metal layer 314, a second plate metal layer 316, a dielectric layer 318, a dielectric layer 320, and a dielectric layer 324 L and TR RIt can be formed prior to forming bit line BL by method 400 using any suitable deposition technique such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), as well as patterning techniques such as lithography and etching processes. Each of the semiconductor layers 306 can have a width in the Y direction of between about 20 nm and about 60 nm, for example, about 40 nm, and a thickness in the Z direction of between about 10 nm and about 30 nm, for example, about 20 nm. The horizontal spacing between adjacent semiconductor layers 306 in the Y direction can be between about 140 nm and about 180 nm, for example, 160 nm, and the vertical spacing between adjacent semiconductor layers 306 in the Z direction can be between about 50 nm and about 100 nm, for example, about 80 nm. The bit line BL can have a width in the Y direction of between about 40 nm and about 120 nm, for example, about 80 nm, and a thickness in the X direction of between about 40 nm and about 120 nm, for example, about 80 nm.

[0036] Method 400 begins at block 410 and, as shown in FIGS. 5A and 5B, a first selective deposition process is performed to form a self-aligned interface 322 on the exposed cross-section 306S of the semiconductor layer 306 on the sidewall of the trench 304 (including the cross-section 306S of the semiconductor layer 306, the cross-section 310S of the gate oxide 310, and the cross-section 312S of the spacer 312). The first selective deposition begins with a suitable doping method to form a doped source / drain region at the cross-section 306S of the semiconductor layer 306. The first selective deposition is a molybdenum silicon compound (Mo x Si y ), titanium silicon compound (Ti x Si y ), cobalt silicon compound (Co x Si y ), nickel (Ni x Si y ), tantalum silicon compound (Ta x Si y) Continue the selective deposition of the metal silicon compound, such as or any combination thereof. Interface 322 provides an ohmic contact between the semiconductor layer 306 and the bit line BL to be formed.

[0037] In some embodiments, the metal source may include molybdenum (Mo), titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), or any combination thereof. The etching gas includes an etchant gas and a carrier gas, where the etchant gas can be a by-product of the deposition gas itself. The etchant gas may include a chlorine-containing gas such as hydrogen chloride (HCl), chlorine (Cl2), carbon tetrachloride (CCl4), chloroform (CHCl3), dichloromethane (CH2Cl2), or chloromethane (CH3Cl). The carrier gas may include nitrogen (N2), argon (Ar), helium (He), or hydrogen (H2).

[0038] The deposition process may include any suitable deposition process such as epitaxial deposition, atomic layer deposition (ALD), chemical vapor deposition (CVD), spin-on, physical vapor deposition (PVD). The deposition process and the etching process in block 410 can each be performed in a processing chamber, such as the processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG. 1, at a temperature between about 300°C and about 800°C and at a pressure between 1 Torr and 50 Torr.

[0039] In block 420, as shown in FIGS. 5C and 5D, a second selective deposition process is performed to form a self-aligned metal interconnect layer 502 on the exposed surface of interface 322 on the sidewall of trench 304 (including interface 322, cross-section 310S of gate oxide 310, and cross-section 312S of spacer 312). The second selective deposition process is a continuation of the first selective deposition process in block 410, and thus there is net deposition of material on interface 322 and 0 deposition or net etching of material on the surrounding surface of the sidewall of trench 304 (including cross-section 310S of gate oxide 310 and cross-section 312S of spacer 312). In the deposition process, the exposed surface of trench 304 is exposed to a deposition gas containing a metal source. The metal source can be the same as the metal source used in block 410 or different from the metal source used in block 410. Interface 322 reacts with the metal source to form metal interconnect layer 502. Metal interconnect layer 502 grows in the X direction and isotopically in the Y-Z plane from each of interface 322 towards the center of trench 304 and merges with the portions growing from adjacent interface 322. The merged metal interconnect layer 502 adjacent to FET module TR L further merges, as shown in FIGS. 3B and 3E, with the merged metal interconnect layer 502 adjacent to FET module TR R to form a continuous bit line BL. In some other embodiments, the merged metal interconnect layer 502 adjacent to FET module TR L forms bit line BL alone, and the merged metal interconnect layer 502 adjacent to FET module TR R forms a separate bit line BL.

[0040] In some embodiments, the metal source can include molybdenum (Mo), titanium (Ti), cobalt (Co), nickel (Ni), tantalum (Ta), or any combination thereof.

[0041] In block 430, as shown in FIG. 5E, a filling process is performed to fill trench 304 with a dielectric material to form dielectric layer 324.

[0042] Dielectric layer 324 is formed from a dielectric material such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), boron nitride (BN), silicon oxycarbide nitride (SiOCN), boron-doped silicon oxycarbide (SiOCBN), aluminum oxide (Al2O3), or hafnium oxide (HfO2), or any combination thereof.

[0043] The filling process in block 430 may include any suitable deposition process, such as a chemical vapor deposition (CVD) process, in a processing chamber such as processing chambers 120, 122, 124, 126, 128, or 130 shown in FIG. 1.

[0044] Embodiments described herein provide a system and method for forming vertical bit lines in a 3D DRAM device having an interface between vertical bit lines and FET devices forming memory cells. The vertical bit lines are formed by a self-aligned deposition process of a metal such as molybdenum (Mo) without the need for a HAR etching process to form slots for the vertical bit lines. Thus, the resistance of the bit lines is reduced compared to polycrystals that have conventionally been used as bit lines that may contain voids. The interface is formed from a metal silicon compound such as molybdenum disilicide (MoSi2) by a selective self-aligned deposition process, providing an ohmic contact between the FET device and the vertical bit line and reducing contact parasitic resistance.

[0045] The foregoing is directed to embodiments of the present disclosure, but other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof, which is determined by the following claims.

Claims

1. A semiconductor structure, comprising: A plurality of memory levels stacked in a first direction, each of the plurality of memory levels comprising: A semiconductor layer; A word line metal layer above the semiconductor layer in the first direction; An interface on a cross-section of the semiconductor layer; And a plurality of memory levels; A spacer between adjacent memory levels among the plurality of memory levels in the first direction; A bit line in contact with the interface of each of the plurality of memory levels, the bit line extending in the first direction; And comprising: The bit line contains a metal material; The interface contains a silicon compound; A semiconductor structure.

2. The semiconductor layer contains silicon; The semiconductor structure according to claim 1.

3. The semiconductor structure according to claim 1, wherein the metal material contains molybdenum (Mo), and the interface contains a molybdenum silicon compound.

4. The semiconductor structure according to claim 1, wherein the metal material contains titanium (Ti), and the interface contains a titanium silicon compound.

5. The semiconductor structure according to claim 1, wherein the spacer contains silicon nitride.

6. The semiconductor layer has: A width between 20 nm and 60 nm in a second direction perpendicular to the first direction; A thickness between 10 nm and 30 nm in the first direction; A vertical interval between adjacent semiconductor layers of the plurality of memory levels between 140 nm and 180 nm; The semiconductor structure according to claim 1, having

7. wherein the bit line has a width between 40 nm and 120 nm in the second direction, and a thickness between 40 nm and 120 nm in a third direction orthogonal to the first direction and the second direction The semiconductor structure according to claim 6, having

8. A method of forming a metal bit line in a semiconductor device, the method comprising: performing a first selective deposition process to selectively form a metal silicon compound layer on sidewalls of a trench, wherein the sidewalls of the trench comprise a first cross-section of each of a plurality of semiconductor layers stacked in a first direction and a second cross-section of a spacer disposed between adjacent semiconductor layers among the plurality of semiconductor layers, performing the first selective deposition process; performing a second selective deposition process to selectively form a metal layer on the sidewalls of the trench; performing a filling process, the filling process including depositing a dielectric material in the trench, performing the filling process and including wherein the metal layer on the sidewalls of the trench is continuous across the plurality of semiconductor layers to form a metal bit line. Method.

9. each of the semiconductor layers includes silicon The method according to claim 8.

10. The method according to claim 8, wherein the metal layer includes molybdenum (Mo) and the metal layer includes a molybdenum silicon compound.

11. The method according to claim 8, wherein the metal layer includes titanium (Ti) and the metal layer includes a titanium silicon compound.

12. The method according to claim 9, wherein the spacer includes silicon nitride.

13. Each of the semiconductor layers has a width between 20 nm and 60 nm in a second direction orthogonal to the first direction, a thickness between 10 nm and 30 nm in the first direction, and a vertical spacing between adjacent semiconductor layers between 140 nm and 180 nm The method according to claim 8.

14. The metal bit line has a width between 40 nm and 120 nm in the second direction, and a thickness between 40 nm and 120 nm in a third direction orthogonal to the first direction and the second direction The method according to claim 13.

15. A three-dimensional (3D) dynamic random access memory (DRAM) device comprising: a plurality of memory levels stacked in a first direction, each of the plurality of memory levels comprising: a semiconductor layer having a first end and a second end in a second direction orthogonal to the first direction; a word line metal layer; an interface on a cross-section at the first end of the semiconductor layer; and a plurality of memory levels comprising: a spacer between adjacent memory levels among the plurality of memory levels in the first direction; a bit line in contact with the interface of each of the plurality of memory levels, the bit line extending in the first direction; and comprising: the bit line includes a metal material, the interface includes a silicon compound, A three-dimensional (3D) dynamic random access memory (DRAM) device.

16. The semiconductor layer includes silicon, The 3D DRAM device according to claim 15.

17. The 3D DRAM device according to claim 15, wherein the metal material contains molybdenum (Mo) and the interface contains a molybdenum silicon compound.

18. The 3D DRAM device according to claim 15, wherein the metal material contains titanium (Ti) and the interface contains a titanium silicon compound.

19. The 3D DRAM device according to claim 15, wherein the spacer contains silicon nitride.

20. The semiconductor layer has a width between 20 nm and 60 nm in the second direction, a thickness between 10 nm and 30 nm in the first direction, and a vertical interval between adjacent semiconductor layers of the plurality of memory levels between 140 nm and 180 nm, and the bit line has a width between 40 nm and 120 nm in the second direction, and a thickness between 40 nm and 120 nm in a third direction orthogonal to the first direction and the second direction. The 3D DRAM device according to claim 15.

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