System and method for interpolating a register-based look-up table

Abstract

A method executed by a computer of the present disclosure for interpolating a register-based look-up table can include identifying, within a set of registers, a look-up table encoded for storage within the set of registers. Further, the method can include receiving a request to look up a value within the look-up table and responding to the request by interpolating a representation of the requested value from the encoded look-up table stored in the set of registers. Further, various other methods, systems, and computer-readable storage media are also disclosed.

Description

Technical Field

[0001] (Priority Claim) This application claims the benefit of U.S. Provisional Patent Application No. 63 / 349,559, filed on June 6, 2022, entitled "SYSTEMS AND METHODS FOR INTERPOLATING REGISTER-BASED LOOKUP TABLES", the entire content of which is incorporated herein by reference.

Background Art

[0002] Lookup tables can be used by acceleration processors to more efficiently approximate the outputs of various calculations. However, many machine learning algorithms typically use various transcendental functions that are not efficiently handled by hardware accelerators.

[0003] The accompanying drawings illustrate some exemplary embodiments and form a part of this specification. In conjunction with the following description, these drawings demonstrate and explain various principles of the present disclosure.

Brief Description of the Drawings

[0004]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

[0005] Throughout the drawings, the same reference numerals and descriptions, while not necessarily identical, indicate similar elements. The exemplary embodiments described herein are capable of various modifications and alternative forms, but specific embodiments are shown by way of example in the drawings and described in detail herein. However, the exemplary embodiments described herein are not intended to be limited to the specific forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternative forms within the scope of the appended claims.

[0006] The present disclosure generally relates to systems and methods for interpolating register-based look-up tables. Depending on the design, it is possible to attempt to include function units (e.g., hardware accelerators) specialized / hardware-ized for specific functions (e.g., sigmoid, Batch Norm, Gaussian Error Linear Unit (GELU), etc.). However, due to the very rapid speed of algorithm changes in the machine learning space, such specialized units are prone to obsolescence. On the other hand, the embodiments described herein utilize a combination of a software programmable look-up table (LUT) and a vector hardware interpolation unit to calculate the result of any numerical function either accurately or approximately, depending on the data width (e.g., half-precision floating point or fp16) and the storage size of the look-up table.

[0007] As an example, the systems and methods disclosed herein can provide high performance for these operations in a flexible, efficient, algorithm-agnostic, and future-proof way, compared to machine learning algorithms that involve some computationally expensive numerical function evaluations (e.g., GELU, batch normalization) that generally degrade performance (and would otherwise require hardware units that are prone to obsolescence). By way of illustration, the following equation can show how the linear activation function GELU (Gaussian Error Linear Unit) is approximated by six multiplications, two additions, and the hyperbolic tangent function (aGELU).

[0008] [Number]

[0009] (As addressed in embodiments of the present disclosure) Mechanisms effective for accelerating such operations can improve the performance of training and inference, and in particular, transcendental functions such as TANH often have low throughput.

[0010] In one or more embodiments, processing other than matrix multiplication can consume a large amount of execution time when attempted by existing hardware accelerators. In general, such operations (e.g., transcendental, square root, reciprocal, composite operations) involve functions that are inefficient and time-consuming for pipelining to achieve high throughput. Thus, as described in more detail below, embodiments of the present disclosure can provide improved computational efficiency in various ways, including using, for example, hardware registers as a source of lookup table inputs instead of using memory space and cache hierarchies. In one or more embodiments, the systems and methods described herein can significantly improve the throughput of complex functions, transcendental functions, etc., while maintaining an acceptable level of accuracy for machine learning. Further, the systems and methods described herein can further reduce the power consumption of the acceleration processor by performing interpolation directly from registers.

[0011] As will be described in detail below, the present disclosure describes various systems and methods for interpolating register-based look-up tables. In one embodiment, a method for interpolating a register-based look-up table may be executed by a computing device including at least one processor, identifying, within a set of registers, a look-up table encoded for storage within the set of registers, receiving a request to look up a value within the look-up table, and responding to the request by interpolating a representation of the requested value from the encoded look-up table stored in the set of registers.

[0012] In one or more embodiments, the method described above may include identifying the number of bits available within the set of registers and encoding the look-up table by reducing the size of the look-up table to fit the number of bits available within the set of registers. For example, reducing the size of the look-up table may include allocating a number of bits to represent intermediate range values within the look-up table and allocating fewer bits to represent at least one of a set of values greater than the intermediate range values or a set of values less than the intermediate range values relative to the number of bits representing the intermediate range values.

[0013] In one or more embodiments, the look-up table may include a table having representative outputs for a machine learning function. Additionally, in one or more embodiments, the set of registers may include at least two registers of at least one processor of the computing device. In at least one embodiment, interpolating a representation of the requested value includes identifying an approximation of the requested value within the look-up table. Further, interpolating a representation of the requested value may include identifying an exact representation of the requested value within the look-up table.

[0014] In an exemplary embodiment, a system for interpolating a register-based look-up table includes at least one physical processor and a physical memory comprising computer-executable instructions that, when executed by the at least one physical processor, cause the at least one physical processor to identify a look-up table encoded for storage within a set of registers, receive a request to look up a value within the look-up table, and respond to the request by interpolating a representation of the requested value from the encoded look-up table stored in the set of registers.

[0015] In some exemplary embodiments, the methods described above may be encoded as computer-readable instructions on a non-transitory computer-readable storage medium. For example, the computer-readable medium includes one or more computer-executable instructions that, when executed by at least one processor of a computing device, cause the computing device to identify a look-up table encoded for storage within a set of registers, receive a request to look up a value within the look-up table, and respond to the request by interpolating a representation of the requested value from the encoded look-up table stored in the set of registers.

[0016] More specifically, FIG. 1 shows an overview of a register-based look-up table system 102 that uses a programmable / reconfigurable look-up table (LUT) 104 instead of implementing N different hardware functions (sqrt, atan, tanh, 1 / x, etc.). In one or more embodiments, as illustrated, the register-based look-up table system 102 can utilize the look-up table 104 in connection with an interpolation unit 106 to generate approximate results of complex machine learning-based operations.

[0017] For example, as shown in FIG. 1, a register-based look-up table system 102 can maintain a look-up table 104 across the register bits of register 108 and then interpolate using the remaining register bits. For example, in one embodiment, the register-based look-up table system 102 can use sign bit 110a, exponent bits 110b - 110i, and mantissa or fraction bits 110j, 110k for the look-up table 104. In at least one embodiment, by using such bits 110a - 110k, the look-up table 104 can be sized 2 11 *2B = 4KB. As further shown, in at least one embodiment, the register-based look-up table system 102 can further interpolate using the remaining mantissa bits 110l - 110p. Using this format, for example, the register-based look-up table system 102 can generate a GELU equation response using a single LUT (e.g., look-up table 104) instead of involving six multiplication operations, two addition operations, and one tanh operation.

[0018] As described above, in addition to using a look-up table stored in one or more hardware registers, the register-based look-up table system 102 can utilize an interpolation unit 106. In one or more embodiments, the interpolation unit 106 can use the contents of the look-up table 104 to calculate or approximate the result of any function (which can be arbitrary due to the fact that a programmer can load what is desired into the contents of the look-up table). Thus, in relation to the embodiment shown in FIG. 1, the look-up table 104 may be too large to store in a look-up table and one or two x86 AVX-512 registers (e.g., 64 bytes per zmm register) that may be required if interpolation instructions are limited to three or fewer register operands.

[0019] Therefore, to fit the lookup table 104 within the bit limits of a conventional hardware system, the register-based lookup table system 102 can take advantage of the fact that most of the functions of interest do not take on completely arbitrary random values. For example, the register-based lookup table system 102 can take advantage of the fact that for very large magnitudes of input or very small absolute values, only a few sample points are needed to maintain accurate interpolation / approximation. This embodiment applies, among other things, to many of the numerical functions utilized in machine learning. By way of illustration, the curves of common functions such as GELU, ReLU, and ELU flatten out abruptly for both very small and very large inputs.

[0020] Therefore, as seen in FIG. 2, the register-based lookup table system 102 can divide the lookup table 104 into regions, where the first region 202 covers a numerical range where the floating-point exponent is neither very large nor very small. For example, in an exemplary embodiment, this is indicated within the register 108 by the four most significant exponent bits closest to the sign bit(s). Further, the register-based lookup table system 102 can divide the lookup table 104 into a top region 204a that represents values having an exponent greater than the threshold range (i.e., the sign bit of the exemplary register 108' indicating that the exponent is positive). Also, the register-based lookup table system 102 can divide the lookup table 104 into a bottom region 204b that represents values having an exponent less than the threshold range (i.e., the sign bit of the exemplary register 108' indicating that the exponent is negative).

[0021] In one or more embodiments, as shown by exemplary register 108’, the register-based look-up table system 102 can use three most significant exponent bits in addition to the sign bit, in relation to the values represented in the most significant region 204a and the least significant region 204b. Thus, for most functions, since very large or very small inputs result in little change to the function output, the register-based look-up table system 102 can use fewer bits to interpolate very large and / or very small inputs (e.g., within the second region 204). Further, as shown by register 108, the register-based look-up table system 102 can use a greater number of bits (e.g., in addition to the sign bit, the four most significant bits) to obtain higher precision in relation to a typical range of values of interest (e.g., within the first region 202).

[0022] In one or more embodiments, the register-based lookup table system 102 can adjust the number of bits utilized within a register according to the area of the lookup table indexed by the register. In at least one embodiment, utilizing various numbers of various types of register bits can lead to various storage capacity requirements for the associated lookup table. More specifically, the precision register (e.g., register 108, etc.) and the interpolation register (e.g., exemplary register 108’, etc.) may include a sign bit (e.g., sign bit 110a shown in FIG. 1), exponent bits (e.g., exponent bits 110b - 110i shown in FIG. 1), and mantissa bits (e.g., mantissa bits 110j - 110k shown in FIG. 1). However, the register-based lookup table system 102 need not utilize all of the available exponent bits and mantissa bits of a given register in order to reduce the required capacity of the associated lookup table. For example, Table 206 shows how the register-based lookup table system 102 can vary the size of the lookup table by utilizing different numbers of the exponent bits and mantissa bits of the register that indexes into these lookup tables.

[0023] For example, as seen in Table 206, a precision register (e.g., similar to register 108) using 1 sign bit, 4 exponent bits, and 2 mantissa bits (e.g., "1,4,2") can index into a look-up table with a size of 320B with higher precision for a typical range of values of interest (e.g., within the first region 202, etc.). Similarly, an interpolation register (e.g., similar to the exemplary register 108') using 1 sign bit, 4 exponent bits, and 0 mantissa bits (e.g., "1,4,0") can also index into a 320B look-up table, although with fewer bits, to interpolate very large or very small inputs. Further, as seen in Table 206, the precision register, together with an interpolation register using 1 sign bit, 3 exponent bits, and 0 mantissa bits (e.g., "1,3,0"), can index into a look-up table with a size of 288B using 1 sign bit, 4 exponent bits, and 2 mantissa bits (e.g., "1,4,2"). Table 206 further shows additional bit arrays for registers that index into look-up tables with sizes of 192B, 160B, 128B, or 96B.

[0024] In summary, look-up tables using bit arrays such as those listed along the top of Table 206 use higher precision for a typical range of values of interest, and look-up tables using bit arrays such as those listed along the left side of Table 206 use fewer bits to interpolate very large and very small inputs. In at least one embodiment, Table 206 can assume the BFloat16 (Brain Floating Point) format. In a further embodiment, the same results can apply to the FP16 (Half Precision Floating Point) format or another suitable format.

[0025] Figure 3 shows a potential embodiment of the register-based lookup table system 102 within the CPU. By way of example, in one embodiment, the register-based lookup table system 102 can execute new instructions for general function evaluation. In the embodiment shown in Figure 3, the small input lookup table 302 can correspond to the first region 202 shown in Figure 2, which represents values with exponents closer to 0. In one or more embodiments, the small input lookup table 302 can use 5 bits (e.g., 1 sign bit, 4 exponent bits, 0 mantissa bits) for the index lookup of the lookup table, which can require 5 2

[0026] = 32 entries, and at 2 bytes per entry (in the case of bf16), a total of 64 bytes. Similarly, the large input lookup table 304 can correspond to the second region 204 shown in Figure 2, which represents values with higher or larger magnitude exponents. In at least one embodiment, the large input lookup table 304 can use 5 bits (e.g., 1 sign bit, 4 exponent bits, 0 mantissa bits) for the index lookup of the lookup table, which can require 5 2

[0027] = 32 entries, and at 2 bytes per entry (in the case of bf16), a total of 64 bytes. In at least one embodiment, each of the small input lookup table 302 and the large input lookup table 304 can fit into a single register (e.g., a 512-bit register). As described above, Figure 3 shows a register-based lookup table system 102 that executes new instructions for general function evaluation. By way of example, the general function can be as follows.

[0028]

Number

[0029] In at least one embodiment, the function VGFUNCBF16 includes three register operands, two of which (e.g., LUT1 and LUT2 corresponding to the small input lookup table 302 and the large input lookup table 304 respectively) specify registers that hold lookup tables. The first operand "src" provides an input value (x) (e.g., 32bfloat16 values packed in a single zmm 512-bit register). If the small input lookup table 302 and the large input lookup table 304 store samples corresponding to the function "f", VGFUNCBF16 extracts each "x" from the source (src) register.

[0030] Next, as seen in FIG. 3, the register-based lookup table system 102 can perform an exponent range check 306 by using the exponent of the x value to determine which lookup table to use. Further, the register-based lookup table system 102 performs lookups from the corresponding lookup tables for the two closest entries (which may be consecutive), and then uses the interpolation unit 308 to perform interpolation based on these two values from the corresponding lookup tables to calculate / approximate the output f(x). Specifically, the register-based lookup table system 102 calculates X LO and X HI (e.g., the two closest x values corresponding to the lookup table index) to enable the interpolation unit 308 to execute. Next, the register-based lookup table system 102 uses X LO and X HI to look up two entries in the lookup table (e.g., f(X LO ) and f(X HI )). In at least one embodiment, next, the interpolation unit 308 performs linear interpolation based on f(X LO ) and (X HI ) to estimate the value of f(x).

[0031] In one or more embodiments, the register - based lookup table system 102 performs this interpolation by using an interpolation unit to use some of the mantissa bits not used by the lookup step. Since there are 32 x's in the input source register (src), this generates 32 f(x) outputs. In at least one embodiment, the register - based lookup table system 102 can write such outputs to a destination register. For example, in some embodiments, 102 can write these outputs to the same source register (src), thereby overwriting the input.

[0032] In some embodiments, the register - based lookup table system 102 can determine the exact selection of exponent bits and mantissa bits selected from the input (and value format and interpolation function) based on the information encoded within the instruction operand. In one example, 6 bits (1, 4, 1) can be used to index into the lookup table. To hold the lookup table within a single register, the register - based lookup table system 102 can reduce each lookup table entry to 1 byte corresponding to (1, 5, 2). In some embodiments, the interpolation unit 308 can take two 1 - byte values from consecutive entries, perform interpolation, and output a 2 - byte bfloat16 value. Further, in some embodiments, each lookup table (e.g., the small - input lookup table 302 and the large - input lookup table 304) can have an associated unique interpolation function.

[0033] Based on the embodiments illustrated in FIG. 3, in additional embodiments, the register-based lookup table system 102 can use smaller source / destination registers such as 256 bits (16 inputs / outputs) or even scalar source / destination registers. In one or more embodiments, the register size is not critical to the operation of the register-based lookup table system 102. Instead, in one or more embodiments, the register-based lookup table system 102 may primarily rely on being able to store the lookup table in the largest possible register.

[0034] FIG. 4 is a block diagram of an exemplary system 400 (e.g., the register-based lookup table system 102 described previously) for interpolating a register-based lookup table. As shown in this figure, the exemplary system 400 can include one or more modules 402 for performing one or more tasks. As will be described in more detail below, the module 402 can include an identification module 404, a lookup module 406, and an interpolation module 408. Although illustrated as individual elements, one or more of the modules 402 in FIG. 4 can represent a single module or part of an application.

[0035] In certain embodiments, one or more of the modules 402 in FIG. 4 can represent one or more software applications or programs that, when executed by a computing device, can cause the computing device to perform one or more tasks. For example, as will be described in more detail below, one or more of the modules 402 can represent modules stored and configured to execute on one or more computing devices. Also, one or more of the modules 402 in FIG. 4 can represent all or part of one or more dedicated computers configured to perform one or more tasks. In a preferred embodiment, the module 402 is implemented as hardware (e.g., circuitry) within the physical processor 430 rather than being stored as a software module within the memory 440.

[0036] As shown in FIG. 4, the exemplary system 400 can also include one or more memory devices such as a memory 440. The memory 440 generally represents any type or form of volatile, non-volatile memory device or medium capable of storing data and / or computer-readable instructions. In one embodiment, the memory 440 can store, load, and / or maintain one or more of the modules 402. Examples of the memory 440 include, but are not limited to, random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid state drive (SSD), optical disk drive, cache, one or more variations or combinations thereof, or any other suitable storage memory.

[0037] As shown in FIG. 4, the exemplary system 400 can also include one or more physical processors such as a physical processor 430. The physical processor 430 generally represents any type or form of hardware-implemented processing unit capable of interpreting and / or executing computer-readable instructions. In one example, the physical processor 430 can access and / or modify one or more of the modules 402 stored in the memory 440. Additionally or alternatively, the physical processor 430 can execute one or more of the modules 402 to facilitate interpolating a register-based look-up table. Examples of the physical processor 430 include, but are not limited to, a microprocessor, a microcontroller, a central processing unit (CPU), a field programmable gate array (FPGA) implementing a softcore processor, an application specific integrated circuit (ASIC), a portion of one or more of these, one or more variations or combinations thereof, or any other suitable physical processor.

[0038] As shown in FIG. 4, an exemplary system 400 can include a set of registers 432. The set of registers 432 can include any suitable number of registers that the physical processor 430 uses to execute instructions. For example, the set of registers 432 can include a single register, two registers, or a large number of registers. In some embodiments, the set of registers 432 can be data registers capable of holding numerical values such as integer values, floating-point values, and / or any other suitable values. The set of registers 432 can also include registers of any suitable size. For example, the registers within the set of registers 432 can be 8-bit registers, 16-bit registers, 32-bit registers, 64-bit registers, 128-bit registers, and so on.

[0039] As described above and as shown in FIG. 4, system 400 can include an identification module 404 within module 402. In one or more embodiments, the identification module 404 determines a look-up table to apply to the input. For example, the identification module 404 can make this determination by performing an exponent range check (e.g., the exponent range check 306 shown in FIG. 3) on the input value. In at least one embodiment, the identification module 404 can determine to utilize a small input look-up table (e.g., the small input look-up table 302 shown in FIG. 3, etc.) when the exponent of the input value is close to 0. Further, the identification module 404 can determine to utilize a large input look-up table (e.g., the large input look-up table 304 shown in FIG. 3) when the exponent of the input value has a larger magnitude exponent.

[0040] As described above, as shown in FIG. 4, the system 400 can include a lookup module 406. In one or more embodiments, the lookup module 406 identifies at least two values from a specified lookup table based on bits of an input value. For example, as previously described with respect to FIG. 3, the lookup module 406 can utilize one or more sign bits, upper exponent bits, lower exponent bits, and mantissa bits to identify the two entries closest to the input value. In at least one embodiment, the two closest entries can be consecutive.

[0041] Further, as described above, as shown in FIG. 4, the system 400 can include an interpolation module 408. As used herein, the term "interpolation" refers to estimating a value based on a range of values. For example, in one or more embodiments, the interpolation module 408 can generate an interpolated value based on at least two input values. For example, the interpolation module 408 can receive two values identified within a specified lookup table from the lookup module 406 and generate an interpolated value based on the received values. In at least one embodiment, the interpolation module 408 generates an interpolated value by determining an intermediate value between the received values. For example, the interpolation module 408 can determine the average of the received values, the median of the received values, or a different intermediate value between the received values.

[0042] Many other devices or subsystems can be connected to the system 400 of FIG. 4. On the other hand, not all of the components shown in FIG. 4 need to be present in order to implement the embodiments described and / or illustrated herein. The devices and subsystems referenced above may be interconnected in a manner different from that shown in FIG. 4. Also, the system 400 can employ any number of software, firmware, and / or hardware configurations. For example, one or more of the exemplary embodiments disclosed herein may be encoded as a computer program (also referred to as computer software, software application, computer-readable instructions, and / or computer control logic) on a computer-readable storage medium.

[0043] As used herein, the term "computer-readable storage medium" generally refers to any form of device, carrier, or medium capable of storing or carrying computer-readable instructions. Examples of computer-readable storage medium include, but are not limited to, transmission-type media such as carrier waves, and non-transitory media such as magnetic storage media (e.g., hard disk drives, tape drives, and floppy (R) disks), optical storage media (e.g., compact disks (CDs), digital video disks (DVDs), and BLU-RAY (R) disks), electronic storage media (e.g., solid state drives and flash media), and other delivery systems.

[0044] FIG. 5 is a flowchart of a method 500 executed by an exemplary computer that interpolates a register-based lookup table. The steps shown in FIG. 5 can be executed by any suitable computer-executable code and / or computing system including the system 400 of FIG. 4. In one embodiment, each of the steps shown in FIGS. 1-3 may be an algorithm whose structure includes and / or is represented by a plurality of sub-steps, examples of which are provided in more detail below.

[0045] As shown in FIG. 5, in step 502, one or more of the systems described herein can interpolate a register-based lookup table. For example, the identification module 404, as part of the system 400 of FIG. 4, can identify a lookup table encoded for storage within a set of registers within the set of registers. The identification module 404 can perform step 502 in any suitable manner. For example, the identification module 404 can identify the lookup table in response to a request for the output of a function of a machine learning algorithm. Additionally or alternatively, the identification module 404 can identify the lookup table in response to a request for the output of any other suitable type of function.

[0046] As used herein, the term lookup table generally refers to any array of data that can replace runtime calculations with array indexing operations. In some embodiments, as previously explained, retrieving values from registers can be significantly faster than performing cost calculations, so savings in processing time can be important. In some embodiments, the lookup table can be pre-computed and / or prefetched. In some embodiments, the lookup table can be stored in hardware within an application-specific platform. Alternatively, the lookup table can be part of a reconfigurable hardware implementation solution provided by an FPGA.

[0047] In step 504, the lookup module 406, as part of the system 400 of FIG. 4, can receive a request to look up a value within the lookup table. The lookup module 406 can receive the request in any suitable manner and / or situation. For example, the lookup module 406 can receive the request as a direct addressing request for the output of a function.

[0048] In step 506, as part of system 400 of FIG. 4, interpolation module 408 can respond to the request by interpolating the representation of the requested value from the encoded look-up table stored in the set of registers. Interpolation module 408 can interpolate the representation of the requested value in any suitable way. For example, in some embodiments, interpolation module 408 can interpolate the representation of the requested value by identifying an approximation of the requested value within the look-up table.

[0049] Alternatively, interpolation module 408 can interpolate the representation of the requested value by identifying the exact representation of the requested value within the look-up table. For example, in one embodiment, the look-up table can include values that act as indices into an interpolation data structure. Thus, in that embodiment, interpolation module 408 can interpolate the representation of the requested value by using two or more values identified by look-up module 406 within the look-up table as indices into the data structure of the interpolated values. Using these indices, interpolation module 408 can identify the exact representation of the requested value.

[0050] In some embodiments, the systems described herein can encode a lookup table for storage within a set of registers. The systems described herein can encode the lookup table in any suitable manner. For example, the systems described herein can identify the number of bits available within a set of registers and reduce the size of the lookup table to fit the number of bits available within the set of registers. This reduction can be linear across the values in the lookup table or can be non-linear based on the data in the lookup table. For example, reducing the size of the lookup table can involve (1) allocating a number of bits to represent an intermediate range of values in the lookup table and (2) allocating fewer bits to represent at least one set of values greater than the intermediate range value or at least one set of values less than the intermediate range value relative to the number of bits representing the intermediate range value. Also, embodiments of the present disclosure can use any other suitable algorithm or mechanism to reduce the size of the lookup table to fit within a particular set of registers.

[0051] Embodiments of the present disclosure can provide various advantages over conventional methods and can be implemented in various situations. For example, embodiments of the present disclosure can provide higher performance than conventional operations (especially significantly higher throughput for complex functions, transcendental functions, etc.) while allowing an acceptable impact on the accuracy of machine learning at a relatively low silicon cost. By directly performing interpolation from registers, power consumption can also be reduced (e.g., compared to the texture cache method of an accelerated processor that repeatedly reads data from the cache hierarchy). These advantages can be realized in various systems including accelerated processors and / or hardware accelerators (e.g., central processing unit (CPU), graphics processing unit (GPU), field programmable gate array (FPGA), neural processing unit (NPU), tensor processing unit (TPU) and / or other hardware accelerators, application specific integrated circuit (ASIC), etc.).

[0052] In the above-described disclosure, specific block diagrams, flowcharts, and examples are used to describe various embodiments. However, the components, flowchart steps, operations, and / or components of each block diagram described and / or illustrated herein can be individually and / or collectively implemented using a wide range of hardware, software, or firmware (or any combination thereof) configurations. Additionally, since many other architectures can be implemented to achieve the same functions, any disclosure of components stored within other components shall be considered illustrative in nature.

[0053] The order of process parameters and steps described and / or illustrated in this specification is provided as an example only and can be changed as desired. For example, the steps illustrated and / or described in this specification can be illustrated or considered in a specific order, but these steps do not necessarily have to be executed in the order illustrated or described. The various exemplary methods described and / or illustrated in this specification can also omit one or more of the steps described or illustrated herein, or include additional steps in addition to the disclosed steps.

[0054] In this specification, various embodiments have been described and / or illustrated in the context of a fully functional computing system. However, one or more of these exemplary embodiments can be distributed as various forms of program products, regardless of the specific type of computer-readable storage medium used to actually execute the distribution. The embodiments disclosed in this specification can also be realized using modules that perform a specific task. These modules can include scripts, batches, or other executable files that can be stored on a computer-readable storage medium or within a computing system. In some embodiments, these modules can configure a computing system to execute one or more of the exemplary embodiments disclosed herein.

[0055] The above description is provided to enable those skilled in the art to make the best use of the various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or limited to any strict form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein are to be considered in all respects as exemplary and not restrictive. When determining the scope of the present disclosure, reference shall be made to the appended claims and their equivalents.

[0056] Unless otherwise specified, the terms "connected to" and "coupled to" (and their derivatives) as used in this specification and the claims are to be construed to permit both direct and indirect (i.e., via other elements or components) connections. Additionally, the term "a" or "an" as used in this specification and the claims is to be construed to mean "at least one of". Finally, for ease of use, the terms "including" and "having" (and their derivatives), when used in this specification and the claims, are interchangeable with the word "comprising" and have the same meaning.

Claims

1. A computer-executable method for interpolating a register-based lookup table, wherein at least a portion of the computer-executable method is executed by a computing device including at least one processor, the computer-executable method comprising: receiving a request to look up a value in a lookup table encoded for storage within a set of registers; responding to the request by interpolating a representation of the requested value from the encoded lookup table stored in the set of registers. A computer-executable method.

2. identifying the number of bits available within the set of registers; reducing the size of the lookup table to conform to the number of bits available within the set of registers; encoding the lookup table thereby. The computer-executable method of claim 1.

3. Reducing the size of the lookup table comprises: allocating some bits to represent intermediate range values within the lookup table; allocating fewer bits than the some bits allocated to represent intermediate range values to represent at least one of a set of values greater than the intermediate range values or a set of values less than the intermediate range values. The computer-executable method of claim 2.

4. The lookup table includes a table having representative outputs of a machine learning function. The computer-executable method of claim 1.

5. The set of registers includes at least two registers of the at least one processor of the computing device. The computer-executable method of claim 1.

6. Interpolating the representation of the requested value includes identifying an approximation of the requested value within the lookup table. The computer-executable method of claim 1.

7. Interpolating the representation of the requested value includes identifying an exact representation of the requested value within the lookup table. The computer-executable method of claim 1.

8. A system for interpolating a register-based lookup table, comprising: at least one physical processor; physical memory comprising computer-executable instructions. When the computer-executable instructions are executed by the at least one physical processor, receiving a request to look up a value in an encoded lookup table stored within a set of registers; responding to the request by interpolating a representation of the requested value from the encoded lookup table stored in the set of registers; causing the at least one physical processor to perform; a system. **Claim 9** When the computer-executable instructions are executed by the at least one physical processor, identifying the number of bits available within the set of registers; reducing the size of the lookup table to conform to the number of bits available within the set of registers; thereby causing the at least one physical processor to encode the lookup table; The system of claim 8. **Claim 10** When the computer-executable instructions are executed by the at least one physical processor, allocating some bits to represent intermediate range values within the lookup table; allocating fewer bits for at least one of a set of values greater than the intermediate range value or a set of values less than the intermediate range value for some bits representing the intermediate range value; thereby causing the at least one physical processor to reduce the size of the lookup table; The system of claim 9. **Claim 11** The lookup table includes a table having representative outputs of a machine learning function; The system of claim 8. **Claim 12** The set of registers includes at least two registers of the at least one physical processor; The system of claim 8. **Claim 13** Interpolating the representation of the requested value includes identifying an approximation of the requested value within the lookup table; The system of claim 8. **Claim 14** Interpolating the representation of the requested value includes identifying an exact representation of the requested value within the lookup table; The system of claim 8. **Claim 15** A computer-readable storage medium including one or more computer-executable instructions, When the computer-executable instructions are executed by at least one processor of a computing device, receiving a request to look up a value in an encoded look-up table for storage within a set of registers; responding to the request by interpolating a representation of the requested value from the encoded look-up table stored in the set of registers; causing the computing device to perform; a computer-readable storage medium. **Claim 16** The one or more computer-executable instructions identify the number of bits available within the set of registers; reduce the size of the look-up table to conform to the number of bits available within the set of registers; and thereby program the computing device to encode the look-up table. The computer-readable storage medium of claim 15. **Claim 17** The look-up table includes a table having representative outputs of a machine learning function. The computer-readable storage medium of claim 15. **Claim 18** The set of registers includes at least two registers of at least one processor of the computing device. The computer-readable storage medium of claim 15. **Claim 19** Interpolating the representation of the requested value includes identifying an approximation of the requested value within the look-up table. The computer-readable storage medium of claim 15. **Claim 20** Interpolating the representation of the requested value includes identifying an exact representation of the requested value within the look-up table. The computer-readable storage medium of claim 15.

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