Display substrate and display device

Abstract

The present application provides a display substrate and a display device, and relates to the technical field of displays. The display substrate can greatly reduce the overlap capacitance between signal lines, achieve low power consumption and high image quality while satisfying a high refresh rate, and has a good user experience. The display substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a plurality of wirings and a driving circuit located on the display area side. The plurality of wirings are all electrically connected to the driving circuit and are located on either of the opposite sides of the driving circuit along a first direction. The first direction is the direction in which the display area points to the driving circuit. The plurality of wirings include at least a plurality of clock signal lines and a plurality of power signal lines. The interval along the first direction between at least one of the power signal lines and the display area is smaller than the interval along the first direction between at least one of the clock signal lines and the display area.

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This disclosure claims the priority of a Chinese patent application with the application number 202210609832.8 and the title "Display Substrate and Display Device", which was filed with the Chinese Patent Office on May 31, 2022, and all the contents of the said application are incorporated herein by reference.

[0002] This application relates to the technical field of displays, and particularly to display substrates and display devices.

Background Art

[0003] With the development of science and technology, the functions of liquid crystal displays (LCDs) are increasing day by day, and the requirements for LCDs are also getting higher. In particular, the requirements for high - value - added display products integrating multiple functions are even more stringent. For example, high - refresh - rate is required for display products.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of this application provide a display substrate and a display device.

Means for Solving the Problems

[0005] Embodiments of this application adopt the following technical solutions.

[0006] In one aspect, it includes a display area and a peripheral area surrounding the display area, the peripheral area includes a plurality of wirings and a driving circuit located on the display - area side, the plurality of wirings are all electrically connected to the driving circuit and are located on either side of the driving circuit facing each other along a first direction, and the first direction is the direction in which the display area points to the driving circuit. the plurality of wirings at least include a plurality of clock signal lines and a plurality of power signal lines. Provided is a display substrate in which the distance along the first direction between at least one of the power signal lines and the display area is smaller than the distance along the first direction between at least one of the clock signal lines and the display area.

[0007] Optionally, the driving circuit is located between the display area and the plurality of wirings, and all of the power signal lines are all located between all of the clock signal lines and the driving circuit.

[0008] Optionally, the driving circuit includes a plurality of cascaded shift registers, at least one of the wirings includes a plurality of first segments and a second segment, the number of the plurality of first segments is the same as the number of the plurality of shift registers, and adjacent first segments are electrically connected via the second segment.

[0009] Optionally, the width of the second segment along the first direction is smaller than the width of the first segment along the first direction.

[0010] Optionally, the first segment includes a first sub-segment and a second sub-segment that are connected in parallel and arranged side by side, and both the first sub-segment and the second sub-segment include a two-layer structure.

[0011] Optionally, both the first sub-segment and the second sub-segment include a first conductive part and a second conductive part that are stacked in order, the first conductive part and the second conductive part are connected via a via, or the first conductive part and the second conductive part are directly in contact and connected.

[0012] Optionally, both the first sub-segment and the second sub-segment further include an insulating portion provided between the first conductive portion and the second conductive portion. The insulating portion has vias, and the first conductive portion is electrically connected to the second conductive portion through the vias of the insulating portion.

[0013] Optionally, the second segment includes a single-layer structure and is provided in the same layer as the second conductive portion.

[0014] Optionally, all of the clock signal lines and a part of the power signal lines all include a two-layer structure.

[0015] Optionally, the display substrate further includes a base, and both the display area and the peripheral area are located on the base. The driving circuit includes a shift register, and the shift register includes a first transistor group and a second transistor group. The first transistor group is located between the second transistor group and the plurality of wirings. The first transistor group includes a plurality of first transistors, and the second transistor group includes a plurality of second transistors. The area of the orthographic projection of each first transistor on the base is smaller than the area of the orthographic projection of each second transistor on the base.

[0016] Optionally, along the first direction, the first transistor group has a spacing of 50 μm or more from the wiring with the shortest distance among all the wirings.

[0017] Optionally, the active layer of any transistor in the first transistor group and the second transistor group includes a plurality of independent active portions.

[0018] Optionally, the drive circuit includes a shift register, the shift register includes a reset unit, the reset unit electrically connects a first reset signal line, a second reset signal line, a power supply signal line, and a first node, and in a reset stage, under time-division alternating control by the reset signals of the first reset signal line and the second reset signal line, the power supply signal of the power supply signal line is configured to be alternately written into the first node in a time-division manner.

[0019] Optionally, the display substrate further includes an organic layer located on a side of the second conductive portion away from the first conductive portion, the organic layer has a groove penetrating therethrough, and the groove is located on a side of all the clock signal lines away from the drive circuit. Alternatively, the groove is located between the plurality of wirings and the drive circuit.

[0020] Optionally, the plurality of wirings further includes at least an input signal line and a reset signal line, the input signal line is located on a side of all the clock signal lines away from the drive circuit. Both the input signal line and the reset signal line are located between all the clock signal lines and the drive circuit.

[0021] In another aspect, a display device including the above display substrate is provided.

Advantages of the Invention

[0022] Embodiments of the present application provide a display substrate, which includes a display area and a peripheral area surrounding the display area. The peripheral area includes a driving circuit located on the display area side. The peripheral area further includes a plurality of wirings, and all the plurality of wirings are electrically connected to the driving circuit and are located on either side of the driving circuit facing each other along a first direction. The first direction is the direction in which the display area points to the driving circuit. The plurality of wirings include at least a plurality of clock signal lines and a plurality of power signal lines. The interval along the first direction between at least one power signal line and the display area is smaller than the interval along the first direction between at least one clock signal line and the display area.

[0023] The above description is only an overview of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, it can be implemented according to the content of the specification, and in order to more clearly and easily understand the above and other objects, features, and advantages of the present application, specific embodiments of the present application are listed below.

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for the description of the embodiments or the prior art will be briefly introduced below. However, the drawings in the following description are only some embodiments of the present application, and it is obvious that those skilled in the art can obtain other drawings based on these drawings without creative efforts.

Brief Description of the Drawings

[0025]

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Embodiments for Carrying Out the Invention

[0026] Hereinafter, with reference to the drawings in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. However, it is obvious that the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative labor belong to the protection scope of the present application.

[0027] In the embodiments of the present application, the use of characters such as "first" and "second" to distinguish the same items or similar items with basically the same functions and actions is only for clearly explaining the technical solution means of the embodiments of the present application, and it cannot be understood that it indicates or implies relative importance or implies the number of technical features shown.

[0028] In the embodiments of the present application, unless specifically specified otherwise, "a plurality" means two or more, and "at least one" means one or more.

[0029] In the embodiments of the present application, the orientation or positional relationship indicated by terms such as "upper" is based on the orientation or positional relationship shown in the drawings, and is only for facilitating the description of the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a specific orientation or be configured and operate in a specific orientation, and it cannot be understood that it limits the present application.

[0030] Currently, the market competition of electronic products such as notebook computers (NB: Notebook) is intensifying. In order to gain an advantage in the market, it is urgent to develop high-value-added display products that integrate multiple functions. The gate on array (GOA) technology has advantages such as significantly reducing the usage amount of integrated circuits (IC: integrated circuit) in display products, reducing the cost and power consumption of display products. As a result, the product has improved competitiveness and has become more and more popular. The GOA technology is to use a thin film transistor (TFT: Thin Film Transistor) array process to fabricate a gate scanning drive circuit on a display substrate to realize a progressive scanning drive method.

[0031] Currently, in some display products integrated with GOA, such as NB for e-sports, an ultra-high refresh rate is required to provide high-quality images for dynamic display. However, normal high-refresh rate products often have drawbacks such as high power consumption and low process stability. As a result, the user experience is significantly reduced, and further optimization design is urgently needed.

[0032] Based on the above description, an embodiment of the present application provides a display substrate. As shown in FIGS. 1 and 2, the display substrate includes a display area AA and a peripheral area BB surrounding the display area AA. The peripheral area BB includes a driving circuit 1 located on the side of the display area AA.

[0033] As shown in FIGS. 1 and 2, the peripheral area BB further includes a plurality of wirings. All the plurality of wirings are electrically connected to the driving circuit 1 and are located on either side of the driving circuit 1 facing each other along the first direction (the OA direction shown in the figure). The first direction is the direction in which the display area AA points to the driving circuit 1. The plurality of wirings at least include a plurality of clock signal lines CLK and a plurality of power signal lines.

[0034] As shown in FIGS. 1 and 2, the interval along the first direction between at least one power signal line and the display area AA is smaller than the interval along the first direction between at least one clock signal line CLK and the display area AA.

[0035] The display area (AA: Active Area) of the above display substrate refers to the area for display.

[0036] The above peripheral area refers to the area outside the display area and is also called the border area. It is generally used to arrange driving wirings, driving circuits (such as GOA driving circuits), or in-screen cameras, earphones, speakers, etc. The above peripheral area is provided in a circle surrounding the display area. FIG. 1 takes the case where the peripheral area BB is provided in a circle surrounding the display area AA as an example, and only the peripheral area BB located on the side of the display area AA is shown in FIG. 2.

[0037] The above-mentioned peripheral region includes a driving circuit located on the display region side. The peripheral region may include one driving circuit located on the display region side. For example, one driving circuit may be located on any one of the left side, right side, upper side, and lower side of the display region, or may include two driving circuits respectively located on the opposite sides of the display region. For example, the two driving circuits may be respectively located on the left side and the right side of the display region, or the two driving circuits may be respectively located on the upper side and the lower side of the display region.

[0038] Here, the type of the above-mentioned driving circuit is not particularly limited. Exemplarily, the above-mentioned driving circuit may include a GOA circuit, and specifically, the GOA circuit may include a gate GOA circuit.

[0039] The fact that the above-mentioned plurality of wirings are located on either side of the opposite sides of the driving circuit along the first direction means that the plurality of wirings are located on the side closer to the display region of the driving circuit along the first direction, or the plurality of wirings are located on the side away from the display region of the driving circuit along the first direction. In either of FIGS. 1 and 2, the plurality of wirings are located on the side away from the display region AA of the driving circuit 1 in the OA direction. Specifically, the driving circuit 1 is depicted by taking as an example the fact that it is located between the plurality of wirings and the display region AA in the OA direction.

[0040] Here, the material of the above-mentioned wiring is not particularly limited. Exemplarily, the material of the above-mentioned wiring may include metal and the like.

[0041] Here, the type of the above-mentioned power supply signal line is not particularly limited. Exemplarily, the above-mentioned power supply signal line may include a first power supply signal line VGL, a second power supply signal line LVGL, a third power supply signal line VDDO, a fourth power supply signal line VDDE, and the like.

[0042] That the interval along the first direction between the at least one power signal line and the display area is smaller than the interval along the first direction between the at least one clock signal line and the display area means that, along the first direction, the at least one power signal line is provided closer to the display area than the at least one clock signal line. Here, the at least one power signal line may be one power signal line, two power signal lines, three power signal lines, etc., or may be all power signal lines. Similarly, the at least one clock signal line may be one clock signal line, two clock signal lines, three clock signal lines, etc., or may be all clock signal lines. In this case, the positions of the at least one power signal, the at least one clock signal line, and the display area are not particularly limited. Exemplarily, along the first direction, the at least one power signal is located between the at least one clock signal line and the display area, or the at least one power signal is not located between the at least one clock signal line and the display area. In both FIG. 1 and FIG. 2, the case where, in the OA direction, at least one power signal is located between at least one clock signal line CLK and the display area AA is depicted as an example.

[0043] The above-mentioned first direction may be the OA direction shown in FIGS. 1 and 2, or may be the direction opposite to the OA direction. Specifically, it may also be determined according to the actual situation.

[0044] The above-mentioned display substrate may be a flexible display substrate or a rigid display substrate, and is not limited here. All examples according to the present application will be described by taking the case where the above-mentioned display substrate is a rigid display substrate as an example.

[0045] FIG. 4 and FIG. 5 are both schematic diagrams of wiring arrays in the related art, and both FIG. 4 and FIG. 5 show the case where the driving circuit 1 is located between a plurality of wirings and the display area AA. As shown in FIGS. 4 and 5, both the power signal line VGL / the power signal line LVGL are located on the side away from the driving circuit 1 of the clock signal lines CLK (in FIGS. 4 and 5, 10 clock signal lines CLK named clock signal lines CLK1 to CLK10 are included). Since all the clock signal lines CLK and the power signal line VGL / the power signal line LVGL are electrically connected to the driving circuit, the power signal line VGL / the power signal line LVGL needs to cross all the clock signal lines CLK, thereby forming a large overlap capacitance, and as a result, the power consumption of the driving circuit increases significantly.

[0046] Embodiments of the present application provide a display substrate, which includes a display area and a peripheral area surrounding the display area. The peripheral area includes a driving circuit located on the display area side. The peripheral area further includes a plurality of wirings. The plurality of wirings are all electrically connected to the driving circuit and are located on either of the opposite sides of the driving circuit along a first direction. The first direction is the direction in which the display area points to the driving circuit. The plurality of wirings include at least a plurality of clock signal lines and a plurality of power signal lines. The interval along the first direction between at least one power signal line and the display area is smaller than the interval along the first direction between at least one clock signal line and the display area. In this way, by configuring at least one power signal line to be closer to the display area than at least one clock signal line, the clock signal line inputs a signal to one row of the driving circuit one by one and row by row. Therefore, only one clock signal line crosses at least one power signal line, thereby greatly reducing the overlap capacitance between the signal lines, meeting the requirements of low power consumption, high image quality, and high refresh rate, and effectively ensuring the performance of the display substrate.

[0047] Optionally, as shown in FIGS. 1 and 2, the driving circuit 1 is located between the display area AA and a plurality of wirings, and all power signal lines are located between all clock signal lines CLK and the driving circuit 1. Thereby, all power signal lines are provided closer to the display area than all clock signal lines. In this way, only one clock signal line crosses all power signal lines, reducing the overlap capacitance between signal lines as much as possible and further effectively ensuring the performance of the display substrate.

[0048] Optionally, as shown in FIGS. 2 and 3, the driving circuit 1 includes a plurality of cascaded shift registers 11, and at least one wiring includes a plurality of first segments 21 and a second segment 22. The number of first segments 21 is the same as the number of shift registers 11, and adjacent first segments 21 are electrically connected via the second segment 22.

[0049] Since the above-mentioned plurality of shift registers are cascaded, the output signal of the upper shift register can function as the input signal of the lower shift register.

[0050] When the clock signal line CLK3 and the clock signal line CLK4 in the dashed circle shown in FIG. 2 are enlarged, a structural schematic diagram of the clock signal line CLK3 and the clock signal line CLK4 shown in FIG. 3 is obtained. FIG. 3 shows, by way of example, a case where one clock signal line CLK3 and one clock signal line CLK4 each include two first segments 21 and three second segments 22. Here, the driving circuit 1 includes two cascaded shift registers 11.

[0051] The structure of each of the above-mentioned first segments is not particularly limited. Exemplarily, each of the above-mentioned first segments may include a single-layer structure, or each of the above-mentioned first segments may include a multi-layer structure. FIGS. 2 and 3 are both drawn by way of example in the case where each of the above-mentioned first segments has a two-layer structure.

[0052] The structure of each of the above-mentioned second segments is not particularly limited. Exemplarily, each of the above-mentioned second segments may include a single-layer structure, or each of the above-mentioned second segments may include a multi-layer structure. FIGS. 2 and 3 are both drawn by taking the case where each of the above-mentioned second segments has a single-layer structure as an example.

[0053] First of all, the clock signal line CLK is electrically connected to the shift register by the connection segment. Specifically, the connection segment is directly connected to the second segment of the clock signal line CLK. When a plurality of wirings include a plurality of first segments and second segments, the second segment connected to one wiring and the connection segment of the shift register may overlap with the second segments of other wirings in the OA direction. FIG. 3 is drawn by taking the case where the clock signal line CLK3 is electrically connected to the shift register 11 by the connection segment 25 and the clock signal line CLK4 is electrically connected to the shift register 11 by the connection segment 26 as an example. As shown in FIG. 3, the connection segment 25 may overlap with the second segment 22 of the clock signal line CLK4 in the OA direction.

[0054] Second, the dashed lines in the figure do not indicate a specific structure and have no practical meaning. They are only schematic diagrams drawn to better explain the structure of the present application.

[0055] In the related art, as shown in FIGS. 4 and 5, a plurality of wirings are all of a single-layer structure. Since the NB products are getting larger, in the direction perpendicular to the first direction (OA direction), the plurality of wirings further extend. Therefore, the current single-layer metal wiring cannot meet the impedance requirements of high-refresh-rate products.

[0056] In the display substrate according to the embodiment of the present application, in the non-crossline region, by designing a two-layer metal wiring, for example, the resistance of the wiring in the clock signal line CLK region can be effectively reduced, and further the delay time of the output signal of the driving circuit can be shortened, and the power consumption of the driving circuit can be effectively reduced.

[0057] Optionally, as shown in FIG. 3, the width d1 of the second segment 22 along the first direction is smaller than the width d2 of the first segment 21 along the first direction. Thereby, while effectively reducing the overlap capacitance of the cross-line region, the impedance of the second segment can be reduced, the driving ability of the driving circuit can be enhanced, and the uniformity of the luminance of the display substrate can be improved.

[0058] Here, the width of the second segment along the first direction is not particularly limited. Exemplarily, the range of the width d1 of the second segment along the first direction may include 15 μm to 18 μm, for example, 15 μm, 16 μm, 17 μm, or 18 μm.

[0059] Optionally, as shown in FIG. 3, the first segment 21 includes a first sub-segment 211 and a second sub-segment 212 that are connected in parallel and arranged side by side, and both the first sub-segment 211 and the second sub-segment 212 include a two-layer structure. Thereby, the two-layer metal wiring in the non-cross-line region all includes four segments. For example, the resistance of the wiring in the clock signal line CLK region is further effectively reduced, the delay time of the output signal of the driving circuit is further shortened, and the power consumption of the driving circuit is further reduced.

[0060] Here, the parallel connection form of the first sub-segment and the second sub-segment is not particularly limited. Exemplarily, the first sub-segment and the second sub-segment may be connected in parallel via vias. FIG. 3 depicts an example in which both the first sub-segment 211 and the second sub-segment 212 may be connected in parallel via vias 23.

[0061] Here, there is no particular limitation on how the above two-layer structures are connected in parallel. Exemplarily, the above two-layer structures may be directly connected in parallel or may be connected in parallel via vias.

[0062] This application provides an example of a parallel connection form of a first sub-segment and a second sub-segment. Optionally, both the first sub-segment and the second sub-segment each include a first conductive part and a second conductive part that are stacked in sequence, and the first conductive part and the second conductive part are connected via vias. Thereby, the overlap capacitance and wiring resistance between wirings can be very effectively reduced, the power consumption of the drive circuit can be reduced, the delay time of the display substrate can be shortened, etc., and the image quality of high refresh rate products can be significantly improved.

[0063] Here, the materials of the above-mentioned first conductive part and second conductive part are not particularly limited. Exemplarily, the materials of the above-mentioned first conductive part and second conductive part may include a metal.

[0064] This application provides another parallel connection form of a first sub-segment and a second sub-segment. Optionally, both the first sub-segment and the second sub-segment each include a first conductive part and a second conductive part that are stacked in sequence, and the first conductive part and the second conductive part are connected by direct contact. Therefore, it is easy to fabricate and easy to implement.

[0065] Optionally, both the first sub-segment and the second sub-segment further include an insulating part provided between the first conductive part and the second conductive part. The insulating part has vias, and the first conductive part is electrically connected to the second conductive part through the vias of the insulating part.

[0066] Here, the material of the above-mentioned insulating part is not particularly limited. Exemplarily, the material of the above-mentioned insulating part may include silicon oxide or silicon nitride.

[0067] When the display substrate further includes a gate layer (Gate), an insulating layer, and a source / drain metal layer (SD layer) that are stacked in sequence, the first conductive part and the Gate layer are provided in the same layer, and the second conductive part and the SD layer are provided in the same layer.

[0068] The phrase "provided in the same layer as described above" means being fabricated by a single patterning process. A single patterning process refers to a process of forming a desired layer structure through one exposure. A single patterning process includes processes such as masking, exposure, development, etching, and stripping.

[0069] Optionally, as shown in FIG. 3, the second segment 22 includes a single-layer structure and is provided in the same layer as the second conductive part. By a simple fabrication process, adjacent first segments can be electrically connected, and the entire fabrication process can also be easily operated.

[0070] The above-mentioned second conductive part may be an SD layer, but specifically, it can be determined according to the actual situation.

[0071] Optionally, as shown in FIG. 2, all of the clock signal lines CLK and a part of the power signal lines all include a two-layer structure. Thereby, through the clock signal lines and the power signal lines, for example, the wiring resistance in the clock signal line CLK region can be more effectively reduced, the delay time of the output signal of the driving circuit can be further shortened, and the power consumption of the driving circuit can be further reduced.

[0072] FIG. 2 depicts an example where the clock signal lines CLK1-10, the power signal line VGL, and the power signal line LVGL all have a two-layer structure, and the power signal lines VDDE, VDDO, and the reset signal line TRST all have a single-layer structure. In this case, the wiring can be effectively designed, space can be saved, and a narrow border can be realized.

[0073] Optionally, the display substrate further includes a base, and both the display area and the peripheral area are located on the base.

[0074] As shown in FIGS. 1 and 2, the drive circuit includes a shift register, and the shift register includes a first transistor group Z1 and a second transistor group Z2. The first transistor group Z1 is located between the second transistor group Z2 and a plurality of wirings. The first transistor group Z1 includes a plurality of first transistors, and the second transistor group Z2 includes a plurality of second transistors. The area of the orthographic projection of the base of each first transistor is smaller than the area of the orthographic projection of the base of each second transistor.

[0075] The material of the base is not particularly limited and may include a rigid material such as glass, or may include a flexible material such as polyimide (PI).

[0076] Here, the size of the transistors in the first transistor group is not particularly limited. Exemplarily, the range of the size of the transistors is 1 μm to 50 μm, such as 1 μm, 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm.

[0077] Here, the type of the transistors in the first transistor group and the second transistor group is not particularly limited. Exemplarily, the transistors in the transistor group may include TFTs, and specifically, may include oxide TFTs, such as indium gallium zinc oxide (IGZO) type TFTs.

[0078] Here, the number of the first transistors included in the above-mentioned first transistor group is not particularly limited. Exemplarily, the number of the first transistors included in the above-mentioned first transistor group may be one or a plurality. FIG. 2 depicts, by way of example, a case where seven transistors, for example, transistors M15, M7B, M5B, M6B, M6A, M5A, and M7A shown in FIG. 2, are included in the first transistor group of one shift register. When a plurality of first transistors are included in the above-mentioned first transistor group, the size of any of the first transistors is not particularly limited. Exemplarily, the sizes of all the first transistors may be the same, different, or some of the sizes of the first transistors may be the same.

[0079] Here, the number of the second transistors included in the above-mentioned second transistor group is not particularly limited. Exemplarily, the number of the second transistors included in the above-mentioned second transistor group may be one or a plurality. FIG. 2 depicts, by way of example, a case where eight transistors, for example, transistors M1, M2, M8B, M12B, M13B, M8A, M12A, and M13A shown in FIG. 2, are included in the second transistor group of two shift registers. When a plurality of second transistors are included in the above-mentioned second transistor group, the size of any of the second transistors is not particularly limited. Exemplarily, the sizes of all the second transistors may be the same, different, or some of the sizes of the second transistors may be the same.

[0080] In the related art, as shown in FIG. 5, M8A is provided in a coating region corresponding to a sealing adhesive (Seal adhesive) of a display substrate, and M8B is a transistor with a large size, for example, a TFT. When the frame of the display substrate is narrow, since there is a large metal in the large-sized TFT, the light transmittance is affected. Since the Seal adhesive requires ultraviolet light (UV) to cure and seal, the large metal in such a large-sized TFT obstructs the curing of the Seal adhesive by the UV light. Also, a part of the large-sized TFT is for the noise reduction function of the shift register. When the size is large, the UV light irradiation time becomes long. When the UV light irradiation time becomes long, such a large-sized TFT is likely to be damaged, which leads to poor characteristics.

[0081] In the shift register according to an embodiment of the present application, the area of the orthographic projection of the base of each first transistor is smaller than the area of the orthographic projection of the base of each second transistor, and the first transistor is located between the second transistor and a plurality of wirings. That is, as shown in FIG. 2, transistors with a small size, such as M5B, are provided on the side closer to the wiring, and transistors with a large size, such as M8B, are provided on the side away from the wiring. Thereby, all of the transistors with a small size are close to the wiring such as the clock signal line CLK. Since the area of the metal in the transistor with a small size is small, the blocking of the sealing adhesive by the transistor can be reduced as much as possible, the transmittance of the UV light can be increased, and the performance of the display substrate can be ensured while optimizing the narrow frame of the display substrate.

[0082] Optionally, the first transistor group has an interval of 50 μm or more from the wiring with the shortest distance among all the wirings along the first direction. Thereby, it is possible to prevent the occurrence of electrostatic discharge (abbreviation: ESD) on the display substrate and the burning of the signal line.

[0083] Exemplarily, the above interval may be 50 μm, 60 μm, 70 μm, etc.

[0084] Optionally, as shown in FIG. 6, the active layer of any transistor in the first transistor group and the second transistor group includes a plurality of independent active portions 31.

[0085] Here, the range of the interval between the adjacent active portions is not particularly limited. Exemplarily, the range of the interval between the adjacent active portions includes 1 μm to 7 μm, such as 1 μm, 3 μm, 5 μm, or 7 μm. When the interval between the adjacent active portions is 5 μm, it is very advantageous for improving the stability of the threshold voltage (Vth) of the shift register.

[0086] Here, the shape of the active portion of any of the above transistors is not particularly limited. Exemplarily, the shape of the orthographic projection of the active portion on the base may be a rectangle or the like.

[0087] Here, the size of the active portion of any of the above transistors is not particularly limited. Exemplarily, when any of the above transistors is a TFT and the shape of the orthographic projection of the active portion of this TFT on the base is a rectangle, the range of the length of the active portion of any TFT includes 5 μm to 10 μm, such as 5 μm, 7 μm, 8 μm, or 10 μm, and the range of the width of the active portion of any TFT includes 5 μm to 7 μm, such as 5 μm, 6 μm, or 7 μm.

[0088] Here, the number and arrangement form of the above active portions are not particularly limited. Exemplarily, the above active portions may be arranged in a 5×5 array.

[0089] Note that FIGS. 6 and 7 also show the gate 32 and source / drain 33 of one TFT.

[0090] In the related art, as shown in FIG. 7, the active layer 30 of the TFT has an overall bulk design. In this case, in the oxide TFT, the mobility is high, the Vth characteristic drift is very likely to occur, and there are also problems such as heat generation. In the transistor according to the embodiment of the present application, one integral active layer 30 in FIG. 7 is divided into a plurality of independent active parts 31 in FIG. 6, that is, all the active parts 31 in FIG. 6 correspond to one active layer 30 in FIG. 7. The design of making the active layer into a plurality of sets in this way is advantageous for improving the Vth stability of the TFT.

[0091] Optionally, as shown in FIG. 13, the driving circuit includes a shift register, the shift register includes a reset unit 5, and the reset unit 5 electrically connects the first reset signal line Reset A, the second reset signal line Reset B, the power supply signal line, and the first node PU. In the reset stage, under the time-division alternating control by the reset signals of the first reset signal line Reset A and the second reset signal line Reset B, the power supply signal of the power supply signal line is configured to be written to the first node PU alternately in a time-division manner.

[0092] In the related art, the types of TFTs constituting the GOA circuit are various, and one of the types is the oxide TFT. In the conventional oxide TFT, if the normal 18T1C driving architecture shown in FIG. 8 is used, there is a problem that the reliability of one or more TFT transistors becomes unstable. As a result, when used for a long time, the TFT characteristics are impaired, and horizontal stripe defects occur in the display product. The circuit shown in FIG. 9 composed of some TFTs in FIG. 8, specifically, TFT1, TFT2, TFT3, and TFT4, and the timing shown in FIG. 10 will be specifically described about the cause of the horizontal stripe defects in the display product.

[0093] As shown in FIG. 9, transistor M1 electrically connects signal line Input and the first node PU, and is configured to write the Input signal on signal line Input to the first node PU and capacitor C under the control of the Input signal on signal line Input. Transistor M3 electrically connects clock signal line CLK, the first node PU, and capacitor C, and is configured to write the CLK signal on clock signal line CLK to output signal line Gout under the control of the Input signal on the first node PU. Transistor M2 electrically connects signal line RESET and power supply signal line LVGL, and is configured to write the LVGL signal on power supply signal line LVGL to the first node PU under the control of the RESET signal on signal line RESET. Transistor M4 electrically connects signal line RESET and power supply signal line VGL, and is configured to write the VGL signal on power supply signal line VGL to output signal line Gout under the control of the RESET signal on signal line RESET.

[0094] Hereinafter, taking the case where all of transistors M1 - M4 are N-type transistors as an example, the operating principle of the GOA circuit shown in FIG. 9 will be described in detail by combining the timing diagrams of the respective signal lines shown in FIG. 10.

[0095] As shown in FIG. 10, at stage t1, a high level is input to signal line Input. At this time, transistor M1 is turned on, the first node PU is pulled up to a high level, and capacitor C is charged. At stage t2, transistor M3 is turned on, a high level is input to clock signal line CLK. At this time, output signal line Gout outputs a high level, and due to the bootstrap action of capacitor C, the first node PU is pulled up again. At stage t3, a high level is input to signal line RESET. At this time, transistors M2 and M4 are turned on, and the low levels input by LVGL and VGL are respectively written to the first node PU, the first node PU is pulled down to a low level, and output signal line Gout outputs a low level.

[0096] In the above process, the signal line Input outputs a high level, the transistor M1 turns on, the first node PU becomes high level, and the transistor M3 turns on. Next, the clock signal line CLK inputs a high level, and the output signal line Gout outputs a high level. For example, the high level is 22V. Due to the bootstrap effect of the capacitor C, the first node PU is pulled up again, for example, pulled up to a higher voltage of 22V to 44V. In this way, when a low level is input to the signal line RESET and the transistor M2 and / or the transistor M4 turn on, for example, in the transistor M2, an LVGL low level of -11V is input. As a result, the voltage difference Vds between the source and drain of the transistor M2 may become 33V to 55V, that is, the voltage difference Vds between the source and drain of the transistor M2 increases. When the transistor M2 is strong against high voltage, the output signal line Gout normally outputs the signal shown in FIG. 11. However, when the transistor M2 is weak against high voltage, the characteristics of the transistor M2 are easily damaged. As a result, the transistor M2 cannot pull down the first node PU due to damaged characteristics, the transistor M3 remains on for a long time, the output of the output signal line Gout increases, and the horizontal stripe defect shown in FIG. 12 occurs.

[0097] As a result of studying the oxide transistors M2 of multiple mainstream products in the related art, when the active layer of the oxide transistor M2 is long, for example, as long as 35.8μm, the oxide transistor M2 generates heat severely. Based on this, when the overall width of the oxide transistor M2 is small, for example, as small as 366μm, and a large SD metal is connected, the heat dissipation ability of the oxide transistor M2 decreases. Therefore, it is necessary to optimize the design of transistors such as the oxide transistor M2.

[0098] To solve the above problems, an embodiment of the present application provides a gate drive circuit. In the reset stage, under the time-division alternating control of the reset signals of the first reset signal line Reset A and the second reset signal line Reset B, the power supply signal of the power supply signal line is alternately written into the first node in a time-division manner. Specifically, as shown in FIG. 13, the transistor M1 is electrically connected to the signal line Input and the first node PU, and is configured to write the Input signal of the signal line Input into the first node PU and the capacitor C under the control of the Input signal of the signal line Input. The transistor M3 is electrically connected to the clock signal line CLK, the first node PU, and the capacitor C, and is configured to write the CLK signal of the clock signal line CLK into the output signal line Gout under the control of the Input signal of the first node PU. The transistor M2A is electrically connected to the signal line RESET A and the power supply signal line LVGL, and is configured to write the LVGL signal of the power supply signal line LVGL into the first node PU under the control of the RESET signal of the signal line RESET A. Also, the transistor M2B is electrically connected to the signal line RESET B and the power supply signal line LVGL, and is configured to write the LVGL signal of the power supply signal line LVGL into the first node PU under the control of the RESET signal of the signal line RESET B. The transistor M4A is electrically connected to the signal line RESET B and the power supply signal line VGL, and is configured to write the VGL signal of the power supply signal line VGL into the first node PU under the control of the RESET signal of the signal line RESET B. Also, the transistor M4B is electrically connected to the signal line RESET A and the power supply signal line VGL, and writes the VGL signal of the power supply signal line VGL into the first node PU under the control of the RESET signal of the signal line RESET A.

[0099] As shown in FIG. 14, at the t1 stage, a high level is input to the signal line Input. At this time, the transistor M1 is turned on, and the first node PU is pulled up to the high level, and the capacitor C is charged. At the t2 stage, the transistor M3 is turned on, and a high level is input to the clock signal line CLK. At this time, the output signal line Gout outputs a high level, and due to the bootstrap action of the capacitor C, the first node PU is pulled up again. At the t3 stage, a high level is input to the signal line RESET A. At this time, the transistors M2A and M4B are turned on, and the low levels input by LVGL and VGL are respectively written to the first node PU, and the first node PU is pulled down to the low level, and the output signal line Gout outputs a low level. At the t4 stage, a high level is input to the signal line Input. At this time, the transistor M1 is turned on, and the first node PU is pulled up to the high level, and the capacitor C is charged. At the t5 stage, the transistor M3 is turned on, and a high level is input to the clock signal line CLK. At this time, the output signal line Gout outputs a high level, and due to the bootstrap action of the capacitor C, the first node PU is pulled up again. At the t6 stage, a high level is input to the signal line RESET B. At this time, the transistors M2B and M4A are turned on, and the low levels input by LVGL and VGL are respectively written to the first node PU, and the first node PU is pulled down to the low level, and the output signal line Gout outputs a low level.

[0100] In the gate driving circuit according to the embodiment of the present application, in adjacent timing cycles, one transistor of the reset unit is alternately turned on. Specifically, in the reset stage of the first cycle, the transistors M2A and M4B shown in FIG. 13 are turned on, and in the reset stage of the second cycle, the transistors M2B and M4A shown in FIG. 13 are turned on, and this is repeated. Compared with the related art in which only one transistor M2 and transistor M4 are provided, the gate driving circuit according to the embodiment of the present application greatly reduces the number of times the transistors of the reset unit are used, improves the characteristics of the transistors, has a large Vds voltage difference, and avoids the deterioration of the transistor characteristics due to the repeated use of the transistors, ensures the stability of the transistors, avoids the output failure of Gout, and can effectively improve the image quality.

[0101] Furthermore, when the space of the display substrate design permits, the size range of the transistors M2 and M4 is designed to include 60 μm to 90 μm, for example, 60 μm, 70 μm, 80 μm, or 90 μm, thereby improving the resistance of the transistors M2 and M4 to damage.

[0102] Furthermore, as shown in FIG. 13, by providing a capacitor C between the first node PU and the transistor M3, the probability of heat generation failure of the transistor M3 is effectively reduced.

[0103] First of all, the above reliability test is a reliability test for display products, and the test items generally include high-temperature and high-humidity environment tests, high-temperature operation tests, low-temperature operation tests, and the like.

[0104] Secondly, the above first node is only defined to facilitate the description of the circuit structure and is not an actual circuit unit.

[0105] Thirdly, in order to unify the manufacturing process and simplify the subsequent circuit driving method, all of the above transistors M1-M4 are N-type transistors. Of course, all of the above transistors may also be P-type transistors. When the above transistors are P-type transistors, their design principles are similar to those of this application and belong to the protection scope of this application.

[0106] The embodiment of this application provides a groove structure. Optionally, as shown in FIG. 16, the display substrate further includes an organic layer located on the side away from the first conductive portion of the second conductive portion. The organic layer has a groove 41 penetrating therethrough, and the groove 41 is located on the side away from the driving circuits of all the clock signal lines CLK.

[0107] The material of the above organic layer is an organic material. Here, the type of the above organic material is not particularly limited and can be specifically determined according to the needs of the product.

[0108] Here, the number of the above grooves is not limited. Exemplarily, the number of the above grooves may all be one or more than one. When there are a plurality of these grooves, the plurality of grooves may be provided at intervals or may be provided in communication.

[0109] The position of the above groove is not limited. Exemplarily, the above groove may be provided only on the side of the display area having the driving circuit, or may be provided around the display area for one circumference.

[0110] It should be noted that the extending directions of the above grooves are all perpendicular to the first direction (OA direction) and parallel to the plane where the base exists.

[0111] In the related art, as shown in FIG. 15, a groove (ORG trench) on the organic layer is usually designed on the STV wiring. When the wiring of the present application has a two-layer structure and the two-layer structure is connected in parallel via vias, if an ORG trench is provided on the wiring of the two-layer structure, water vapor, oxygen gas, etc. will enter the position of the via through the ORG trench, corroding the via portion, causing defects, and further causing defects in the display horizontal bars.

[0112] In the display substrate according to the embodiment of the present application, by providing the ORG trench between the input signal line STV and the clock signal line CLK wiring, it is possible to avoid water vapor, oxygen gas, etc. from entering the position of the via of the two-layer wiring through the ORG trench, and prevent a decrease in reliability.

[0113] The embodiment of the present application provides another groove structure. As shown in FIG. 17, the display substrate further includes an organic layer located on the side of the second conductive portion away from the first conductive portion. The organic layer has a groove 41 penetrating therethrough, and the groove 41 is located between a plurality of wirings and the driving circuit. By setting the position of the ORG trench between the driving circuit and the clock signal line CLK, it is possible to avoid water vapor, oxygen gas, etc. from entering the position of the via of the two-layer wiring through the ORG trench, and also avoid water vapor, oxygen gas, etc. from entering the transistors of the shift register and causing corrosion, further preventing a decrease in reliability.

[0114] In addition, in order to better maintain the performance of the transistors, it is necessary to provide an organic layer for the transistors of the shift register, and it is not possible to fabricate an ORG trench on the transistors.

[0115] Optionally, as shown in FIGS. 1 and 2, the plurality of wirings further include at least an input signal line STV and a reset signal line TRST. The input signal line STV is located on the side away from the driving circuit 1 of all the clock signal lines CLK, and both the input signal line STV and the reset signal line TRST are located between all the clock signal lines CLK and the driving circuit 1. Thereby, a signal can be input to the driving circuit via the input signal line STV, and only one clock signal line straddles at least one power supply signal line closer to the display area provided on the clock signal line, thereby greatly reducing the overlap capacitance and effectively ensuring the performance of the display substrate.

[0116] Embodiments of the present application also provide a display device including the above display substrate.

[0117] The above display device may be a flexible display device (also called a flexible screen), or a rigid display device (i.e., a non-foldable screen), and is not limited herein. The above display device may be a liquid crystal display (LCD) display device or an organic light-emitting diode (OLED) display device. The above display device may be any product or component having a display function such as a television, a digital camera, a mobile phone, a tablet terminal, etc. The above display device can also be applied to fields such as identity identification and medical devices. Products that are already popular or whose future popularity is expected include security identity authentication, smart door locks, medical image collection, etc. This display device has advantages such as a high refresh rate, low power consumption, good stability, good display effect, long life, high stability, high contrast ratio, good imaging quality, and high product quality.

[0118] It should be noted that the embodiments of the present application will be described by taking the above display device as an LCD display device as an example.

[0119] In the display device according to the embodiment of the present application, at least one power signal line is configured to be provided closer to the display area than at least one clock signal line. As a result, since the clock signal line inputs a signal to one row of the driving circuit for each row, only one clock signal line is provided on the clock signal line and straddles at least one power signal line closer to the display area, thereby significantly reducing the overlap capacitance and effectively ensuring the performance of the display substrate.

[0120] In this specification, "embodiment" means that a specific feature, structure, or characteristic described with reference to the embodiment is included in at least one embodiment of the present application.

[0121] Many specific details are described in the description provided herein. However, it is understood that the embodiments of the present application can be implemented without these details. In some examples, well-known methods, structures, and technologies are not shown in detail so as not to obscure the understanding of this specification.

[0122] It should be noted that the above embodiments are only used to explain the technical solutions of the present application and do not limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they may modify the technical solutions described in each of the foregoing embodiments or equivalently replace some of their technical features. However, these modifications or replacements do not deviate from the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of each embodiment of the present application.

Explanation of Reference Numerals

[0123] AA Display area BB Peripheral area 1 Driving circuit CLK Clock signal line 11 Shift register 21 First segment 22 Second segment

Claims

1. It includes a display area and a peripheral area surrounding the display area, the peripheral area includes a plurality of wirings and a driving circuit located on the display area side, and all of the plurality of wirings are electrically connected to the driving circuit and are located on either one of the opposite sides of the driving circuit along a first direction, and the first direction is the direction in which the display area points to the driving circuit, the plurality of wirings at least include a plurality of clock signal lines and a plurality of power signal lines, A display substrate in which the interval along the first direction between at least one of the power signal lines and the display area is smaller than the interval along the first direction between at least one of the clock signal lines and the display area.

2. The driving circuit is located between the display area and the plurality of wirings, and all of the power signal lines are all located between all of the clock signal lines and the driving circuit. The display substrate according to Claim 1.

3. The driving circuit includes a plurality of cascaded shift registers, at least one of the wirings includes a plurality of first segments and a second segment, the number of the plurality of first segments is the same as the number of the plurality of shift registers, and adjacent first segments are electrically connected via the second segment. The display substrate according to Claim 1.

4. The display substrate according to Claim 3, wherein the width of the second segment along the first direction is smaller than the width of the first segment along the first direction.

5. The first segment includes a first sub-segment and a second sub-segment that are connected in parallel and arranged side by side, and both the first sub-segment and the second sub-segment include a two-layer structure. The display substrate according to Claim 3.

6. Both the first sub-segment and the second sub-segment include a first conductive part and a second conductive part that are stacked in sequence, the first conductive part and the second conductive part are connected via a via, or the first conductive part and the second conductive part are directly in contact and connected. The display substrate according to Claim 5.

7. Both the first sub-segment and the second sub-segment further include an insulating portion provided between the first conductive portion and the second conductive portion. The insulating portion has vias, and the first conductive portion is electrically connected to the second conductive portion through the vias of the insulating portion. The display substrate according to claim 6.

8. The second segment includes a single-layer structure and is provided in the same layer as the second conductive portion. The display substrate according to claim 6.

9. All of the clock signal lines and a part of the power signal lines include a two-layer structure. The display substrate according to claim 8.

10. The display substrate further includes a base, and both the display area and the peripheral area are located on the base. The driving circuit includes a shift register, and the shift register includes a first transistor group and a second transistor group. The first transistor group is located between the second transistor group and the plurality of wirings. The first transistor group includes a plurality of first transistors, and the second transistor group includes a plurality of second transistors. The area of the orthographic projection of each first transistor on the base is smaller than the area of the orthographic projection of each second transistor on the base. The display substrate according to claim 1.

11. The first transistor group has an interval of 50 μm or more from the wiring with the shortest distance among all the wirings along the first direction. The display substrate according to claim 10.

12. The active layer of any transistor in the first transistor group and the second transistor group includes a plurality of independent active portions. The display substrate according to claim 10.

13. The driving circuit includes a shift register, and the shift register includes a reset unit. The reset unit electrically connects a first reset signal line, a second reset signal line, a power signal line, and a first node. In the reset stage, under the time-division alternating control by the reset signals of the first reset signal line and the second reset signal line, the power signal of the power signal line is configured to be written into the first node alternately in time division. The display substrate according to claim 1.

14. The display substrate further includes an organic layer located on a side of the second conductive portion away from the first conductive portion, the organic layer has a groove penetrating therethrough, and the groove is located on a side of all the clock signal lines away from the driving circuit. Or, the groove is located between the plurality of wirings and the driving circuit. The display substrate according to claim 8.

15. The plurality of wirings further includes at least an input signal line and a reset signal line, the input signal line is located on a side of all the clock signal lines away from the driving circuit. The input signal line and the reset signal line are both located between all the clock signal lines and the driving circuit. The display substrate according to claim 2.

16. A display device including the display substrate according to any one of claims 1 to 15.

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