A test apparatus, method, and computer program for testing a device under test that separates errors in a received pattern associated with different functional blocks of the device under test or different blocks of one or more bits

Abstract

A test apparatus (100; 200; 300; 500) for testing a device under test is configured to receive from the device under test (102; 202; 302) a pattern including information from a plurality of functional blocks of the device under test. The test apparatus is configured to isolate errors in the received pattern associated with different functional blocks of the device under test during execution of a test program, or the test apparatus is configured to isolate errors in the received pattern associated with different blocks of one or more bits during execution of a test program. A method and a computer program are also described.

Description

Technical Field

[0001] Embodiments according to the present invention relate to a test apparatus for testing a device under test.

[0002] Further embodiments according to the present invention relate to a method for testing a device under test.

[0003] Further embodiments relate to results for each core processor.

Background Art

[0004] Background of the Invention Testing is an important step in the manufacture of electronic circuits, such as integrated circuits. However, the complexity of electronic circuits, such as integrated circuits, poses a significant problem.

[0005] Therefore, in order to increase the optimal utilization of the bandwidth available for SCAN and functional testing, those involved in EDA software and test design have resorted to interleaving the test patterns of different cores when transmitting them to a device under test (DUT) via a test interface, instead of sending pure (e.g., single core) patterns (individual cores) one by one to the target IP cores.

[0006] Here, a "core" represents the basic unit of logical design (in the context of this application) and is to be analyzed individually in testing (e.g., test unit, granularity of test results). For example, a core can be regarded as a functional block of a device under test.

[0007] Considering such a situation, in a situation where the test patterns of different cores are interleaved, a concept is needed that allows a good compromise among complexity, test scope, and test time.

Summary of the Invention

[0008] One embodiment according to the present invention creates a test device (e.g., a test processor, or a channel module of an automatic test device, or an automatic test device) for testing a device under test. The test device is configured to receive a pattern (e.g., a result pattern; e.g., a response pattern) from the device under test. This pattern includes information (e.g., test results; e.g., test response information; e.g., a sequence of bits) from a plurality of functional blocks of the device under test (e.g., a "core"; e.g., a result block; e.g., a functional block that provides substantially independent test results or test responses) (e.g., in an associated manner) (e.g., in a combined form; e.g., in an interleaved form). The test device is configured to separate errors in the received pattern associated with different functional blocks of the device under test (e.g., separate and handle errors of different cores, or record them separately) (e.g., for separating errors of different cores) during the execution of a test program (e.g., to obtain test results for each functional block of the device under test, e.g., for each core of the device under test) during the execution of the test program.

[0009] It is recognized that when the test results of a plurality of functional blocks of a device under test are combined into a common result pattern, for example, in a scenario where they are output in a time-division multiplexing manner via a single pin of the device under test, by separating errors in the received pattern associated with different functional blocks of the device under test during the execution of a test program, it is possible to test the device under test in an efficient manner while avoiding saving a complete received pattern that is usually provided at a very high data rate.

[0010] For example, by separating errors in the received pattern associated with different functional blocks of the device under test, it is possible to quickly overview which functional blocks of the device under test have errors without saving or buffering the received test pattern. In some cases, this concept allows one to grasp which functional blocks of the device under test are "significantly" malfunctioning (a large number of errors associated with functional blocks with large failures in the received pattern) during or immediately after the execution of the test program. For example, based on prior knowledge about the positions (e.g., bit positions) in the received pattern associated with different functional blocks (or assigned to the test result bits of different functional blocks), errors associated with different functional blocks (in the received pattern) can be separated very quickly even during the execution of the test program.

[0011] Therefore, it is possible to obtain separate information regarding the malfunctions of different functional blocks of the device under test during or immediately after the completion of the test program. As a result, based on the information regarding the malfunctions of different functional blocks (indicated by the errors in the received pattern at the bit positions associated with the malfunctioning functional blocks), decisions regarding (further) test flows can be made.

[0012] In conclusion, separating errors in the received pattern associated with different functional blocks of the device under test during the execution of the test program (as a result, information indicating the malfunctions of different functional blocks is obtained separately for individual functional blocks, for example) has been found to reduce the complexity of the test because it may not be necessary to save the complete received pattern for subsequent analysis when separating the errors (in the received pattern) associated with different functional blocks of the device under test "during execution" (during the execution of the test program).

[0013] Thus, aggregated information indicating whether the functional blocks of the device under test cause an error in the received pattern can be obtained separately for different functional blocks of the device under test, or even further separately for each functional block of the device under test. Thus, the test apparatus described above enables efficient identification of one or more faulty functional blocks of the device under test during the execution of the test program, even when the test results of multiple functional blocks are combined in the received pattern (e.g., in a combined bitstream), for example, different positions within the received pattern may be associated with test results from different functional blocks of the device under test, and also, for example, the test apparatus may separate test results (results of comparison with expected bit values) originating from (or caused by) different functional blocks of the device under test based on knowledge of the association of the functional blocks of the device under test with bit positions within the received pattern.

[0014] By separating errors within the received pattern associated with different functional blocks during the execution of the test program, it is not necessary to upload the received pattern to another processing unit for post-processing. Therefore, the (separated) detection of faults in different functional blocks of the device under test can be achieved in a very efficient way. In particular, by separating errors within the received pattern during the execution of the test program (rather than as a post-processing step), it may not be necessary to save the received pattern for later detection of errors within the received pattern. Thus, very excellent functionality can be achieved with low complexity, which helps to improve test efficiency and test speed.

[0015] In this way, this test apparatus provides a very good trade-off between complexity, the functionality provided, and test speed.

[0016] In one embodiment, the test apparatus is configured to separate on-the-fly errors in received patterns associated with different functional blocks of the device under test (e.g., without buffering or logging the complete received pattern, such as before starting to separate errors associated with different functional blocks of the device under test, such as before a continuous stream of test patterns is fully received by the test apparatus, such as without recording the received stream).

[0017] By separating on-the-fly errors in received patterns associated with different functional blocks of the device under test, it is possible to avoid buffering or logging the complete received pattern, which consumes a great deal of resources. Thus, by associating on-the-fly the bit positions in the received pattern with different functional blocks of the device under test, error information associated with different functional blocks of the device under test (e.g., indicating errors in the received pattern) can be distinguished and / or separated. For example, error information associated with different functional blocks of the device under test can be distributed to different error registers or error counters (associated with different functional blocks of the device under test). In this way, using on-the-fly separation of errors in the received pattern (or equivalently, on-the-fly routing of error information indicating errors in the received pattern) helps to reduce or minimize the buffering effort for buffering the received pattern, and further avoid the delay caused by post-processing after the execution of the test program.

[0018] In a preferred embodiment, the test apparatus is configured to separate errors in received patterns associated with different functional blocks of the device under test in real time (e.g., at the same rate as the data rate at which the received pattern is received from the device under test) and / or in temporal synchronization with the data rate at which the received pattern is received from the device under test.

[0019] By separating in real time errors within received patterns associated with different functional blocks of a device under test, it is not necessary to buffer most of the received pattern or the entire received pattern. Rather, by separating the errors in real time (or equivalently, separating the error formation indicating the errors within the received pattern), it becomes possible for error information indicating the errors within the received pattern to already be available during the reception of the continuous pattern. In other words, the error information describing the errors occurring in the first part of the received pattern may be available before the subsequent part of the same continuous pattern is received by the test apparatus. Also, in some cases, it may be sufficient to buffer a very short portion of the received pattern necessary for actual error detection, but after the errors are separated (in real time), the received pattern can be discarded. In some implementations, buffering of the received pattern may even be completely avoided. Thus, it is recognized that separating the errors (more precisely, separating the error information describing the errors within the received pattern) helps to make error handling more efficient and enables the error information to be utilized very quickly.

[0020] However, in some embodiments, the tester hardware detects errors within the received pattern (''exactly'') in real time on the fly. This means that what is often referred to as an ''edge comparator'' analyzes the logic levels at programmed times and compares them to the expected states. The errors identified in this process are first combined, for example, within a so-called test processor period (for example, up to 8 comparators), and then, for example, within a so-called comparator word (for example, 4 as described above). Further processing in this sense (analysis of the faults related to the core to which it belongs) is no longer instantaneous, but is delayed by a short time, for example a few nanoseconds. However, in the overall picture of data processing (and also in the sense of this application), this processing is considered ''on the fly''. Also, this processing is approximately synchronized in time with the data rate at which the received pattern is received from the device under test and the data clock at which the received pattern is received from the device under test.

[0021] In a preferred embodiment, the test apparatus comprises dedicated hardware (e.g., a multiplexer) configured to isolate errors in received patterns associated with different functional blocks of the device under test.

[0022] By using dedicated hardware to isolate errors in the received pattern, particularly high-speed and efficient processing can be achieved. In particular, since the received pattern generally has a very high data rate, using dedicated hardware is particularly advantageous, and it should be noted that errors associated with different functional blocks of the device under test can be processed and isolated "on the fly" or "in real time".

[0023] In particular, by using dedicated hardware, there is no need to store the received pattern, and as a result, the resource requirements of this concept are significantly reduced. Furthermore, dedicated hardware is generally recognized to be much more energy-efficient compared to separating errors in the received pattern based on a microprocessor (e.g., by software control). Therefore, by using dedicated hardware, the separation of errors in the received pattern associated with different functional blocks of the device under test can be performed even before error bit logging occurs, and hardware-based error separation can also be used to control the error bit logging of the received pattern.

[0024] In conclusion, using dedicated hardware for separating errors in the received pattern associated with different functional blocks of the device under test is recognized to improve power efficiency and may result in a very fast provision of error information indicating (or describing) errors associated with different functional blocks of the device under test. Therefore, the error information obtained by separating errors associated with different functional blocks of the device under test can be used in further processing steps, such as error bit logging of the received pattern.

[0025] In a preferred embodiment, the test apparatus selectively transfers an error signal indicating a deviation of a bit value of a received pattern (e.g., at a bit position associated with a specific functional block of the device under test) from an expected bit value defined by an expected pattern to a result unit (e.g., an error flag register or an error counter) associated with a specific functional block of the device under test (or equivalently, associated with the bit position of the received pattern) (e.g., among a plurality of result units associated with different functional blocks of the device under test, or equivalently, a result unit associated with a different bit position of the received pattern), via dedicated hardware (e.g., a multiplexer; e.g., a core mapper) configured to do so. For example, the dedicated hardware can determine to which result unit to transfer the error signal using an assignment rule that defines the association between the bit position and the functional block of the device under test, or equivalently, defines the association of the bit position, based on the bit position currently under consideration.

[0026] By selectively transferring an error signal indicating a deviation of a bit value of a bit of a received pattern associated with a specific functional block of the device under test from an expected bit value defined by an expected pattern to a result unit associated with the specific functional block of the device under test, the separation of errors within the received pattern associated with different functional blocks of the device under test can be performed in a very fast and efficient manner. For example, the comparison between simply the expected bit defined by the expected pattern and the bit value of the bit of the received pattern can be performed in a particularly efficient manner in hardware, where it should be noted that the current test apparatus has a powerful and efficient mechanism for providing an electrical signal representing the expected pattern.

[0027] Thus, for example, the output signal of a very fast comparator that compares the electrical signal representation of a received pattern with the electrical signal representation of an expected pattern can provide a result signal (e.g., in the form of an electrical signal), and such a (comparison) result signal, which can also be considered an error signal, can be efficiently distributed, for example, using a multiplexer (thereby selectively transferring the error signal to respective result units).

[0028] Also, it is recognized that the selective transfer of an error signal to respective result units (where, for example, different result units may be associated with different functional blocks of the device under test) can be controlled by a hardware mechanism that tracks the association between the bits (or bit positions) of the received pattern and the different functional blocks of the device under test. Thus, the selective transfer of an error signal to different result units (e.g., by a multiplexer) can be controlled by a functional block (of the test apparatus) that tracks the association between the bit positions of the received pattern and the different functional blocks of the device under test.

[0029] As a result, the separation of errors associated with different functional blocks of the device under test can be achieved by dedicated hardware in a fast, reliable, and power - efficient circuit. Further, different result units that can be associated with different functional blocks of the device under test can separately record or count the errors associated with different functional blocks of the device under test, whereby information (e.g., separate information) regarding the occurrence of one or more errors in different functional blocks of the device under test becomes available in a resource unit. Thus, the information provided by the result units can be used for the evaluation of the device under test and / or for the control of the test flow and / or for other test purposes.

[0030] In a preferred embodiment, the test apparatus selectively disables the comparison (e.g., performed by a comparator) between one or more bits of a received pattern (e.g., at a bit position associated with a particular functional block of the device under test) and one or more corresponding bits of an expected pattern (e.g., based on an identified logical or functional block to which an error belongs), and / or selectively disables the transfer of the result of the comparison (e.g., performed by a comparator) between one or more bits of a received pattern (e.g., at a bit position associated with a particular functional block of the device under test) and one or more corresponding bits of an expected pattern (e.g., based on a specified logical or functional block to which an error belongs), and / or selectively disables the processing of the result of the comparison (e.g., performed by a comparator) between one or more bits of a received pattern (e.g., at a bit position associated with a particular functional block of the device under test) and one or more corresponding bits of an expected pattern, and is provided with dedicated hardware configured to do so.

[0031] By using such a concept, it is possible to selectively mask the processing of errors associated with one or more specific functional blocks of the device under test. This is particularly useful when it is recognized that a particular functional block of the device under test generates a large number of errors that interfere with further processing units. For example, the logging or more detailed analysis of such errors can be disabled using the mechanism described, which can help maintain (save) sufficient resources for the processing of errors caused by a functional block of the device under test that shows only a small number (and is sufficiently manageable) of errors. Thus, for example, if in a previous execution of a test program (or a part of the test program) it is found that a functional block of the device under test causes an excessive number of errors in the received pattern, the test apparatus can be freed from processing this large number of errors and concentrate on testing other functional blocks of the device under test. Thus, in some cases, the test efficiency can be significantly improved, and as a result, the test time can also be shortened.

[0032] In other words, it is possible to avoid wasting test resources on functional blocks of the device under test that generate an excessive number of errors in the received pattern.

[0033] In a preferred embodiment, the test apparatus comprises dedicated hardware configured to identify different blocks of one or more bits of the received patterns associated with different functional blocks of the device under test in order to separate the errors in the received patterns associated with the different functional blocks of the device under test.

[0034] By using dedicated hardware to identify different blocks of one or more bits of the received pattern associated with different functional blocks of the device under test, it may be easier to isolate errors in the received pattern associated with different functional blocks of the device under test. For example, by utilizing the periodicity of the association of different blocks of one or more bits of the received pattern with respect to the functional blocks of the device under test, different blocks of one or more bits of the received pattern associated with different functional blocks of the device under test can be efficiently identified. Further, the dedicated hardware can utilize the fact that there may be a clearly defined association rule between a block of one or more bits of the received pattern and the functional blocks of the device under test. For example, this association pool may be defined by a repeating sequence, and the length of the block of one or more bits associated with different functional blocks of the device under test may be known (e.g., may be predefined or defined in a lookup table, etc.). However, by using dedicated hardware to identify different blocks of one or more bits of the received pattern associated with different functional blocks of the device under test, a fast and power - efficient solution is provided that enables the separation of errors according to the identification of the blocks of one or more bits of the received pattern associated with different functional blocks of the device under test.

[0035] By using such a table, it has been found that it is possible to efficiently and favorably identify different blocks of one or more bits of received patterns associated with different functional blocks of a device under test. In particular, a table that defines the names of blocks of one or more bits of received patterns associated with different functional blocks of a device under test has been found to be an efficiently and favorably configurable description of typical repetitive occurrences of bits associated with different functional blocks of the device under test within the received pattern. Also, it has been recognized that such a table can be efficiently evaluated using dedicated hardware, and as a result, efficient implementation is possible.

[0036] In a preferred embodiment, the test apparatus includes a reference pattern generator configured to generate a time signal representing an expected pattern, and the test apparatus includes a comparator circuit configured to compare a time signal representing a received pattern with a time signal representing an expected pattern, and the comparator is configured to provide an error signal (e.g., by activating an error signal), where the test apparatus is configured to selectively activate and / or deactivate the comparison performed by the comparator, and / or the test apparatus is configured to selectively transfer this error signal to one of a plurality of result units based on the current bit position, thereby being configured to isolate errors within the received pattern associated with different functional blocks of the device under test.

[0037] It has been recognized that the present concept can be efficiently implemented by using a reference pattern generator and a comparator circuit, and the reference pattern generator can usually be reused for other functions of the test apparatus. Further, the comparator can also be used for testing a conventional device under test that does not multiplex the test results of a plurality of functional blocks into a single signal. Therefore, this implementation is particularly efficient and is recognized as being suitable for integration into a test apparatus.

[0038] In a preferred embodiment, the test apparatus is configured to individually track the test results (e.g., error flags, error counts) of different functional blocks of the device under test (where the test results may be based, for example, on errors in the received pattern).

[0039] Accordingly, the test apparatus can provide individual information indicating whether a functional block has generated an error and / or individual information indicating how many errors a functional block has generated. Thus, an overview of the error status (whether an error has occurred or how many errors have occurred) of different functional blocks is already available during the execution of the test program and can be used, for example, to make decisions about the test flow based thereon. Further, basic test results, such as whether a functional block of the device under test has generated an error, are available immediately after the completion of the test program without further post-processing, making the test very time-efficient.

[0040] In a preferred embodiment, the test apparatus is configured to individually track the test results (e.g., error flags, error counts) of different functional blocks of the device under test. The test results are derived based on a (common) received pattern for each test pattern (where the apparatus can, for example, read out one or more result units during the subsequent provision of test patterns to the device under test and / or the test apparatus can reset one or more result units during the subsequent provision of test patterns to the device under test) or for each test execution (where, for example, a test execution may include the provision of a plurality of test patterns (to the device under test)).

[0041] Therefore, an overview of the integrity of different functional blocks of the device under test can be efficiently obtained in test pattern units (if necessary). Alternatively, if sufficient, an overview of the integrity of different functional blocks can also be obtained in test execution units. In other words, a result unit that individually logs (or counts) the test results of different functional blocks of the device under test can be read out, for example, for each test pattern. This provides information to the test flow control or the user of the test device as to which test patterns caused one or more errors in different functional blocks of the device under test. As a result, the test flow control or the user of the test device is provided with very useful test results and can very quickly provide these meaningful test results by separating the errors associated with different functional blocks of the device under test during the execution of the test program.

[0042] A result unit that individually tracks the test results of different functional blocks may comprise, for example, a "hold" function (temporarily saving the test results) and / or a reset function (performing a reset at a time defined, for example, by the test program). Further, it should be noted that the test program can also control the reading of the result unit (individually tracking the test results of different functional blocks of the device under test) and / or the reset of the result unit.

[0043] In this way, meaningful information is provided with good efficiency and without (or with very little) latency.

[0044] In a preferred embodiment, the apparatus comprises a plurality of result units associated with different functional blocks of the device under test. The test apparatus is configured to selectively reset one or more of the result units (for example, during the provision of subsequent test patterns to the device under test), and / or the test apparatus is configured to selectively freeze one or more of the result units (for example, during the provision of subsequent test patterns to the device under test).

[0045] By having the possibility of selectively resetting one or more of the result units and / or the possibility of selectively freezing one or more of the result units, it is possible to determine for which time portions the results that describe the errors provided by different functional blocks of the device under test (e.g., for a test program or test flow control) must be determined. For example, by resetting the result unit, the result unit may be prepared for logging the results of the desired part of the test program. Also, by freezing the result unit, the result unit can be prevented from being affected by the errors occurring in a certain part of the test program. Furthermore, by resetting and / or freezing the result unit, for example under the control of a test program, reliable and meaningful results can be surely read out from the result unit.

[0046] In a preferred embodiment, the test apparatus is configured to compare a received pattern with an expected pattern. Further, the apparatus is configured to separately record comparison failures associated with different blocks of one or more bits of the received pattern and / or to separately record comparison failures associated with different functional blocks of the device under test (where different blocks of one or more bits of the received pattern may be associated with different functional blocks of the device under test).

[0047] By comparing the received pattern with the expected pattern and separately recording comparison failures associated with different blocks of one or more bits of the received pattern and / or by separately recording comparison failures associated with different functional blocks of the device under test, since different blocks of one or more bits of the received pattern are typically associated with these different functional blocks of the device under test, the test apparatus can efficiently determine (e.g., record) the errors occurring in different functional blocks of the device under test. Thus, meaningful test result information indicating the integrity of different functional blocks of the device under test can be provided.

[0048] In a preferred embodiment, the test apparatus is configured to separately record comparison failures associated with different functional blocks of the device under test using a mapping scheme that defines an association of bits of the received pattern to different result units (e.g., an error flag register or an error counter) that record comparison failures, and / or using a mapping scheme that defines an association of bits of the received pattern to different functional blocks of the device under test.

[0049] For example, the mapping scheme that defines the association of bits of the received pattern to different result units that record comparison failures may be equivalent to the mapping scheme that defines the association of bits of the received pattern to different functional blocks of the device under test. For example, the different result units may be associated with different functional blocks of the device under test.

[0050] Such a concept of utilizing a mapping scheme can provide test results that characterize the integrity of the device under test in a meaningful way, namely, separately for each functional block of the device under test. The mapping scheme can reflect including result bits associated with different functional blocks of the device under test in the pattern received by the test apparatus. Thus, the test results can be useful for the test flow control or the user of the automatic test apparatus to determine the device under test, and the separate recording of comparison failures may typically be performed during the execution of the test program, and the test results are typically provided with a very low latency. For example, the mapping scheme may be implemented in a form that can be evaluated "on the fly" or in real time.

[0051] In a preferred embodiment, the test apparatus comprises a plurality of individual result units configured to track (e.g., individually) test results (e.g., faults) associated with different functional blocks of the device under test (e.g., tracking individually the deviation between different bits of the received pattern and the corresponding bits of the expected pattern; e.g., tracking individually the deviation between bits (e.g., blocks of bits) of the received pattern associated with different functional blocks of the device under test and the corresponding bits of the expected pattern).

[0052] By using individual result units that separately track test results associated with different functional blocks of the device under test, the integrity of different functional blocks of the device under test can be individually determined. Thus, it is possible to distinguish functional blocks of the device under test that exhibit one or more errors from error - free functional blocks in a very fast and efficient manner. For example, when the individual result units are implemented using individual hardware (e.g., using an individual error register that is set by the first occurrence of an error in a received pattern associated with a given functional block of the device under test and reset, for example, by a dedicated reset signal, or using individual counters that each count errors in a received pattern associated with one or more functional blocks of the device under test), meaningful test results can be achieved in a fast and efficient manner without the need for post - processing of the received pattern using, for example, a microprocessor. Since the individual result units can be "triggered" in real - time or synchronized with the data clock of the received pattern (e.g., recording the presence of an error associated with a particular functional block of the device under test), it may not be necessary to buffer most of the received pattern. It has been found that individually - implemented result units in hardware are particularly suitable for such applications.

[0053] In a preferred embodiment, the test apparatus comprises a plurality of individual error - flag registers associated with different functional blocks of the device under test.

[0054] It has been found that individual error flag registers can be implemented with very little effort. For example, an individual error flag register can be a "sticky" register that is set upon the first occurrence of an error associated with each functional block of the device under test. Thus, for example, each error flag register is associated with one or more functional blocks of the device under test, and an error in a received pattern originating from one or more respective functional blocks of the device under test can result in the setting of the error flag register. Thus, the state of the error flag register can effectively indicate whether one or more functional blocks associated with each error flag register exhibit an error (such that one or more bits of the received pattern associated with this functional block deviate from the expected bit value). Thus, the error flag register provides very compact "go / no-go" or "pass / fail" information for different functional blocks of the device under test, and such "go / no-go" information can be very useful in making decisions regarding the classification and / or test flow of the device under test.

[0055] In a preferred embodiment, the test apparatus comprises a plurality of individual error flag registers configured to be set in response to comparison errors (e.g., mismatches) between bits of the received pattern and corresponding bits of the expected pattern occurring in different blocks of the received pattern (where, for example, different individual error flags are (individually) associated with comparison errors in different blocks of one or more bits of the received pattern, and, for example, different blocks of one or more bits of the received pattern are associated with different functional blocks of the device under test).

[0056] With such an arrangement, it has been found that, according to the separation of errors associated with different functional blocks of the device under test, it is possible to determine which of the individual error flag registers should be set, and meaningful test results can be obtained. For example, using the above-described multiplexer controlled according to a mapping rule or mapping scheme, in response to an error signal, it is possible to determine which individual error flag register among a plurality of error flag registers is set. For example, the error signal can be selectively transferred according to the distinction of different blocks of one or more bits in the received pattern. In conclusion, the individual error flag registers can constitute a very efficient approach for obtaining test result information.

[0057] In a preferred embodiment, the test apparatus comprises a plurality of individual error counters associated with different functional blocks of the device under test.

[0058] For example, the presence of individual error counters that can individually count errors in the received pattern associated with different functional blocks of the device under test is very useful for obtaining meaningful test information regarding different functional blocks. For example, the error counters can recognize how many errors different functional blocks have generated in the received pattern. Thus, it is possible to distinguish between functional blocks that do not generate errors, functional blocks that generate only a few errors, and functional blocks that generate a large number of errors. Therefore, by evaluating the count values of the individual error counters, different functional blocks of the device under test can be classified, and thus can be used to obtain an overall classification of the device under test and / or to control the test flow. Therefore, it is clear that the use of individual error counters is a very powerful tool for providing meaningful insights into the functionality of the device under test.

[0059] In a preferred embodiment, the test apparatus comprises a plurality of individual error counters configured to be incremented in response to a comparison error (e.g., a shift) between bits of the device under test. For example, different individual error counters are configured to be incremented in response to a comparison error (e.g., a shift) between bits of the received pattern and corresponding bits of the expected pattern that occurs in different blocks of one or more bits of the received pattern (where, for example, different individual error counters are (individually) associated with comparison errors in different blocks of one or more bits of the received pattern, for example, different individual error counters are configured to count errors in different blocks of one or more bits of the received pattern, and for example, different blocks of one or more bits of the received pattern are associated with different functional blocks of the device under test.).

[0060] It has been found that such individual error counters can efficiently and quickly obtain meaningful test information regarding different functional blocks of the device under test.

[0061] In a preferred embodiment, the test apparatus is configured to selectively set an error flag (e.g., a single error flag; e.g., a sticky error flag that remains valid until explicitly reset) among a plurality of individual error flags (e.g., a single error flag; e.g., a sticky error flag that remains valid until explicitly reset) based on an association rule (which defines, for example, an association between bits of the received pattern and functional blocks of the device under test and / or an association between bits of the received pattern and error flags (where an error signal indicating a comparison error may be routed to the set input of each error flag register, for example)) in response to detection of a shift between bits of the received pattern and bits of the expected pattern (e.g., a reference pattern). This association rule may be, for example, flexible and may be programmable in some form.

[0062] Using a concept where the association rules determine which of a plurality of individual error flags should be set in response to detecting a shift between the bits of the received pattern and the bits of the expected pattern constitutes an efficient mechanism for handling received patterns where different bits or groups of bits are associated with different functional blocks of the device under test. Thus, different individual error flags can indicate errors arising from different functional blocks of the device under test. However, by using, for example, programmable and flexible association rules, the test apparatus can be adapted to different devices under test, and the association between the bit positions in the received pattern and the functional blocks of the device under test can vary between different devices under test.

[0063] In a preferred embodiment, the test apparatus is configured to set an individual error flag associated with a given functional block of the device under test in response to detecting that the bits of the received pattern associated with a given functional block of the device under test deviate from the expected pattern, in order to individually record comparison failures associated with different functional blocks of the device under test.

[0064] Thus, by setting an individual error flag in response to detecting that the bits of the received pattern associated with a given functional block of the device under test have deviated from the expected pattern, meaningful test result information characterizing different functional blocks of the device under test can be obtained with little effort.

[0065] In a preferred embodiment, the test apparatus selectively increments an error counter (e.g., an individual error counter) (which can route, for example, an error signal indicating a comparison error to the increment input of the clock input of each error counter) among a plurality of individual error counters (associated with different functional blocks of the device under test) in response to detecting a shift between a bit of the received pattern and a bit of the expected pattern (reference pattern), and based on an association rule (which defines an association between a bit of the received pattern (e.g., a block of bits of the received pattern) and a functional block of the device under test, and / or an association between a bit of the received pattern and an error counter).

[0066] By using such a configuration, details regarding the integrity of different functional blocks of the device under test can be obtained with reasonable effort. For example, the association rule determines which error counter is incremented in response to detecting a shift between a bit of the received pattern and a bit of the expected pattern. For this purpose, the association rule may be based on prior knowledge of which bit positions within the received pattern are associated with which functional blocks of the device under test. As a result, very meaningful error information characterizing the device under test can be obtained in a very quick manner without requiring a large processing time.

[0067] In a preferred embodiment, the test apparatus is configured to increment an individual error counter associated with a given functional block of the device under test in response to detecting that a bit of the received pattern associated with the given functional block of the device under test deviates from the expected pattern, in order to individually count comparison failures associated with different functional blocks of the device under test.

[0068] Therefore, a highly reliable characteristic evaluation of different functional blocks of the device under test can be achieved, for example, using hardware with low complexity. For example, a microprocessor-based evaluation of the received pattern is not necessary to obtain meaningful error information regarding different functional blocks of the device under test.

[0069] In a preferred embodiment, the apparatus is configured to record individual failure information (which, for example, can be uploaded to a workstation for detailed analysis after the execution of the test) indicating the failure position of each of a plurality of comparison failures (such that the individual failure information describes the actual bit position of each comparison failure within the received pattern). Further, the apparatus is configured to obtain summary failure information (for example, a summary failure map; for example, information describing the state of a plurality of error flag registers; for example, information describing the state of a plurality of error counters) separately describing errors (such as comparison errors) associated with different functional blocks of the device under test in a summary form (for example, in the form of a single binary value for each functional block of the device under test indicating whether at least one bit of the received pattern associated with each functional block of the device under test deviates from the corresponding bit of the reference pattern, or in the form of a single counter value for each functional block indicating the number of bits that deviate from the corresponding bits of the reference pattern among the received patterns associated with each functional block of the device under test).

[0070] By determining both individual failure information that can accurately determine which bits within the received pattern are in error, and summary failure information that only indicates which of the different functional blocks of the device under test caused an error within the received pattern (optionally providing information on how many errors a functional block caused within the received pattern), it has been found that an efficient test of the device under test becomes possible. For example, typically, summary failure information that does not include accurate information regarding the position of error bits within the received pattern can quickly determine whether a functional block of the device under test is generating no errors, or whether a functional block of the device under test is generating one or more errors. Also, in some cases, such as when there is an error counter, summary failure information can distinguish between functional blocks that generate a very small number of errors within the received pattern and functional blocks that generate a large number of errors within the received pattern. Thus, summary failure information is very quickly available and is suitable for determining the test flow from the perspective of being quickly available. Furthermore, summary failure information contains the most relevant information, namely the question of which functional blocks of the device under test are causing errors within the received pattern, in a very compact form.

[0071] On the other hand, the recorded individual failure information enables more detailed analysis by the user of the test apparatus. The recorded individual failure information can usually indicate which bits within the received pattern have errors, and thus potentially identify the cause of the error in great detail (for example, down to a single gate level or a single transistor level). However, it should be noted that under certain resource constraints, the amount of individual failure information that can be recorded is generally limited. Therefore, there may be a situation where only errors caused by a single functional block of the device under test are described while errors caused by other functional blocks of the device under test can also be recognized by the summary failure information, given the limited amount of recorded individual failure information.

[0072] Furthermore, it should be noted that since individual failure information usually contains much more information, such as detailed error location information for example, summary failure information is usually available much faster than individual failure information and / or can draw some conclusions much faster.

[0073] In conclusion, it is recognized that it is valuable to determine both individual failure information and summary failure information. This is because summary failure information is particularly suitable for obtaining an overview of the integrity of the device under test and / or for classifying the device under test and / or for making decisions about the test flow, while individual failure information enables a more detailed failure analysis.

[0074] In a preferred embodiment, the apparatus is configured to record failure cycles (e.g., where the comparison between bits of a reference pattern and a received pattern indicates a deviation) in a temporally distinguishable (e.g., temporally documented, traceable) manner (e.g., with bit position information or timestamp information) (e.g., with a limited logging capacity), in addition to error flags per functional block and / or error counts per functional block.

[0075] In addition to the error flag for each functional block and / or the error count for each functional block, by recording the failed cycles in a time-discernible manner, the test apparatus makes available both compact summary information that can be well used for classifying the device under test and / or determining the test flow, and more detailed information suitable for a detailed analysis of the errors. By recording the failed cycles, for example, with a time stamp or a bit position value, information that is particularly useful when the number of errors is relatively small becomes available. This recording of the failed cycles in a time-discernible manner can be stored, for example, in the test apparatus and analyzed, for example, in a post-processing step after the execution of the test program. Alternatively or additionally, the recording of the failed cycles in a time-discernible manner can be uploaded from the test apparatus to a workstation, where it is further analyzed using software tools. The error flag for each functional block and / or the error count for each functional block can be evaluated, for example, during the execution of the test program and used directly, for example, for classifying the device under test or for controlling the execution of the test flow. For example, the error flag for each functional block and / or the error count for each functional block can be used to determine which test should be executed next in the test flow.

[0076] Thus, the concept of recording both detailed information and compact "summary" information regarding the failed cycles enables a quick, efficient, and thorough test and provides detailed insight into the integrity of the device under test.

[0077] In a preferred embodiment, the test apparatus is configured to continue updating the summary fault information (e.g., the error flag for each functional block and / or the error count for each functional block) even if the memory for recording individual failure information is depleted (e.g., by a large number of comparison failures).

[0078] Accordingly, the summary failure information provides highly reliable information regarding the functional states of different functional blocks of the device under test, even when there are many individual failure information that may be caused by, for example, malfunctioning functional blocks. Thus, with the summary failure information, it is possible to very quickly determine the classification and / or test flow of the device under test even in a situation where there are many bit errors in the received pattern. Therefore, for example, even if a single defective block of the device under test causes many errors in the received pattern and obstructs the recording of individual failure information, it is possible to recognize the non-defective functional blocks of the device under test. Thus, the test efficiency can be greatly improved.

[0079] In a preferred embodiment, the test apparatus is configured to selectively mask (e.g., omit) the recording of individual failure information (e.g., recording of an error map) for bits of a received pattern associated with one or more functional blocks of the device under test (e.g., for each functional block or at the granularity of a functional block unit). Alternatively or additionally, the test apparatus is configured to selectively enable (e.g., for each functional block or at the granularity of a functional block unit) the recording of individual failure information (e.g., recording of an error map) for bits of a received pattern associated with one or more functional blocks of the device under test.

[0080] By selectively masking or selectively enabling the recording of individual failure information for bits of a received pattern associated with one or more functional blocks of a device under test, resources available for recording individual failure information can be focused on failures of one or more functional blocks of particular interest. Alternatively, by selectively masking or selectively enabling the recording of individual failure information, recording of individual failure information for one or more malfunctioning functional blocks of the device under test can be avoided, and interference with resources for recording individual failure information can be avoided. Accordingly, it becomes possible to record individual failure information focused on failures caused by one or more selected functional blocks of the device under test. As a result, particularly meaningful individual failure information can be obtained in a resource-saving manner.

[0081] In a preferred embodiment, the test apparatus is configured to determine, using a table that defines the length of a block of one or more bits of a received pattern associated with different functional blocks of the device under test, which bits of the received pattern should have recording of individual failure information omitted (masked).

[0082] Accordingly, the table can be used to define the selection of bits of the received pattern for which individual failure information should or should not be recorded. In this way, selective masking of a portion of the individual failure information can be achieved, which may be useful, for example, in avoiding interference with individual failure records. In particular, the use of a table that defines the length of a block of one or more bits of a received pattern associated with different functional blocks of the device under test is recognized as an efficient mechanism for distinguishing bits of the received pattern for which individual failure information should be recorded from bits for which individual failure information should not be recorded.

[0083] In a preferred embodiment, the test apparatus is configured to identify bits of a received pattern for which the recording of individual failure information should be omitted (e.g., masked) (e.g., during execution; e.g., during reception of a received pattern from the device under test) using (e.g., one or more bit blocks of the length of a received pattern associated with different functional blocks of the device under test, optionally the length of a start block, optionally a table defining periodicity). The test apparatus includes dedicated hardware for this purpose.

[0084] By using dedicated hardware to identify bits of the received pattern for which the recording of individual pattern information should be omitted, a particularly efficient implementation can be achieved. In particular, by using dedicated hardware, just-in-time processing can be performed and a large buffering mechanism is not required. For example, when using dedicated hardware, the generation of individual failure information can be enabled or disabled at a very early stage of the processing chain, for example, by suppressing a comparison or invalidating (or interrupting) an error signal of a comparison between the received pattern and a reference pattern. Therefore, the computational complexity can be kept very low and the memory requirements can also be relaxed.

[0085] In a preferred embodiment, the test apparatus is configured to (e.g., automatically) initiate (e.g., selective) masking of the recording of individual failure information (e.g., during execution; e.g., during reception of a received pattern from the device under test) in response to detecting that an individual error counter that selectively counts comparison errors of bits associated with a specific functional block of the device under test has reached a predetermined maximum value, (e.g., when a predetermined maximum number of faults generated by that specific functional block has been reached, the recording of individual failure information associated with that specific functional block is automatically stopped).

[0086] By using such an arrangement, when a particular functional block is recognized as generating an excessive number of errors, the recording of individual failure information associated with that functional block can be stopped. In this way, by counting the number of errors attributable to a particular functional block of the device under test, the amount of individual failure information associated with that particular functional block of the device under test can be limited. Thereby, when there are one or more malfunctioning functional blocks of the device under test, it is possible to avoid the recording of individual failure information being obstructed. Instead, for errors attributable to other functional blocks of the device under test, the individual failure recording capacity is maintained. Thus, in this concept, even when there are malfunctioning functional blocks (and considering the limitation of the recording capacity of individual failure information), the possibility of recording individual failure information for multiple functional blocks of the device under test is maintained, so that particularly meaningful test results can be obtained. Therefore, this concept enables a user of a test apparatus capable of limiting the amount of individual failure information for each functional block to obtain meaningful test results that can be analyzed. However, this limitation on the amount of individual failure information for each functional block is typically not a problem. This is because malfunctioning functional blocks typically do not need to have complete individual failure information.

[0087] Therefore, this concept enables very efficient test execution and provides meaningful test results.

[0088] In a preferred embodiment, the test apparatus is configured to identify different blocks of one or more bits of a received pattern (and optionally the length of a start block and optionally the periodicity) associated with different functional blocks of the device under test, using a table that defines the length (and optionally the start block length and optionally the periodicity) of one or more bit blocks of the received pattern associated with different functional blocks of the device under test (e.g., as being associated with different functional blocks of the device under test).

[0089] Using a table that defines the length of one or more bit blocks of a received pattern associated with different functional blocks of a device under test to identify different blocks of one or more bits of the received pattern is in good agreement with the typical structure of the received pattern including a sequence of bit blocks associated with different functional blocks of the device under test, and since the one or more bit blocks have a predetermined length that can be easily represented in a table, it is recognized as a very efficient concept. Further, in the mechanism, the periodicity of the bit blocks associated with different functional blocks of the device under test can also be considered. As a result, it is possible to reliably identify different blocks of one or more bits of the received pattern associated with different functional blocks of the device under test, and thus reach an efficient implementation of the concept that enables separating errors originating from these different functional blocks of the device under test.

[0090] In a preferred embodiment, the test apparatus is configured to identify a periodic sequence of one or more bit blocks of a received pattern associated with different functional blocks of the device under test using a table (such as where there is a periodic association of different bit blocks to different functional blocks).

[0091] By utilizing the periodicity of the received pattern, the complexity of the mechanism for separating errors originating from different functional blocks of the device under test can be significantly reduced. For example, the table of a table-based mechanism may include entries that define the periodicity. However, the table of a table-based mechanism may have a mechanism for recognizing, for example, an initial portion of the received pattern that should be ignored. Thus, the use of the table may, for example, define the length of one or more bit portions associated with different functional blocks of the device under test. If appropriate, the table may define a set of values including length information and an index of the functional block. Additionally, the table may include a reference to an ongoing table entry, for example, to represent the periodicity.

[0092] As a conclusion, the table-based mechanism may include, for example, a list of the lengths of one or more bit blocks, a list of the indexes of the functional blocks associated with one or more bit blocks, and periodic information defining, for example, a sequence or subsequent repetition of bit blocks. Therefore, by evaluating the table, the bits of the received pattern can be reliably associated with the functional blocks, so that the separation of errors associated with different functional blocks of the device under test can be achieved in an efficient way.

[0093] In a preferred embodiment, the test apparatus is configured to adapt the test flow based on information regarding errors in the received pattern associated with a given functional block of the device under test (e.g., based on the value of an error flag register associated with a given functional block of the device under test and / or based on the value of an error counter associated with a given functional block of the device under test).

[0094] Accordingly, the test flow can be adapted according to result information that describes the test results of the individual functional blocks of the device under test, and this test information is made available very quickly (even during the execution of the test program) by separating errors associated with different functional blocks of the device under test that occur during the execution of the test program. As a result, the rapid availability of test results associated with different functional blocks of the device under test, achieved by the concepts disclosed herein, is utilized to improve the quality of the test. For example, if it is determined that a particular functional block of the device under test generates one or more errors in the received pattern, retesting of this particular functional block can be triggered. On the other hand, if the test result information obtained during the execution of the test program (by separating errors associated with different functional blocks of the device under test) indicates that the failure of a particular functional block is significant, the test can be adapted so as to omit the test of this particular functional block with a significant failure in order to efficiently obtain meaningful test results for other functional blocks. Thus, the test result information associated with different functional blocks of the device under test obtained by separating errors during the execution of the test program can be used to influence decisions regarding the execution of the test flow. As a result, high test efficiency can be achieved by executing a test program or test function adapted to the previously obtained test result information.

[0095] In a preferred embodiment, the test apparatus is configured to adapt the test flow in response to a determination (e.g., discovery or detection) that the number of errors (e.g., the number of comparison errors) in the received pattern associated with a predetermined functional block of the device under test has reached or exceeded a predetermined maximum number.

[0096] By using this concept, for example, the test flow can be adapted so that malfunctioning functional blocks do not reduce the reliability and efficiency of further testing of the device under test. For example, further testing can be restricted to other functional blocks of the device under test that have been found to generate no errors or only a small number of errors. For example, spending test time on testing functional blocks that have already been found to generate a large number of errors can be avoided because it cannot be expected that these functional blocks are defect-free. As a result, test resources (e.g., test time and / or individual failure recording capacity) can be concentrated on testing functional blocks of the device under test that do not generate an excessive number of errors in the received pattern. As a result, good test efficiency can be achieved.

[0097] In a preferred embodiment, the test apparatus is configured to repeat a test (e.g., a full test flow or a part of the test flow) (e.g., with the same multicore) in response to a determination (e.g., discovery or detection) that the number of errors (e.g., the number of comparison errors) in the received pattern associated with a given functional block of the device under test has reached or exceeded a predetermined maximum number (e.g., a limit value), by enabling or disabling masking of the recording of individual failure information for the bits of the received pattern associated with a given functional block of the device under test.

[0098] By using such a concept, it is guaranteed that a sufficient amount of individual failure information can be recorded for a plurality of different functional blocks of the device under test, even if there are functional blocks with significant failures in the device under test. In particular, if it is found that a particular functional block of the device under test generates an excessive number of errors, the individual recording of these errors can be automatically disabled, thereby ensuring sufficient recording capacity for individually recording errors caused by other functional blocks of the device under test (other than the functional blocks with significant failures in the device under test) in a re-execution of the test program.

[0099] As a result, meaningful test results can be obtained without being disturbed by errors caused by functional blocks with significant failures in the device under test.

[0100] One embodiment creates a test device (e.g., a test processor, or a channel module of an automatic test device, or an automatic test device) for testing a device under test, where the test device is configured to receive a pattern (e.g., a result pattern; e.g., a response pattern) from the device under test, and this pattern is from a plurality of functional blocks of the device under test (e.g., a "core"; e.g., a result block; e.g., a functional block that provides substantially independent test results or test responses) (e.g., associated) (e.g., in a combined form; e.g., in an interleaved form) information (e.g., test results; e.g., test response information) in the form of a sequence of bits. The test device is configured to separate (e.g., handle separately, or record separately) errors in the received pattern associated with different blocks of one or more bits during the execution of the test program (e.g., to obtain test results for each functional block of the device under test, e.g., for each core of the device under test) during the execution of the test program.

[0101] This embodiment is based on considerations similar to those of the embodiments disclosed above, and it should be noted that during the execution of the test program, the test device is configured to separate errors in the received pattern associated with different blocks of one or more bits. Therefore, there is no need to have a fixed association between the bits in the received pattern and the functional blocks of the device under test. Rather, this concept can generally be used when different blocks of one or more bits in the received pattern constitute different meanings, indicate different types of errors, etc. However, it should be noted that this concept can be optionally supplemented by any of the features, functions, and details disclosed herein.

[0102] One embodiment creates a method for testing a device under test. The method includes receiving a pattern (e.g., a result pattern; e.g., a response pattern) from the device under test, the pattern including information (e.g., test results; e.g., test response information; e.g., a sequence of bits) from a plurality of functional blocks of the device under test (e.g., a "core"; e.g., a result block; e.g., a functional block that provides substantially independent test results or test responses), where the information is (e.g., associated) (e.g., in combined form; e.g., in interleaved form). The method further includes separating (e.g., handling separately or recording separately) errors within the received pattern associated with different functional blocks of the device under test (e.g., to obtain test results for each functional block of the device under test, such as for each core of the device under test) during execution of a test program.

[0103] This method is based on considerations similar to those of the test apparatus described herein. Further, it should be noted that this method can be optionally supplemented individually and in combination by any of the features, functions, and details disclosed herein.

[0104] An embodiment according to the invention creates a computer program for executing the method according to claim 37 when the computer program is executed on a computer.

Brief Description of the Drawings

[0105] Hereinafter, embodiments according to the invention will be described with reference to the accompanying drawings.

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0106] Detailed Description of Embodiments 1. Test Apparatus According to FIG. 1 FIG. 1 is a block schematic diagram of a test apparatus 100 according to an embodiment of the present invention.

[0107] The test apparatus 100 is configured to receive an input signal 110 from a device under test 102, and the device under test 102 is usually not part of the test apparatus 100. For example, the input signal 110 may define an input pattern. Further, the test apparatus 100 is configured to provide test result information 112 based on the input signal 110.

[0108] Note that the test apparatus 100 may be part of a test system. However, the test apparatus 100 may be implemented, for example, in a test processor, a channel module of an automatic test apparatus, or generally in an automatic test apparatus.

[0109] The test device 100 is configured to receive a pattern (e.g., a result pattern, e.g., a response pattern) from the device under test. The received pattern typically has (e.g., in a combined form; e.g., in an interleaved form) information (e.g., test results; e.g., response information; e.g., a sequence of bits) from a plurality of functional blocks of the device under test (e.g., a "core"; e.g., a result block; e.g., a functional block that provides substantially independent test results or test responses) (e.g., associated). The test device includes an error separation or error separator configured to separate (e.g., process separately and / or transfer separately and / or record separately) errors in the received pattern associated with different functional blocks of the device under test, e.g., to separate errors of different functional blocks or "cores" of the device under test, during execution of a test program.

[0110] Accordingly, the test device 100 can obtain (e.g., separate or different) test results for each functional block of the device under test, e.g., for each core of the device under test, during execution of a test program. Accordingly, the test result information 112 can describe, e.g., separate test results associated with different functional blocks or cores of the device under test.

[0111] In this way, by separating errors in the received patterns associated with different functional blocks during the execution of the test program, or by separating errors in the received patterns associated with different blocks of one or more bits, meaningful test result information can be obtained with a moderate implementation effort and a very low latency. Therefore, the test result information 112 can, during the execution of the test program, for example, without large-scale buffering of the complete received pattern, constitute meaningful information that individually describes the integrity of different functional blocks or cores of the device under test. Therefore, the described concept has been found to provide a very good compromise among complexity, test scope, latency, and accuracy. Therefore, the test apparatus 100 helps to efficiently test a device under test that provides test results of different functional blocks or cores in a multiplexed form (e.g., via a single common pin).

[0112] Furthermore, it should be noted that the test apparatus 100 can optionally be supplemented by any of the features, functions, and details disclosed herein.

[0113] 2. Test Apparatus According to FIG. 2 FIG. 2 is a block schematic diagram of a test apparatus 200 according to an embodiment of the present invention. The test apparatus 200 receives an input signal 210 from a device under test 202. For example, the input signal 210 may be a signal from one pin of the device under test. For example, the input signal may be a response of the device under test to a stimulus signal, and the input signal 210 may define, for example, an input pattern.

[0114] Furthermore, the test apparatus 200 may provide test result information 212 that includes, for example, summary failure information 212a and / or individual failure information 212b. For example, the summary failure information 212a can be individually described in a form that summarizes errors associated with different functional blocks of the device under test 202. For example, the summary failure information 212a can indicate, for a plurality of functional blocks or groups of functional blocks, which of the functional blocks or groups of functional blocks caused at least one error within the received pattern (e.g., within the pattern determined by the input signal 210). For example, the summary failure information 212a may include one binary value per functional block or group of functional blocks, each binary value indicating whether the corresponding functional block or group of functional blocks of the device under test caused at least one error within the received pattern. Alternatively or additionally, the summary failure information 212a may include separate count values that count the number of errors generated by different functional blocks or groups of functional blocks of the device under test. Thus, the different count values can describe, for example, errors occurring in different blocks of one or more bits within the received pattern (where the different blocks of one or more bits may be associated with different functional blocks or groups of functional blocks of the device under test). Thus, the counter values can individually indicate, for example, how many errors within the received pattern were caused by different functional blocks or groups of functional blocks of the device under test.

[0115] Therefore, the summary fault information 212a can provide meaningful information about, for example, whether different functional blocks caused errors within the received pattern and / or how many errors different functional blocks (or groups of functional blocks) of the device under test caused within the received pattern. Thus, based on the summary fault information, it can be determined whether different blocks (or groups of functional blocks) are operating as expected (e.g., when no errors are caused within the received pattern) or whether different functional blocks (or groups of functional blocks) are not operating as expected (e.g., when at least one error is caused within the received pattern).

[0116] Furthermore, when counter information is provided as part of the summary fault information 212a, it can also be quickly determined whether one or more functional blocks (or groups of functional blocks) of the device under test have failed significantly and caused a relatively large number of errors within the received pattern. For example, if it is found that the number of errors within the received pattern due to a specific functional block (or group of functional blocks) of the device under test reaches a predetermined number or more, the test apparatus can conclude that the failure of that functional block (or group of functional blocks) is significant. For example, such a specified functional block (or group of functional blocks) can be excluded from further testing. This is because there is no need to further test a functional block (or group of functional blocks) with a significant failure, which may complicate or interfere with the testing of other functional blocks that do not cause errors or cause only a small number of errors within the received pattern.

[0117] However, the summary failure information 212a generally provided during the execution of a test program is generally provided with low latency and may in some cases be sufficient to classify the device under test (e.g., as being operable properly or defective), and thus it should be noted that it is very useful for testing the device under test. In particular, the summary failure information may provide an overview of the integrity of different functional blocks (or groups of functional blocks) of the device under test, which is useful for making decisions about the test flow and / or for performing a more detailed classification of the device under test.

[0118] Individual failure information 212b, which can be part of the test result information 212, can describe individual faults in the received pattern, for example, in a time - distinguishable way. For example, the individual failure information 212b may describe individual failures in the received pattern using timing information that describes the time at which an individual error occurred (e.g., using a timestamp or a bit - position index to describe the bit - position of an individual error in the received pattern). Usually, the individual error information does not describe a complete copy of the received pattern, but rather describes individual errors within the received pattern, thereby saving memory capacity. For example, the individual failure information is useful for detailed analysis of the faults, such as determining which hardware components of the device under test have failed.

[0119] The test apparatus 200 includes a comparator 220 that compares a received pattern (which may be represented by the input signal 210) to an expected pattern (which may be considered a reference pattern and may be provided, for example, by a reference signal generator or a reference pattern generator). The comparator 220 may provide an error signal 222 in response to, for example, the detection of an error in the received pattern (where a deviation between a bit of the received pattern and a bit of the reference pattern may be considered an error). For example, the comparator may provide error signaling 222 for all errors between the reference pattern and the received pattern, but in some cases, for different blocks of one or more bit positions within the received pattern, comparison and / or provision of error signaling 222 and / or transfer of error signaling 222 may be selectively enabled and / or selectively disabled (for example, to isolate errors associated with different functional blocks (or groups of functional blocks) of the device under test).

[0120] The test device 200 also includes a summary failure information determination / summary failure information determiner 230 that receives an error signal 222 from a comparator 220 and provides summary information 212. The summary failure information determiner 230 may be configured to perform, for example, bit position-dependent / function block-dependent error recording and / or bit position-dependent / function block-dependent error counting. For example, the error recording may perform a comparison failure recording, and comparison failures in different blocks of one or more bits of the received pattern may be recorded in different error registers. Similarly, the error counting may perform a comparison failure count, and comparison failures occurring in different blocks of one or more bits of the received pattern may be counted by different counters. For example, the summary failure information determination may receive a control signal from a control 240, and the control signal 242 may indicate to the summary failure information determination, for example, in response to the failure signaling 222, which error register should be enabled by the error signal or which error counter among a plurality of error counters should be incremented. The control 240 can provide one or more control signals 242 based on, for example, prior knowledge of which bit positions in the received pattern are associated with which functional blocks (or groups of functional blocks) of the device under test, taking into account the timing of the input signal 210. Thus, the summary failure information determination can individually record and / or count comparison failures caused by different functional blocks (or groups of functional blocks) of the device under test. Thus, meaningful summary failure information can be generated.

[0121] Furthermore, the test apparatus 200 includes an individual failure information recording / individual failure information recording device 250. This individual failure information recording / individual failure information recording device 250 can receive an error signal 222 from the comparator 220 and can also receive one or more control signals 244 from the controller 240. The individual failure information recording / individual failure information recording device provides individual failure information 212b. For example, the individual failure information recording / individual failure information recording device 250 can perform bit position-dependent / function block-dependent error recording, thereby obtaining the individual failure information 212b. The individual failure information 212b may include, for example, timing information describing the timing position of the comparison failure. However, the individual failure information recording / recording device 250 may be controlled such that comparison failures (comparison errors) associated with different functional blocks of the device under test are recorded individually and / or such that the recording of individual failure information can be individually enabled and / or disabled for failures associated with different functional blocks of the device under test. For example, the enabling and / or disabling of the recording of individual failure information can be controlled by a control signal 244 provided by the controller 240. Thus, it is possible to selectively record individual failure information associated with different functional blocks of the device under test. For example, for failures caused by one or more specific functional blocks of the device under test, the recording of individual failure information can be disabled. Thus, it is possible to focus the recording of individual failure information on individual failure information associated with one or more functional blocks of the device under test that are currently of interest. Alternatively, or in combination, for failures caused by one or more specific functional blocks of the device under test, for example, one or more specific functional blocks of the device under test that have a large number of failures (and thus generate an excessive number of failures), the recording of individual failure information can be selectively suppressed.

[0122] For example, if the general failure information determination 230 determines that this specific functional block of the device under test has received a number of errors that reach or exceed a predetermined threshold in the received pattern, for the specific functional block of the device under test, the recording of individual failure information may be automatically invalidated by the test apparatus (e.g., by control 240). Thus, for example, for a predetermined functional block of the device under test (or for all functional blocks of the device under test), only a predetermined maximum amount of individual failure information may be recorded. This prevention of further recording of individual failure information for the malfunctioning functional blocks of the device under test may be controlled, for example, by the control signal 244 provided by the general failure information determination.

[0123] Thus, the test apparatus 200 can isolate errors in the received patterns associated with different functional blocks of the device under test during the execution of the test program. The general failure information 212a can, for example, individually indicate failure information indicating whether different functional blocks of the device under test have caused failures in the received pattern and / or the number of failures caused by different functional blocks of the device under test. Further, the apparatus enables the provision of individual failure information that can determine (set) which errors the individual failure information 212b is recorded for by separating the errors in the received patterns associated with different functional blocks. For example, for errors caused by a specific functional block of the device under test, the recording of individual failure information can be selectively enabled and / or disabled. Thus, the amount of individual failure information can be kept appropriately small, thereby reducing memory requirements and / or preventing interference with the available memory (e.g., by invalidating the recording of errors generated by malfunctioning functional blocks of the device under test).

[0124] In this way, the test apparatus provides a very efficient test of the device under test, and the summary fault information that is available with little delay helps to classify the device under test and also helps to determine the test flow. Further, the selective recording of individual failure information may help to conserve test resources and efficiently obtain meaningful test results even when one or more functional blocks of the device under test are severely faulty.

[0125] Furthermore, it should be noted that the test apparatus 200 can optionally be supplemented individually and in combination by any of the features, functions, and details disclosed herein.

[0126] 3. Test Apparatus According to FIG. 3 FIG. 3 is a block schematic diagram of a test apparatus 300 according to another embodiment of the present invention.

[0127] The test apparatus 300 according to FIG. 3 is configured to receive an input signal 310 and, based thereon, provide result information 312 including, for example, general failure information 312a and individual failure information 312b. Here, it can be assumed that the device under test 302 provides the input signal 310 of the test apparatus 300. The input signal 310 may be, for example, a signal output by the device under test 302 at a pin of the device under test 302. For example, the input signal 310 may be a digital signal, and the test result data from the first functional block of the device under test is included in the input signal 310 in the first block of one or more bit positions, and the test result data from the second functional block of the device under test 302 is included in the second block of one or more bit positions. In other words, the test result data from different functional blocks of the device under test 310 may be multiplexed (e.g., time multiplexed) in the input signal 310 using, for example, a predetermined multiplexing rule. Thus, the input signal 310 may be, for example, a signal transmitted from one pin of the device under test, and may represent, for example, the response of the device under test to a stimulus signal that may also be provided by the test apparatus. For example, the input signal 310 can define an input pattern, which is also designated as a received pattern herein.

[0128] The input signal 310 may optionally undergo some preprocessing in a test apparatus not shown in FIG. 3. The preprocessing may include, for example, conversion of the actual analog input signal 310 to a digital signal, discretization of time (e.g., sampling), etc.

[0129] Thus, for example, a time-discretized digital version of the input signal may be supplied to the comparator 320. The comparator 320 also receives a reference signal or a reference pattern from the reference signal generator / reference pattern generator 326. Thus, the comparator may compare the input signal 310 (or its digitized and time-discretized version) with the reference signal 328 provided by the reference signal generator 326, or the comparator 320 may compare the received pattern (defined by the input signal 310) with the reference pattern provided by the reference pattern generator 326. For example, the comparator 320 may compare the input signal (or its digitized and time-discretized version) with the corresponding reference signal on a bit-by-bit basis, or the comparator may compare the received pattern with the reference pattern on a block-by-block basis.

[0130] In this concept, it should be noted that both the bit-by-bit comparison between the input signal 310 (or its digitized and time-discretized version) and the reference signal and the block-by-block comparison between the received pattern and the corresponding reference pattern may be used to identify errors in the received pattern (where the difference between a bit of the input signal and a bit of the reference signal indicates an error in the received pattern, and it is assumed that the difference between one or more bits in the received pattern and a bit in the reference pattern also indicates an error in the received pattern). In other words, it should be noted that the input signal received by the test device can be regarded as a representation of the received pattern.

[0131] Putting it another way, detecting whether the bits of the input signal received by the test apparatus deviate from the corresponding bits of the reference signal is one possibility of detecting an error in the received pattern. However, a block-by-block comparison between the block of bits of the input signal 310 and the block of bits of the reference pattern provided by the reference signal generator 326 is another concept for identifying errors within the received pattern. Generally speaking, it should be noted that the temporal evolution of the input signal 310 defines the received pattern, and the detection of an error within the received pattern corresponds to the detection of a deviation of the input signal from the corresponding reference signal.

[0132] Furthermore, it should be noted that the received pattern received by the test apparatus may be a bit pattern in which test result data from different functional blocks of the device under test are time-division multiplexed (preferably according to a predetermined time-division multiplexing rule).

[0133] The comparator provides an error signal 322, and the error signal 322 may indicate, for example, a deviation between the bits of the received signal and the bits of the reference signal, or equivalently, an error within the received pattern.

[0134] The error signal may be evaluated, for example, for determining the general fault information. For example, the test device 300 may comprise one or more error separators / error signal transmitters 332a, 332b (where, for example, the use of a plurality of error separators / error signal transmitters may be advantageous when a plurality of error signals are generated simultaneously or in close temporal succession), and the test device 300 may also comprise a plurality of result units 336a, 336b, 336n. For example, the error signal separator 332a may receive the error signal 322 and transfer the error signal 322 to one of the result units 336a, 336b, 336n according to control information (for example, according to the error separator control signal 342). For example, the error separator 332a may be considered as an error signal transmitter and may be implemented, for example, using a multiplexer. Thus, the error separator 332a can determine to which of the result units 336a, 336b, 336c the error signal is transferred.

[0135] The determination of to which of the result units 336a, 336b, 336n the error signal is transferred may be based on the determination of which functional block of the device under test the wrong bit in the received pattern that caused the activation of the error signal 322 is associated with. For example, if the wrong bit in the received pattern that caused the activation of the error signal 322 is associated with (or caused by) the first functional block of the device under test, the error signal 322 may be transferred to the first result unit 336a. In contrast, if the wrong bit in the received pattern that caused the activation of the error signal 322 is associated with (or caused by) the second functional block of the device under test, the error signal 322 may be transferred to the second result unit 336b. Further, generally speaking, if the activation of the error signal 322 is caused by a wrong bit in the received pattern that is associated with (or caused by) the nth functional block of the device under test, the error signal 322 may be transferred by the error separator 332a to the nth result unit 336n.

[0136] Each of the result units 336a, 336b, 336n may be configured to record, for example, the activation of an error signal transferred to each respective result unit. For example, the first result unit 336a may have an error flag register 337a and / or an error counter 338a. Thus, when an error signal 322 is transferred to the first result unit 336a, the error flag register 337a of the first result unit 336a is set, thereby indicating that an error in the received pattern was caused by the first functional block of the device under test (wherein, in effect, the first result unit 336a is associated with the first functional block of the device under test). Alternatively or additionally, when an error signal (i.e., the valid error signal 322) is transferred to the first result unit 336a, the error counter 338a of the first result unit 336a is incremented. Thus, the error counter 338a of the result unit 336a can count the number of errors in the received pattern associated with the first functional block of the device under test. Thus, the result unit 336a can record, for example, whether there is an error in the received pattern caused by the first functional block and / or how many errors there are in the received pattern caused by the first functional block of the device under test. Similarly, the error flag register 337b of the second result unit 336b becomes valid when a (valid) error signal is transferred to the second result unit 336b via the error separator 332a. In other words, the error flag register 337b is set in response to an error in the received pattern associated with (or caused by) the second functional block of the device under test. Alternatively or additionally, the error counter 338b of the second result unit 336b is incremented in response to the presence of an error in the received pattern associated with (or resulting from) the second functional block of the device under test.

[0137] Accordingly, each result unit records and / or counts errors in the received pattern associated with the corresponding functional block of the device under test. However, alternatively, each result unit can also record and / or count errors in the received pattern due to a group of functional blocks of the device under test. In other words, there need not be a one-to-one relationship between the functional blocks of the device under test and the result units. Rather, multiple functional blocks of the device under test may, in some cases (e.g., when the number of result units is less than the number of functional blocks of the device under test), be associated with a single result unit.

[0138] In conclusion, using the selective transfer of error signals to one of the result units, controlled, for example, by error separator 332a or control unit 340 providing error separator control signal 342, errors in the received pattern associated with different functional blocks of the device under test can be recorded and counted in different result units. As a result, the error flag register of each result unit indicates whether the functional block of the device under test associated with that result unit caused an error in the received pattern. Similarly, the error counter of each result unit indicates how many errors the functional block of the device under test associated with that result unit caused within the received pattern. Accordingly, different result units provide information regarding the integrity of different functional blocks of the device under test. For example, each error flag register of the result units indicates whether each functional block of the device under test caused one or more errors within the received pattern, and the error counter of each result unit indicates how many errors each functional block of the device under test caused within the received pattern.

[0139] Accordingly, the information of the error flag register and / or the information of the error counter of the result units can be used as the general failure information 312a.

[0140] It should be noted that the result unit may have a function to reset the error flag register and / or the error counter, and / or a function to freeze the state of the error flag register and / or the error counter, and a function to read the state of the error flag register and / or the count value of the error counter. For example, the read value (e.g., the binary value of the error flag register and / or the numerical value of the error counter) can form summary failure information. In this way, the summary failure information 312a can quickly provide an overview of which functional blocks of the device under test caused one or more errors in the received pattern. Further, the summary failure information 312a can also quickly provide an overview of which functional blocks of the device under test have large failures, that is, which functional blocks caused a large number of errors in the received pattern.

[0141] The test apparatus 300 may also optionally include an error recording device 350 that can provide individual failure information 312b. For example, the error recording device 350 may record (e.g., store in memory) individual failure information that describes the error in detail and typically includes timing information that accurately defines the timing of the error. For example, the individual failure information may include the exact time (or bit position) at which the error occurred and can describe multiple errors in the received pattern in detail. Usually, since the received pattern is assumed to include only a relatively small number of errors, it is generally more memory-efficient to save individual error information than to save the entire received pattern for later evaluation. However, individual error information typically enables the user of the test apparatus to analyze the errors of the device under test in detail. Therefore, with individual error information, it is usually possible to more accurately grasp which types of errors occurred in the device under test, while with the summary failure information 312a, it is usually only possible to recognize that an error occurred in a functional block of the device under test and the degree to which the functional block of the device under test failed.

[0142] However, the test apparatus 300 can be configured to selectively enable and / or disable the recording of individual failure information for errors resulting from specific functional blocks of the device under test. For example, the control 340 can provide one or more error recording control signals 343 to selectively enable and / or disable the recording of individual failure information for errors within the received pattern associated with a specific functional block of the device under test. For example, if the control 340 discovers that the currently analyzed bit position of the received pattern is associated with the functional block of the device under test for which individual failure information should be recorded, the control 340 can enable the recording of individual failure information and / or enable the transfer of the failure signal 322 to the error recording device 350. On the other hand, if the control 340 discovers that the currently analyzed (or processed) bit position is associated with a functional block of the device under test for which individual error information should not be recorded, the control 340 can provide one or more control signals to disable error recording by the error recording device 350 or to disable the transfer of the error signal 320 to the error recording device 350 (thereby preventing the recording of individual error information).

[0143] Accordingly, the control 340 can track which functional block of the device under test the current bit position currently being processed by the comparator 320 is associated with, and in response, control the error separator 332a to transfer possible error signals to the appropriate result unit and can enable or disable the recording of individual failure information. Accordingly, it is possible to avoid recording individual failure information for one or more functional blocks of the device under test. This is particularly advantageous when it is known in advance that one or more functional blocks of the device under test are grossly malfunctioning, i.e., providing a very large number of errors within the received pattern. In such cases, by disabling the recording of individual failure information within the received pattern originating from the grossly malfunctioning functional block of the device under test, interference with the error recording device or the individual failure memory of the error recording device can be prevented.

[0144] Furthermore, in the test apparatus 300, it should be noted that, for example, the recording of individual failure information can be automatically disabled for the functional blocks of the device under test in which the result unit has recognized an excessive number of failures. For example, when the error counter of the result unit associated with a certain functional block of the device under test reaches a predetermined threshold or more, the recording of individual failure information can be automatically disabled for the bit positions associated with the functional block with a large specific failure of the device under test. For this purpose, a simple control logic can be used to recognize that the error counter of a certain result unit has reached or exceeded a predetermined threshold and to disable the recording of individual failure information for the associated blocks of one or more bits of the received pattern.

[0145] Control 340 supplies a control signal to the error separator 332a and should be noted that it can also be used to enable and disable the recording of individual failure information by the error recorder 350. For example, the control 340 can be synchronized in timing with a stimulus generator that supplies a stimulus signal to the device under test, a reference signal generator 326, and a comparator 320. Therefore, the control unit 340 may operate, for example, in temporal synchronization with the bit clock of the input signal 310. Therefore, the control unit 340 may count the received bits of the input signal 310 and thus can operate in synchronization with the bits of the received signal 310. For example, the control unit can count the received bits of the input signal 310 and conclude which functional block of the device under test each individual bit is associated with. For example, the control unit 340 can define groups of bit positions in the input signal 310 on a table basis. The table-based definition can describe, for example, the lengths of different groups (or blocks) of bits in the input signal 310. For example, the table-based definition of a group of bit positions may indicate that the input signal starts with a large number of "unreliable" bits that should be discarded. The table-based definition of the group of bit positions used by the control 340 can specify that the next bit group is associated with the first functional block of the device under test and that subsequent bit groups are associated with the second functional block of the device under test. Also, the lengths of different groups of one or more bits can also be defined in the table-based definition of the group of bit positions.

[0146] Furthermore, the table-based definition of a group of bit positions may also include information regarding the repetition of the bit group (e.g., the number of repetitions). For example, the table-based definition of a group of bit positions may include, for example, jump position information or periodicity information that may define the repetition of a sequence of groups of bit positions. For example, the jump position information may indicate to jump back to a specific row of the table-based definition in order to define the repetition of the association definition between a group of bit positions and a functional block of the device under test. Thus, the periodicity of a group of bit positions within the input signal 310 may be defined by a table.

[0147] Accordingly, the control 340 can determine the functional block index for all bits within the received pattern. In other words, the control 340 can determine for each bit within the received pattern which functional block of the device under test this bit is associated with (where some bits of the received pattern may in fact not be associated with any functional block of the device under test, which may be indicated, for example, by a “special” functional block index indicating non - association). Thus, for example, a functional block index including an index indicating non - relevance may be provided by the control 340 for each bit (bit position) of the received pattern. This index can be used to control the error separator 332a, since it can define, for example, to which result units 336a, 336b, 336n an error signal (or error signaling) should be transferred. Further, the index determined by the control 340 can also be used to determine whether the error recording device 350 should record individual error information 312b when each bit is an error. For example, it can be defined that for an erroneous bit (bit position) for which the control 340 has associated a particular index value, individual failure information should be recorded, and that individual failure information should not be recorded when other index values are associated with the erroneous bit (bit position). Thus, the control 340 can distinguish different groups of one or more bit positions, for example, using timing synchronization with the stimulus generator, reference signal generator, and comparator, based on a table - based definition of groups of bit positions, and the control 340 can control the generation of summary failure information and the recording of individual failure information based on a determination of which group of one or more bits (as defined by the table - based definition of groups of bit positions) an error has occurred in. As a result, the test apparatus 300 can obtain summary failure information 312a indicating the integrity of different functional blocks of the device under test, and the test apparatus can obtain individual failure information 312b for selected functional blocks of the device under test.

[0148] Furthermore, it should be noted that the test apparatus includes, for example, a test flow control 380 that determines which test program is to be executed. For example, the test flow control can control the stimulator and the reference signal generator, but the test flow control can also control other components of the test apparatus. However, the test flow control 380 can make a decision regarding the execution of the test flow based on the summary failure information 312a. In this regard, it should be noted that since the summary failure information 312a is typically determined during the execution of the test program, the summary failure information 312a is available with little latency. Therefore, the test flow control 380 can quickly recognize, based on the summary failure information, which functional blocks of the device under test appear to be error-free, which functional blocks of the device under test are failing, or are significantly malfunctioning. Therefore, the test flow control 380 can determine which test program should be executed in consideration of the information on the functional states of the different functional blocks of the device under test provided by the summary failure information. Therefore, a particularly efficient test flow can be implemented, for example, further testing of functional blocks with significant failures can be avoided, or, for example, a more detailed analysis of functional blocks with significant failures can be performed.

[0149] Of course, it is also possible to change test parameters such as the power supply voltage and the clock frequency according to the summary failure information.

[0150] In conclusion, the test apparatus 380 provides a significant amount of information regarding the device under test in a very efficient and fast manner. It can also prevent interference with the recording of individual failure information and direct the recording of individual failure information to one or more functional blocks of particular interest. Also, by using the summary failure information, the test flow control can be optimized.

[0151] Furthermore, it should be noted that the functionality of apparatus 300 can be implemented fully or partially in hardware, especially to enable a particularly fast response time. However, it should be noted that at least a part of the functionality of test apparatus 300 may optionally be implemented in software.

[0152] Furthermore, it should be noted that the test apparatus may optionally include a plurality of error separators / error signal transmitters. This is advantageous, for example, when a comparator performs a block-by-block comparison between a block of bits of an input signal and a block of bits of a reference signal. In this case, a plurality of error signals resulting from the block-by-block comparison can be processed in parallel. However, it should be noted that it is not necessary to include a plurality of error separators / error signal transmitters.

[0153] Furthermore, it should be noted that the functionality described herein can be implemented using different functional blocks. For example, the functionality of the error separator / error signal transmitter may be implemented in the result unit, for example, using a selective enabling mechanism.

[0154] Similarly, it should be noted that different actual implementations can be used to selectively enable and disable the recording of individual failure information. However, it seems important to have a control mechanism for tracking which group of one or more bits the currently considered bit of the received pattern is associated with (this corresponds to tracking which functional block the bits of the received pattern are associated with). Knowing which group of bits (or equivalently, which functional block of the device under test) the bits of the received pattern are associated with allows for efficient and accurate control of the determination of summary failure information and / or the determination of individual failure information.

[0155] Furthermore, it should be noted that the test apparatus 300 according to FIG. 3 can be optionally supplemented by any of the features, functions, and details disclosed herein.

[0156] 4. Bitstream according to FIG. 4 FIG. 4 is a schematic diagram showing an example of a bitstream provided by a device under test. This bitstream is designated by 400.

[0157] This bitstream may be provided by a device under test and may constitute a received pattern received by the test apparatus described herein.

[0158] For example, the bitstream is logically divided into 32-bit blocks, and each row 410a, 410b, 410c shows a 32-bit sequence generated from different pins of the device under test. For example, bits 0-2, 8-10, 16-18, 24-26 may not be associated with functional blocks of the device under test, but may provide general information such as, for example, synchronization information, parity information, undefined information, or determined fixed values. However, bit positions 3-7, 11-15, 19-23, and 27-31 may provide information associated with different functional blocks of the device under test. For example, bit positions 3-7, 11-15, 19-23, and 27-31 may include test results of different functional blocks of the device under test.

[0159] For example, different functional blocks of the device under test may be stimulated by one or more stimulus signals provided by the test apparatus, and the stimulus signals may be input, for example, into a scan chain of the device under test and / or (for example, at the input terminals of the device under test). However, the result information of the functional blocks of the device under test may be based on internal signals of the device under test (or functional blocks of the device under test) multiplexed together, for example, into the bitstream 400.

[0160] For example, as seen in the first row 410a, the sequence of bits designated by 422a may start with bit e0 from the (first) functional block e of the device under test, followed by two bits c7, c3 from the (second) functional block c of the device under test, followed by two bits b6, b3 from the (third) functional block b of the device under test, followed by three bits a8, a4, a0 from the (fourth) functional block a of the device under test, followed by two bits g4, g0 from the (fifth) functional block g of the device under test, and end with two bits e8, e4 from the first functional block e of the device under test. Thus, the sequence 422a may have 12 bits (3 bits from functional block e, 2 bits from functional block c, 2 bits from functional block b, 3 bits from functional block a, and 2 bits from functional block g) derived from five different functional blocks of the device under test. In this way, bits derived from different functional blocks of the device under test (which may represent, for example, the state of internal signals of each functional block) are interleaved in a common signal. For example, different bit positions are associated with different internal signals of different functional blocks of the device under test, and the actual values of the different bit positions may actually change over time, for example, in response to "stimuli" of different functional blocks of the device under test. Thus, for example, the bit at bit position e0 describes the state of a particular internal signal of the first functional block e, the bit at bit position e8 describes the state of another internal signal of the first functional block e, and the bit at bit position e4 can describe yet another internal signal of functional block e. Similarly, the bits at bit positions c7 and c3 can describe different internal signals of functional block c.

[0161] However, the assignment of positions can continue with a certain periodicity. For example, bit position 21 of the 32-bit group shown in the first row of row 410a may represent again the same internal signal of the device under test signaled at bit position 3 within the first block of 32 bits ( / but at a later time event). Further, the next bit positions 22, 23, 27, 28, 29, 30, and 31 may represent the same internal signals of the respective functional blocks represented at positions 4, 5, 6, 7, 11, 12, and 13.

[0162] However, as seen in the second line 410b and the third line 410c, similar signals may exist on different pins of the device under test.

[0163] In general, it should be noted that the device under test typically functions as an input signal to the test apparatus and provides a signal having periodicity. The signal provided by the device under test at the input of the test apparatus generally has a repetitive sequence of bits that describe various signals within the device under test, which are typically internal signals of the functional blocks of the device under test but may also include signals available externally.

[0164] However, the test apparatus is configured to track which bits of the sequence of bits belong to which functional blocks of the device under test (or which bits of the received signal or "received pattern" belong to which groups of functional blocks), and thus can isolate errors belonging to different functional blocks or groups of functional blocks of the device under test. For this purpose, the test apparatus may be configured to re-trace the assignment using rules that define which bits (or bit positions) of the received signal or received pattern are associated with which functional blocks of the device under test, for example using a table-based definition of the association rules.

[0165] For example, a table - based description of an association rule can define a group of bits by its length (one or more bits) and an index that specifies an associated functional block or a group of associated functional blocks. Further, the table - based definition of the association rule may optionally include a definition of periodicity and a definition of bits that are not associated with any functional block of the device under test (e.g., bit positions 0 - 2, 8 - 10, 16 - 18, 24 - 26, etc.).

[0166] However, it should be noted that the bitstream 400 as shown in FIG. 4 should be considered only as an example, and various forms of bitstreams are possible.

[0167] 5. Mapping mechanism according to FIG. 5 FIG. 5 is a block schematic diagram of a mapping mechanism that can be used in the test apparatus according to the present invention. For example, the mapping mechanism 500 according to FIG. 5 can be optionally used in any of the test apparatuses described in this specification, such as the test apparatus 100 according to FIG. 1, the test apparatus 200 according to FIG. 2, or the test apparatus 300 according to FIG. 3. However, the mapping mechanism 500 can also constitute an independent embodiment that can be used by itself.

[0168] The mapping mechanism 500 according to FIG. 5 is configured to receive pass / fail data (PFD: Pass / Fail - Data) 510.

[0169] Furthermore, the mapping mechanism 500 provides masked pass / fail data 512 and / or pass / fail data for each core 514 based on the pass / fail data 510. For example, the mapping mechanism 500 includes a hardware mapper 520 that receives the pass / fail data 510 and provides masked pass / fail data 512 and / or pass / fail data for each core 514 based on it. The hardware mapper 520 receives mapping data 522 from a mapping scheme 530.

[0170] For example, the mapping scheme 530 may define how the pass / fail data 510 should be mapped to the masked pass / fail data 512 and / or the pass / fail data 514 for each core by the hardware mapper 520. For example, the mapping scheme 530 can define which pass / fail data 510 should be blocked (or omitted) in the masked pass / fail data 512, and / or which pass / fail data 510 should be carried over to the masked pass / fail data 512. For example, the mapping scheme 530 may define that specific bits of the pass / fail data 510 are carried over to the masked pass / fail data 512, or the mapping scheme 530 may define that specific bits of the pass / fail data 510 should be blocked and should not be carried over to the masked pass / fail data 512.

[0171] The mapping scheme 530 may have, for example, a definition of the bit positions (e.g., of a group of bits) of the pass / fail data 510 that should be carried over to the masked pass / fail data 510, and / or a definition of the bit positions (e.g., of a group of bits) of the pass / fail data 510 that should not be carried over to the masked pass / fail data 512. For example, the hardware mapper 520 may have a controllable transmission gate for obtaining the masked pass / fail data 512 based on the pass / fail data 510, and the controllable transmission data may be controlled by the mapping data 522.

[0172] Furthermore, the hardware mapper 520 distributes the pass / fail data 510 (e.g., to a plurality of different outputs), thereby enabling the pass / fail data per core or the pass / fail signal 514 per core to be obtained. For example, the hardware mapper can transfer a part of the pass / fail data 510 to a first output and transfer another part of the pass / fail data 510 to another output. For example, the hardware mapper 520 may constitute a multiplexer that selectively transfers the pass / fail data 510 to respective outputs, and the multiplexer may be controlled by, for example, the mapping data 522. Accordingly, one or more bits of the pass / fail data associated with (e.g., derived from) the first functional block (e.g., core) of the device under test are transferred by the hardware mapper to the first output, and the hardware mapper 510 (or its multiplexer) can transfer one or more other bits of the pass / fail data 510 associated with another functional block (e.g., core) of the device under test to another output. Accordingly, the pass / fail data 510 may be separated into pass / fail data associated with different functional blocks (e.g., cores) of the device under test. For example, different bits of the pass / fail data 510 may be transferred to different outputs for the pass / fail data signals for each separate core. This multiplexing can also be controlled by the mapping data 522 derived from the mapping scheme 530.

[0173] As a mere example, the mapping mechanism 500 may be configured to transfer the pass / fail data based on, for example, bits e0, e4, e8, c3, c7, b2, b6, g0, and g4 to the masked pass / fail data 512. However, for example, the pass / fail data derived from bits a0, a4, and a8 may be blocked so that the pass / fail data based on bits a0, a4, and a8 is not included in the masked pass / fail data 512. This is useful, for example, when the functional block (or core) a is severely malfunctioning (e.g., generating a large number of faulty bits). Accordingly, the amount of pass / fail data indicating error bits can be appropriately reduced.

[0174] Furthermore, the mapping mechanism 500 may be configured to selectively transfer pass / fail data based on, for example, bits a0, a4, and a8 to a first output (output of pass / fail data for each first core), transfer pass / fail data based on bits b2 and b6 to a second output (output of pass / fail data for each second core), transfer pass / fail data resulting from bits c3 and c7 to a third output (e.g., output of pass / fail data for each third core), transfer pass / fail data resulting from bits e0, e4, and e8 to a fourth output (e.g., output of pass / fail data for each fourth core), and transfer pass / fail data resulting from bits g0 and g4 to a fifth output (e.g., output of pass / fail data for each fifth core). Accordingly, the pass / fail data based on bits within the received pattern associated with different functional blocks (cores) of the device under test may be transferred to different outputs of the hardware mapper 520 such that errors associated with different functional blocks (e.g., cores) of the device under test can be separately recorded and / or counted.

[0175] Furthermore, it should be noted that the hardware mapper 520 can inherit, for example, the functions of the error separator / error signal transferrer 332a and / or the function of selectively transferring error signals to the error recorder 350. For example, the pass / fail data 510 can correspond to one or more error signals 322, and the masked pass / fail data 512 can correspond to one or more masked error signals that trigger, for example, the error recording device 350. Furthermore, the pass / fail signal for each core 514 can correspond to, for example, an error signal that is selectively transferred to the result units 336a, 336b, 336n. The mapping scheme 530 may be evaluated, for example, by the control 340, and the mapping data 522 may correspond to, for example, the error separation control signal 342 and / or the error recording control signal 343. For example, the multiplexing function implemented in the hardware mapper 520 may correspond to the multiplexing function implemented in the error separator / error signal transferrer 332a.

[0176] The masking function implemented in the hardware mapper 520 may, for example, correspond to the selective transfer of more than one error signal from the comparator 320 to the error recorder 350. The evaluation of the mapping scheme 530 may be performed, for example, by the control 340, and the mapping scheme 530 may correspond to, for example, a table-based definition of a group of bit positions shown in FIG. 3.

[0177] Furthermore, it should be noted that the mapping defined by the mapping scheme 530 should preferably be periodic after X cycles. However, the mapping function typically depends on the mapping scheme used (in some embodiments, a table-based mapping scheme may be used).

[0178] In conclusion, FIG. 5 shows a block diagram of a mapping mechanism that can be used in any of the embodiments disclosed herein.

[0179] Furthermore, it should be noted that the mapping mechanism of FIG. 5 can be optionally supplemented by any of the features, functions, and details disclosed herein.

[0180] 6. Result mapper per core and mapping scheme according to FIG. 6 Hereinafter, with reference to FIG. 6, the result mapper per core (RPC: Result Per Core, RPCM: Result Per Core Mapper) will be described. Note that the result mapper per core described below can be optionally used in any of the embodiments disclosed in this specification.

[0181] The per-core result mapper (RPC) may be configured to look at comparison results (e.g., evaluate comparison results), but may be configured to look at comparison results at a granularity of, e.g., 4 device cycles (e.g., at a granularity of 4 bits, or, e.g., if the device cycle provides 4 bytes, at a granularity of 4 bytes). However, different lengths of device cycles can be used, and different numbers of device cycles processed by the per-core result mapper can also be used. Also, the per-core result mapper can optionally operate on a single bit.

[0182] Regarding this issue, it should be noted that if the mapping description does not end at the end of the mapper line, it should be rolled out until it fits (in some cases, it may be necessary to roll it out).

[0183] For example, if it is desirable (or necessary) to initially ignore the number of cycles of the test processor, it can be mapped to an unused core. For example, the index of the unused core can be associated with such data (associated with the test processor cycles to be ignored).

[0184] Next, referring to FIG. 6, the mapping scheme and the table-based definition of the mapping scheme will be described. For example, the mapping scheme is used in a so-called "X4 mode" where, for example, 4 device cycles are processed together. However, the mapping scheme can also be used in different modes, even in a mode where individual bits of the received pattern are processed individually.

[0185] For example, the table-based definition 600 (which can be regarded as a mapping description) includes a plurality of rows 610a - 610n. For example, the table-based definition 600 may include a plurality of columns 612a - 612d, and the number of columns may vary between one column and a plurality of columns.

[0186] For example, one column may be associated with each device cycle, although different associations are possible. For example, in a simple embodiment, there may be only one column, and this column may be associated with one group of one or more bits.

[0187] Optionally, a row may have a repeat indicator 616 that indicates, for example, whether the row should be repeated and / or how many times the row should be repeated. Optionally, a row may have a jump indicator (not shown) that defines, for example, whether to jump back to the previous row or jump to the next row.

[0188] In the example shown in FIG. 6, rows 610a, 610b, 610c, 610d (or at least some of the rows) constitute one data field per device cycle, and the data field may have, for example, one functional block index (or core index) per bit associated with each device cycle. For example, in the first four device cycles DC1, DC2, DC3, DC4 (described by the first row 610a), if it is assumed that the bits of the received pattern should not be evaluated, the first row's data field related to the association of the bits of the received pattern to the functional blocks contains an otherwise unused functional block index (e.g., "9"). For example, the functional block indices of all bits of device cycle 1, all bits of device cycle 2, all bits of device cycle 3, and all bits of device cycle 4 may be set to the unused functional block index value of "9". Thereby, for example, the control 340 or the mapping scheme 530 or the hardware mapper 540 may discard (not transfer) the error signal associated with the relevant device cycle.

[0189] For example, the first line 610a may also include a repetition instruction 616 indicating that the definition of the first line 610 should be repeated n times. Accordingly, the received bits of the received pattern of 4×n device cycles are discarded. This may be reasonable, for example, if the device under test requires 4×n device cycles to provide a predictable (deterministic) result after the start of the test. Accordingly, the received patterns associated with these 4×n device cycles do not contribute to error registration, error counting, or error recording (used for recording individual signal information).

[0190] However, from the first line (610b), one or more lines of the mapping 600 define the association between the bits of the received pattern and the (actual) functional blocks (cores) of the device under test.

[0191] For example, the first entry in row 610b can define that the bits of the first device cycle are associated with the first functional block (functional block index "1") of the device under test. The second entry in row 610b may indicate that three bits of the second device cycle are associated with the second functional block (functional block index "2") of the device under test, and further bits of the second device cycle are associated with the third functional block (functional block index "3"). Further, the third entry in row 610b may indicate that the first bit of the third device cycle is associated with the third functional block (functional block index "3") of the device under test, and further bits of the third device cycle are associated with the fourth functional block (functional block index "4") of the device under test. Further, the fourth entry in row 610b indicates that all bits of the fourth device cycle are again associated with the first functional block (functional block index "1") of the device under test.

[0192] Furthermore, the definitions of rows 610c and 610d are similar. However, as is apparent from FIG. 6, the bits associated with different functional blocks of the device under test have a periodicity of, for example, 3 device cycles. Therefore, considering the fact that each of rows 610b to 610d defines an association of bits of 4 device cycles with the functional blocks of the device under test, the periodicity as seen in the total number of rows of the table in FIG. 6 reaches the end of row 610d.

[0193] Therefore, when the mapping of row 610d is completed, it may be indicated, for example, in the entry of row 610d, or the entry of the next row, or another piece of information, that the mapping should jump back to the start of row 610b. Therefore, the associations defined from row 610b to row 610d will be repeated. Therefore, the periodicity of the association of bit positions with respect to the functional blocks can be efficiently considered.

[0194] However, it should be noted that different mechanisms may be used to define the association between one or more blocks of bits and the functional blocks of the device under test. For example, when the length of the block is long, it may be more efficient to define the length of the block of bits using a value (for example, in bit units, byte units, or any length unit that seems appropriate), and it is still advantageous to use repeated or jump indications within such a table or list.

[0195] In conclusion, the concepts described with respect to FIGS. 5 and 6 can be used in any embodiment or the present invention. However, it should be noted that the functionality described with respect to FIGS. 5 and 6 can be optionally supplemented individually and in combination by any of the features, functionality, and details disclosed herein. Also, the concepts described with respect to FIGS. 5 and 6 can be used optionally alone.

[0196] The following briefly describes, by way of example, how the per-core result mapper (RPC, RPCM) functions. In one embodiment, the RPC looks at comparison results, and the granularity is 4 device cycles. If the mapping scheme does not end at the end of the mapper row, it can be rolled out until it fits. For example, the automatic test apparatus operates in X4 mode, and 4 device cycles are processed per step.

[0197] For example, if you want to ignore the number of cycles of the test processor first, it can be mapped to an unused core.

[0198] For example, the mapping starts from row #1.

[0199] At the end of row #3, it can be programmed to jump back to the beginning of row #1. For example, if reset, the point returns to the start of #0.

[0200] In other words, the table-based mechanism may be able to handle jump instructions that jump to another row of the table, for example, jump back to the previous row. Infinite loops may be programmed, which may be stopped, for example, by the test flow control 380. However, instead, in the table-based mechanism, the number of repetitions may be limited.

[0201] However, it should be noted that all of these implementations should be considered optional.

[0202] 7. The method according to FIG. 7 FIG. 7 shows a flowchart of a method 700 for testing a device under test. The method 700 includes receiving 710 from the device under test a pattern including information from a plurality of functional blocks of the device under test. The method further includes separating 720 errors within the received pattern associated with different functional blocks of the device under test during the execution of the test program. Thus, the test result for each functional block can be obtained using the method 700.

[0203] It should be noted that method 700 is based on the same considerations as the test apparatus described above.

[0204] Furthermore, it should be noted that method 700 can be optionally supplemented, individually and in combination, by any of the features, functions, and details disclosed herein.

[0205] 8. Further Aspects and Conclusions in Embodiments The following describes further aspects and details regarding the present invention. Furthermore, conclusions are provided accordingly. However, it should be noted that any of the aspects and embodiments disclosed herein can be optionally combined with other embodiments disclosed herein, both individually and in combination.

[0206] It should be noted that embodiments according to the present invention create results for each core processor.

[0207] To increase the optimal utilization rate of the bandwidth available for scan and functional testing, it should be noted that those involved in EDA software and test designs have begun to work on a method of interleaving test patterns of different cores when transmitting test patterns to a device under test (DUT) via a test interface, instead of sending pure patterns (individual cores) to the target IP core one by one. This is done on both the stimulus side and the device response side of the test.

[0208] It has been recognized that it is advantageous to have special hardware in order to understand (e.g., evaluate) the response of the device and quickly derive the determination of the necessary test flow.

[0209] The following describes an overview of basic considerations.

[0210] To increase the optimal utilization rate of the bandwidth available for scanning and functional testing, those involved in EDA software and test designs have started working on a method of interleaving test patterns of different cores when transmitting them to a device under test (DUT) via a test interface, rather than sending single core patterns (individual cores) one by one to the target IP core.

[0211] In the context of the present invention, it should be noted that a "core" here refers to the basic unit of logical design, which is to be analyzed separately in a test (for example, as a test unit, for example, the granularity of test results). Further, it should be noted that a "core" is an example of a "functional block".

[0212] The level at which this occurs may vary depending on the case. For example, the present invention is directed to the following examples, but is not limited thereto. · As an example, the device under test may be composed of four cores 1, 2, 3, and 4. The division of test data is as follows, and the sequence is repeated 1 to N times with test patterns. N is usually in the range of 10,000... 500,000 (however, other values are also possible). · 32 bits of core 1 · 18 bits of core 2 · 24 bits of core 3 · 48 bits of core 4 · As a second example, the sequence of cores may be longer, and the cores may be interleaved or may not stop. · 10,000 bits of core 1 · 32,000 bits of core 2 · 50,320 bits of core 3 · 200,010 bits of core 4 · These sequence examples are expected to be different for all test pins involved in the test, but as a special case, they may be the same.

[0213] As a conclusion, the received pattern may have, for example, multiple groups of bits from different cores, the received pattern may include, for example, (for example, periodic) repetitions of a sequence, and each sequence may include, for example, multiple groups of one or more bits associated with different functional blocks (cores) of the device under test. However, when the sequence is relatively long, etc., there may be no repetition of the sequence.

[0214] FIG. 4 shows an example of a sequence of bits over time (column, x-axis) for different test pins (rows).

[0215] This is done, for example, on the stimulus side for testing as well as on the response side of the device. In an automated test equipment (ATE), it is desirable to have a result processor that can process such patterns. Such a pattern is hereinafter referred to as a "multi-core pattern".

[0216] Generally, during test execution, a stimulus pattern is sent to the device under test (DUT) (where the stimulus pattern is generated, for example, by the stimulus generator 390 shown in FIG. 3.), and at the same time, the response of the device under test is compared with a response pattern (where the response pattern may be generated, for example, by the reference signal generator 326, and here the response pattern may be specified as a "reference pattern", and here the response pattern may be represented, for example, by the reference signal 328.). For example, both parts constitute a test pattern.

[0217] A comparison unit (for example, comparator 320) checks the level information from the device under test (DUT) against the expected logic state and knows the correct expected state (where the expected state may be defined, for example, by a reference pattern or a reference signal). The response part of the pattern usually defines an expected value of 0 (low, L), an expected value of 1 (high, H), or a mask (ignoring the state, X).

[0218] If a deviation is recognized and the expected pattern is not in the "X" state, this is typically a status flag (e.g., global and / or per-signal) that emphasizes "comparison failed", and detailed error records of a large number of N failed cycles (the states expected in the sequence within the pattern) are recorded along with their addresses (sequence numbers).

[0219] In classical SCAN and functional test flows, it is often determined based on global pass / fail status flags and pass / fail status flags for each test signal. However, since many cores are behind signal pins or may contribute to test result failures, there is no longer a signal that identically maps core / functional block failures. Therefore, this usage model is recognized as failing separately in the case of the multi-core pattern described above. Thus, it has been found that the ATE architecture needs to introduce new elements to handle such test patterns.

[0220] According to one aspect of the present invention, the design of the result processor covers the following functions (e.g., as also defined in the claims).

[0221] Tracking test results per core According to one aspect, there is tracking of test results per core.

[0222] According to one aspect of the present invention, it is desirable for the hardware to support multiple cores, where "core" refers to a result unit. For each of these result units, it is tracked whether a failure occurred during test execution. As an example, the hardware can support 64 result units, and these result units can be assigned to track the results of one or more IP cores within the device under test. This hardware is hereinafter referred to as a "core mapper". This includes mapping the failure locations to the cores of other blocks (or generally referred to herein) described later.

[0223] For example, the error separator / error signal transfer unit 332a can perform some or all of the functions of a so-called "core mapper". However, the result units 336a, 336b, 336n can also inherit some of the functions of a so-called "core mapper".

[0224] The core mapper can, for example, track these test results for each test execution or for each pattern used in this test execution (where, for example, intermediate results may be reset after the result pattern). Thus, for example, the time granularity of one test pattern may be achieved for the test results per core.

[0225] In the analysis per pattern, it may be desirable (or necessary) to reset (re-prepare) the analysis device, freeze and reset the results obtained with the just-completed pattern, and perform fine-grained control to start from a clean state at the start of the next pattern.

[0226] For example, the reset input and / or freeze input of the result units 336a, 336b, 336n can enable resetting of the respective error flag registers and / or the respective error counters, and the time to read the result units 336a, 336b, 336n, and / or the time to reset the result units, and / or the time to "freeze" the result units can be determined, for example, by the control 340 or the test flow control 380 according to requirements.

[0227] According to one aspect, it is also supported that the core mapper is started only once per test execution and all results are processed at the end (for example, after the test execution). For example, the test flow control 380 or the control 340 can control such a mechanism.

[0228] According to one aspect of the present invention, the hardware should support not only short sequences of a plurality of cores but also sequences of long blocks tested in order (see above).

[0229] Results per core According to one aspect, an embodiment of the present invention provides results per core.

[0230] According to one aspect, the hardware can operate in parallel with the recording of normal comparison failures executed by the test apparatus and can record which core saw at least one comparison failure. For example, the hardware can be configured to report the results discussed herein at the granularity of each single test pattern or in combination for a burst (list) of patterns. This can be implemented, for example, in the (sticky) bits of the core summary error map and set at the first failure and can be read out after the test is completed.

[0231] For example, error flag registers 337a, 337b, 337n function as "sticky bit" registers, and the outputs of these error flag registers can together form a "core summary error map". Therefore, by reading the "core summary error map" formed by an individual error flag register or a combination of the outputs of error flag registers, an overview of which functional blocks of the device under test caused at least one error in the received pattern can be quickly obtained.

[0232] For example, according to one aspect of the present invention, this function should exist even if the failure recording (for example, the failure recording executed by the error recording device 350) is limited or not executed at all. This is because information about which core saw a failure is important for the determination of the test flow (which may be performed by the test flow control 380, for example). Such determinations include, for example, additional test executions for further analysis of the failure (including, for example, special diagnostic patterns), or branching to new test content for repair or the like.

[0233] For example, the summary error map should have a function that is reset at the start of a pattern or, if appropriate, should be reset more generally from a test execution controller (e.g., test flow control 380). However, individual resets of, for example, error flag registers 337a, 337b, 337n are also possible.

[0234] Failure log requirements In the following, some failure log requirements that can be arbitrarily applied in some embodiments according to the present invention will be described.

[0235] Originally, since the pattern of the ATE test still originates from an ATPG tool (e.g., an automatic test pattern generator tool), a data logger that generates an STDF file (e.g., a standard test data format file) records failure cycles as before, and an EDA (Electronic Design Automation) tool (electronic design automation tool) has to generate an STDF or other format of logger file for analyzing device failures. Originally, this remains unchanged.

[0236] In practical applications, the depth of the error map that records these errors is limited in order to find a balance between upload time and processing time. In the case of the scenarios listed (or listed here) below, this can result in the effect of having one large or critically failing core that generates a huge amount of comparison files (or comparison failures) in the response pattern, preventing the analysis of the targeted core or function in the sequence behind these large failing cores. As a result, the failure contribution of elements tested later in one pattern may not be visible in the error record.

[0237] However, the user can know that the core has failed from the sticky bit of the core's summary error map.

[0238] In other words, based on the output of the "core summary error map" or error flag registers 337a, 337b, 337n, the user of the test apparatus (or test flow control) can quickly grasp the overview regarding the integrity of the functional blocks of the device under test.

[0239] Masking function for each core Hereinafter, the masking function for each core that can be implemented in the embodiments according to the present invention will be described.

[0240] According to one aspect of the present invention, a central feature is the function of masking comparison failures. Conventionally, this has been done by setting the state character expected for the bit to a mask (often designated by "X"). This is a classical test pattern and may be necessary to ignore the initially failed state until a stable device state is reached, and the initial random internal state is discarded until the first test result of the stimulus pattern becomes available. The same also applies to regions of the test pattern where the results are expected to be unstable (for example, logical analysis patterns and timing analysis patterns).

[0241] According to one aspect, this heritage is extended to multi-core patterns in the sense that it can mask the results attributed to a specific core on a per-core basis. Applications include, but are not limited to, the following. · Mask the (incorrect) results of cores that are critical or have a large failure. This is because when the error map record overflows and the record length is limited for practical reasons (test time, post-processing time), cores with minor failures cannot be recorded. · Focused recording of one or more single cores.

[0242] For example, the masking function for each core can be implemented in several ways. For example, the test apparatus can automatically insert mask information (e.g., "X") into a reference signal / reference pattern at a position associated with a functional block to be masked (e.g., during the execution of a test program). Alternatively, the test apparatus may disable a comparator and / or an error recording device at a bit position associated with a functional block to be masked. For example, the test apparatus can disable the transfer of an error signal from a comparator to an error recording device for a bit (or bit position) associated with a functional block of the device under test to be masked.

[0243] Thus, different hardware implementations can be used to obtain an automatic masking function for each core. In a preferred embodiment, it should be noted that the masking function for each core can be achieved "on the fly", for example, during the execution of a test program, without the need to modify the input signal or input data of a reference signal generator / reference pattern generator (e.g., by introducing masking behind the output of the reference signal generator / reference pattern generator).

[0244] Error counting function for each core Hereinafter, the error counting function for each core will be described. According to one aspect of the present invention, new logic has been designed to enable an accurate count of failures recorded for each timing cycle, not only in total but also for each core set in a core table. For example, failures (e.g., comparison failures) can be recorded for each core (e.g., for each core set in a core table).

[0245] This function is useful (or even necessary) for identifying which cores (test units) show sufficient failures for analysis and which cores are severely malfunctioning. This function is useful (or, in some cases, necessary) to enable the analysis of which cores should be masked (or must be masked) in subsequent executions of the same multi-core pattern when more results for specific cores are required for higher-resolution result data. For example, it enables the determination of which cores the test should focus on, allowing the selection of cores and thus saving the time required for logging the results of cores with many (critical) failures that the user is not interested in.

[0246] In other words, by counting failures at the functional block level, it is possible to distinguish between error-free functional blocks, functional blocks with few errors, and functional blocks with many errors. Therefore, this information indicating whether a functional block shows no errors, only a few errors, or many errors can be used to determine how to continue the test. For example, the test flow control 380 can use this information regarding the number of errors per functional block. For example, different test programs can be selected based on the number of errors associated with different functional blocks, thereby concentrating the test on blocks with many defects if desired, or concentrating the test on functional blocks that show no errors or only a few errors in the previous stage of the test. As a result, efficiency can be improved.

[0247] Automatic masking function for each core The following describes the per-core masking function that can be used in accordance with an aspect of the present invention. This function combines an accurate error count and a masking function. Also, a comparison with a limit value of the error count is added and used (or sometimes required). When the limit is reached for one of the cores (or functional blocks) within a running test, for example, the mask can be reprogrammed for comparison of subsequent failures for this core in order to mask subsequent failures of this core. This enables recording a limited number of failures for all cores, regardless of whether it is the beginning or the end of the test execution, and avoiding flooding and jamming.

[0248] For example, when the error counter associated with a certain core reaches a threshold or more, the control unit 340 can invalidate the recording of individual failure information associated with a certain core with a large failure by the error recording device 350. As a result, the amount of individual failure information recorded for each functional block of the device under test can be limited, and thus, even when there is one or more functional blocks or cores with large failures, it is possible to record individual failure information for many different functional blocks or cores (or all functional blocks). As a result, an efficient test becomes possible.

[0249] However, it should be noted that the per-core masking function, per-core error counting function, and per-core automatic masking function described in this specification should be considered optional and not necessarily implement all of these functions within a specific embodiment of the present invention.

[0250] Conclusion The following briefly summarizes aspects of the present invention.

[0251] Due to the capabilities described herein, in some embodiments, the following results are available, so that, for example, without re-execution, most or all of the required test results are available in one execution of the test pattern. · Pass / fail information for each core (e.g., for flow decision) · Absolute number of failures per core → Determination of critical failures and, if re - execution of a specific core is necessary (for flow determination) · There is a limit to the number of failures recorded per core (for all cores, etc.) → Sufficient for failure data logging for post - processing with EDA software · In the first failure test cycle, standard information for analysis purposes can be obtained per core (e.g., guaranteed) · In most cases, re - execution is only necessary when re - executing a single core for the purpose of recording a large number of comparison failures. · Disable a specific core for testing. In some cases, two functions need to be combined: · Function to disable the test of an individual core in the test design circuit of the DUT (outside the scope of the present invention). · Function to mask the comparison failures of the disabled core so that a large number of (random) failures are generated in the comparison with the expected multi - core pattern. (Covered by an aspect of the present invention).

[0252] According to one aspect of the present invention, this new hardware function eliminates the need for complex post - processing and filtering of comparison results by ATE software, and dramatically reduces the amount of data to be recorded and post - processed. Also, special single - core patterns are eliminated, and the test time consumed by re - execution is avoided, so the required setup data size is also reduced.

[0253] Furthermore, it should be noted that the embodiments according to the present invention can be used in digital cards, such as digital channel modules for automatic test equipment.

[0254] In particular, the embodiments according to the present invention can be used in V93000 automatic test equipment, for example, to improve T4 scan capabilities and handle multi - core patterns.

[0255] 9. Implementation method Although several aspects have been described in the context of apparatus, it will be apparent that these aspects also represent corresponding descriptions of methods, and that blocks or apparatus correspond to method steps or features of method steps. Similarly, aspects described in the context of method steps represent corresponding descriptions of blocks or items, or features of corresponding apparatus. Some or all of the method steps may be performed by (or using) hardware devices such as, for example, a microprocessor, a programmable computer, or an electronic circuit. In some embodiments, one or more of the most important method steps may be performed by such a device.

[0256] Depending on specific implementation requirements, embodiments of the invention can be implemented in hardware or software. The implementation can be a digital storage medium, such as a floppy disk, DVD, Blu-ray, CD, ROM, PROM, EPROM, EEPROM, or FLASH memory, having electronically readable control signals stored thereon and cooperating (or capable of cooperating) with a programmable computer system so that respective methods are executed. Thus, the digital storage medium may be computer-readable.

[0257] Some embodiments according to the invention comprise a data carrier having electronically readable control signals, which can cooperate with a programmable computer system so that one of the methods described herein is executed.

[0258] Generally, embodiments of the invention can be implemented as a computer program product having program code, the program code being operative to perform one of the methods when the computer program product is executed on a computer. The program code can be stored, for example, on a machine-readable carrier.

[0259] Other embodiments include a computer program for performing one of the methods described herein, stored on a machine-readable carrier.

[0260] In other words, an embodiment of the method of the present invention is thus a computer program having program code for executing one of the methods described herein when the computer program is executed on a computer.

[0261] Thus, a further embodiment of the method of the present invention is a data carrier (or digital storage medium, or computer-readable medium) having recorded thereon a computer program for executing one of the methods described herein. The data carrier, digital storage medium or recording medium is typically tangible and / or non-transitory.

[0262] Thus, a further embodiment of the method of the present invention is a sequence of a data stream or signal representing a computer program for executing one of the methods described herein. The sequence of the data stream or signal may be configured to be transferred via a data communication connection such as the Internet, for example.

[0263] A further embodiment comprises processing means, such as a computer or a programmable logic device, configured to execute or adapted to execute one of the methods described herein.

[0264] A further embodiment comprises a computer having installed thereon a computer program for executing one of the methods described herein.

[0265] A further embodiment according to the present invention comprises an apparatus or system configured to transfer (for example, electronically or optically) a computer program for executing one of the methods described herein to a receiver. The receiver may be, for example, a computer, a mobile device, a memory device, etc. The apparatus or system may comprise, for example, a file server for transferring the computer program to the receiver.

[0266] In some embodiments, a programmable logic device (e.g., a field programmable gate array) can be used to execute some or all of the functions of the methods described herein. In some embodiments, the field programmable gate array may cooperate with a microprocessor to execute one of the methods described herein. Generally, the methods are preferably executed by any hardware device.

[0267] The devices described herein may be implemented using a hardware device, or using a computer, or using a combination of a hardware device and a computer.

[0268] The devices described herein, or any component of the devices described herein, may be implemented at least partially in hardware and / or software.

[0269] The methods described herein may be executed using a hardware device, or using a computer, or using a combination of a hardware device and a computer.

[0270] The methods described herein, or any component of the devices described herein, may be executed at least partially by hardware and / or software.

[0271] The above-described embodiments are merely illustrative of the principles of the present invention. It is understood that modifications and variations of the arrangements and details described herein will be apparent to those skilled in the art. Accordingly, it is intended to be limited only by the following claims and not by the specific details presented in the description and explanation of the embodiments herein.

Claims

1. A test apparatus for testing a device under test, wherein the test apparatus is configured to receive from the device under test a pattern including information from a plurality of functional blocks of the device under test, and the test apparatus is configured to separate errors in the received pattern associated with different functional blocks of the device under test during execution of a test program. Test apparatus.

2. The test apparatus according to claim 1, wherein the test apparatus is configured to separate on-the-fly the errors in the received pattern associated with different functional blocks of the device under test. The test apparatus according to claim 1.

3. The test apparatus is configured to separate errors in the received pattern associated with different functional blocks of the device under test in real time and / or time-synchronized with the data rate at which the received pattern is received from the device under test and / or time-synchronized with the data clock at which the received pattern is received from the device under test. The test apparatus according to claim 1 or 2.

4. The test apparatus includes dedicated hardware configured to separate errors in the received pattern associated with different functional blocks of the device under test. The test apparatus according to any one of claims 1 to 3.

5. The test apparatus includes dedicated hardware configured to selectively transfer to a result unit associated with a specific functional block of the device under test an error signal indicating a deviation from an expected bit value defined by an expected pattern of bit values of bits of the received pattern associated with the specific functional block of the device under test. The test apparatus according to any one of claims 1 to 4.

6. The test apparatus is configured to: optionally disable comparison between one or more bits of the received pattern associated with a specific functional block of the device under test and one or more corresponding bits of an expected pattern, and / or optionally disable transfer of the result of comparison between one or more bits of the received pattern associated with a specific functional block of the device under test and one or more corresponding bits of the expected pattern. Dedicated hardware configured to selectively disable the processing of the result of a comparison between one or more bits of the received pattern associated with a particular functional block of the device under test and one or more corresponding bits of the expected pattern The test apparatus according to any one of claims 1 to 5 Claim 7 The test apparatus includes dedicated hardware configured to identify different blocks of one or more bits of the received pattern associated with different functional blocks of the device under test in order to isolate errors within the received pattern associated with different functional blocks of the device under test The test apparatus according to any one of claims 1 to 6 Claim 8 The test apparatus includes dedicated hardware configured to identify different blocks of one or more bits of the received pattern using a table that defines the length of the blocks of one or more bits of the received pattern associated with different functional blocks of the device under test The test apparatus according to any one of claims 1 to 7 Claim 9 The test apparatus includes a reference pattern generator configured to generate a time signal representing an expected pattern The test apparatus includes a comparator circuit configured to compare a time signal representing the received pattern with a time signal representing the expected pattern The comparator is configured to provide an error signal in response to a shift between a bit of the expected pattern and a bit of the received pattern The test apparatus according to any one of claims 1 to 8 Claim 10 The test apparatus is configured to individually track test results of different functional blocks of the device under test The test apparatus according to any one of claims 1 to 9 Claim 11 The test apparatus is configured to individually track test results of different functional blocks of the device under test derived based on the received pattern for each test pattern or each test execution The test apparatus according to claim 10 Claim 12 The apparatus includes a plurality of result units associated with different functional blocks of the device under test The test apparatus is configured to selectively reset one or more of the result units and / or The test device is configured to selectively freeze one or more of the result units. The test device according to claim 10 or 11.

13. The test device is configured to compare a received pattern with an expected pattern. The device is configured to individually record comparison failures associated with different blocks of one or more bits of the received pattern and / or configured to individually record comparison failures associated with different functional blocks of the device under test. The test device according to any one of claims 1 to 12.

14. The test device uses a mapping scheme that defines an association between different result units that record comparison failures and bits of the received pattern and / or uses a mapping scheme that defines an association between different functional blocks of the device under test and bits of the received pattern, configured to separately record comparison failures associated with different functional blocks of the device under test. The test device according to claim 13.

15. The test device includes a plurality of individual result units configured to track test results associated with different functional blocks of the device under test. The test device according to any one of claims 1 to 14.

16. The test device includes a plurality of individual error flag registers associated with different functional blocks of the device under test. The test device according to any one of claims 1 to 15.

17. The test device includes a plurality of individual error flag registers configured to be set in response to comparison errors between bits of the received pattern and corresponding bits of the expected pattern that occur in different blocks of one or more bits of the received pattern. The test device according to any one of claims 1 to 16.

18. The test device includes a plurality of individual error counters associated with different functional blocks of the device under test. The test device according to any one of claims 1 to 17.

19. The test device includes a plurality of individual error counters configured to be incremented in response to comparison errors between bits of the received pattern and corresponding bits of the expected pattern that occur in different blocks of one or more bits of the received pattern. The test apparatus according to any one of claims 1 to 18.

20. The test apparatus is configured to selectively set one error flag from among a plurality of individual error flags in response to detection of a deviation between a bit of the received pattern and a bit of the expected pattern and based on an association rule. The test apparatus according to any one of claims 1 to 19.

21. The test apparatus is configured to set an individual error flag associated with a given functional block of the device under test in response to detection that a bit of the received pattern associated with the given functional block of the device under test deviates from the expected pattern, for individually recording comparison failures associated with different functional blocks of the device under test. The test apparatus according to any one of claims 1 to 20.

22. The test apparatus is configured to selectively increment one error counter among a plurality of individual error counters in response to detection of a deviation between a bit of the received pattern and a bit of the expected pattern and based on an association rule. The test apparatus according to any one of claims 1 to 21.

23. The test apparatus is configured to increment an individual error counter associated with a given functional block of the device under test in response to detection that a bit of the received pattern associated with the given functional block of the device under test deviates from the expected pattern, for separately counting comparison failures associated with different functional blocks of the device under test. The test apparatus according to any one of claims 1 to 22.

24. The apparatus is configured to record individual failure information indicating a failure position of each of a plurality of comparison failures. The apparatus is configured to obtain summary failure information separately describing errors associated with different functional blocks of the device under test in a summarized form. The test apparatus according to any one of claims 1 to 23.

25. The apparatus is configured to record failure cycles in a time - distinguishable manner in addition to error flags per functional block and / or error counts per functional block. The test apparatus according to any one of claims 1 to 24.

26. The test apparatus is configured to continue updating the summary failure information even when the memory for recording the individual failure information is depleted. The test apparatus according to claim 24 or 25. **Claim 27** The test apparatus is configured to selectively mask the recording of individual failure information for bits of the received pattern associated with one or more functional blocks of the device under test, and / or The test apparatus is configured to selectively enable the recording of individual failure information for bits of the received pattern associated with one or more functional blocks of the device under test. The test apparatus according to any one of claims 24 to 26. **Claim 28** The test apparatus is configured to determine, using a table that defines the length of a block of one or more bits of the received pattern associated with different functional blocks of the device under test, which bits of the received pattern should have the recording of individual failure information omitted. The test apparatus according to claim 27. **Claim 29** The test apparatus includes dedicated hardware configured to identify the bits of the received pattern for which the recording of individual failure information should be omitted. The test apparatus according to claim 27 or 28. **Claim 30** In response to detecting that an individual error counter that selectively counts comparison errors for bits associated with a specific functional block has reached a predetermined maximum value, the test apparatus is configured to activate masking of the recording of individual failure information for the bits of the received pattern associated with the specific functional block of the device under test. The test apparatus according to any one of claims 27 to 29. **Claim 31** The test apparatus is configured to identify different blocks of one or more bits of the received pattern associated with different functional blocks of the device under test, using a table that defines the length of a block of one or more bits of the received pattern associated with different functional blocks of the device under test. The test apparatus according to any one of claims 1 to 30. **Claim 32** The test apparatus is configured to identify a periodic sequence of blocks of one or more bits of the received pattern associated with different functional blocks of the device under test, using the table. The test apparatus according to claim 31. **Claim 33** The test device is configured to adapt the test flow based on information regarding errors in the received pattern associated with a given functional block of the device under test. The test device according to any one of claims 1 to 32. **Claim 34** The test device is configured to adapt the test flow in response to a determination that the number of errors in the received pattern associated with a given functional block of the device under test has reached or exceeded a predetermined maximum number. The test device according to claim 33. **Claim 35** The test device is configured to enable or disable masking of the recording of individual failure information for bits of the received pattern associated with a given functional block of the device under test, and to repeat the test in response to a determination that the number of errors in the received pattern associated with a given functional block of the device under test has reached or exceeded a predetermined maximum number. The test device according to claim 34. **Claim 36** A test device for testing a device under test, wherein the test device is configured to receive a pattern including a sequence of bits from the device under test, and the test device is configured to separate errors in the received pattern associated with different blocks of one or more bits during execution of a test program. Test device. **Claim 37** A method for testing a device under test, the method including receiving from the device under test a pattern including information from a plurality of functional blocks of the device under test, and the method including separating errors in the received pattern associated with different functional blocks of the device under test during execution of a test program. Method. **Claim 38** A computer program which, when executed on a computer, implements the method according to claim 37.

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