Channel Routing for Simultaneous Switching Output

Abstract

The data processor accesses a memory having a first virtual channel and a second virtual channel. The data processor includes at least one memory access agent, a memory controller, and a data fabric. The at least one memory access agent generates a generated memory access request including a first memory access request to access the memory. The memory controller provides a memory command to the memory in response to the first memory access request. The data fabric routes the first memory access request to a first downstream port in response to the corresponding first memory request accessing the first virtual channel, and routes it to a second downstream port in response to the corresponding first memory request accessing the second virtual channel. The memory controller has a first and a second upstream port respectively coupled to the first and second downstream ports of the data fabric, and a downstream port coupled to the memory.

Description

Background Art

[0001] Modern dynamic random-access memory (DRAM) provides high memory bandwidth by increasing the speed of data transmission on a bus that connects the DRAM to one or more data processors such as a graphics processing unit (GPU) and a central processing unit (CPU). DRAM is typically inexpensive and high-density, thereby enabling the integration of large amounts of DRAM per device. Most DRAM chips sold today are compatible with various double data rate (DDR) DRAM standards promoted by the Joint Electron Devices Engineering Council (JEDEC). Typically, several DDR DRAM chips are combined on a single printed circuit board to form a memory module that is not only relatively fast but also provides scalability.

[0002] One type of DDR DRAM known as Graphics Double Data Rate (GDDR) DRAM has pushed the boundaries of data transmission rates to meet the high data bandwidth requirements of graphics applications. A new GDDR standard, known as GDDR, version 7 (GDDR7), is being developed that supports significantly higher data rates than the existing version 6 (GDDR6) DRAM. For example, instead of the conventional binary data transmission used in existing versions of DDR and graphics DDR standards, GDDR7 defines multi-level data transmission and reception modes in addition to the conventional two-level (NRZ) system. For example, when complete, GDDR7 may include a four-level pulse amplitude modulation (PAM4) scheme that enables the transmission and reception of not just two but two binary bits per clock transition. The use of PAM4 signaling doubles the data transmission bandwidth for a given clock speed. With support for 4x8 channels and PAM4 signaling, GDDR7 can achieve high data rates of up to 160 gigabits per second (GB / s). However, due to crosstalk and interference caused by high-density package routing used in modern ball grid array (BGA) packages, transmitting at high data rates makes it very difficult to accurately receive signals.

Brief Description of the Drawings

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[0004] In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word "coupled" and its related verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted, any description of direct connection also means alternative embodiments that use suitable forms of indirect electrical connection.

[0005] The integrated circuit has a double data rate (DDR) memory controller and includes a semiconductor die. The semiconductor die includes a physical interface circuit and a plurality of signal pads. The physical interface circuit is coupled to the DDR memory controller, conducts a plurality of data signals, and generates a plurality of command and address signals. The plurality of signal pads are disposed on the surface of the semiconductor die, and in a plan view of the surface, the plurality of signal pads include a first subset of data signal pads in the upper left portion, a second subset of data signal pads in the upper right portion, a third subset of command and address signal pads in the lower left portion, and a fourth subset of command and address signal pads in the lower right portion.

[0006] The integrated circuit includes a semiconductor die and a plurality of signal pads. The semiconductor die includes a physical interface circuit that generates signals of a first signal group and a second signal group, and a plurality of signal pads disposed on the surface of the semiconductor die. The plurality of signal pads include, in a plan view, a first subset of data signal pads that conduct a first portion of the signals of the first signal group in the upper left portion, a second subset of data signal pads that conduct a second portion of the signals of the first signal group in the upper right portion, a third subset of command and address signal pads that conduct a first portion of the signals of the second signal group in the lower left portion, and a fourth subset of command and address signal pads that conduct a second portion of the signals of the second signal group in the lower right portion.

[0007] A method of manufacturing an integrated circuit having a DDR memory controller and a first DDR memory physical interface circuit on a semiconductor die is provided. The method includes separating die signal pads disposed on the surface of the semiconductor die into a first group of signal pads conducting data signals and a second group of signal pads conducting command and address signals. A first subset of the data signal pads is disposed in the upper left portion in a plan view of the surface. A second subset of the data signal pads is disposed in the upper right portion of the plan view. A third subset of the command and address signal pads is disposed in the lower left portion in the plan view. A fourth subset of the command and address signal pads is in the lower right portion of the plan view. Signals of the first subset of the data signal pads are routed within a first routing layer of the integrated circuit package in a cross section. Signals of the second subset of the data signal pads are routed within a second routing layer of the integrated circuit package in a cross section.

[0008] FIG. 1 is a block diagram of a data processing system 100 having a simultaneous switching output according to some embodiments. The data processing system 100 generally includes a data processor in the form of a graphics processing unit (GPU) 110, a host central processing unit (CPU) 120, a double data rate (DDR) memory 130, and a graphics DDR (GDDR) memory 140.

[0009] The GPU 110 is a discrete graphics processor having very high performance for optimized graphics processing, rendering, and display, but requires a high memory bandwidth to execute these tasks. The GPU 110 generally includes a set of command processors 111, graphics single instruction, multiple data (SIMD) cores 112, a set of caches 113, a memory controller 114, a DDR physical interface circuit (DDR PHY) 117, and a GDDR PHY 118.

[0010] The command processor 111 is used to interpret high-level graphics instructions such as those specified in the OpenGL programming language. The command processor 111 has a bidirectional connection to the memory controller 114 for receiving high-level graphics instructions such as OpenGL instructions, a bidirectional connection to the cache 113, and a bidirectional connection to the graphics SIMD core 112. In response to receiving a high-level instruction, the command processor uses the cache 113 as a temporary storage device to issue low-level instructions for rendering, geometric processing, shading, and rasterization of data such as frame data. In response to a graphics instruction, the graphics SIMD core 112 executes low-level instructions on a large data set in a massively parallel manner. The command processor 111 and the cache 113 are used for temporary storage of input data and output (e.g., rendered and rasterized) data. Also, the cache 113 has a bidirectional connection to the graphics SIMD core 112 and a bidirectional connection to the memory controller 114.

[0011] The memory controller 114 has a first upstream port connected to the command processor 111, a second upstream port connected to the cache 113, a first downstream bidirectional port to the DDR PHY 117, and a second downstream bidirectional port to the GDDR PHY 118. As used herein, an "upstream" port is on the side of the circuit that faces the data processor and away from the memory, and a "downstream" port is in the direction away from the data processor and towards the memory. The memory controller 114 controls the timing and sequencing of data transfers between the DDR memory 130 and the GDDR memory 140. The DDR and GDDR memories have asymmetric access, i.e., access to an open page in the memory is faster than access to a closed page. The memory controller 114 stores memory access commands and processes them out of order for efficiency, e.g., by prioritizing access to open pages while complying with certain service quality goals.

[0012] DDR PHY 117 has an upstream port connected to the first downstream port of the memory controller 114 and a downstream port bidirectionally connected to the DDR memory 130. DDR PHY 117 meets all the specified timing parameters of the version of the DDR memory 130, such as DDR version 5 (DDR5), and executes a timing calibration operation under the instruction of the memory controller 114. Similarly, GDDR PHY 118 has an upstream port connected to the second downstream port of the memory controller 114 and a downstream port bidirectionally connected to the GDDR memory 140. GDDR PHY 118 meets all the specified timing parameters of the version of the GDDR memory 140, such as GDDR version 7 (DDR7), and executes a timing calibration operation under the instruction of the memory controller 114.

[0013] The GPU 110 uses the calibration controller 115 to capture the read data within the GPU 110 by finding the center of each "data eye" and establish the initial timing parameters for the delay time when sending the write data that can be correctly captured by the GDDR memory 140. The GPU 110 uses the compensation circuit 116 to compensate for the voltage drift and temperature drift during operation and avoid the need for periodic recalibration during operation.

[0014] Known layout patterns were sufficient to support communication with dual-channel GDDR6 DRAM at existing memory clock speeds. However, GDDR7 doubles the number of signal channels, each having fewer data signals, and introduces multi-level signaling, such as PAM4. The inventors have discovered that due to these changes, inter-channel interference and crosstalk, as well as intra-channel signal interference and crosstalk for simultaneously switched outputs of the same channel, may cause data eye closure and frequent data errors using these known layout techniques.

[0015] Figure 2 is a perspective view of an integrated circuit GPU 200 suitable for use in the data processing system 100 of FIG. 1 according to some embodiments. The integrated circuit GPU 200 includes a GPU die 210 and an integrated circuit package 220. The GPU die 210 is a semiconductor integrated circuit chip having a back surface facing upward in FIG. 2 and a front surface or active surface facing downward in FIG. 2. The GPU die 210 includes a set of die pads suitable for bonding to corresponding terminals on the integrated circuit package 220. The integrated circuit package 220 includes a top surface for connecting to the GPU die 210 and a bottom surface having a plurality of solder balls in a ball grid array (BGA) structure. The BGA package uses larger solder balls for final bonding to corresponding metal terminals on the top surface of a printed circuit board (PCB) including other components such as the GDDR memory 140 shown in FIG. 1. The GPU die pads are smaller and more compact, and thus are more susceptible to the effects of signal interference from adjacent pads. This interference can cause significant cross-coupling of signals and, at the same time, data errors in the switched outputs.

[0016] FIG. 3 is a cross section 300 of the integrated circuit GPU 200 of FIG. 2. The cross section 300 includes a GPU die 310 and an integrated circuit package 320 corresponding to the GPU die 210 and the integrated circuit package 220 of FIG. 2. The GPU die 310 is connected to the integrated circuit package 320 via a series of small solder bumps 312 (or by using other suitable metal interconnect technologies), which are not to scale and, in various embodiments, are significantly smaller than shown in FIG. 2. The small solder bumps 312 bond to and make electrical connection with corresponding die pads and an associated set of solder or other metal connections (not shown) on the top surface of the integrated circuit package 320. The integrated circuit package 320 is a ceramic package having an integral multi-layer signal redistribution structure for repositioning and fan-out of the die pads to corresponding IC package pads and solder balls having larger dimensions.

[0017] As is apparent from cross section 300, the closest routing of the simultaneous switching outputs of the GDDR die 310 occurs at or near the die surface to the multi-layer PCB connection, from where the signals ultimately fan out.

[0018] FIG. 4 is a plan view of a floorplan of a graphics processing unit (GPU) die 400 having two GDDR memory physical interface (PHY) circuits known in the prior art. The GPU die 400 includes a first PHY circuit region 410 and a second PHY circuit region 420. As shown, the PHYs are included in an area that is small compared to the total area of the GPU die 400. They are located near the edges of the GPU die 400 to enable signals to be quickly and properly fanned out to a plurality of package solder balls that are routed on the PCB through the package PCB layers to adjacent memory dies on the PCB. As is known in the conventional floorplan, the memory PHY circuits have a very high aspect ratio with the horizontal direction as the width and the vertical direction as the length since the die is oriented as in FIG. 4. This nearly horizontal layout helps fan out signals to the periphery of the package. However, the inventors have discovered that this characteristic causes significant inter-conductor signal interference in SSO and potentially causes eye closure in ultra-high-speed memories such as high-speed GDDR memories, particularly GDDR memories using multi-level signaling such as PAM-4.

[0019] FIG. 5 is a plan view of the bottom of an integrated circuit GPU die 500 having a GDDR physical memory interface circuit known in the prior art. The memory PHY includes a first die pad region 510 labeled "DQ" for data input / output signals of a first channel, a second die pad region 520 similarly labeled "DQ" for data input / output signals of a second channel, and a third die pad region 530 labeled "CA" for commands, addresses, and control signals for both data channels. The portion of the integrated circuit GPU die 500 shown in FIG. 5 has the same extent as the circuit region below for the memory PHY (as shown in FIG. 5). Each data channel includes 16 data input / output (DQ) signals, 2 data bus inversion control signals, 2 error detection code (EDC) signals, and 2 sets of true and complement write clock signals, for a total of 24 active signals that are distributed along with power and ground signals. The CA signals include active signals for each of the two channels, and each channel includes 10 command and address (C / A) signals, 1 set of true and complement command clock signals for a total of 2 signals, 1 clock enable signal, 1 command bus inversion signal for a total of 14 CA signals for each channel, and a total of 28 active signals for both channels with power and ground signals interspersed. The DQ and CA signal routings approximately correspond to the physical layout of a GDDR, version 6 (GDDR6) ball grid array BGA die layout, thus reducing the number of crossovers and the total number of layers required for PCB design. In the example shown, the signal routing can be achieved in three layers of a BGA package having one signal layer, one power plane, and one ground plane, or in five layers of a BGA package having three signal layers, one power plane, and one ground plane.

[0020] Note that the aspect ratio of the PHY layout is high, about 8.7:1 in this example. This aspect ratio allows many signals to fan out in parallel to the balls distributed on the lower side of the package within the BGA package, but it also creates opportunities for signal interference and data eye closure for newer and faster GDDR memories, especially GDDR memories that support multi-level signaling such as PAM-3 or PAM-4.

[0021] FIG. 6 is a partial plan view of a single package routing layer 600 of the integrated circuit package of FIG. 5 known in the prior art. The single package routing layer 600 provides a one-layer breakout of the DQ and CA signal groups. The single package routing layer 600 includes a first routing region 610 labeled "DQ" for the data input / output signals of the first channel, a second routing region 620 similarly labeled "DQ" for the data input / output signals of the second channel, and a third routing region 630 labeled "CA" for the command, address, and control signals for both data channels. As can be seen from the figure, the single package routing layer 600 has many parallel signal lines routed in close proximity to each other. Signal interference was acceptable for single-level (NRZ) signaling in GDDR6 memory at a command clock frequency of about 1.5 gigahertz (GHz) and a data clock frequency of about 3.0 GHz, but as the overall data bandwidth increases, such as by implementing PAM-3 or PAM-4 signaling at existing GDDR6 clock frequencies, increasing the command and data clock frequencies, or both, signal interference can cause data eye closure or frequent data errors.

[0022] FIG. 7 is a plan view of two package routing layers 700 of the integrated circuit package of FIG. 5 known in the prior art. The package routing layer 700 includes a first package routing layer 710 in the third or L3 layer labeled "L3 / DQ" and a second package routing layer 720 in the fifth or L5 layer labeled "L5 / CA". The first package routing layer 710 includes a first DQ signal region 711 for the DQ group pins of the first channel and a second DQ signal region 712 for the DQ group pins of the second channel. The second package routing layer 720 includes a CA signal region 721 for the CA group pins of the first and second channels. As can be visually understood from the package routing layers 710 and 720, adjacent signal pins continue to have adjacent routing because signals from the dense signal grouping, particularly the CA signal, break out at the points where they are adjacent. These breakouts may have been acceptable for GDDR6 DRAM, but the inventors have found that these breakouts are insufficient because the clock speed and data transfer speed are doubled for GDDR7 DRAM.

[0023] FIG. 8 is a plan view of a floorplan of a GPU die 800 having two GDDR physical memory interface circuits according to some embodiments. The GPU die 800 includes a first PHY circuit region 810 and a second PHY circuit region 820. As shown, the PHYs are included in an area that is small compared to the total area of the GPU die 800 and occupy approximately the same percentage of the total area of the die floorplan 800 as the PHYs on the die floorplan of the GPU die 400 of FIG. 4. Each of the PHY circuit regions 810 and 820 has two channels of a 4-channel × 8 GDDR7 architecture together with a common CA region. They are still placed near the edge of the GPU die 800 to enable signals to be quickly and properly fanned out through the package PCB layer to a plurality of package solder balls that will be routed to adjacent memory dies on the PCB, but their aspect ratio is significantly reduced compared to the aspect ratio of the PHY circuit regions 410 and 420 of FIG. 4. In particular, the aspect ratio of each of the PHY circuit regions 810 and 820 is approximately equal to 2.35:1. In addition to the new layer routing, this lower aspect ratio significantly reduces the inter-conductor signal interference in SSO and enables the SSO to operate with high-speed and multi-level signaling, such as PAM-4 proposed for GDDR7.

[0024] FIG. 9 is a plan view of a floorplan 900 of a die pad of the GPU die 800 of FIG. 8 according to some embodiments. The floorplan 900 includes a GDDR memory PHY region 910 that includes an array of signal pads 920. The array of signal pads 920 includes a set of DQ pads 930 and a set of CA pads 940 arranged as a first subset of DQ signal pads 931 in the upper left portion of the floorplan 900, a second subset of DQ pads 932 in the upper right portion, a third subset of CA signal pads 941 in the lower left portion, and a fourth subset of CA signal pads 942 in the lower right portion, as the floorplan 900 is oriented in FIG. 9. Each also includes scattered power and ground signal pads. By rearranging the underlying circuit blocks, the inventors were able to reduce the aspect ratio of the GDDR PHY and utilize a greater signal separation to reduce signal interference during signal breakout in the package routing layer.

[0025] FIG. 10 is a partial plan view and partial cross-sectional view of an integrated circuit package 1000 showing the distribution of the die pad of the GPU die of FIG. 9 to the package layer according to some embodiments. The integrated circuit package 1000 shows two PHYs corresponding to the PHY circuit regions 810 and 820 of FIG. 8, an L3 layer 1010, an L5 layer 1020, and an L7 layer 1030. For the integrated circuit package 1000, the DQ signals are routed from the die surface layer to the L5 layer 1020 together with the WCK signal for channel 0, whereas the DQ signal and the WCK signal for channel 1 are routed from the die surface layer to the L3 layer 1010, indicating that the L3 layer and the L5 layer are separated by a power plane or a ground plane. Similarly, the DQ signals are routed from the die surface layer to the L5 layer 1020 together with the WCK signal for channel 2, whereas the DQ signals together with their respective WCK signals for channel 3 are routed from the die surface layer to the L3 layer 1010. The CA and RCK signals for channels 0 to 3 are routed from the die surface layer to the L7 layer 1030, where the CA and RCK signals for channel 0 are horizontally separated from the CA signal for channel 1 by the DQ and WCK signals for channel 0, the CA signal for channel 1 is horizontally separated from the CA and RCK signals for channel 2 by the DQ and WCK signals for channel 1 and the DQ and WCK signals for channel 2, and the CA and RCK signals for channel 2 are horizontally separated from the CA signal for channel 3 by the DQ and WCK signals for channel 3. The L5 layer and the L7 layer are separated by a power plane or a ground plane. It should be noted that the PHY circuit regions 810 and 820 have the same layout but are oriented in a mirror image form along the vertical symmetry line therebetween.

[0026] FIG. 11 shows a set 1100 of plan views showing the die pad to package layer correspondence of the GPU dies of FIGS. 8-10, according to some embodiments. Set 1100 includes an L3 layer 1110 that routes the DQ and WCK signals for channels 1 and 3, an L5 layer 1120 that routes the DQ and WCK signals for channels 0 and 2, and an L7 layer that routes the CA and RCK signals for both channels. As shown previously, the L3 layer 1010 and the L5 layer 1020 are separated by an L4 layer (not shown) having a power or ground plane, and the L5 layer 1020 and the L7 layer 1030 are separated by an L6 layer (not shown) having a power or ground plane. Set 1100 shows that by staggering the channels on separate package layers, the DQ signals for each channel are laterally separated from each other by a significant VSS region, providing good inter-channel separation. Further, by routing the DQ signals and the CA signals using three package layers, the spacing between signals within each signal group can be increased.

[0027] The PHY circuits, GPUs, SOCs, or portions thereof described in this specification can embody one or more integrated circuits, each of which can be described or represented by a computer-accessible data structure in the form of a database or other data structure that can be read by a program and used directly or indirectly to manufacture the integrated circuit. For example, the data structure may be a behavioral-level description or a register-transfer level (RTL) description of hardware functionality in a high-level design language (HDL) such as Verilog or VHDL. The description can be read by a synthesis tool that can synthesize the description to generate a netlist that includes a list of gates from a synthesis library. The netlist includes a set of gates that also represent the functionality of the hardware including the integrated circuit. The netlist may then be placed and routed to generate a dataset that describes the geometric shapes to be applied to the mask. The mask may then be used in various semiconductor manufacturing processes to manufacture the integrated circuit. Alternatively, the database on a computer-accessible storage medium may be, if desired, a netlist (with or without a synthesis library) or a dataset, or Graphic Data System (GDS) II data.

[0028] Although specific embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. For example, the specific package routing layers used can be changed in different embodiments. Further, although the techniques described herein have been shown in the context of GDDR7 DRAM, it should be apparent that the corresponding techniques can be applied to other or future GDDR or DDR DRAMs, or other types of integrated circuits, that involve high-speed signal transmission and / or multilevel signaling to improve signal integrity.

[0029] Accordingly, the appended claims are intended to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.

Claims

1. It is an integrated circuit, Equipped with a semiconductor die, The aforementioned semiconductor die is A physical interface circuit that generates signals for a first signal group and a second signal group, comprising a physical interface circuit having a physical interface circuit region on the surface of the semiconductor die, The semiconductor die comprises a plurality of signal pads arranged on the surface within the physical interface circuit region of the semiconductor die, In the plan view, the aforementioned plurality of signal pads are, In the upper left portion, a first subset of data signal pads that conduct the first portion of the signals of the first signal group, In the upper right portion, a second subset of data signal pads that conduct the second portion of the signals of the first signal group, In the lower left portion, a third subset of command and address signal pads that conduct the first portion of the signals of the second signal group, The lower right portion includes a fourth subset of command and address signal pads that conduct the second portion of the signals of the second signal group, Integrated circuit.

2. The integrated circuit package comprises a first routing layer and a second routing layer, The first routing layer conducts signals from a first subset of the data signal pads. The second routing layer conducts signals from a second subset of the data signal pads. The integrated circuit according to claim 1.

3. The aforementioned integrated circuit package is The system comprises a third routing layer that conducts signals from a third subset of the command and address signal pads and a fourth subset of the command and address signal pads. The integrated circuit according to claim 2.

4. The physical interface circuit includes a double data rate (DDR) dynamic random access memory (DRAM) physical interface circuit. The integrated circuit according to claim 1.

5. The physical interface circuit includes a graphics DDR (GDDR) DRAM physical interface circuit. The integrated circuit according to claim 4.

6. The physical interface circuit includes a GDDR version 7 (GDDR7) DRAM physical interface circuit. The integrated circuit according to claim 5.

7. The signals of the first signal group include a data signal and a data clock signal. The integrated circuit according to claim 4.

8. The signals of the second group of signals include command and address signals. The integrated circuit according to claim 7.

9. The physical interface circuit conducts the multiple data signals using more than two signal levels. The integrated circuit according to claim 1.

10. The physical interface circuit conducts the plurality of data signals using four-level pulse amplitude modulation (PAM4) signaling. The integrated circuit according to claim 9.

11. A method for manufacturing an integrated circuit having a DDR memory controller and a first DDR memory physical interface circuit having a physical interface circuit region on the surface of a semiconductor die, The die signal pads arranged on the surface of the semiconductor die are separated into a first group of signal pads that conduct data signals and a second group of signal pads that conduct command and address signals. A first subset of data signal pads is placed in the upper left portion of the physical interface circuit area in the plan view of the surface, A second subset of data signal pads is placed in the upper right portion of the physical interface circuit area in the aforementioned plan view, A third subset of command and address signal pads is placed in the lower left portion of the physical interface circuit area in the aforementioned plan view. A fourth subset of command and address signal pads is placed in the lower right portion of the physical interface circuit area in the aforementioned plan view, The signals of the first subset of the data signal pads are routed to the first routing layer of the integrated circuit package in cross-section. This includes routing the signals of a second subset of the data signal pads to a second routing layer of the integrated circuit package in the cross-section, method.

12. The signals of the third subset of the command and address signal pads are routed to the third routing layer of the integrated circuit package in the cross-section. This includes routing the signals of a fourth subset of the command and address signal pads to the third routing layer of the integrated circuit package in the cross-section, The method according to claim 11.

13. The integrated circuit includes a second DDR memory physical interface circuit on the semiconductor die, The second die signal pads arranged on the surface of the semiconductor die are separated into a third group of signal pads that conduct a second data signal and a fourth group of signal pads that conduct a second command and address signal. A fifth subset of data signal pads is placed in the upper left portion of the second plan view, The sixth subset of data signal pads is placed in the upper right portion of the second plan view, A seventh subset of command and address signal pads is placed in the second lower left portion of the aforementioned plan view, An eighth subset of command and address signal pads is placed in the second lower right portion of the aforementioned plan view, The signals of the fifth subset of the data signal pads are routed to the first routing layer of the integrated circuit package in the cross-section. The signals of the sixth subset of the data signal pads are routed to the second routing layer of the integrated circuit package in the cross-section. The signals of the seventh subset of the command and address signal pads are routed to the third routing layer of the integrated circuit package in the cross-section. This includes routing the signals of an eighth subset of the command and address signal pads to the third routing layer of the integrated circuit package in the cross-section, The method according to claim 12.

14. The first DDR memory physical interface circuit and the second DDR memory physical interface circuit are arranged adjacent to each other on the semiconductor die in the plan view. The method of claim 13.

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