Power Management for a Computing System

Abstract

This application describes a power management system for controlling the transmission of power to a plurality of processing elements. The power management system includes a plurality of power management circuits disposed between the terminals of a power source. Each power management circuit is connected to a processing element among the plurality of processing elements and is configured to either supply sufficient power for power supply processing in the processing element or prevent the supply of sufficient power for power supply processing in the processing element. The power management system includes one or more power controllers arranged to determine whether a processing element among the plurality of processing elements supplies sufficient power for the processing element to perform processing.

Description

Technical Field

[0001]

Background Art

[0002] The large amount of power consumption required for application-specific processing such as cryptocurrency mining or artificial intelligence processing requires a large amount of energy. This amount of energy is likely to increase over time, especially in the case of cryptocurrency mining using the proof-of-work (PoW) consensus mechanism. In that mechanism, the value of the reward for each block and the complexity of the mathematical problems to be solved increase over time, which means that there is a higher incentive for the cryptocurrency mining network to improve its mining capacity. Current systems and methods for performing application-specific processing use non-renewable energy sources, which result in large carbon emissions due to the large amount of energy required. An alternative to current systems and methods may be the use of renewable energy sources, which has the advantages of reducing carbon emissions, reducing energy costs, and utilizing abundant energy supplies. However, the variability of the stability and efficiency of renewable energy sources makes application-specific processing difficult.

Brief Description of the Drawings

[0003] The features, nature, and various advantages of the present disclosure will become more apparent upon consideration of the following detailed description in conjunction with the accompanying drawings. A detailed description is presented below with reference to the accompanying drawings. In the figures, the leftmost digit of the reference number identifies the drawing in which the reference number first appears. The use of the same reference number in different drawings indicates similar or identical items. The systems depicted in the accompanying drawings are not to scale, and the components in the figures may not be drawn to scale with each other.

[0004]

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[0005] The technical problem of powering multiple processing elements with a power source that provides a varying voltage is overcome by the use of the power management system disclosed herein. Renewable energy sources such as solar power generation cells produce a variable voltage due to the changing nature of the energy source being converted to electricity. For example, at various times of the day, as the sun rises and sets and clouds thicken and clear, the amount of electricity produced changes. Cryptocurrency mining, which involves multiple application-specific processors operating together, attempts to solve complex mathematical problems and identify new blocks on the blockchain. The use of a variable power source may simply not be possible because the fixed nature of the power consumption of cryptocurrency mining is incompatible with the variable nature of the power source. Cryptocurrency mining may therefore rely on non-renewable energy sources, which can have an adverse environmental impact.

[0006] The power management system disclosed herein overcomes those technical problems by enabling cryptocurrency mining to have a variable power demand, which can track the variable power available from renewable energy sources.

[0007] Cryptocurrency mining is a computing system that includes a number of application-specific processors, i.e., a group of processors that operate together under central control to attempt to collaboratively identify the next block of a blockchain. Due to the repetitive nature of the processing tasks executed by the individual application-specific processors, assuming they have a relatively uniform power consumption, a power management system can turn on and off a particular application-specific processor among the many application-specific processors in mining in order to vary the overall power usage of the mining. Thus, by monitoring the power transmitted by the power source and turning on and off a particular application-specific processor among the many application-specific processors in mining to vary the overall power usage of the mining, the power usage can be made to follow the available power.

[0008] The power management system disclosed herein controls the power provided to each of the application-specific processors within a computing system, or in the example of cryptocurrency, within cryptocurrency mining. The power management system may include an array of switching circuits each having a respective switch, with a switch associated with each application-specific processor. Each switch is controlled to activate or deactivate the processor, and thus vary the overall power demand of the mining. The controller can monitor the input voltage and uses logic to determine how to control the switching circuit to match the number of application-specific processors that are on, and thus the overall power consumption of the mining, to the available power.

[0009] In the configurations disclosed herein, the amount of processing performed in cryptocurrency mining, or any other computing system managed by a power management system, can be increased because the computing power of the system is proportional to the power available at the power supply. It is all due to the new logic and the switching performed by the power management system that adapts the mining. Advantageously, since it is possible to effectively mine cryptocurrencies using a renewable energy power source, the carbon footprint associated with proof-of-work-based cryptocurrency mining can be significantly reduced. Additionally, the efficiency of a mining facility that includes a number of application-specific processors can be improved. Commercially, this increases the amount of cryptocurrency mined for the available renewable energy.

[0010] In some configurations, the controller may be able to consider additional factors to make the power management system more adaptive. For example, the power management system may use logic to determine which of a group of processors to turn off or on. If a particular processor is overheating or showing anomalies, or is at a critical stage in processing, a decision may be made to turn off or keep on that processor rather than one or more other processors. Thus, sophisticated logical decisions can be made to have a highly intelligent power management system. This additional functionality can increase the lifespan of the mining components or increase the processing efficiency. In turn, it can increase the opportunity to identify the next block of the blockchain by mining, because the amount of processing achieved for the available power produced increases.

[0011] The implementations of the following disclosure relate to a power management system configured to deliver power to a computing system 130 having multiple processing elements, such as an application specific integrated circuit (ASIC). The processing elements may be configured to perform cryptocurrency mining. However, the power management system may also be applicable to power management of other processes where the power usage remains relatively constant during processing, specifically, application specific processing such as artificial intelligence processing.

[0012] Cryptocurrency mining that utilizes the mechanism of the PoW consensus requires solving complex mathematical formulas and expending a certain amount of effort as the processing power of the application to prevent the cryptocurrency network from being invaded. For the purpose of identifying new cryptocurrencies, known as mining, miners will operate a powerful computing system to solve the complex mathematical formulas for identifying the next block of the blockchain. It is common to set up a cryptocurrency mining farm with a large-scale computing system including a number of ASICs. Each ASIC is controlled by a central processing controller and tasked with attempting to solve a complex mathematical formula or a part thereof. The central processing controller essentially communicates with the distributed blockchain ledger via the network and transmits the data to be processed to the ASIC. Cryptocurrency mining, specific cryptocurrency protocols such as Bitcoin and Ethereum, and the associated blockchain technology are well-known, and those skilled in the art are assumed to have an understanding of the power demand and function of the computing system 130 that drives those technologies. Furthermore, it will be understood that other cryptographic or blockchain-related processes, such as the minting of non-fungible tokens (NFTs) resulting from blockchain updates or the transfer of cryptocurrencies, may also utilize the systems disclosed herein.

[0013] Cryptocurrency mining has a predictable power usage because its processing is not very user-dependent and does not vary much. As a result, each ASIC that makes up the computing system will have very similar power requirements, and thus, the power management circuitry of the power management system can be connected in series between the terminals of the power supply for power. Further, since the current must be the same across the series stack of the power management circuitry of the power management system, the amount of current used is constant along the series chain of ASICs. Arranging the ASICs in series is advantageous for cryptocurrency mining and other application-specific processing because it draws significantly less current than arranging the ASICs in parallel.

[0014] In FIG. 1A, a cryptocurrency mining farm 100 includes a power supply 110, a power management system 120, a computing system 130, and a network 140. The power supply 110 provides power to the computing system 130 through the power management system 120 via a power supply terminal 111 of the power supply 110, and is a solar power generation array that uses the sun as an energy source 191. Essentially, as the sun rises and sets during the course of a day and clouds cover the direct line connecting the sun and the solar power generation array (power supply 110), the output voltage of the power supply will change. To manage the computing system 130 when the power supply 110 has a variable voltage, the power management system 120 adapts the power usage requirements of the computing system 130 to the power transmitted by the variable power supply. In particular, when the power transmitted by the power supply 110 decreases, for example when clouds pass over the solar power generation array, the power management system 120 can disable one or more processing elements 131 of the computing system 130 to reduce the power requirements of the computing system 130. This is shown in FIG. 1A, where the sun as an energy source 101 is partially covered by clouds, and as a result, only two of the three power management circuits 121 of the power management system 120 are connected to their respective processing elements 131 (or the load of the processing elements). Although only three power management circuits 121 and processing elements 131 are shown, the examples provided may each be any number. When a processing element 131 is connected to a power management circuit 121, the processing element 131 can process data received from a central processing controller 132 of the computing system 130. The central processing controller 132 communicates with the network 130 and transmits data for processing to the processing elements 131.

[0015] Furthermore, when the power generated by the power supply 110 increases, for example, when clouds covering solar power generation clear or become thinner, the power management system 120 can activate one or more processing elements 131. The power demand of the computing system 130, and thus the processing capacity of the computing system 130, can be increased or decreased in accordance with the available power generated by a variable power source that obtains power from the sun.

[0016] The power management system 120 described herein thus enables the effective use of the maximum amount of available power generated by the power supply 110. The number of processing elements 131 to be activated dynamically changes to follow the extraction of power from the power supply 110 based on one or more characteristics, which in this case is the variation in the voltage of the power supply 110. However, the power management system 120 may also take into account other characteristics such as temperature characteristics, one or more faults in the processing element 131, the current processing state of the processing element 131, or the current draw of the processing element 131. Advantageously, the impact of the instability of the power supply 110 on the efficiency of the computing system 130 is reduced due to the power management system 120 described herein. Furthermore, the processing volume that can be achieved by the computing system 130 can be dynamically changed to satisfy the available power of the power supply 110. By providing this adaptive system for matching the power demand to the power supply 110, it is possible to efficiently and effectively use renewable energy sources to perform cryptocurrency mining, which in turn reduces the carbon footprint of the cryptocurrency mining farm 100.

[0017] Additional details will be described below with reference to some exemplary implementations.

[0018] Figure 1B shows an exemplary diagram of the power management system 120 of FIG. 1A that includes a plurality of processing elements 131 for managing the transmission of power from the power supply 110 to the computing system 130. The power management system 120 includes a plurality of power management circuits 121. Each power management circuit 121 includes a power controller 124, a switching circuit 123, and a connector 122, and each of them will be discussed in more detail with reference to FIG. 1C. The plurality of power management circuits 121 are connected in series between the terminals 111 of the power supply 110. The series connection of the power management circuits 121 forms a series stack of the processing elements 131.

[0019] The power supply 110 is a photovoltaic array that converts solar energy received from the sun into electricity. The power supply 110 thus outputs a variable DC voltage. In some embodiments, the power supply 110 is a power source of other forms of renewable energy sources such as wind power, geothermal energy, biomass, tidal power, or hydropower. In other embodiments, the power supply 110 is a non-renewable energy source having a variable output voltage. In still further embodiments, the power supply 110 is an AC power supply rectified to DC, i.e., an AC rectified mains power supply. In some embodiments, the power supply 110 is a differential voltage. The power supply 110 may be referred to as a DC power supply, a first power supply, a voltage supply source, a variable voltage supply source, a direct current (DC) power supply, an AC power supply, a rectified AC power supply, or an AC rectified mains power supply.

[0020] Power management system 120 includes a power management circuit 121 that controls the transmission of power from power supply 110 to associated processing elements 131 (not shown in FIG. 1B) as will be described in more detail. The power management circuit 121 essentially controls the transmission of power to enable and disable specific processing elements 131. This balances the power requirements of computing system 130 against the power available from power supply 110. The power management circuits 121 may each be identical and thus may be disposed anywhere within the plurality of power management circuits. In other words, each power management circuit 121 may be disposed anywhere within the stack of ASICs. Also, although 15 power management circuits 121 are shown in FIG. 1B, it will be understood that any number of power management circuits 121 may be used depending on the power and processing requirements of computing system 130 served by power management system 120. Each power management circuit 121 may also be referred to as a development platform or a hashing platform.

[0021] FIG. 1C shows an exemplary diagram of a power management circuit 121 within the power management system 120 of FIG. 1B. The power management circuit 121 is configured to be connected to an adjacent power management circuit 121 by one or both of an upper connector 150 and a lower connector 151. The upper and lower connectors 150, 151 allow a flow of current from the switching circuit 123 to the connector 122 and to the processing element 131, as indicated by the solid arrows, to enable the processing element 131. The upper connector 150 and the lower connector 151 also allow the transmission and reception of control signals 160, 161 (throttle control, management signals, and / or communication control signals). The first control signal 160 is transmitted from the power controller 124 to the connector 122 (as indicated by the dashed arrow) to throttle the power usage of the processing element 131, i.e., the first control signal provides throttle control. In some embodiments, the throttle functionality is not provided, and thus the connector 122 does not provide a connection for the first control signal 160. The second control signal 161 is transmitted from the power controller 124 to the switching circuit 123 (as indicated by the dashed arrow) to determine when the switching circuit 123 should switch between an active state and a non-active state. The first control signal 160 may instruct the processing element to stop processing in terms of reducing latency prior to the switching of the corresponding switching circuit 123 to the non-active state by the second control signal 161. The low latency in the control of the processing element 131 means that there is less inefficiency associated with the activation and deactivation of the processing element 131.

[0022] It is noted for the avoidance of doubt that the upper connector 150 and the lower connector 151 need not be physically arranged above and below each other, this is merely a schematic representation. Thus, the upper connector 150 and the lower connector 151 may be referred to as the first and second connectors.

[0023] Each power management circuit 121 may only recognize the power domain of an adjacent power management circuit 121. As a result, a power management circuit 121 that is not operating or a power management circuit 121 in which the switching circuit 123 is in an inactive state will not affect other power management circuits 121 within the series chain. This is because a plurality of power management circuits 121 are connected in series, thereby improving energy savings within the power management system 120. In other embodiments, the power management circuits 121 may be grouped together. As a result, a plurality of groups of power management circuits will be connected in series to form a stack. The voltage at both ends of the power management circuit 121 is limited to a certain power domain. Therefore, the connection of adjacent power management circuits 121 enables symmetric stacking. Symmetric stacking may be defined as stacking groups of power management circuits.

[0024] The power management circuit 121 may be a printed circuit board (PCB) module. The power management circuit 121 may have a low voltage power supply. This is advantageous because if the power requirements of the power management circuit 121 are reduced, the requirements when the processing element 131 of the computing system 130 is performing processing (or hashing) will result in lower energy.

[0025] The power management circuit 121 includes a connector 122 that connects the power management circuit 121 to a processing element 131 arranged to execute application-specific processing. Each connector 122 may interface with one processing element 131 or the load of the processing elements. The connector 122 may be a socket into which the processing element 131 is inserted. In other embodiments, the connector 122 may be a track or through-hole on a circuit board to which the processing element 131 is soldered. The connector 122 may also, in a further embodiment, be solder that connects the processing element 131 to the power management circuit 121. The processing element 131 has a relatively predictable current draw. The processing element 131 is, in this embodiment, an ASIC. However, the processing element 131 may be a plurality of ASICs, such as a cluster of ASICs, connected to one power management circuit 121. The processing element 131 may be any other suitable processing means and, in most configurations, is some form of processor arranged to execute some kind of application-specific processing.

[0026] Connector 122 provides a connection means to the power management system 120 for the processing element 131, but the connector 122 may not recognize the power management system 120 and / or the power supply 110. This is because the connector 122 may simply be a means of connecting the processing element 131 to the input voltage and the first control signal 160 from the power controller 124, and in some embodiments, may also be a means of enabling access to a register or a part thereof that stores the solution of a complex mathematical formula. Each power management circuit 121 may provide sufficient power from the power supply 110 to the connector 122 through the serial stacking of a plurality of power management circuits 121, and thus a plurality of processing elements 131. Any processing element 131 connected to any connector 122 should be able to consume sufficient power to enable processing. The processing element has a minimum voltage and / or power requirement that enables it to function accurately and thus execute the processing operations it is designed to perform. Such a minimum voltage and / or power requirement represents sufficient power to enable processing. When there is sufficient power and thus the processing element is performing processing, that processing element can be considered to be in an active state.

[0027] The processing element 131 receives data for processing from the central processing controller 132 via a separate data connector. However, in other embodiments, the connector 122 provides both power and data connectivity.

[0028] The switching circuit 123 is configured to control the transfer of power from the power supply 110 to the connector 122 for use by the processing element 131 connected to the connector 122 during use. The switching circuit 123 switches between (i) an active state in which sufficient power to enable processing is provided from the power supply 110 to the processing element 131 via the connector 122, and (ii) an inactive state in which sufficient power to enable processing is not provided to the processing element 131. This functionality will be discussed in more detail in connection with other features and the drawings. In the active state, the power transferred from the power supply 110 to the connector 122 and used by the processing element 131 can be equal to or greater than a power threshold indicating sufficient power to power the processing. In the inactive state, the power transferred from the power supply 110 to the connector 122 and used by the processing element 131 can be less than a power threshold indicating sufficient power to power the processing.

[0029] The switching circuit 123 includes a direct analog feedback circuit that provides power normalization and protection for the processing element. If the switching circuit 123 is not used, when a certain processing element 131 stops drawing a set amount of current, the voltage across the processing element 131 will increase, which may cause damage to the processing element 131. The switching circuit 123 includes a transistor-based element having conductivity controlled by a second control signal 161. The conductivity of the transistor-based element is controlled by an input voltage from the power controller 124. In the present example, the switching circuit 123 is a field effect transistor (FET). Thus, the switching circuit 123 includes a source, a gate, and a drain. The switching circuit 123 may include a metal oxide semiconductor FET (MOSFET) that, when driven in enhancement mode, has no path between the drain and the source when no voltage is applied between the gate terminal and the source terminal. However, when a gate-source voltage is applied, the MOSFET can conduct current. During operation in a stable state, the MOSFET is fully off, so that accurate power control tuning can be achieved through adjustment of the power consumption by the load as described herein. Since the FET is controlled by gate charge, once the gate is closed or opened, no additional power is drawn, thereby enabling low-power switching.

[0030] The power controller 124 controls the switching circuit 123. Specifically, the switching circuit 123 switches between an active state and a non-active state depending on a second control signal 161 received from the power controller 125 of the corresponding power management circuit 121. The power controller 124 determines whether the switching circuit 123 of one of the plurality of power management circuits 121 should be in an active state or a non-active state based on at least one characteristic. In the present embodiment, the characteristic is the voltage of the power supply 110. However, in other embodiments, the characteristic may be a change in the voltage of the power supply 110. The output power of the power supply or fluctuations in the output power may also be the above characteristics in other embodiments. In some embodiments, the above characteristic is a slew rate. The slew rate is the maximum rate at which the system can respond to a rapid change in the voltage of the power supply. Since the system can better accept a rapid but predictable change in the voltage of the power supply or a less rapid but unpredictable change compared to a rapid but unpredictable change in the voltage of the power supply, the slew rate can be considered. In yet further embodiments, changes detected in a renewable energy source such as lumens received from the sun may be used to enable an early determination of a likely change in the output power.

[0031] In other embodiments, the power controller 124 may be configured to consider other characteristics. For example, the other characteristics may be one or more characteristics of the power management system 120, one or more processing elements 131 configured to be connected to one or more of the plurality of power management circuits 121 in use, and the computing system 130 to which the power managed by the power management system 120 is transmitted.

[0032] For example, at least one other characteristic may include a temperature characteristic. In such a situation, overheating of a particular processing element 131 may be detected, and the range within the overall system where the processing element 131 is located may be detected. If it is necessary to disable a number of processing elements 131 due to a detected voltage drop in the power supply 110, the power controller 124 can choose to disable the processing elements 131 at risk of overheating. Advantageously, this can help improve the lifespan of the processing hardware and the reliability of the overall system.

[0033] Another characteristic considered in other embodiments is the current state of the processing element 131 configured to be connected to each of the plurality of power management circuits 121. For example, if a particular processing element 131 is close to completing a processing task, it may be preferable not to disable that processing element 131 so that the processing can be completed. In contrast, it may be preferable to disable a processing element 131 that has only just started processing, thereby allowing the processing task that has just started to be assigned to a different processing element 131.

[0034] Other characteristics may include one or more of a failure of the processing element 131 or a current draw of the processing element 131. The processing element 131 has a relatively predictable current draw, but if it fails or otherwise changes within the processing element 131, the power management circuit 121 may disable the processing element 131, replace the processing element 131 within the computing system 130, and substitute the processing element 131.

[0035] Each power controller 124 may be described as a wide - level controller, a development - board controller, a hashing - board controller, a low - power controller, a programmable interface controller (PIC), a microcontroller, or an advanced RISC (Reduced Instruction Set Computer) machine (ARM) controller.

[0036] In some embodiments, each of the power controllers 124 includes one or more controller switching elements, each of which is associated with a power management circuit 121 among the plurality of power management circuits 121 and is configured to switch on or off according to whether the threshold of the at least one characteristic is satisfied.

[0037] In other embodiments, the power management circuit 121 may not have a dedicated power controller 124, but instead a single central power controller 124 may be provided. In such embodiments, the central power controller 124 may be a dedicated circuit or an electronic chip configured to perform the required functionality. Alternatively, the central power controller 124 may include a processor and a memory, and the memory stores a computer-readable medium, such as code, configured to implement a method for controlling the power demand of the computing system 130 to the processor. In other words, the central power controller 124 may be implemented in software.

[0038] In any case, one or more power controllers 124 are configured to determine whether one of the switching circuits 123 of the plurality of power management circuits 121 should be in an active state or an inactive state based on one or more characteristics of the power supply 110, and the one or more power controllers 124 transmit a second control signal 161 to one of the switching circuits 123 of the plurality of power management circuits 121 based on the determined state. The central power controller 124 may make a determination related to the activation or deactivation of each of the processing elements 131 in a single operation, and may transmit a first control signal 160 to one or more connectors 122 so that the connected processing element 131 either re-initializes the drawing of current from the power management system 120 or stops an attempt thereof. In response to the above determination, the central power controller 124 transmits a second control signal 161 instructing to change the switch to either an active state or an inactive state to the corresponding switching circuit 123. In this way, the first control signal 160 enables the ability to stop the drawing of current from the processing element 131 before the input voltage for the processing element 131 is bypassed when the switching circuit 123 is in an inactive state due to the second control signal 161. In this example, the latency is reduced due to the reduction of inefficiency.

[0039] In an alternative embodiment, a central controller 124 may be present, or a power controller 124 of each power management circuit 121 may be present and communicate with a separate central controller 124. In such embodiments, if the activation and deactivation of the processing elements 131 can be tolerated with relatively short notice for short periods, the nodes of the power management system 120 among the power management circuits 121 can rapidly adapt to changing instantaneous levels of the total voltage Vstack across multiple power management circuits. The total voltage across multiple power management circuits is equal to the sum of the individual voltage drops in the power management system and is described with reference to FIG. 8C. There may be a current state of processing of the processing elements 131 that permits disabling some of the processing elements 131 rather than disabling different processing elements 131 in different processing states, for example, if the processing element 131 has just started a processing task. For a power management circuit having a processing element 131 that has just started a processing task, when the total voltage Vstack across multiple power management circuits decreases due to, for example, clouds obscuring a direct line between the sun and a photovoltaic array connected to the power source 110, the corresponding switching circuit 123 may be switched to an inactive state.

[0040] The power controller 124 may be configured to adjust or increase / decrease the power consumption of each processing element 131 arranged to be connected to the power management circuit 121 when the corresponding switching circuit 123 is in an active state. The adjustment of the power consumption may be referred to as throttle control, which is provided from the power controller 124 to the connector 122 via the first control signal 160. Throttle control may be used to make small adjustments to the power consumption of the processing element 131 when there are relatively small changes in the power from the power supply 110 (for example, clouds passing over a solar power generation array), but not sufficient changes to justify deactivating the processing element. In some embodiments, since throttle control helps with fine-tuning the power consumption of the processing element 131, it is possible to increase the electronic stability of the power management circuit 121. The second control signal 161 flows from the power controller 124 to the connector 122 and the switching circuit 123. The second control signal 161 may also include a management signal and / or a communication control signal. And the second control signal 161 may be received by the processing element 131 and used by the processing element 131 to adjust the power demand on the connector 122. In some embodiments, accurate throttle control is required to match the entire system to the power curve of the power supply 110 as described with reference to FIG. 5 (for example, when a pure analog circuit is connected around the processing element 131 in a system (such as the cryptocurrency mining farm 100) including the power supply 110 of solar power generation). Throttle control may be provided from the voltage monitor of the power management circuit, more specifically the switching circuit 123.

[0041] The communication channel between adjacent power management circuits 121 enables the flow of a first control signal 160 between the power management circuits 121. The functionality of the communication channel can be implemented using the upper connector 150 and the lower connector 151, the central power controller 124, or a separate communication channel between adjacent power management circuits. The adjustment and control of power usage using the control signals 160, 161 include one or more of clock dithering, clock skipping, analog inputs for phase-locked loop (PLL) steering, and fully digital protocol control for the communication channel. The PLL generates the core clock inside each processing element 131.

[0042] The total power draw of each processing element 131 can be tunable through the PLL value. In this example, which is also an example of throttle control, a UART (Universal Asynchronous Receiver-Transmitter) register may command the processing element 131 to reduce the internal clock speed or turn off or disable some or all of the (hashing) engines within the processing element 131 in order to reduce the load on the processing element 131.

[0043] In some examples, the clock speed may be used to finely balance the stack of power management circuits 121 and set the PLL value to adjust the imbalance within the stack of power management circuits 121 to maintain the total voltage Vstack. In this example, which is also an example of throttle control, the reference input clock frequency supplied to the processing element 131 is changed. This is an example of an analog called clock skewering and can be used to improve system performance and make small adjustments because changing the reference input clock frequency too much or too rapidly can have an adverse effect on the PLL.

[0044] In other examples, when the input pin of processing element 131 is logically driven active, the internal clock of processing element 131 stops synchronously. This is known as clock gating and includes the removal of the clock signal when the circuit is not in use, i.e., the internal clock of processing element 131 is stopped. Hardware clock gating is advantageous as it reduces the dissipation of dynamic power within the system. The input pin is a high-gain pin. In this example, clock dithering or skipping is possible since an AC waveform can be used at the input pin to generate a dithered clock signal in the internal (hashing) engine of processing element 131. This is advantageous in that the use of hardware clock gating provides reduced control latency due to its speed, leading to fewer inefficiencies associated with the activation and deactivation of processing element 131.

[0045] Registers that need to be initialized may be maintained within the voltage domain of the corresponding power management circuit 121. In one example, the registers that need to be initialized may be maintained within the voltage domain of the second voltage source Valways, described with reference to FIGS. 2A-2B. When processing element 131 is near completion of a processing task and receives a second control signal 161 for the corresponding switching circuit 123 to switch the switching circuit to an inactive state, the registers of processing element 131 may be read. This is because the registers of processing element 131 can be rewritten before the next processing cycle begins, resulting in the need to solve complex mathematical formulas from the beginning being eliminated, thus reducing the required computational power. If the power supply 110 is traceable or predictable, the rewriting of registers can be reduced. For example, when the power supply 110 is an AC power supply rectified to DC.

[0046] In the case where there is no hardware control line for the control signal, software or the UART communication protocol may be referred to as a first control signal 161 for invalidating the processing by the processing element 131 before the corresponding switching circuit 123 switches to the inactive state, whereby the related power management circuit 121 is excluded from the stack of the power management circuit 121. As already explained, this may be required when the power supply 110 is variable. Once the processing by the processing element 131 is invalidated (i.e., when the processing element 131 is not provided with sufficient power to enable processing), any register having a solution to a complex mathematical formula may be read. When the switching circuit 123 switches to the active state where sufficient power is provided to enable processing to the processing element 131, the UART packet may reactivate the processing element 131 and refresh the registers of the processing element 131. By using the UART for clock skewering, a solution can be provided while reducing the control latency. However, this is merely an example, and hardware clock gating may be used to perform clock dithering or skipping due to the reduction of dynamic power dissipation in the system.

[0047] When the voltage of the power supply 110 changes predictably, latency may be well considered. When the voltage of the power supply 110 changes slowly but unpredictably, latency may still be appropriately considered. Conversely, when the voltage of the power supply 110 changes rapidly and unpredictably, it is more difficult to consider latency, so the power management system 120 may only be efficient with a low level of latency. To quickly turn on each processing element 131, a slow ramp-up voltage may be used within the scope of the software method for power supply to the power supply 110, which can slowly increase the ramp-up voltage to the power management circuit 121. As long as the total voltage across the power management circuit 121 is balanced, any processing element 131 may be turned off. PoW in cryptocurrency mining, since the system creates a new block on the blockchain when it outputs an accurate hash, the blockchain generation process has a rapidly changing time limit. In fact, there is a certain time limit during which the work done in cryptocurrency mining is still valid. Therefore, latency or delay in the working process is not as critical as in other applications, since the miner still receives a reward for the work done when the output of the cryptocurrency mining architecture 100 fits into the block within the blockchain.

[0048] FIG. 2A shows an exemplary circuit diagram of the switching circuit 200. The switching circuit 200 in FIG. 2A is an example of any switching circuit 123 in any example and can be implemented in any example. Each power management circuit 121 should be able to guarantee a minimum series load of the processing element 131 across the stack of power management circuits 121. Thus, the switching circuit 200 is configured to provide this when the processing element 131 is enabled or disabled. Ideally, each switching circuit 200 should have a constant voltage drop across both ends of the first transistor-based element (or FET) M1, which can be modeled as an ideal zener diode across the low power rail Vlow and the high power rail Vhigh connected in parallel to the load I1 of the processing element 131.

[0049] The switching circuit 200 includes an inverting operational amplifier (op-amp) U1. This may also be referred to as an amplifying element. The op-amp U1 has an output that is fed back through a second resistor R2 to the negative or inverting input of the op-amp U1. The input signal V1 is applied to the inverting input of the op-amp U1 through a first resistor R1. The input signal V1 is the second control signal 161 supplied by one or more power controllers 124. The input signal V1 may be approximately equal to the differential voltage Vdiff (not shown in FIG. 2A) across the power management circuit and may be a reference voltage derived from the second power source Valways or a bandgap reference.

[0050] The positive pin of the operational amplifier U1 is connected to the second power supply Valways. The output signal and the input signal of the operational amplifier U1 are out of phase. The value of the first resistor R1 is significantly smaller than the value of the second resistor R2, resulting in a high gain. Thus, the operational amplifier U1 amplifies the second control signal 161 to be suitable for controlling the first transistor base element M1 and bypassing the processing element 131 if necessary. The first transistor base element M1 may be referred to as a switching element. The output of the operational amplifier U1 is supplied to the first transistor base element M1 for the normalization and protection of the power of the processing element. The switching circuit 200 protects the processing element 131 when an event of the stop of the processing element 131 occurs by forcing the power envelope through the first transistor base element M1. The first transistor base element M1 may be a high-power MOSFET. As a result of the power envelope, when the current draw of the processing element 131 decreases, for example, by a stop, the transistor base element M1 dissipates the excess power not being used by the processing element 131.

[0051] The mechanism of power normalization and protection can also be described from the perspective of the first transistor-based element M1 or FET. When the FET is fully closed (or the FET is fully turned on) and the differential voltage Vdiff across the power management circuit is equal to 0, the processing element 131 is not in processing. In other words, due to the reduction in the available power from the power supply 110, the switching circuit 123 has switched to an inactive state where sufficient power for processing is not supplied to the processing element 131. This can also be described as the bypass-idle mode or the case where the processing element 131 is deactivated. When the FET is fully open (or the FET is turned off) and the differential voltage Vdiff across the power management circuit is sufficient for processing or the processing element 131 is carrying a sufficient amount of current, the processing element 131 is in processing. In other words, the switching circuit 123 has switched to an active state. This can also be described as the normal-run mode or the case where the processing element 131 is activated. When a failure occurs in the processing element 131, or it is not using power fully, or it is in the process of restarting, and the FET is simulating the load of the processing element 131, the FET will enter the linear mode and dissipate power. This can also be called the hot-idle mode and can occur when overheating occurs in a specific processing element 131 or the area where a certain processing element 131 of the entire system is located.

[0052] As described above in connection with FIGS. 1A-1B, the second power source Valways is not lost during the bypass idle mode period or when the switching circuit 200 is in an inactive state. The second power source Valways is a feature of the power management system 120 when the power source 110 is the first power source. The second power source Valways is arranged to transfer a low level of power sufficient to enable the control of each power management circuit 121 to the plurality of power management circuits 121. When a power management circuit 121 is removed from the stack due to a reduction in the power source 110, the corresponding power controller 124 is still communicable due to the low level and constant power and / or current provided by the second power source Valways. The above level of power to enable the control of the power management circuit 121 may even be less than the power sufficient to enable processing by the processing element. Thus, the second power source Valways is independent of the first power source 110. The second power source Valways may always be present when the power management system 120 and / or the computing system 130 is operating. This is advantageous because the power management circuit 121 can conserve energy in the stack while the power controller 124 can still enable the processing element 131 because the current from the first power source 110 is not drawn to the processing element 131. The second power source Valways may always be within the same voltage domain as the corresponding processing element 131. The first control signal 160 may be provided to the connector 122 of the power management circuit 121 and thus may be provided to the corresponding processing element 131 within the local voltage domain of the corresponding processing element 131. As described herein, capacitive coupling for generating the second power source Valways may exist, and thus the power source 110 may be supplied to each power management circuit 121 as a differential voltage. The differential voltage may be supplied to the connector 122 within the local voltage domain of the processing element 131. The voltage domain of the power management circuit 121 or the processing element 131 may be reset by the capacitive coupling.

[0053] The stack of the power management circuit 121 may start operating when the total voltage Vstack (not shown in FIG. 2A) across the plurality of power management circuits becomes equal to or greater than the differential voltage Vdiff across the power management circuit. For example, when the cloud covering the solar power generation clears or thins, the power management system 120 can activate one or more processing elements 131. As the total voltage Vstack across the plurality of power management circuits increases, more switching circuits 200 can be switched to the active state to supply sufficient power to enable processing to the corresponding processing element 131. In other words, more power management circuits 121 in the stack are turned "on" by the opening of the FETs of the corresponding switching circuits 200, and thus current can flow through the corresponding processing element 131 (i.e., the processing element 131 consumes current). Conversely, as the total voltage Vstack across the plurality of power management circuits decreases, the switching circuit 200 switches to the non-active state and begins to stop supplying sufficient power to the corresponding processing element 131 to enable processing. In other words, more power management circuits 121 in the stack are turned "off" by the blocking of the FETs of the corresponding switching circuits 200, and thus the flow of current to the corresponding processing element 131 is stopped and the operation of the processing element 131 is stopped.

[0054] If the number of processing elements 131 that are activated to track the extraction of power from power supply 110 changes dynamically based on one or more of one or more characteristics, such as temperature characteristics, one or more faults of processing element 131, the current state of the processing of processing element 131, or the current draw of processing element 131, then such characteristics should be considered more closely. To consider temperature characteristics (i.e., tracking which processing elements 131 are at a high temperature and need to be deactivated, and replacement with processing elements 131 that can be activated because they have not been used for some time), fault removal (i.e., a certain processing element 131 is not operating normally), and the tolerance of voltage fluctuations of each processing element 131 (i.e., tracking their tolerances because each processing element 131 has different manufacturing tolerances), the power management system 120 can have the following number of power management circuits 121, where Vstack is the total power across a stack of multiple power management circuits, Vdiff is the differential voltage across both ends of one power management circuit, and N is equal to the number of extra processing elements:

Number

[0055] FIG. 2B shows another exemplary circuit diagram of the switching circuit 201 of each of the plurality of power management circuits 121. The switching circuit 201 of FIG. 2B is an example of any switching circuit 123 in any example and can be implemented in any example. Similar to the switching circuit 200 of FIG. 2A, the switching circuit 201 of FIG. 2B is essentially an ideal diode with a power FET M2 (which may also be called a switching element) or a second transistor-based element M2, and provides normalization and protection of the power of the processing element 131 (not shown in FIG. 2B).

[0056] When the processing element 131 is observed at the output, the high power rail Vhigh and the low power rail Vlow are in parallel with the output, and there is a fixed voltage drop at that output. When there is a voltage across the high power rail Vhigh and the low power rail Vlow, the operational amplifier U2 exhibits very strong conduction. The operational amplifier U2 (which may sometimes be referred to as an amplification element) has both positive feedback due to the sixth resistor R6 and the seventh resistor R7, and negative feedback due to the eighth resistor and the third resistor R3 in parallel with the fifth resistor R5 and the capacitor C1. The fourth resistor R4 also exists at a node connected to the enable input to the fixed reference diode D1. The diode D1 may set the voltage limit of the second transistor base element M2, and the second transistor base element supplies the output of the operational amplifier via the ninth resistor R9. The purpose of the capacitor C1 and the resistors R3, R4, R5, R6, R7, R8, R9 is to provide filtering. The diode D1 may alternatively be the output of a bandgap reference or a digital-to-analog converter (DAC).

[0057] The second power supply Valways may always be present while the power management circuit 121 is operating and before the application of the power supply 110. A reverse second power supply Vnegalways may exist to provide bias to the second transistor base element M2. The enable signal goes high according to the second power supply Valways to activate the processing element 131, and in so doing, the switching circuit 201 dissipates the surplus current not being used by the processing element 131. The enable signal goes low according to the strong reverse second power supply Vnegalways for the bias, suppressing (or bypassing) the processing element 131 and resulting in no processing (hashing). It may not be necessary to have the reverse second power supply Vnegalways. When the switching circuit 201 is in an inactive state, the second transistor base element M2 is driven to full saturation due to the positive terminal of the operational amplifier U2 being driven low. Also, software control may activate or deactivate the processing element 131 by driving the transistor base elements M1, M2 to full saturation when the power supply 110 decreases.

[0058] Figure 3 shows an exemplary circuit diagram for supplying power at a level sufficient to enable control of each of the plurality of power management circuits 121. As described above, the power at a level sufficient to enable control of each power management circuit 121 is described as the second power supply Valways. The second power supply Valways may be a (DC) Vdd at a level sufficient to activate the logic of the controller, such as throttle control, adjustment control, management logic, communication control, and / or management control, via the first and second control signals 160, 161, even when the switching circuit 201 in the power management circuit 121 is in an inactive state. The second power supply Valways may be a low power rail.

[0059] In the exemplary circuit diagram 300 of FIG. 3, the transformer 302 within the power management circuit 121 and the supply 301 separated within the backplane 321 are used to provide the second power supply Valways. The backplane may be described as a set of electrical connectors in parallel with each other and / or as an electrical connector connecting several electrical circuits. In this example, AC power is provided to each power management circuit 121, rectified, and becomes DC referenced to a local ground. If the AC power source were not isolated by the transformer 302 and adjusted to DC, inefficiencies would have to be tolerated. An alternative to having a DC supply is an AC rectified backbone power supply.

[0060] Another example of providing the second power supply Valways involves using a local supercapacitor maintained by the main power supply 110 each time the switching circuit 123 of the power management circuit 121 becomes active, or using a capacitor charge pump method. The capacitor charge pump method can isolate the power domain, double the voltage, and can be beneficial at low load levels. During the capacitor charge pump method, the power management circuit 121 should be able to tolerate differential voltages because a DC voltage is differentially supplied to each power management circuit 121. In an example where each power management circuit 121 has a set of opto-isolated FETs or insulated gate bipolar transistors (IGBTs) capable of activating or deactivating a local capacitor, different pairs of FETs or IGBTs may be switched to pump charge to the second supply voltage Valways in this capacitor when the local capacitor is not charged. This switching can be done synchronously across the entire stack to equalize the draw on the DC line. In other words, the capacitor is continuously switched from attachment to the DC voltage for charging to attachment to the load for discharging. Since at least two capacitors are used, at any given time, at least one capacitor is either charged or discharging.

[0061] FIG. 4A shows an exemplary graph 400 depicting communication such as transmission of a communication signal through a plurality of power management circuits 121 using an AC-coupled signal, and FIG. 4B shows an exemplary graph 401 depicting communication such as transmission of a communication signal through a plurality of power management circuits 121 using carrier-based signaling. The communication signal may be either or both of the first control signal 160 and the second control signal 161. The connection of adjacent power management circuits 121 may be via the upper connector 150 and / or the lower connector 151. When transmitting a communication signal through the upper connector 150 and the lower connector 151 of the stack of power management circuits 121, operating signaling occurs between the power management circuits 121. Operating signaling is a way of electrically transmitting information, which is in this case the communication signal, using two complementary signals. The complementary signals used in the example of FIG. 4A are the first AC-coupled communication signal 420 and the second AC-coupled communication signal 421, and those complementary signals used in the example of FIG. 4B are the communication signal 460 and the carrier signal 430 for providing the modulated communication signal 461.

[0062] Differential signaling is advantageous to use for transmitting the communication signal since it helps maintain the signal-to-noise ratio (SNR) of the communication signal. Additionally, since the communication signal is provided to the power management circuits 121 when the low-power second power supply Valways is input without the first power supply 110, differential signaling offers the advantage of operating at a lower voltage. Further, this results in reduced power consumption and reduced EMI emissions.

[0063] In FIG. 4A, the communication signal to be transmitted (here, a DC-coupled signal) 410 is coupled with AC to generate a first AC-coupled communication signal 420 of the first power management circuit. Then, the first AC-coupled communication signal 420 is transmitted to the second power management circuit to generate a second AC-coupled communication signal 421. Then, the second AC-coupled communication signal 421 is reconstructed, and at the connector of the second power management circuit, a reconstructed communication signal 411 in the local or unique voltage domain of the corresponding processing element connected to the connector is generated. AC coupling enables flexible attachment and reduces problems associated with updates to the power management system.

[0064] AC coupling is performed within the range of one voltage domain. In this implementation, each power management circuit 121 will have a voltage domain in which AC coupling is performed. This is one of various techniques having capacitively coupled buses. Each power management circuit 121 transmits an AC-coupled communication signal to an adjacent power management circuit 121 through the use of an AC-coupled communication line (possibly through the upper connector 150 and / or the lower connector 151).

[0065] In FIG. 4B, a carrier signal 430, or more specifically an AC carrier signal 430, is modulated with a communication signal 460, or more specifically a DC communication signal 460 (which can be described as either or both of the first control signal 160 and the second control signal 161). As a result, the modulated communication signal 461 enables the transmission of the communication signal 460 via the carrier signal 430 from the first power management circuit to the second power management circuit. Carrier-based signaling enables dramatically faster communication of communication signals between adjacent power management circuits, along with reduced power dissipation. Carrier-based signaling does not rely on a DC bias.

[0066] The physical-level topology and interface are the same for the examples of FIGS. 4A and 4B. The signal to be modulated is treated in the same way as the transmission line with AC coupling.

[0067] In some embodiments, within the stack of power management circuits 121, the power management circuits may be automatically addressed, whereby each power management circuit 121 knows where it is in the chain of connected power management circuits 121. Each communication signal may travel via AC coupling. Each communication signal may be buffered on each power management circuit 121. Buffering is advantageous since the first and last power management circuits 121 to be initialized are connected to the terminals of the power supply 110, allowing each power management circuit 121 to be initialized. The stack may include any number of power management circuits 121 for any overall power supply 110.

[0068] The last power management circuit 121 directly connected to the terminals of the power supply 110 within a stack including a plurality of power management circuits 121 may be connected to software enabling boundary scan. Boundary scan is a method for testing the interconnections or wiring on a PCB module. As previously explained, each power management circuit 121 may include a PCB module. This helps to solve any problems or issues within the hardware. If more increased bandwidth is required, there may be multiple communication channels enabling the flow of multiple communication signals between adjacent power management circuits. Advantageously, those communication signals may be synchronous, which means that they are transferred in real time between at least two power management circuits. Synchronous communication may be made using SPI (Serial Peripheral Interface) or I2C (Inter-Integrated Circuit).

[0069] FIG. 5 shows an exemplary graph 500 that illustrates how a power management system can be used to track a solar power source 110 and improve power extraction by a power management system. The graph 500 of FIG. 5 has the output voltage of the solar panel on the x-axis, the output current of the solar panel on the left side of the y-axis, and power on the right side of the y-axis. The current is shown as a solid line and the power is shown as a dashed line. The theoretically maximum power extraction is identified on the graph using a dotted line, and given the identification of the power peak that provides the maximum power Pmp, the ideal current Imp and the ideal voltage Vmp are identified. The current starts at around 5 A where the output voltage is 2 V, decreases to about 4.4 A as the output voltage increases from 2 V to 32 V from 5 A, and further decreases to 0 A as the output voltage increases from 32 V to 40 V from about 4.4 A. The power starts at around 10 W where the output voltage is 2 V, increases to 140 W as the output voltage increases from 2 V to 32 V from 10 W, and then decreases to 0 W as the output voltage increases from 32 V to 40 V from 140 W. Thus, it can be seen that the maximum power Pmp can be extracted when the panel output voltage Vmp is 32 V and the panel output current Imp is around 4.4 A. This is just an example, and when solar cells are used, the point of the individual maximum power IV (current-voltage) by the solar panel varies. A battery charging system such as a solar charge controller automatically tracks the load and extracts the increased amount of power from a given panel. When determining the increase in power extraction from the solar panel of the power source 110, it should be considered that the amount of current drawn by the power source 110 from each solar panel increases, and due to the DC resistance within each solar panel, the voltage may rapidly decrease and drop to 0 V.

[0070] Applying this to the present example, when the power source 110 is a renewable energy source such as solar energy, as the sun waxes and wanes with the changes in clouds and weather, the switching circuit 123 may use the change in the number of power management circuits in the active state to track the increase in power extraction like a solar charge controller. Although the solar power system is being tracked in FIG. 5, it will also be understood that other renewable energy sources may be tracked in the same way.

[0071] Each of FIGS. 6A - 7B shows exemplary circuit diagrams 600, 601, 700, 701 associated with various implementations of the power management system 100 or any part of the power management system 100 described herein. The diode 612 in each of the circuit diagrams of FIGS. 6A, 7A, and 7B is based on the premise that the ASICs for mining (processing elements 131, 710, 711) require a certain low - level second power source Valways even when the switching circuit 123 (shown in FIG. 6B) switches to an inactive state. Thus, due to the second power source Valways, the supply of Vdd may be turned off without requiring extensive re - initialization by the processing elements 131, 710, 711. In some examples, the power management circuits 121, 740, 741 write to the registers of the processing element 131, pause the PLL, turn off the clock, and stop the power consumption of the processing element 131 while using a low - output power source Vdd via a capacitor 613 and a diode 612 (as shown in FIGS. 6A, 7A, and 7B).

[0072] FIG. 6A shows a power management system 600 as an example including a plurality of power management circuits 121. The power management system 600 has the features of the power management system described herein. The power management system 600 also includes a central power controller 124. Each power management circuit 121 includes two switches 610, 611, a diode 612, and a capacitor 613, and is connected to the ASIC for mining (processing element 131) through a connector 122 (not shown in FIG. 6A, and previous circuit diagrams showed the connector 122). In practice, the two switches 610, 611, the diode 612, and the capacitor 613 of each power management circuit 121 are included in the switching circuit 123 of the corresponding power management circuit 121. Although only four power management circuits 121 are shown, the number of power management circuits 121 may be arbitrary.

[0073] In this manner, the controller 124 determines whether one of the plurality of power management circuits 121 should be in an active or inactive state based on the characteristics of the power supply 110 to the power management system 600 and at least one of the characteristics of the power management system 600, the mining ASIC (processing element 131), or the computing system 130 including the mining ASIC (processing element 131). Thus, there are two switches 610, 611 in the switching circuit 123. In other embodiments, the central power controller 124 may instead be one or more power controllers 124 included in each power management circuit 121 or included in the power management system 600. The second control signal 161 transmitted from the central power controller 124 to the switching circuit 123 is indicated by a dashed line.

[0074] Each mining ASIC of each power management circuit 121 is provided with a low voltage supply (second power source Valways), or more specifically, a Vdd supply between 0.6V and 0.85V. A Vdd supply of approximately 0.71V may be provided to each ASIC (processing element 131). When the power required for each processing element 131 is 11W, a 45mΩ resistor is used. The total voltage Vstack across multiple power management circuits will not increase beyond the product of n and Vdd, where n is equal to the number of ASICs (processing elements 131). The ASICs perform initialization very quickly. Therefore, to enable and stop the flow of current through each mining ASIC (processing element 131) by writing a few bytes to each power management circuit 121 and thereby effectively increase or decrease their power consumption, the UART communication protocol can be used. Power gating is a method of reducing power consumption by cutting off the current to a part of the circuit that is not in use, or in this case, by stopping the flow of current to the processing units 131 connected to the multiple power management circuits 121. To maintain effective load distribution, the voltage across both ends of each ASIC (processing element 131) is monitored by the controller 124. To dissipate the excess power not used by each ASIC (processing element 131), in each switching circuit 124 of each power management circuit 121, a current sinking transistor (i.e., switch 611) operates. In other words, each of the multiple power management circuits 121 is configured to adjust the power usage of each processing element 131 arranged to be connected to each of the multiple power management circuits 121 when the corresponding switching circuit 123 is in an active state.

[0075] For a given power supply 110, a plurality of mining ASICs (processing elements 131) can operate, i.e., a plurality of mining ASICs (processing elements 131) can be enabled, or the corresponding switching circuit 123 can be put into an active state so that the required Vdd (or sufficient power to enable processing) is maintained. When Vdd decreases below the sufficient power to enable processing for some power management circuits 121, the ASICs (processing elements 131) connected to those power management circuits 121 are removed from the chain by the controller 122 by sending a second control signal 161 for switching to an inactive state to the corresponding switching circuit 123. In this way, the length of the series chain becomes dynamic, and the number of power management circuits 121 in the active state becomes dynamic. Conversely, when Vdd increases, sufficient power can be provided to enable processing for more ASICs (processing elements 131). Therefore, by enabling the current (and the required Vdd) to pass through each ASIC (processing element 131), more mining ASICs (processing elements 131) operate. The current of the stack may be set by the ASIC (processing element 131), and the voltage requirement may be enforced by the power management system 600.

[0076] FIG. 6B shows an exemplary diagram of a plurality of power management circuits 121 of the power management system 601. Each mining ASIC (processing element 131) or a set of n ASICs sharing a voltage domain is connected to the switching circuit 123 through a connector 122 (not shown in FIG. 6B) within the power management circuit 121 of the power management system 601. Each switching circuit 123 includes a transistor-based element, more specifically a P-MOSFET. Thereby, since the power management circuit 121 is essentially modular and has the ability to control the power consumption of each ASIC (processing element 131), the length of the stack of the power management circuits 121 can be made dynamic.

[0077] As already explained, the current of the stack is set by the ASIC (processing element 131), and separately, the power management system 601 enforces the voltage requirement by conducting the amount of current required through each ASIC (processing element 131). Only the current due to the imbalance may be carried by the switching circuit 123, because the switching circuit 123 serves as protection for each ASIC (processing element 131). In other words, the switching circuit 123 will dissipate the excess power only when the input voltage exceeds the set value. When all ASICs (processing elements 131) are operating at the same power, the chain of ASICs is not imbalanced and no current flows through the PFET. When the voltage of an ASIC rises (i.e., the current it uses is small), the PFET conducts slightly so that the differential voltage remains constant, and dissipates the current not used by the ASIC. Conversely, when the voltage across an ASIC decreases (i.e., the ASIC is drawing more current than other ASICs or more current than in its past state), the voltage across the other ASICs will rise substantially in proportion to the total number of ASICs in the chain. This activates the power protection within the other power management circuits, i.e., the PFET conducts and dissipates the current. In other words, in some examples, the ASIC that draws the most current will set the total current for the loop, and all other ASICs will draw that amount of current and activate all of the PFETs, and the current dissipated should be zero.

[0078] Due to the power management system 601, the processing element 131 rapidly and dynamically rotates within the computing system 130 (not shown in FIG. 6B), i.e., switches the on / off of the corresponding FET (switching circuit 123) to improve the load and balance the power across the entire stack of ASICs. Further, the power management system 601 dynamically switches the mining ASICs (processing elements 131) within the series stack.

[0079] Figures 7A - 7B illustrate exemplary diagrams of power management systems 700, 701 that include multiple power management circuits. Figure 7A shows an example 700 where three power management circuits 740 are in an active state and one power management circuit 741 is in an inactive state, while Figure 7B shows an example 701 where one power management circuit 740 is in an active state and three power management circuits 741 are in an inactive state. The exemplary power management system 700 provided in Figures 7A - 7B uses the same configuration as the power management system 600 in Figure 6A, but in Figures 7A - 7B, varying levels of power are input to the power management system 700. Each of the power management circuits 740, 741 includes the same diode 612 and capacitor 613 as in Figure 6A for a low - level second power source Valways. Although only four power management circuits are shown in each of the examples, the number of power management circuits can be arbitrary. The second control signal 161 is transmitted from the central power controller 124 to the switching circuit 123, which is shown by a dotted line.

[0080] The active power management circuit 740 includes a first open switch 720 and a first closed switch 730 respectively. Due to the second control signal 161 (shown by a dotted line) from the controller 124, the first open switch 720 is open and the first closed switch 730 is closed. The second control signal 161 determines whether the switching circuit is in an active state or an inactive state. In this example, the switches 720, 730 are in an active state. The flow of current from the DC supply 110 is shown using thick solid lines, and it can be seen that it passes through each first closed switch 730 of the active power management circuit 740, the mining ASIC 710, and then flows to the next power management circuit. In other words, the switching circuit is in an active state and the mining ASIC has sufficient power to hash data.

[0081] The inactive power management circuit 741 includes a second open switch 731 and a second closed switch 721 respectively. Due to the second control signal 161 (shown by the dotted line) from the controller 124, the second open switch 731 is open and the second closed switch 721 is closed. In these circuit diagrams, the second open switch 731 is shown as "open" in that no current flows through the mining ASIC 711. The second open switch 731 inhibits the mining ASIC 711 and allows the current to bypass the mining ASIC 711. The second control signal 161 determines whether the switching circuit is in the active state or the inactive state. In this example, the switches 721 and 731 are in the active state. The flow of current from the DC supply 110 is shown using a thick solid line, flowing to the second closed switch 730, completely bypassing the mining ASIC 711 and then flowing to the next power management circuit, and it can be seen that a bypass circuit including the capacitor 613 shown by the dashed line is activated. In other words, the switching circuit is in the inactive state and the mining ASIC does not have sufficient power to hash data.

[0082] Each of FIGS. 7A - 7B shows the same power management system, but with different weather conditions in each figure when the DC power source is a solar power generation type. In FIG. 7A, there are more clouds pulling in than the clouds flowing in front of the sun, so that more sunlight hits the solar panel, and as a result, the power supply increases. In this example, there is sufficient power source 110 to supply most of the mining ASICs 710, 711 (there are more operating mining ASICs than the suppressed mining ASICs). In FIG. 7B, there are more clouds flowing in front of the sun than the clouds pulling in, so that less sunlight hits the solar panel than before, and as a result, the power supply decreases. In this example, since the power source 110 is insufficient to enable processing in most of the mining ASICs 710, 711, many of the ASICs 710, 711 are bypassed by the corresponding switching circuits (there are more suppressed mining ASICs than the operating mining ASICs). These figures reinforce the idea that the ASICs 710, 711 are dynamically rotated within the computing system 130. One or more ASICs in each of FIGS. 7A - 7B are dynamically rotated within the computing system 130 depending on the variable input power source 110.

[0083] In any of FIGS. 8A - 8G, the voltage clamp circuit referred to may also be described as the switching circuit 123. FIG. 8A shows an exemplary circuit diagram of a voltage clamp 800 of the switching circuit 123 of a certain power management circuit 121. The voltage clamp should be able to sink all the current (i.e., allow all the current to flow) in order to enable the processing of the processing element 131 (not shown in FIG. 8A). FIG. 800 provides two input voltages V3, V4, where the first input voltage V3 is provided at the second power source Valways and the enable input, and the second input voltage V4 is provided at the reverse second power source Vnegalways. It may not be necessary to have the reverse second power source Vnegalways. At the location where the processing element 131 can be observed (at the output), the high power rail Vhigh and the low power rail Vlow are in parallel with the output, and there is a fixed voltage drop at the output.

[0084] In this example, the following test conditions were used: a voltage sweep between 0V and 1V (or a voltage that periodically changes between 0V and 1V), along with a fixed voltage drop V5; and a resistor (or load) on the output rail having a resistance value of 0.005Ω. When the voltage clamp circuit is fully saturated, the current increases. As previously explained, the processing element 131 that can be observed between the output rails can be provided with a Vdd supply between 0.6V and 0.85V. Therefore, the provided voltage clamp circuit can have a limit of approximately 875mV once saturated, and the increase in current is as follows:

Number

[0085] FIG. 8B shows an exemplary graph 801 of the voltage of the voltage clamp of FIG. 8A when the voltage of the power supply 110 is supplied to the power management circuit 121. As seen in FIG. 8B, a dashed line depicting the voltage and a solid line depicting the current of the voltage clamp in the switching circuit 123 of the power management circuit 121 are shown. The x-axis indicates time in milliseconds, the left side of the y-axis indicates voltage in mV, and the right side of the y-axis indicates current in A. When the voltage is lower than the voltage at full saturation (i.e., V < 875mV), the voltage clamp circuit draws only approximately 0A of current. When the voltage increases beyond the voltage at full saturation, the voltage clamp circuit draws current (e.g., 25A). As soon as the voltage attempts to exceed the threshold (e.g., 875mv), the voltage clamp operates like a diode. In some embodiments, stopping the voltage from reaching the processing element 131 and removing the processing element 131 from the chain of the power management circuit 121 can be performed synchronously, but requires fine tuning so that the voltage clamp operates as a protection mechanism.

[0086] FIG. 8C shows an exemplary circuit diagram of a plurality of voltage clamps 802 of the switching circuit 123 of the plurality of power management circuits 121. The plurality of voltage clamps 802 are similar to the voltage clamp 800 provided in FIG. 8A. Similar to FIG. 8A, the plurality of voltage clamps 802 include a second power supply Valways, an enable input powered by the second input voltage Valways, and a reverse second power supply Vnegalways powered by the first input voltage V06. A voltage V07 is provided at a location where the processing element 131 can be observed (at the output). Also, the high power rail Vhigh and the low power rail Vlow are in parallel with each other at the output, and there is a voltage drop at the output. The voltage drop is between each of the plurality of nodes V01, V02, V03, V04, V05. In this way, the first voltage drop V(V01) is equal to the voltage at the first node V01, the second voltage drop V(V02-V01) is equal to the difference between the voltage at the second node V01 and the voltage at the first node V01, the third voltage drop V(V03-V02) is equal to the difference between the voltage at the third node V03 and the voltage at the second node V02, the fourth voltage drop V(V04-V03) is equal to the difference between the voltage at the fourth node V04 and the voltage at the third node V03, and the fifth voltage drop V(V05-V04) is equal to the difference between the voltage at the fifth node V05 and the voltage at the fourth node V04. In this example, the following test conditions were used: a sweep of the voltage between 0V and 5V (or a voltage that periodically changes between 0V and 5V), the input voltage V3; and a plurality of resistors (or loads) R01, R02, R03, R04, R05 across both ends of the output rail of each voltage clamp having any of the following resistance values: 100MΩ to provide a test fixed condition for an infinite load (ideal load), 45mΩ to provide a test fixed condition for a heavy load, or an asymmetric load across both ends of the voltage clamp to provide a test fixed condition for imbalance. The first resistor R01 spans the first voltage drop V(V01), the second resistor R02 spans the second voltage drop V(V02-V01), the third resistor R03 spans the third voltage drop V(V03-V02), the fourth resistor R04 spans the fourth voltage drop V(V04-V03), and the fifth resistor R05 spans the fifth voltage drop V(V05-V04).

[0087] In each of FIGS. 8D, 8F, and 8H, the first voltage drop V(V01) is depicted by a dashed line, the second voltage drop V(V02 - V01) is depicted by a dotted line, the third voltage drop V(V03 - V02) is depicted by a one-dot chain line, the fourth voltage drop V(V04 - V03) is depicted by a long dashed line, and the fifth voltage drop V(V05 - V04) is depicted by a two-dot chain line. Each of FIGS. 8E, 8G, and 8I shows the voltage of each node instead of the voltage drop. Therefore, the voltage V(V01) of the first node V01 is depicted by a dashed line, the voltage V(V02) of the second node V02 is depicted by a dotted line, the voltage V(V03) of the third node V03 is depicted by a one-dot chain line, the voltage V(V04) of the fourth node V04 is depicted by a long dashed line, and the voltage V(V05 - V04) of the fifth node V05 is depicted by a two-dot chain line. Further, the current I(V) of the plurality of voltage clamps 802 in FIG. 8C is depicted by a solid line.

[0088] FIG. 8D shows an exemplary graph 803 of the voltage drop between each adjacent node V01, V02, V03, V04, V05 of the plurality of voltage clamps 802 in FIG. 8C when the voltage of the power supply 110 is supplied to the plurality of power management circuits 121 and the load is ideal. FIG. 8E shows an exemplary graph 804 of the current of the plurality of voltage clamps 802 in FIG. 8C when the voltage of the power supply 110 is supplied to the plurality of power management circuits 121 and the load is ideal. The x-axis represents the increase in time (from left to right) in milliseconds. The y-axis represents the voltage drop in volts.

[0089] As can be seen, the first and second voltage drops V(V01), V(V02 - V01) are the first two voltage drops that reach approximately 0.8V. The third and fourth voltage drops V(V03 - V02), V(V04 - V03) are the next two voltage drops that reach 0.8V. The fifth voltage drop V(V05 - V04) is the last to reach 0.8V, but once it does, all the voltage drops increase rapidly. In other words, the voltages across the first and second resistors R02, R02 increase first, and then the voltages across the third to fifth resistors R03, R04, R05 increase respectively, and these voltages increase rapidly and synchronously. This means that when the voltage across the load R05 reaches 0.8V, it means that the total voltage Vstack across multiple power management circuits has been reached.

[0090] As seen in FIG. 8E, the x-axis represents time in milliseconds, the left side of the y-axis represents the node voltage in volts, and the right side of the y-axis represents the stack current in amperes. When the voltage Vstack across multiple power management circuits has been reached (i.e., approximately 0.8V), the current in the multiple voltage clamps 802 in FIG. 8C increases exponentially.

[0091] FIG. 8F shows an exemplary graph 805 of voltage drops V(V01), V(V02-V01), V(V03-V02), V(V04-V03), V(V05-V04) between adjacent nodes V01, V02, V03, V04, V05 of the plurality of voltage clamps 802 in FIG. 8C when the voltage of the power supply 110 is supplied to the plurality of power management circuits 121 and the load is heavy. The x-axis represents the increase in time (from left to right) in milliseconds. The y-axis represents the voltage drop in volts. As can be seen, unlike the voltages seen in FIGS. 8D-8E, the voltage drops V(V01), V(V02-V01), V(V03-V02), V(V04-V03), V(V05-V04) across the loads R01, R02, R03, R04, R05 all increase simultaneously because the tracking of the differential voltage is tight. The voltage drops V(V01), V(V02-V01), V(V03-V02), V(V04-V03), V(V05-V04) become flat when the FETs in the power management circuit 121 start to conduct excess current.

[0092] FIG. 8G shows an exemplary graph 806 of the current I(V) of the plurality of voltage clamps 802 in FIG. 8C when the voltage of the power supply 110 is supplied to the plurality of power management circuits 121 and the load is heavy. The x-axis represents time in milliseconds, the left side of the y-axis represents the node voltage in volts, and the right side of the y-axis represents the stack current in amperes. When the voltage Vstack across the plurality of power management circuits has reached (i.e., about 0.8V), the current of the plurality of voltage clamps 802 in FIG. 8C increases exponentially.

[0093] FIG. 8H shows an exemplary graph 807 of voltage drops V(V01), V(V02-V01), V(V03-V02), V(V04-V03), V(V05-V04) between adjacent nodes V01, V02, V03, V04, V05 of the plurality of voltage clamps 802 of FIG. 8C when the voltage of the power supply 110 is supplied to the plurality of power management circuits 121 and the load is asymmetric. In this example, each of the loads R01, R02, R03, R05 has the same resistance value as a test fixed condition for a heavy load (45 mΩ), but the fourth resistor R04 has a resistance value of 50 Ω to create asymmetry. The load R04 acts as a defect in the circuit. The x-axis represents the increase in time (from left to right) in milliseconds. The y-axis represents the voltage drop in volts. If provided to the output power rail, the voltage drop V(V04-V03) clamps at approximately 825 mV to protect the processing element 131.

[0094] FIG. 8I shows an exemplary graph 808 of the current I(V) of the plurality of voltage clamps 802 of FIG. 8C when the voltage of the power supply 110 is supplied to the plurality of power management circuits 121 and the load is asymmetric. As above, the load R04 acts as a defect in the circuit. The x-axis represents time in milliseconds, the left side of the y-axis represents the node voltage in volts, and the right side of the y-axis represents the stack current in amperes. The current I(V) remains relatively unchanged compared to FIG. 8G due to the protection circuit provided to the switching circuit 123 including the voltage clamp.

[0095] Figure 8J shows an exemplary graph 809 of the stack current in either the case where the load is heavy (indicated by the thick solid line) or the load is asymmetric (indicated by the solid line). The x-axis represents the increase in time (from left to right) in milliseconds. The y-axis represents the stack current in amperes. Figure 8J shows an exemplary graph 809 of the stack current in either the case where the load is heavy (indicated by the thick solid line) or the load is asymmetric (indicated by the solid line). When there is an asymmetric load, there is additional current on the FET. The kinks shown on the right side of the graph for both lines indicate that if the voltage continues to increase, all the FETs will sharply increase the current.

[0096] Figure 9A shows an exemplary circuit diagram of a power management system 900 including a plurality of voltage clamps and a plurality of power controllers 124 of a switching circuit 123 of a plurality of power management circuits 121 together with a power supply 110. The plurality of voltage clamps are similar to the plurality of voltage clamps in Figure 8C and the voltage clamps provided in Figure 8A. In this example, each voltage clamp of the plurality of voltage clamps has the same inputs and outputs of a second power supply Valways, an inverse second power supply Vnegalways, an enable input Enable, a high power rail Vhigh, and a low power rail Vlow. The plurality of voltage clamps includes a plurality of loads R30, R31, R32,..., R3n, and a plurality of voltage drops V10, V11, V12,..., V1n can be seen at the output of each of the voltage clamps. The voltage clamps of the switching circuit 123 are connected to the plurality of power controllers 124 within the power management system 120. In this example, the plurality of power controllers 124 includes a plurality of comparators U10, U11, U12,..., U1n, and a plurality of resistors R10, R11, R12,..., R1n and R20, R21, R22,..., R2n together with other filtering components within a filter 910. There are common input voltages Vinput, Vlocal, Vneglocal, Vreference throughout the circuit diagram.

[0097] In the stack of comparators U10, U11, U12, ..., U1n, which provide the function of the power controller 124 and each have the same resistance value, as the voltage rises, the current travels through the stack. Therefore, the transistor base element at the top of the stack is driven into deeper saturation to resist the increase in voltage. As the voltage continues to increase, more comparators turn on in such a way that the bottom comparator of the stack turns on first and the top comparator of the stack turns on last. This example provides a basic scenario. Each comparator within the stack of comparators U10, U11, U12, ..., U1n may be integrated as the power controller 124 into each power management circuit 121, or in an embodiment having a central controller, may be integrated into a single circuit to form the central controller 124.

[0098] In some examples, there may be a field programmable gate array (FPGA) with a look-up table dynamically written by software to determine which comparator connects a path to which transistor base element to turn on or off each transistor base element. In this example, the chain is shortened and lengthened at the top of the stack. In some examples, based on a software-based decision, there may be an analog-to-digital converter (ADC) having a processor and a digital output to turn off or on each transistor base element. In some examples, a circuit may be prototyped using a digital signal processor (DSP). Further, FIG. 9B shows an exemplary graph 901 displaying how the voltage of the power supply 110 in the exemplary circuit diagram of FIG. 9A increases in 10 ms units from 0V to 10V. As the voltage of the power supply 110 rises or falls, a toggle of the value of the enable line connected to Venable of the plurality of power management circuits can be performed so that the effective length of the chain can change dynamically based on the stack voltage.

[0099] FIG. 9C shows an exemplary graph 902 displaying the differential voltage across each processing element 131 connected to the connector 122 of each of the plurality of power management circuits 121 in the exemplary circuit diagram of FIG. 9A, where the power supply 110 includes the voltage of FIG. 9B, and FIG. 9D shows an exemplary graph displaying the voltage when each switching circuit 123 of each of the power management circuits 121 in the exemplary circuit diagram of FIG. 9A is switched to the active state, where the power supply 110 includes the voltage of FIG. 9B. The x-axis shows the increase in time (from left to right) in milliseconds, and the y-axis shows the voltage in volts or millivolts. The operating voltages across both ends of each processing element 131 connected to the connector 122 of each power management circuit in FIG. 9A are shown in FIG. 9C. As the voltage rises in the stack of comparators, more comparators turn on. This can be seen in FIG. 9C, as the time is moved from left to right along the x-axis, each comparator in the stack turns on in sequence. As can be seen in graph 902, the operating voltages across both ends of each processing element 131 remain within a limited range as the voltage rises from the supplied power. In FIG. 9D, the power management circuits 121 switch to the active state in sequence from the bottom to the top of the stack in the order shown in FIG. 9A and turn on from left to right over time in the figure. In this way, based on the total voltage Vstack across the plurality of power management circuits (or stack), the enable line gradually switches from low to high. Since the voltage increases dynamically within the stack, voltage drift may be apparent. Some Vdd voltage may be required to activate the processing element. In other examples, the total voltage Vstack across the stack may be required to activate the processing element.

[0100] In an alternative embodiment, it is possible to use an AC rectified main power supply as the input voltage. Assuming that the AC rectified main power supply has a variable voltage, the present disclosure can increase the power transmitted by the AC rectified main power supply. FIG. 10A shows an exemplary graph 1000 displaying the rectified AC main power supply of the power management system. When the AC rectified main power supply is used, the capacity of the processing by the processing element 131 increases. When the AC rectified main power supply is used, the inefficiencies of other examples can be reduced because optical isolation can be used for AC. The graph of FIG. 10A shows time on the x-axis and the number of power management circuits 121 for which the corresponding switching circuit 123 is switched to the active state on the y-axis. As can be seen over time, the number of active switching circuits 123 rises and falls due to the characteristics of the power supply 110, such as voltage fluctuations. However, in the rectified signal, the number of power management circuits 121 for which the corresponding switching circuit 123 is switched to the active state can cycle depending on one or more characteristics of at least one of the power management system, the processing element, or the computing system 130, more specifically the temperature characteristics. Thus, the power management system 120 can repeatedly activate and deactivate the processing elements via those power management circuits 121 by matching the power across the stack of processing elements 131 with the varying power transmitted by the rectified AC voltage. Advantageously, the repetitive nature of the rectified AC main power supply means that the power profile of the rectified AC main power supply can be predicted and closely mapped to convey an increased processing power capability within the computing system 130.

[0101] The graph of FIG. 10B shows the problem of load distribution across the power supply by the rectified AC backbone power supply. Each of the lines in graph 1001 represents the voltage across each of the power management circuits of FIG. 9A. The group of lines with lower voltages represents oversubscribed ASICs that are used when the voltage of the power supply is low, and the group of lines with higher voltages represents undersubscribed ASICs that can only be used when the voltage of the power supply is high. This can occur when the number of active switching circuits 123 goes up and down due to the characteristics of the power supply, which may include the voltage of the power supply and / or variations in the voltage of the power supply. This results in sub-optimal power extraction from the power supply by the oversubscribed ASICs. When the number of active switching circuits 123 also goes up and down due to the characteristics of at least one of the power management system, processing element, or computing system 130, more specifically the temperature characteristics, load distribution is improved as a result of various processing elements 131 being provided with sufficient power to enable processing. If a processing element 131 is excessive in terms of heat, a temperature sensor may be used to determine the hottest component within the power management system and deactivate the corresponding processing element. Based on job scheduling and power distribution across the entire ASIC stack, various processing elements 131 may be determined to be activated or deactivated. This example may be made possible through the use of an improved interface between the switching circuit 123 (or comparator or op-amp) and the processing element 131 (or FET). Since the processing elements 131 can be rotated quickly and dynamically in the computing system 130, due to the improved load distribution, the processing elements 131 can be operated in a slightly hotter state than normal operation.

[0102] The power management system for use with the computing system 130 disclosed herein may be included in a method for managing the transmission of power to a computing system 130 that includes a plurality of processing elements. The method includes: in one or more power controllers 124, based on one or more characteristics of a power source, determining whether a switching circuit 123 of a plurality of power management circuits arranged to be connected in series between terminals of the power source should be in an active state in which sufficient power is provided to enable processing to a processing element 131 arranged to be connected via a connector 122 of the power management circuit from the power source and execute application-specific processing, or (ii) a non-active state in which sufficient power is not provided to enable processing to the processing element; and transmitting, from one or more power controllers 124 to a switching circuit 123 of a plurality of power management circuits, a control signal 160 / 161 based on the determined state so that the switching circuit 123 can switch between the active state and the non-active state based on the control signal 160 / 161. One or more computer-readable temporary or non-temporary storage media embodying software operable to perform the method disclosed herein at runtime may be included. Further, there may be a power controller 124 for managing the transmission of power to a computing system 130 that includes a plurality of processing elements, the power controller 124 being arranged to perform the method disclosed herein as a method.

[0103] FIG. 11 shows a flowchart 1100 for explaining a process of controlling a power management system. Although the disclosed method may be implemented as a software power controller, it will be understood that the method may be implemented by other means. In operation 1110, one or more characteristics of a power supply may be received. In operation 1110, software power controller 124 may receive one or more characteristics of a power supply. The power supply may be any of the power supplies described herein or any other power supply. Next, in operation 1120, a first control signal is determined based on one or more characteristics of the power supply. Separately, in operation 1130, a second control signal may also be determined based on one or more characteristics of the power supply. The first and second control signals may be the first and second control signals 160, 161 described herein. In some examples, the first control signal 160 is transmitted to a processing element of a computing system via a connector of a power management circuit. In some examples, the second control signal 161 is transmitted to a switching circuit of a power management circuit. The first control signal may be transmitted to the processing element and the second control signal may be transmitted to the switching circuit. Next, in operation 1150, it may be determined whether the first or second control signal has disabled or re-enabled the processing element. If the processing element has not been disabled or re-enabled, the power management system may wait for a subsequent reception of one or more characteristics of the power supply in operation 1110 for a period of time. If the processing element has been disabled or re-enabled, in 1160, it is determined whether the processing element has been disabled or enabled. If the processing element has been disabled, in operation 1160a, the registers of the processing element are read, and then the power management system may wait for a subsequent reception of one or more characteristics of the power supply in operation 1110 for a period of time. If the processing element has been enabled, in operation 1160b, the registers of the processing element are refreshed or written, and then the power management system may wait for a subsequent reception of one or more characteristics of the power supply in operation 1110 for a period of time. The order of the steps of the above method is not bound by the order of the steps of the method in the flowchart, and those steps of the method may occur in any order if possible.While the controller may implement this process in software, a hardware implementation of the above method would follow the same process.

[0104] FIG. 12 depicts an exemplary block diagram showing a system 1200 for performing the techniques described herein. In particular, FIG. 12 shows how a power management system 1210 including a power controller 1220 and a switching circuit 1230 can communicate with a user device 1250 and a server or data store 1260 via one or more networks 1240. System 1200 includes a user device 1250 that communicates with a server computing device (e.g., server 1260) via a network 1240 (e.g., the Internet, a cable network, a cellular network, a cloud network, a wireless network (e.g., Wi-Fi) and a wired network, as well as short-range communication such as Bluetooth® and BLE (Bluetooth® Low Energy)). Although a single user device 1250 is shown, in additional or alternative examples, system 1200 can have multiple user devices. System 1200 also includes a computing system 1270 that performs application-specific processing such as cryptocurrency mining.

[0105] In at least one example, user device 1250 can be any suitable type of computing device, such as a portable, semi-portable, semi-fixed, or fixed computing device. Some examples of user device 1250 include, but are not limited to, tablet computing devices, smartphones or mobile communication devices, laptops, netbooks or other portable or semi-portable computers, desktop computing devices, terminal computing devices or other semi-fixed or fixed computing devices, dedicated devices, wearable computing devices or other body-mounted computing devices, augmented reality devices, virtual reality devices, Internet of Things (IoT) devices, and the like. That is, user device 1250 can be any computing device capable of transmitting communication signals and executing functions according to the techniques described herein. User device 1250 can include devices such as, for example, a payment card reader or a component capable of accepting payments, as described below.

[0106] In the illustrated example, user device 1250 includes one or more processors 1251, one or more computer-readable media 1252, one or more communication interfaces 1253, one or more input / output (I / O) devices 1254, a display 1255, and a sensor 1256.

[0107] In at least one example, each processor 1251 can itself include one or more processors or processor cores. For example, processor 1251 can be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that operates signals based on a group of operational instructions. In some examples, processor 1251 can be one or more suitable types of hardware processors and / or logic circuits that are specifically programmed or configured to execute the algorithms and processes described herein. Processor 1251 can be configured to obtain and execute a set of computer-readable and processor-executable instructions stored within computer-readable medium 1252.

[0108] Depending on the configuration of user device 1250, computer-readable medium 1252 may be an example of a tangible non-transitory or transitory computer storage medium, and may include volatile and non-volatile memories implemented with any type of technology for storing information such as computer-readable and processor-executable instructions, data structures, program components, or other data, and / or removable and non-removable media. Computer-readable medium 1252 may include, but is not limited to, technologies of RAM, ROM, EEPROM, flash memory, solid state storage, magnetic disk storage, optical storage, and / or other computer-readable media. Further, in some examples, user device 1250 may access external storage such as RAID storage systems, storage arrays, network-attached storage, storage area networks, cloud storage, or other media that can be used for storing information and that are accessible by processor 1251 directly or through other computing devices or networks. Thus, computer-readable medium 1252 may be a computer storage medium capable of storing instructions, components, or components executable by processor 1251. Further, when referred to, non-transitory computer-readable storage media exclude media such as energy, carrier signals, electromagnetic waves, and signals themselves.

[0109] The computer-readable medium 1252 can be used to store any number of functional components executable by the processor 1251. In some implementations, those functional components are groups of instructions or programs executable by the processor 1251 that, when executed, implement the operational logic for performing the actions and services attributed above on the user device 1250. The functional components stored within the computer-readable medium 1252 can include a user interface 1257 that enables a user to interact with the user device 1250 and with the server 1260 and / or other network-connected devices such as, for example, the power management system 1210 or the computing system 1270. In at least one example, the user interface 1257 can be presented via a web browser or the like. In other examples, the user interface 1257 can be presented via an application such as a mobile application or a desktop application, which can be provided by a service provider associated with the server 1260 or other computing devices on the network or can otherwise be a dedicated application. In some examples, the user interface 1257 can provide means for a user to perform either direct control or monitoring of processing in the computing system 1270 or direct control or monitoring of the power management system 1210. For example, the user interface 1257 may enable a user to directly switch off or on the power supply to a particular application-specific processor. In at least one example, a user can interact with the user interface via touch input, voice input, gesture, or any other type of input. The word "input" is also used to describe "contextual" input that may not be directly provided by the user via the user interface 1257.For example, an interaction by a user with the user interface 1257 may be analyzed to determine the user's context or intent, for example using natural language processing techniques, and may be treated in a manner similar to "direct" user input.

[0110] Depending on the type of the user device 1257, the computer-readable medium 1252 may optionally include other functional components and data, such as other components and data 1258 including programs, drivers, etc., and data used or generated by the functional components. Additionally, the computer-readable medium 1252 may store data and data structures used by the functional components. Further, the user device 1250 can include many other logical, programmatic, and physical components, and those described herein are merely examples relevant to the discussion here.

[0111] In at least one example, the computer-readable medium 1252 may include additional functional components such as an operating system 1259 to control and manage the various functions of the user device 1250 and to enable basic user interactions.

[0112] The communication interface 1253 can include one or more interfaces and hardware components to enable communication with various other devices, such as over or directly on the network 1240. For example, the communication interface 1253 can enable communication through one or more networks 1240, which can include any type of network known in the art, such as, but not limited to, a local area network or a wide area network such as the Internet, a wireless network such as a cellular network, a cloud network, a local wireless network such as Wi-Fi, and / or short-range wireless communications such as Bluetooth®, BLE, NFC, RFID, a wired network, or any other such network or any combination thereof. Thus, the network 906 can include both wired and / or wireless communication technologies, including wired or fiber optic technology in addition to Bluetooth®, BLE, and Wi-Fi, cellular communication technologies. The components used for such communication can depend at least in part on the type of network, the selected environment, or both. Protocols for communicating over such networks are well known and will not be discussed in detail here.

[0113] In some implementations, some of the above functionality may be provided to the user through a cloud computing infrastructure. Cloud computing refers to enabling convenient on-demand network access to a shared pool of configurable computing resources that can be rapidly provisioned and released with minimal management effort or interaction with a service provider, providing scalable computing resources on a network as a service. Thus, cloud computing enables a user to access virtual computing resources (such as storage, data, applications, and even fully virtualized computing systems) within the "cloud" regardless of the physical system (or the location of those systems) that serves as the underlying basis for providing the computing resources.

[0114] User device 1250 may further include one or more input / output (I / O) devices 1254. I / O devices 1254 may include speakers, microphones, cameras, various user controls (such as buttons, joysticks, keyboards, keypads, etc.), and haptic output devices. I / O devices 1254 may also include accessories that utilize accessories (such as audio jacks, USB-C, Bluetooth, etc.) to connect to user device 1250.

[0115] In at least one example, the user device 1250 may include a display 1255. Depending on the type of computing device used as the user device 1250, the display 1255 may employ any suitable display technology. For example, the display 1255 may be a liquid crystal display, a plasma display, a light-emitting diode display, an OLED (organic light-emitting diode) display, an electronic paper display, or any other suitable type of display capable of presenting digital content. In at least one example, the display 1255 may be an augmented reality display, a virtual reality display, or any other display capable of presenting and / or projecting digital content. In some examples, the display 1255 may have a touch sensor associated with the display 1255 to provide a touch screen display configured to receive touch input to enable interaction with the graphic interface presented on the display 1255. Thus, the implementation here is not limited to any specific display technology. Alternatively, in some examples, the user device 1250 may not include a display 1255, and information may be presented by other means such as voice or touch.

[0116] In addition, the user device 1250 may include a sensor 1256. The sensor 1256 may include a GPS device capable of indicating location information. Further, the sensor 1256 may include, without limitation, an accelerometer, a gyroscope, a compass, a proximity sensor, a camera, a microphone, and / or a switch.

[0117] In some examples, a GPS device can be used to identify a user's location. In at least one example, the user's location can be used by the service provider described above to provide one or more services. That is, in some examples, the service provider can implement geofencing to provide a specific service to the user. As an example, in a lending service, the location can be used to confirm that the stated purpose of the loan corresponds to the evidence of use (e.g., whether the use of the loan by the user is consistent with what the person stated they would use it for). Additionally, in some examples, the location can be used for the purpose of paying rewards. As an example, when a contractor completes a project, the contractor can provide geotagged images (e.g., those tagged based on location information available from a GPS device). In some examples, the location can be used to facilitate peer-to-peer payments among nearby users and / or to send notifications to the user regarding available appointments with stores located near the user. In at least one example, the location is used for the user to receive payment when a nearby customer leaves the geofence, or the location can be used to initiate an action in response to the user entering a seller's physical store or mining facility. The location can also be used in additional or alternative ways.

[0118] Additionally, the user device 1250 may include a variety of other components not shown, examples of which can include removable storage, a power source such as a battery and a power control unit, a barcode scanner, a printer, a cash drawer, and the like.

[0119] In addition, in some examples, the user device 1250 includes a reader device 1280 for reading an identifier associated with a payment means and / or a payment object, and can be connected to or otherwise coupled to the reader device 1280. In some examples, as described above, the reader device 1280 can be plugged into a port within the user device 1250, such as a microphone port, a headphone port, an audio jack, a data port, or other suitable port. In additional or alternative examples, the reader device 1280 can be coupled to the user device 1250 via other wired or wireless connections, such as via Bluetooth® or BLE. The reader device 1280 can include a reading head for reading the magnetic stripe of a payment card, and can further include an encryption technique for encrypting the information read from the magnetic stripe. Additionally or alternatively, the reader device 1280 can be an EMV payment reader that can be incorporated into the user device 1250 in some examples. Further, depending on the type and configuration of the user device 1250, many other types of readers can be employed along with the user device 1250 here.

[0120] The reader device 1280 may be a portable magnetic stripe card reader, an optical scanner, a smart card (a card with an embedded IC chip) reader (e.g., an EMV-compliant card reader or a near-field communication-compatible reader), or an RFID reader, etc., configured to detect and acquire data from any payment means. Thus, the reader device 1280 may include hardware implementations such as slots, magnetic tracks, and rails, along with one or more sensors or electrical contacts, to facilitate the detection and acceptance of payment means. That is, the reader device 1280 acquires payment data associated with a customer, and the reader device 1280 interacts with the payment means through swiping (i.e., a card transaction with a card where the customer slides a card with a magnetic stripe through the payment reader and the payment reader captures the payment data contained in the magnetic stripe), dipping (i.e., a card transaction with a card where the customer first inserts an embedded microchip (i.e., a chip) into the payment reader and waits until the payment reader prompts for the card to be removed), or tapping (i.e., a card transaction where the customer taps or holds their electronic device, such as a smartphone running a payment application, against the payment reader to complete a near-field communication transaction), and may include hardware implementations to enable such interactions. Additionally or optionally, the reader device 1280 may also include a biometric sensor that accepts and processes such biometric characteristics and processes them as a payment means, assuming that the biometric characteristics are registered with the payment service and are connected to a financial account with a bank server.

[0121] The reader device 1280 may include a processing unit, a computer-readable medium, a reader chip, a transaction chip, a timer, a clock, a network interface, and a power supply, among others. The processing unit of the reader device 1280 may execute one or more components and / or processes to cause the reader device 1280 to perform various functions as described above and further detailed in the following disclosure. In some examples, the processing unit may include a central processing unit (CPU), a graphics processing unit (GPU), a CPU and a GPU, or a processing unit or component known in the art. Additionally, each of the processing units may have its own local memory that can also store program components, program data, and / or one or more operating systems. Depending on the exact configuration and type of the reader device 1280, the computer-readable medium may include volatile memory (such as RAM), non-volatile memory (such as ROM, flash memory, a small hard drive, or a memory card), or some combination thereof. In at least one example, the computer-readable medium of the reader device 926 may include at least one component for performing various functions as described herein.

[0122] The reader chip may perform the functionality of controlling the operation and processing of the reader device 1280. That is, the reader chip may perform the functionality of controlling a payment interface (e.g., a contactless interface, a contact interface, etc.), a wireless communication interface, a wired interface, a user interface (e.g., a signal conditioning device (FPGA)), etc. Additionally, the reader chip may perform the functionality of controlling a timer that can provide a timer signal indicating the amount of elapsed time following a specific event (e.g., events such as an interaction or a power-down). Moreover, the reader chip may perform the functionality of controlling a clock that can provide a clock signal indicating time. Further, the reader chip may perform the functionality of controlling a network interface that can serve as an interface with the network 1240, as described below.

[0123] Additionally, the reader chip may perform the functionality of controlling the power supply. The power supply may include one or more power sources such as a physical connection to AC power or a battery. The power supply may include a power conversion circuit for converting AC power for use by components of the reader device 1280 and generating a plurality of DC voltages. If the power supply includes a battery, the battery may be charged via a physical power connection, via electromagnetic induction charging, or via any other suitable method.

[0124] The transaction chip can perform functions related to the processing of payment transactions, the interface with payment means, encryption, and other payment-specific functionalities. That is, the transaction chip may access payment data associated with the payment means as described above and may provide the payment data to the POS terminal. The payment data may include, but is not limited to, the customer's name, the customer's address, the type of payment means (e.g., credit, debit, etc.), the number associated with the payment means, the verification value associated with the payment means (e.g., PIN verification key indicator (PVKI), PIN verification value (PVV), card verification value (CVV), card verification code (CVC), etc.), the expiration date associated with the payment means, the primary account number (PAN) corresponding to the customer (which may or may not match the number associated with the payment means), restrictions on what types of billing / liabilities can be made, etc. Additionally, when receiving payment data, the transaction chip may encrypt the payment data.

[0125] The reader device 1280 can be arranged to receive payments in fiat currency, cryptocurrency, or any other suitable payment medium. When a user makes a payment using a user device 1250 connected to the reader device 1280, funds obtained directly or indirectly from cryptocurrency mined by the computing system 1270 can be used for the payment.

[0126] It should be understood that in some examples, the reader chip may have its own processing unit and computer-readable medium, and / or the transaction chip may have its own processing unit and computer-readable medium. In other examples, the functionality of the reader chip and the transaction chip may be embodied in a single chip or multiple chips, each including any suitable combination of a processing unit and a computer-readable medium for jointly performing the functionality of the reader chip and the transaction chip as described herein.

[0127] Although the user device 1250 and the reader device 1280, which can be POS terminals, are shown as separate devices, in additional or alternative examples, the user device 1250 and the reader device 1280 may be part of a single device, which may be a battery-operated device. In such examples, components of both the user device 1250 and the reader device 1280 may be associated with a single device. In some examples, the reader device 1280 may have an integrated display, which may be added (or alternative) to the display 1255 associated with the user device 1250.

[0128] The server 1260 may include one or more servers or other types of computing devices, which can be implemented in any number of ways. For example, in the case of a server, components, other functional components, and data can be implemented in a single server, a cluster of servers, a server farm or data center, a computing service hosted in the cloud, and a storage service hosted in the cloud, etc., but other computer architectures can also be used additionally or alternatively.

[0129] Server 1260 can be connected via network 1240 to any one or more of user device 1250, computing system 1270, and power controller 1220. The server can store data related to the activities of any perspective of these components of system 1200, or the interactions between one or more of these components of system 1200. For example, server 1260 can store data related to the cryptocurrency successfully mined. Server 1260 can store data related to the processes executed by computing system 1270. The server can store the account data associated with the user logging into user device 1250. Each of these functionalities may be provided by a single server or may be distributed across multiple servers.

[0130] Furthermore, although the figure shows the components and data of server or data store 1260 as existing in a single location, those components and data can alternatively be distributed in any way across different multiple computing devices and different multiple locations. As a result, those functions can be implemented by one or more server computing devices in such a way that the various functionalities described are distributed across different multiple computing devices in various ways. Multiple servers 1260 may be located together or separately and can be organized, for example, as virtual servers, server banks, and / or server farms. The described functionality can be provided by the servers of a single vendor or company, or can be provided by the servers and / or services of multiple different customers or companies.

[0131] When the server 126 executes the function of the data store, it may be configured to store data that is accessible, manageable, and updatable. In some examples, the data store 1260 may be integrated with the user device 1250 and / or the power controller 1220. In other examples, as shown in FIG. 12, the data store 1260 may be located remotely from the power controller 1220 and may be accessible to the power controller 1220. The data store 1260 may include a plurality of databases and / or a plurality of servers that are connected locally or remotely via the network 1240.

[0132] In at least one example, the data store 1240 may store user profiles that may include, for example, seller profiles, customer profiles, and miner profiles.

[0133] A merchant's profile may store or otherwise be associated with data related to the merchant. For example, a merchant's profile may include information about the merchant (such as the merchant's name, geographical location, business hours, employee information, etc.), the merchant's merchant category code (MCC), the items offered for sale by the merchant, the hardware used by the merchant (such as device type), transaction data associated with the merchant (such as transactions conducted by the merchant, payment data associated with the transactions, items associated with the transactions, descriptions of the items associated with the transactions, details and / or total expenditures of each transaction, parties to the transaction, dates, times, and / or locations associated with the transaction, etc.), loan information associated with the merchant (such as past loans made to the merchant, past defaults on such loans, etc.), risk information associated with the merchant (signs of risk, fraud cases, chargebacks, etc.), appointment information (such as past appointments, future (scheduled) appointments, timing of appointments, length of appointments, etc.), salary information (such as employees, salary payment frequency, salary amount, etc.), employee information, reservation data (previous reservations, future (scheduled) reservations, interactions associated with such reservations, etc.), inventory data, customer service data, etc., and may store or otherwise be associated with them. The merchant's profile may securely store bank account information as provided by the merchant. Additionally, the merchant's profile may store payment information associated with payment means linked to the merchant's balance, such as the balance maintained in the ledger by the service provider.

[0134] A customer profile may store customer data including, but not limited to, customer information (such as name, phone number, address, bank information, etc.), customer preferences (such as what has been learned or specified by the customer, etc.), purchase history data (such as what identifies one or more purchased items (and their respective item information), the payment means used for the purchase of one or more items, returns associated with one or more orders, the status of one or more orders (such as in preparation, packing, shipping, delivered, etc.), etc.), appointment data (such as previous appointments, future (scheduled) appointments, the timing of the appointments, the length of the appointments, etc.), salary data (such as employer, salary payment frequency, salary amount, etc.), reservation data (such as previous reservations, future (scheduled) reservations, reservation period, interactions associated with such reservations, etc.), inventory data, customer service data, etc.

[0135] A miner profile may store data related to the miner. For example, data related to the mining activities performed may be stored. Additionally, data related to the blocks on the blockchain successfully mined may be stored. If the miner is part of a mining pool, data related to the pool, other members of the pool, and other related data associated with the pool may be stored. In some implementations, the data store may store data on a private or public blockchain.

[0136] Furthermore, in at least one example, the data store 1240 may store an inventory database and / or a catalog database. As described above, the inventory may store data associated with the quantity of each item the seller has available for sale. Additionally, the catalog may store data associated with the items the seller has available for purchase. The data store 1240 may store additional or alternative types of data as described herein.

[0137] In the illustrated example, the power controller 1220 may include one or more processors 1221, one or more computer-readable media 1222, one or more I / O devices 1223, and one or more communication interfaces 1224. Each processor 1221 may be a single computing device or multiple computing devices, and may include a single or multiple computing units or multiple processing cores. The processor 1221 may be implemented as one or more microprocessors, microcomputers, microcontrollers, digital signal processors, central processing units, state machines, logic circuits, and / or any device that operates on signals based on a group of operation instructions. For example, the processor 1221 may be one or more suitable types of hardware processors and / or logic circuits that are specifically programmed or configured to execute the algorithms and processes described herein. The processor 1221 can be configured to obtain and execute a group of computer-readable instructions stored in the computer-readable media 1222, whereby the processor 1221 can be programmed to perform the functions described herein.

[0138] The computer-readable medium 1222 can include volatile and non-volatile memories implemented in any type of technology for storing information such as computer-readable instruction sets, data structures, program components, or other data, and / or removable and non-removable media. Such computer-readable media 1222 can include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, optical storage, solid-state storage, magnetic tape, magnetic disk storage, RAID storage systems, storage arrays, network-attached storage, storage area networks, cloud storage, or any other media that can be used to store desired information and is accessible by a computing device. Depending on the configuration of the power controller 1220, the computer-readable medium 1222 can be a type of computer-readable storage medium, and / or, in the scope excluding media such as energy, carrier signals, electromagnetic waves, and signals themselves when mentioned, can be a tangible non-transitory medium.

[0139] The computer-readable medium 1222 can be used to store any number of functional components executable by the processor 1221. In many implementations, these functional components include instruction sets or programs executable by the processor 1221 that, when executed, specifically configure one or more processors 1221 to perform actions attributed above with respect to the service provider and / or payment processing service.

[0140] One or more of the "components" referred to herein may be implemented as more components or fewer components, and the functions described for those components may be reassigned depending on the implementation details. The term "component" as used herein broadly refers to components of software, hardware, or firmware (or any combination thereof) stored in a non-transitory storage medium (e.g., volatile or non-volatile memory for a computing device). A module is typically a functional one that can generate useful data or other outputs using specified inputs. A component may or may not be self-contained. An application program (also referred to as an "application") may include one or more components, or a component may include one or more application programs, which may be accessed over a network or downloaded as software to a device (e.g., executable code that causes an action to be performed on the device). An application program (also referred to as an "application") may include one or more components, or a component may include one or more application programs. In additional and / or alternative examples, a component may be implemented as computer-readable instruction sets and various data structures that configure the computing device described herein via at least one processing unit to execute the instruction sets described herein and perform operations.

[0141] In some examples, a component may include one or more application programming interfaces (APIs) that perform some or all of its functionality (e.g., operations). In at least one example, a software development kit (SDK) may be provided by a service provider to enable third-party developers to incorporate the functionality of the service provider and / or to utilize the service provider's services in connection with the third party's own applications. Additionally or alternatively, in some examples, a service provider may be able to utilize the SDK to integrate the functionality of a third-party service provider into its own applications. That is, the APIs and / or SDKs can enable third-party developers to customize how their respective third-party applications interact with the service provider, and vice versa.

[0142] The computer-readable medium 1222 may additionally include an operating system for controlling and managing the various functions of the power controller 1220.

[0143] The communication interface 1224 may include one or more interfaces and hardware components to enable communication with various other devices, such as over the network 1240 or directly. For example, the communication interface 1224 can enable communication through one or more networks 1240, which may include any type of network known in the art, such as, but not limited to, a local area network or a wide area network such as the Internet, a wireless network such as a cellular network, a local wireless network such as Wi-Fi, and / or short-range wireless communications such as Bluetooth®, BLE, NFC, RFID, a wired network, or any other such network or any combination thereof. Thus, the network 1240 may include both wired and / or wireless communication technologies, including wired or fiber optic technology in addition to Bluetooth®, BLE, and Wi-Fi, cellular communication technologies. The components used for such communication may depend at least in part on the type of network, the selected environment, or both. Protocols for communicating over such networks are well known and will not be discussed in detail here.

[0144] Also, the communication interface 1222 can provide control signals from the power controller 1220 to the switching circuit 1230, which then controls whether power is transmitted to the components of the computing system 1270.

[0145] The power controller 1220 may further comprise various I / O devices 1223. Such I / O devices 1223 may include a display, various user interface controls (e.g., buttons, joysticks, keyboards, mice, touchscreens, biometric or sensory input devices, etc.), audio speakers, and connection ports, among others.

[0146] The power controller 1220 can control the switching circuit 1230 including the switching circuits 1 to 3 (1231, 1232, 1233) to the switching circuit n (1234). The control can be performed by the various methods described. And each of the switching circuits can control whether to transmit sufficient power to each of the application-specific processors or application-specific integrated circuits (ASICs) from ASIC 1 (1271), ASIC 2 (1271), ASIC 3 (1273) to ASIC n (1274) to enable processing. Although the power controller 1220 can determine whether to switch on or off a certain ASIC based on the measured characteristics from the input / output device 1223, for example, the power controller may be remotely controlled by the user device 1250 or another external computing system (not shown) additionally or alternatively. The user device 1250 may be able to change the parameters used to determine whether a certain ASIC should be turned on or off by the controller 1220. For example, the user device 1250 should be able to set the power controller 1220 to use as much as possible of the power available for mining cryptocurrency in the computing system 1270. Alternatively, the user device 1250 may be set to reserve a certain percentage of the power available for some other use. Also, the user device 1250 can set the range in which various inputs in the input / output device 1223 are used in the determination of whether to turn on or off a certain ASIC. For example, the user device 1250 may set the agreed temperature limit for the operation of the component. In some arrangements, the power management system 1210 may use power from both a variable renewable energy source and the grid. The user device 1250 may set the amount of power drawn from the grid.

[0147] FIG. 12 shows that the power management system 1210 includes the power controller 1220 and the switching circuit 1230. However, in an alternative arrangement, the power controller 1220 and the switching circuit 1230 are separate devices. For example, the switching circuit 1230 and the power controller 1220 may be located at different locations and communicate via the network 1240.

[0148] Phrases such as "in some examples", "according to various examples", "in the illustrated examples", "in one example", "in other examples", "various examples", and "some examples" generally mean that the specific features, structures, or characteristics following such phrases are included in at least one example of the present invention and may be included in more than one example of the present invention. In addition, such phrases do not necessarily refer to the same example or different examples.

[0149] If a certain component or feature is described in the specification as being "able to be" included, "may", "obtain", or "would" or having a certain feature, it is not a requirement that the specific component or feature be included or have that feature.

[0150] Furthermore, the foregoing description is directed to devices and applications related to payment technologies. However, it will be understood that the present technology can be extended to any device and application. Moreover, the techniques described herein can be configured to operate regardless of the type of payment object reader, POS terminal, web application, mobile application, POS topology, payment card, computer network, and environment.

[0151] The various drawings included herein are flowcharts showing exemplary methods including the techniques as described herein. The exemplary methods are described with reference to the components illustrated in the figures for purposes of understanding and assistance. However, the exemplary methods are not limited to execution using the components illustrated in the drawings, and such components are not limited to execution of the methods illustrated herein.

[0152] Furthermore, the methods described above are shown as a collection of blocks in a logical flow diagram, which represent a sequence of operations that can be implemented in hardware, software, or a combination thereof. In a software context, the blocks represent computer-executable instructions stored in one or more computer-readable storage media that, when executed by a processor, perform the recited operations. Generally, computer-executable instructions include routines, programs, objects, components, and data structures, among others, that perform a particular function or implement a particular abstract data type. The order in which the operations are described is not intended to be construed as a limitation, and any number of the recited blocks can be combined in any order and / or parallelized to implement the process. In some embodiments, one or more blocks of the process can be entirely omitted. Moreover, multiple methods can be combined, in whole or in part, with each other or with other methods.

[0153] Examples are presented below.

[0154] A power management system is disclosed for managing the delivery of power to a computing system that includes a plurality of processing elements. The power management system can include a plurality of power management circuits arranged to be connected in series between terminals of a power supply. Each power management circuit can include a connector for connecting the power management circuit to a processing element arranged to execute application-specific processing. Each power management circuit can also include a switching circuit arranged to switch between (i) an active state in which sufficient power is provided from the power supply to the processing element via the connector to enable processing, and (ii) an inactive state in which sufficient power is not provided to the processing element to enable processing, in response to a control signal. The power management system can also include one or more power controllers arranged to determine whether one of the plurality of power management circuits should be in an active state or an inactive state based on one or more characteristics of the power supply. The one or more power controllers can transmit a control signal to the one first switching circuit of the plurality of power management circuits based on the determined state. Advantageously, the processing level can be improved against variations in the characteristics of the power supply. Thus, more processing can be achieved within the range of power available from the power supply.

[0155] The one or more characteristics of the power supply can include the voltage of the power supply and / or variations in the voltage of the power supply. The power supply can have a variable voltage. The power supply can be a renewable energy source. Thus, the carbon footprint of such processing can be reduced. The plurality of power management circuits can include the one or more power controllers. Advantageously, the amount of processing can be improved against a changing input voltage and thus against power.

[0156] One or more of the power controllers may be a central power controller. The central power controller may include a processor and a memory, and the memory stores a computer-readable medium arranged to implement a method for controlling the power demand of the computing system on the processor. Each of the one or more power controllers may include one or more controller switching elements. Each controller switching element may be associated with a power management circuit among the plurality of power management circuits. Each controller switching element may be arranged to switch on or off according to whether a threshold value of the at least one characteristic is satisfied. The one or more power controllers are arranged to determine whether a switching circuit of one of the plurality of power management circuits should be in an active state or an inactive state based on at least one other characteristic of the power management system, the one or more processing elements arranged to be connected to one or more of the plurality of power management circuits in use, and the computing system to which the power managed by the power management system is transmitted. The at least one other characteristic may include a temperature characteristic, or one or more of one or more failures of the processing elements, the current state of the processing of the processing elements, and the current draw of the processing elements, and may include one or more of the states of the processing elements arranged to be connected to each of the plurality of power management circuits. Advantageously, a long lifespan of the hardware can be achieved. In addition, unnecessary processing can be avoided.

[0157] The switching circuit may include a transistor-based element having conductivity controlled by the control signal. Each of the plurality of power management circuits may be configured to adjust the power consumption of each processing element arranged to be connected to each of the plurality of power management circuits when the corresponding switching circuit is in an active state. The power supply may be a first power supply. The power management system may further include a second power supply. The second power supply may be arranged to transmit a sufficient level of power to the plurality of power management circuits to enable control of the power management circuits. The sufficient level of power to enable control of the power management circuits may be less than the power sufficient to enable processing by the processing elements.

[0158] The processing element may include at least one application-specific integrated circuit. The application-specific processing is one of cryptocurrency mining or artificial intelligence processing.

[0159] A system is also disclosed. The system may include the power management system described above. The system may also include a computing system including one or more processing elements. The computing system may include a central processing controller arranged to provide data for processing to each processing element. The central processing controller may control the processing operations executed by each processing element.

[0160] A method for managing the transmission of power to a computing system including a plurality of processing elements is disclosed. The method includes, in one or more power controllers, determining, based on one or more characteristics of a power source, whether a switching circuit of a plurality of power management circuits arranged to be connected in series between terminals of the power source should be in an active state in which sufficient power is provided to enable processing to a processing element connected via a connector of one of the power management circuits from the power source and arranged to perform application-specific processing, or in an inactive state in which sufficient power is not provided to enable processing to the processing element. The method may further include transmitting, from the one or more power controllers to a switching circuit of the plurality of power management circuits, a control signal based on the determined state such that the switching circuit can switch between the active state and the inactive state based on the control signal. The active state may be regarded as a processing state. The inactive state may be regarded as a non-processing state.

[0161] One or more computer-readable non-transitory storage media embodying executable software are disclosed. The computer-readable non-transitory storage media may be capable of implementing any of the methods disclosed herein.

[0162] A power controller for managing the transmission of power to a computing system including a plurality of processing elements is disclosed. The power controller may be arranged to execute any of the power control methods disclosed herein.

[0163] A power management circuit is disclosed that is arranged to be connected in series with one or more other power management circuits between terminals of a power supply so as to form a power management system for managing the transmission of power to a computing system including a plurality of processing elements. The power management circuit may include a connector for connecting the power management circuit to a processing element arranged to perform application-specific processing. The power management circuit includes a switching circuit arranged to switch between (i) an active state in which sufficient power is provided from the power supply to the processing element via the connector to enable processing, and (ii) an inactive state in which sufficient power is not provided to the processing element to enable processing, in response to a control signal based on one or more characteristics of the power supply.

[0164] A power management system for controlling the transmission of power to a plurality of processing elements is also disclosed. The power management system may include a plurality of power management circuits arranged between terminals of a power supply. Each power management circuit may be configured to connect to a processing element among the plurality of processing elements. Each power management circuit may be configured to either supply sufficient power for the processing element to perform processing or prevent the supply of sufficient power to the processing element associated with the power management circuit. The power management system may further include one or more power controllers arranged to determine whether sufficient power is supplied for a processing element among the plurality of processing elements to perform processing.

[0165] A method for managing power transmission is also disclosed. The power can be transmitted to a computing system including a plurality of processing elements. The method includes determining, based on one or more characteristics of the power source, whether a switching circuit of one of the plurality of power management circuits arranged to be connected in series between the terminals of the power source should be in a first state in which sufficient power is provided to enable processing from the power source, through one of the connectors of the power management circuit, to a processing element arranged to perform application-specific processing connected to the connector of the power management circuit, or a second state in which sufficient power is not provided to enable processing to the processing element. The method may further include transmitting a control signal based on the determined state to a switching circuit of one of the plurality of power management circuits such that the switching circuit can switch between the first state and the second state based on the control signal.

[0166] Also disclosed is a power management system including a plurality of power management circuits that can be arranged to be connected in series between the terminals of a power source. Each power management circuit may include a connector through which power is supplied to a processing element. Each power management circuit may include a switching circuit arranged to either supply sufficient power to enable the processing element to perform processing or prevent sufficient power from being supplied to the processing element to enable processing. The power management system may further include one or more power controllers arranged to determine, based on one or more characteristics of the power source, whether a switching circuit of one of the plurality of power management circuits should supply sufficient power to the processing element to enable processing.

[0167] In some embodiments, a power management system for controlling the delivery of power to a plurality of processing elements is described. The power management system may include a plurality of power management circuits disposed between terminals of a power supply. Each power management circuit may be configured to be connected to a processing element among the plurality of processing elements and either supply sufficient power for power supply processing in the processing element or prevent the supply of sufficient power for power supply processing in the processing element. The power management system may include one or more power controllers arranged to determine whether a processing element among the plurality of processing elements is supplied with sufficient power to perform processing.

[0168] As will be apparent from the above discussion, any of the methods discussed here may be implemented by a computer. In other words, a data processing apparatus, device or system may include means for performing any group of steps of the methods disclosed here. A computer program may include instructions that cause the computer to perform any group of steps of the methods disclosed here when the program is executed by the computer. Finally, a computer-readable medium may include instructions that cause the computer to perform any group of steps of the methods disclosed here when executed by the computer.

[0169] Exemplary aspects of the present disclosure include the following:

[0170] [Aspect 1] A power management system for managing the transmission of power to a computing system including a plurality of processing elements, the power management system comprising a plurality of power management circuits arranged to be connected in series between terminals of a power supply, each power management circuit including a connector for connecting the power management circuit to a processing element arranged to execute application-specific processing, and a switching circuit arranged to switch between (i) an active state in which the power supplied from the power supply to the processing element via the connector is equal to or greater than a power threshold indicating sufficient power for powering the processing, and (ii) a non-active state in which the power supplied to the processing element is less than the power threshold, and one or more power controllers arranged to determine a state to be taken by a first switching circuit of the plurality of power management circuits, the state being the active state or the non-active state, based on one or more characteristics of the power supply, the one or more power controllers transmitting a control signal to the first switching circuit of the plurality of power management circuits based on the state.

[0171] [Aspect 2] The power management system according to Aspect 1, wherein the one or more characteristics of the power supply include fluctuations in the voltage of the power supply.

[0172] [Aspect 3] The power management system according to any one of Aspects 1 to 2, wherein the power supply is a renewable energy source that transmits a variable voltage.

[0173] [Aspect 4] The power management system according to any one of Aspects 1 to 3, wherein each of the one or more power controllers includes one or more controller switching elements, each controller switching element being associated with a power management circuit of the plurality of power management circuits and arranged to switch between an on state and an off state according to whether a threshold of the one or more characteristics is satisfied.

[0174] [Aspect 5] A power management system according to any one of Aspects 1 to 4, wherein the processing element includes at least one application-specific integrated circuit (ASIC) configured to perform cryptocurrency mining.

[0175] [Aspect 6] A power management system according to any one of Aspects 1 to 5, wherein the one or more power controllers include a central power controller.

[0176] [Aspect 7] A power management system according to any one of Aspects 1 to 6, wherein the central power controller includes a processor and a memory, and when executed by the processor, causes the central power controller to control the power demand of the computing system.

[0177] [Aspect 8] A power management system for controlling the transmission of power to a plurality of processing elements, the power management system including a plurality of power management circuits disposed between terminals of a power supply, each power management circuit being connected to a processing element among the plurality of processing elements, and controlling whether sufficient power is supplied for power supply processing to the processing element associated with the power management circuit; and one or more power controllers arranged to determine whether to supply sufficient power for power supply processing to the processing element among the plurality of processing elements.

[0178] [Aspect 9] The power management system according to Aspect 8, wherein the plurality of power management circuits are arranged in series between the terminals of the power supply.

[0179] [Aspect 10] The power management system according to any one of Aspects 8 to 9, wherein the one or more power controllers are arranged to determine whether to supply sufficient power for power supply processing based on one or more characteristics of the power supply.

[0180] [Aspect 11] A power management system according to any one of Aspects 8 to 10, wherein the one or more characteristics of the power supply include the voltage of the power supply and fluctuations in the voltage of the power supply.

[0181] [Aspect 12] A power management system according to any one of Aspects 8 to 11, wherein each of the plurality of power management circuits includes a connector for connecting to the processing element to supply power and a switching element for controlling the supply of power to the processing element.

[0182] [Aspect 13] A power management system according to any one of Aspects 8 to 12, wherein the power supply is a renewable energy source having a variable voltage.

[0183] [Aspect 14] A power management system according to any one of Aspects 8 to 13, wherein the plurality of power management circuits includes the one or more power controllers.

[0184] [Aspect 15] A power management system according to any one of Aspects 8 to 14, wherein each of the one or more power controllers includes one or more controller switching elements, each controller switching element is associated with a power management circuit among the plurality of power management circuits, and is arranged to switch between an on state and an off state according to whether a threshold value is satisfied, and the threshold value is based on one or more characteristics of the power supply.

[0185] [Aspect 16] A power management system according to any one of Aspects 8 to 15, wherein the one or more power controllers are arranged to determine whether to supply sufficient power based on at least one characteristic of at least one of the power management system, the processing element, or a computing system that is a destination of power transmission managed by the power management system.

[0186] [Aspect 17] A power management system according to any one of Aspects 8 to 16, wherein the at least one characteristic includes at least one of a temperature characteristic, or one or more failures of the processing element, a current state of processing of the processing element, or a current draw of the processing element, that is, at least one of states of the processing element.

[0187] [Aspect 18] A power management system according to any one of Aspects 8 to 17, wherein each of the plurality of power management circuits is configured to adjust a power consumption of each processing element arranged to be connected to each of the plurality of power management circuits.

[0188] [Aspect 19] A power management system according to any one of Aspects 8 to 18, wherein the power supply is a first power supply, and the power management system further includes a second power supply arranged to transmit a level of power sufficient for power control in a power management circuit among the plurality of power management circuits to the plurality of power management circuits, and the level of power sufficient for power control in the power management circuit is less than the power sufficient for supplying power to processing in the processing element.

[0189] [Aspect 20] A power management system according to any one of Aspects 8 to 19, wherein the processing element includes at least one application-specific integrated circuit (ASIC) configured to execute application-specific processing.

[0190] [Aspect 21] A power management system according to any one of Aspects 8 to 20, wherein the application-specific processing is one of cryptocurrency mining or artificial intelligence processing.

[0191] [Aspect 22] A method for managing the transmission of power to a computing system including a plurality of processing elements, the method comprising determining, based on one or more characteristics of a power supply, a state to be taken by a switching circuit that is one of a plurality of power management circuits arranged to be connected in series between terminals of the power supply, the state being one of (i) a first state in which power supplied from the power supply, through a connector of one of the plurality of power management circuits, to a processing element arranged to be connected to the connector of the one of the plurality of power management circuits and to perform application-specific processing is equal to or greater than a power threshold indicating sufficient power for powering the processing, and (ii) a second state in which power supplied to the processing element is less than the power threshold, and transmitting a control signal based on the state to the switching circuit to cause the switching circuit to switch between the first state and the second state based on the control signal.

[0192] [Aspect 22a] A method for managing the transmission of power to a computing system including a plurality of processing elements within a power management system according to any one of Aspects 1 to 7.

[0193] [Aspect 22b] A method for controlling the transmission of power to a plurality of processing elements within a power management system according to any one of Aspects 8 to 21.

[0194] [Aspect 23] A power management circuit arranged to be connected in series between terminals of a power supply together with one or more other power management circuits to form a power management system for managing the transmission of power to a computing system including a plurality of processing elements, the power management circuit comprising a connector for connecting the power management circuit to a processing element arranged to perform application-specific processing, and a switching circuit arranged to switch between (i) a processing state in which power supplied from the power supply, through the connector, to the processing element is equal to or greater than a power threshold indicating sufficient power for powering the processing, and (ii) a non-processing state in which power supplied to the processing element is less than the power threshold, in response to a control signal based on one or more characteristics of the power supply.

[0195] [Aspect 24] A non-transitory computer-readable medium storing a set of instructions which, when executed by one or more processors, cause the one or more processors to determine a state to be taken by a switching circuit, which is one of a plurality of power management circuits arranged to be connected in series between terminals of a power supply based on one or more characteristics of the power supply, wherein the state is (i) a first state in which power supplied from the power supply through a connector of one of the plurality of power management circuits to a processing element arranged to be connected to the connector of the one of the plurality of power management circuits and execute application-specific processing is equal to or greater than a power threshold indicating sufficient power for powering the processing, and (ii) a second state in which the power supplied to the processing element is less than the power threshold, and to transmit a control signal based on the state to the switching circuit to cause the switching circuit to switch between the first state and the second state based on the control signal.

[0196] [Aspect 25] A non-transitory computer-readable medium according to Aspect 24, further including an operation according to any one of Aspects 2 to 21.

[0197] [Aspect 26] A means for determining a state to be taken by a switching circuit which is one of a plurality of power management circuits arranged to be connected in series between terminals of a power supply based on one or more characteristics of the power supply, wherein the state is (i) a first state in which power supplied from the power supply to a processing element arranged to execute application-specific processing and connected to the one of the plurality of power management circuits via a connector of the one of the plurality of power management circuits is equal to or greater than a power threshold indicating sufficient power to supply power to the processing; and (ii) a second state in which the power supplied to the processing element is less than the power threshold, and means for transmitting a control signal based on the state to the switching circuit to cause the switching circuit to switch between the first state and the second state based on the control signal.

[0198] [Aspect 27] The apparatus according to Aspect 26, further comprising means for performing the operation according to any one of Aspects 2 to 21.

Claims

1. A power management system for controlling the transmission of power to a plurality of processing elements, comprising: a plurality of power management circuits disposed between terminals of a power supply, each power management circuit being connected to a processing element among the plurality of processing elements and configured to control whether sufficient power for a power supply process is supplied to the processing element; the plurality of power management circuits; one or more power controllers configured to determine whether to supply sufficient power for a power supply process to the processing element among the plurality of processing elements; A power management system comprising the above.

2. The power management system according to claim 1, wherein the plurality of power management circuits are arranged in series between the terminals of the power supply.

3. The power management system according to claim 1 or 2, wherein the one or more power controllers are arranged to determine whether to supply sufficient power for a power supply process based on one or more characteristics of the power supply.

4. The power management system according to claim 3, wherein the one or more characteristics of the power supply include fluctuations in the voltage of the power supply.

5. The power management system according to any one of claims 1 to 4, wherein each of the plurality of power management circuits includes: a connector for connecting to the processing element to supply power; a switching element for controlling the supply of power to the processing element; A power management system including the above.

6. The power management system according to any one of claims 1 to 5, wherein the power supply is a renewable energy source having a variable voltage.

7. The power management system according to any one of claims 1 to 6, wherein the plurality of power management circuits include the one or more power controllers.

8. The power management system according to any one of claims 1 to 7, wherein each of the one or more power controllers includes one or more controller switching elements, each controller switching element being associated with a power management circuit among the plurality of power management circuits and arranged to switch between an active state and an inactive state according to whether a threshold value is satisfied, the threshold value being based on one or more characteristics of the power supply.

9. The power management system according to claim 8, wherein in the active state, power is configured to be provided from the power source to the processing element via a connector at a level exceeding a power threshold indicating the power sufficient for the power supply process, and in the non-active state, power is optionally configured to be provided from the power source to the processing element via the connector at a level below the power threshold.

10. The power management system according to any one of claims 1 to 9, wherein the one or more power controllers determine whether to supply sufficient power based on the power management system, the processing element, or a computing system that is a destination of power transmission managed by the power management system, and is arranged to determine based on at least one characteristic of at least one of them.

11. The power management system according to claim 10, wherein the at least one characteristic is a temperature characteristic, or one or more failures of the processing element the current state of the processing of the processing element, or the current draw of the processing element, and includes at least one of the states of the processing element including at least one of them, and includes at least one of them.

12. The power management system according to any one of claims 1 to 11, wherein each of the plurality of power management circuits is configured to adjust the power consumption of each processing element arranged to be connected to each of the plurality of power management circuits.

13. The power management system according to any one of claims 1 to 12, wherein the power source is a first power source, and the power management system further includes a second power source arranged to transmit power at a level sufficient for power control in the power management circuit among the plurality of power management circuits to the plurality of power management circuits, and the level of power sufficient for power control in the power management circuit is less than the power sufficient for powering the processing in the processing element.

14. The power management system according to any one of claims 1 to 13, wherein the processing element includes at least one application-specific integrated circuit (ASIC) configured to execute application-specific processing.

15. A power management system according to claim 14, wherein the application-specific processing is artificial intelligence processing.

16. A method for power management for controlling the transmission of power to a plurality of processing elements, connecting a power management circuit among a plurality of power management circuits to a processing element among the plurality of processing elements, the plurality of power management circuits being arranged between terminals of a power supply, determining, using one or more power controllers, whether sufficient power should be supplied to the processing element among the plurality of processing elements for power supply processing, controlling, using the power management circuit, whether sufficient power is supplied to the processing element, A method including the above.

17. The method according to claim 16, wherein determining whether sufficient power should be supplied for power supply processing is based on one or more characteristics of the power supply.

18. The method according to claim 17, wherein the one or more characteristics of the power supply include fluctuations in the voltage of the power supply.

19. The method according to any one of claims 16 to 18, further including determining whether a threshold value based on one or more characteristics of the power supply is satisfied, switching a controller switching element between an active state and a non-active state according to whether the threshold value is satisfied, A method including the above.

20. The method according to any one of claims 16 to 19, wherein determining whether sufficient power should be supplied for power supply processing is based on one or more characteristics of at least one of the power management system including the plurality of power management circuits and the one or more power controllers, the processing element, or a computing system that is a transmission destination of power managed by the power management system.

21. A computer program including a set of instructions that cause a computer to perform the method according to any one of claims 16 to 20 when the program is executed by the computer.

22. A computer-readable medium including a set of instructions that cause a computer to perform the method according to any one of claims 16 to 20 when executed by the computer.

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