Semiconductor Package

Abstract

A top-cooled semiconductor package is disclosed. The top-cooled semiconductor package can be a leaded semiconductor package or a leadless semiconductor package. The top-cooled semiconductor package can include a built-in electrical shield for a semiconductor die within a housing of the semiconductor package. The top-cooled semiconductor package can include one or more arrangements of a creepage extension structure. The creepage extension structure can be disposed as a part of an upper surface of the housing, as a part of at least one circumferential surface of the housing, as a part of a bottom surface of the housing, or a combination thereof.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 17 / 849,316, filed on Jun. 24, 2022, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to semiconductor packages, and more particularly, to semiconductor packages having enhanced thermal conduction capabilities.

Background Art

[0003] Semiconductor devices such as transistors and diodes are ubiquitous in modern electronic devices. Wide bandgap semiconductor material systems such as gallium arsenide (GaAs), gallium nitride (GaN), and silicon carbide (SiC) are increasingly being used in semiconductor devices to push the limits of device performance in areas such as switching speed, power handling capabilities, and thermal conductivity. Exemplary power semiconductor dies include metal-oxide-semiconductor field-effect transistors (MOSFETs), insulated gate bipolar transistors (IGBTs), Schottky barrier diodes, PiN diodes, thyristors, and high electron mobility transistors (HEMTs).

[0004] Packaging technology can play a major role in the performance of power semiconductor dies. For example, the packaging of a power semiconductor die can dissipate heat from the semiconductor die, conduct current, and further limit the ability to switch at a certain speed (e.g., due to stray inductance). Ineffective heat dissipation can lead to problems with semiconductor devices (e.g., small form factor semiconductor devices), or problems in situations where the semiconductor device is in close contact with the housing. Excessive heat can negatively affect not only the operation of the semiconductor device itself, but also the operation of the electronic system using the semiconductor device. SUMMARY OF THE INVENTION

[0005] The present disclosure relates to a top-side cooled semiconductor package for housing a semiconductor die. The top-side cooled semiconductor package may be a leadless top-side cooled semiconductor package or a top-side cooled semiconductor package with leads. The top-side cooled semiconductor package may include a built-in electrical shield for the semiconductor die within the housing of the top-side cooled semiconductor package. For example, the housing of the top-side cooled semiconductor package can include a power substrate such as a direct bond copper (DBC) substrate. To facilitate an improvement in current capacity and voltage capacity, the top-side cooled semiconductor package may include one or more arrangements of a creepage extension structure. The creepage extension structure may be included anywhere within the housing of the top-side cooled semiconductor package. For example, the creepage extension structure may be a part of the top surface of the housing and / or a part of the bottom surface of the housing. The creepage extension structure may also be arranged as a part of the top surface of the top-side cooled semiconductor package and along or as a part of one or more peripheral surfaces of the top-side cooled semiconductor package.

[0006] In certain embodiments, the semiconductor die includes transistors such as MOSFETs. In some embodiments, the transistors are SiC-based transistors. In other embodiments, the semiconductor die includes diodes. One example of a diode is a Schottky diode.

[0007] In one aspect, a top-cooled semiconductor package includes a housing and a first contact located within the housing on the top surface of the housing. The first contact is included in a heat transfer path for the top-cooled semiconductor package. A semiconductor die is located within the housing below the first contact. The semiconductor die includes a conductive pad on a first surface of the semiconductor die. A second contact is located within the housing on or near the bottom surface of the housing. An electrical connector operably connects the second contact to the conductive pad of the semiconductor die. A creepage extension structure including one or more trenches extends into the top surface of the housing.

[0008] In another aspect, a system includes a top-cooled semiconductor package, a heat sink operably connected to the top surface of the housing, and a circuit board operably connected to the bottom surface of the housing. The top-cooled semiconductor package includes a housing having a top surface and a bottom surface. The top-cooled semiconductor package includes a housing and a first contact located within the housing on the top surface of the housing. The first contact is included in a heat transfer path for the top-cooled semiconductor package. A semiconductor die is located within the housing below the first contact. The semiconductor die includes a conductive pad on a first surface of the semiconductor die. A second contact is located within the housing on or near the bottom surface of the housing. An electrical connector operably connects the second contact to the conductive pad of the semiconductor die.

[0009] In another aspect, the top surface cooled semiconductor package includes a housing and a first contact located within the housing on the top surface of the housing. A semiconductor die is located within the housing below the first contact. The semiconductor die includes conductor pads on a first surface of the semiconductor die. A power substrate is located within the housing between the first contact and a second surface of the semiconductor die. The first contact and the power substrate are included in the heat transfer path of the top surface cooled semiconductor package. A second contact is located within the housing on the bottom surface of the housing. An electrical connector operably connects the second contact to the conductor pads of the semiconductor die.

[0010] In yet another aspect, the top surface cooled semiconductor package includes a housing and a first contact located within the housing on the top surface of the housing. The first contact is included in the heat transfer path of the top surface cooled semiconductor package. A semiconductor die is located within the housing below the first contact. The semiconductor die includes a first conductor pad on a first surface of the semiconductor die, and the first conductor pad is operably connected to the first contact and a second conductor pad located on a second surface of the semiconductor die. A second contact is located within the housing on or near the bottom surface of the housing. An electrical connector operably connects the second contact to the second conductor pad of the semiconductor die.

[0011] In certain embodiments, the creepage extension structure extends into one or more faces of the housing of the top surface cooled semiconductor package. The creepage extension structure includes one or more trenches, which can be formed in the top surface of the housing, the bottom surface of the housing, at least one peripheral surface of the housing, or combinations thereof. Each trench in the creepage extension structure can have any shape, such as a rectangular shape, a "V" shape, or a "U" shape. Further, each trench can extend to any depth in the face of the housing. For example, the creepage extension structure can extend into the top surface of the housing. The creepage extension structure includes three trenches, all having the same shape and the same depth. In another example, two of the three trenches in the creepage extension structure have a first shape and a first depth, while the third trench has a different second shape and / or a different second depth. Further, each trench can have any width along the face of the housing.

[0012] In another aspect, any of the above-described aspects, individually or together, and / or various separate aspects and features described herein can be combined for further advantages. Unless otherwise indicated herein, any of the various features and elements disclosed herein can be combined with one or more other disclosed features and elements.

[0013] Those skilled in the art will recognize the scope of the present disclosure and will realize additional aspects of the present disclosure upon reading the detailed description of the preferred embodiments below in connection with the accompanying drawings.

[0014] The accompanying drawings, which are incorporated herein and form a part hereof, illustrate some aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

Brief Description of the Drawings

[0015]

Figure 1

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DETAILED DESCRIPTION OF THE INVENTION

[0016] The embodiments described below represent the information necessary for those skilled in the art to implement the embodiments and show the best mode of implementing the embodiments. Those skilled in the art will understand the concepts of the present disclosure and recognize the uses of those concepts not specifically described herein by reading the following description with reference to the accompanying drawings. It should be understood that those concepts and their uses fall within the scope described in the present disclosure and the appended claims.

[0017] Although terms such as first, second, etc. may be used in this specification to describe various elements, it will be understood that those elements should not be limited by those terms. Those terms are only used to distinguish one element from another. For example, without departing from the scope of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. In this specification, the term "and / or" includes any combination of one or more of the associated listed items.

[0018] When an element such as a layer, region, or substrate is referred to as being "on" another element or extending "onto" another element, it will be understood that the element may be located directly on or extend directly onto the other element, or there may also be intervening elements. In contrast, when an element is referred to as being "directly on" another element or extending "directly onto" another element, there are no intervening elements. Similarly, when an element such as a layer, region, or substrate is referred to as being located "over" another element or extending "over" another element, it will be understood that the element may be located directly over or extend directly over the other element, or there may also be intervening elements. In contrast, when an element is referred to as being located "directly over" another element or extending "directly over" another element, there are no intervening elements. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element may be directly connected or coupled to the other element, or there may also be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0019] As used herein, relative terms such as "below" or "above" ~, or "upper" or "lower", or "horizontal" or "vertical" may be used to describe the relationship between one element, layer, or region and another element, layer, or region, as shown in the figures. It will be understood that these terms and those described above are intended to encompass various orientations of the device in addition to the orientation shown in the figures.

[0020] The technical terms used herein are for the purpose of merely describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises", "comprising", "includes", and / or "including", when used herein, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0021] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terms used herein should be interpreted as having a meaning consistent with the context of this specification and their meaning in the prior art, and it will be further understood that they should not be interpreted in an idealized or overly formal sense unless clearly defined herein.

[0022] In this specification, examples of the present disclosure are described with reference to schematic diagrams of the examples. Accordingly, the actual dimensions of the layers and elements may be different, and for example, as a result of manufacturing techniques and / or manufacturing tolerances, deformations from the illustrated shapes are expected. For example, regions shown or described as square or rectangular may have rounded or curved features, and regions shown as straight lines may have some irregularity. Thus, the regions shown in the figures are schematic and their shapes are not intended to indicate the exact shape of the regions of the device and are not intended to limit the scope of the present disclosure. Further, the sizes of structures or regions may be exaggerated relative to other structures or regions for illustrative purposes and are thus provided to show the general structure of the subject matter and may or may not be drawn to scale. In this specification, common elements between figures may be denoted using common element numbers and may not be described again later.

[0023] Individual semiconductor packages containing semiconductor dies such as MOSFETs or Schottky diodes have been developed. Such semiconductor packages containing MOSFETs can be used in various applications to enable higher switching frequencies, higher blocking voltages, and improved avalanche capabilities with associated reduction in losses. Exemplary applications include high-performance industrial power supplies, server / telecom power, electric vehicle charging systems, energy storage systems, uninterruptible power supplies, high-voltage DC / DC converters, and battery management systems. Individual semiconductor packages containing Schottky diodes can be used in many of the same high-performance power applications as described above for MOSFETs, and in some cases, in systems that also include individual power packages for MOSFETs. As described above, packaging technology for semiconductor devices plays an important role in determining the performance of semiconductor devices. Specifically, packaging for semiconductor devices is often a limiting factor for semiconductor dies within the semiconductor device to dissipate heat, conduct current, and further switch at a particular speed.

[0024] The present disclosure relates to an upper surface cooled semiconductor package that houses a semiconductor die. In certain aspects, the upper surface cooled semiconductor package can include an upper surface cooled power semiconductor package that includes a power semiconductor die. As previously explained, the upper surface cooled semiconductor package can be a leadless upper surface cooled semiconductor package or a leaded upper surface cooled semiconductor package. The housing of the upper surface cooled semiconductor package may include a built-in electrical shield for the semiconductor die. For example, the upper surface cooled semiconductor package can include a power substrate such as a direct bond copper (DBC) substrate. To facilitate improved current and voltage capabilities, the upper surface cooled semiconductor package may include one or more arrangements of a creepage extension structure. The creepage extension structure may be included anywhere in the housing as part of the upper surface cooled semiconductor package.

[0025] FIG. 1 shows a side view of an exemplary first system 100 according to an embodiment of the present disclosure. The first system 100 includes the exterior of a first semiconductor package 102 mounted on a circuit board 104. The first semiconductor package 102 can be arranged to house a semiconductor die disposed within a housing 106 and to provide external electrical connections to the semiconductor die. In certain embodiments, the semiconductor die is a power semiconductor die that can include components such as transistors, diodes, or thyristors. Exemplary transistors include, but are not limited to, MOSFETs or IGBTs. Exemplary diodes include, but are not limited to, Schottky diodes, PiN diodes, or high electron mobility transistors (HEMTs). In some embodiments, the components within the semiconductor die are silicon carbide (SiC)-based components such as SiC-based MOSFETs.

[0026] The housing 106 can be formed by a molding process such that the housing 106 is provided around a semiconductor die (shown in FIG. 2), one or more contacts (shown in FIG. 2), a portion of one or more first pins (collectively, the first pins 108), and a portion of one or more second pins (collectively, the second pins 110). The housing 106 may also be provided around one or more wire bonds, one or more conductive clips, and / or one or more conductive segments (not shown in FIG. 1). The material of the housing 106 can electrically isolate the components within the housing 106 from each other. Exemplary materials for the housing 106 include epoxy materials, or epoxy mold compounds (EMC).

[0027] The first semiconductor package 102 is a leadless semiconductor package. The first semiconductor package 102 can be arranged as a surface mount technology (SMT) package such that the bottom surface 106A of the housing 106 is mounted on the first surface 104A of the circuit board 104. Any suitable circuit board 104 can be used. In non-limiting non-exclusive examples, the circuit board 104 is a printed circuit board (PCB) or a flexible printed circuit board. External electrical connections for the first semiconductor package 102 and the included semiconductor die can be provided by structures including the first pins 108 and / or structures including the second pins 110. In certain embodiments, the structures including the first pins 108 and / or the second pins 110 include wire bonds, conductive segments, conductive clips, or other types of electrical connectors.

[0028] The heat sink 112 is positioned to cover the first semiconductor package 102. Specifically, the first surface 112A of the heat sink 112 is disposed to cover the upper surface 106B of the housing 106. The heat sink 112 is included in the heat transfer path of the first semiconductor package 102. Heat generated by the semiconductor die within the housing 106 is conducted to the upper surface 106B of the housing 106, and the heat sink 112 dissipates the heat at the upper surface 106B. In certain embodiments, an interface material 114 is positioned between the first surface 112A of the heat sink 112 and the upper surface 106B of the housing 106. In certain embodiments, the interface material 114 is a thermal interface adhesive or thermal interface paste that can improve the thermal conductivity between the heat sink 112 and the housing 106. The interface material 114 also provides electrical shielding between the heat sink 112 and the semiconductor die within the housing 106.

[0029] In some embodiments, one or more components may be operably attached to the second surface 104B of the circuit board 104. FIG. 1 shows four components 116, 118, 120, 122 that are operably attached to the second surface 104B of the circuit board 104, although any number of components may be operably attached to the second surface 104B of the circuit board 104. Any suitable components, such as electrical components (e.g., passive elements) or electronic components (e.g., active elements), may be operably attached to the second surface 104B of the circuit board 104. Non-limiting and non-exclusive examples of components are resistors, capacitors, inductors, sensors, diodes, transistors, or integrated circuits.

[0030] Figure 2 shows a cross-sectional view of an example of the first semiconductor package 102 shown in FIG. 1 according to an embodiment of the present disclosure. The first semiconductor package 102 includes a semiconductor die 200, a first contact 202, and a second contact 204. The first contact 202 and the second contact 204 can be made of any suitable conductive material such as metal. The first surface 202A of the first contact 202 is positioned on the upper surface 106B of the housing 106. The first surface 202A of the first contact 202 can be exposed in that the first surface 202A is not covered by the upper surface 106B of the housing 106. In a particular embodiment, the first surface 202A of the first contact 202 is coplanar with the upper surface 106B of the housing 106.

[0031] The first surface 200A of the semiconductor die 200 is attached to the second surface 202B of the first contact 202. The first conductor pad 206 on the first surface 202A of the semiconductor die 200 is operably connected (e.g., electrically connected) to the second surface 202B of the first contact 202.

[0032] The second contact 204 is positioned on or near the bottom surface 106A of the housing 106. The first electrical connector 208 operably connects (e.g., electrically connects) the second contact 204 to the second conductor pad 210 on the second surface 200B of the semiconductor die 200. In the example shown, the first electrical connector 208 is a wire bond. The first electrical connector 208 can be implemented differently in other embodiments. For example, the first electrical connector 208 can be a conductive segment, a conductive clip, or another type of electrical connector.

[0033] The first pin 108 and the second pin 110 are positioned on or near the bottom surface 106A of the housing 106. The first pin 108 and the second pin 110 can be made of any suitable conductive material such as metal. The second contact 204 is operably connected to the first pin 108. As shown in FIG. 2, the second contact 204 physically and electrically contacts the first pin 108. Thus, an electrical signal (e.g., voltage or current) can be transmitted between the semiconductor die 200 and the first pin 108 via the second contact 204, the first electrical connector 208, and the second conductor pad 210.

[0034] The second electrical connector 212 operably connects the second pin 110 to the first contact 202. An electrical signal (e.g., voltage or current) can be transmitted between the semiconductor die 200 and the second pin 110 via the second electrical connector 212, the first contact 202, and the first conductor pad 206. In FIG. 2, the second electrical connector 212 is a conductive segment, but other embodiments are not limited to this configuration. The second electrical connector 212 can be a wire bond, a conductive clip, or another type of electrical connector in other embodiments.

[0035] The first surface 104A of the circuit board 104 is disposed to cover the bottom surface 106A of the housing 106 and can be operably connected to the first semiconductor package 102. Although not shown in FIG. 2, one or more components can be operably connected to the second surface 104B of the circuit board 104.

[0036] The first semiconductor package 102 may further include one or more creepage extension structures (collectively referred to as creepage extension structures 214). When the first semiconductor package 102 includes a creepage extension structure 214, the creepage extension structure 214 may be formed as part of the upper surface 106B of the housing 106 at a location between the first pin 108 and the first contact 202. In this way, the creepage extension structure 214 may be configured to improve the voltage separation between the first pin 108 and the first contact 202. Voltage separation is a challenging issue in semiconductor packages, especially as package sizes continue to decrease. The creepage extension structure 214 effectively increases the surface distance or creepage distance along the housing 106 between the first pin 108 and the first contact 202 without the need to position the first pin 108 and the first contact 202 further apart, thereby allowing for a smaller overall footprint of the first semiconductor package 102. In certain embodiments, the creepage distance may be in the range of 5 millimeters (mm) to 20 mm, or in the range of 5 mm to 15 mm, or in the range of 5 mm to 10 mm, or in the range of 10 mm to 20 mm, or in the range of 12 mm to 20 mm, or in the range of 12 mm to 15 mm, or in the range of 3 mm to 10 mm, depending on the power handling capabilities of the first semiconductor package 102.

[0037] As shown, the creepage extension structure 214 may be formed as a number of slots or trenches 214A, 214B, 214C, 214D, 214E, 214F, 214G that extend from the upper surface 106B into the housing 106. The trenches 214A - 214G may have the same dimensions, or at least one of the trenches 214A - 214G may have at least one dimension different from the other trenches 214A - 214G. For example, as shown in FIG. 2, trenches 214C and 214E are formed to a first depth (e.g., the deepest depth), trenches 214A and 214G are formed to a different second depth (e.g., the first intermediate depth), trench 214D is formed to a different third depth (e.g., the second intermediate depth), and trenches 214B and 214F are formed to a different fourth depth (e.g., the shallowest depth). Further, or alternatively, the widths of the trenches 214A - 214G (e.g., along the upper surface 106B of the housing) may be the same, or the width of at least one of the trenches 214A - 214G may be different from the widths of the other trenches 214A - 214G.

[0038] The creepage extension structure 214 may also be referred to as having a number of ribs or protrusions formed by portions of the housing 106 between the trenches 214A - 214G. The creepage extension structure 214 may be formed simultaneously with the molding of the housing 106 around the first pin 108 and the first contact 202. In a particular embodiment, the creepage extension structure 214 is disposed only as a part of the upper surface 106B and along the shortest path of the housing 106 between the first pin 108 and the first contact 202. In other embodiments, the creepage extension structure 214 may be disposed as a part of the upper surface 106B of the housing 106, as a part of at least one circumferential surface of the housing 106, as a part of the bottom surface 106A of the housing 106, or in a combination thereof.

[0039] The interface material 114 is disposed to cover the upper surface 106B of the housing 106 and the first surface 202A of the first contact 202. The first surface 112A of the heat sink 112 is disposed to cover the interface material 114. Thus, the first surface 202A of the first contact 202 is in thermal contact with the first surface 112A of the heat sink 112. The first contact 202 and the heat sink 112 are included in the heat transfer path of the first semiconductor package 102. The heat generated by the semiconductor die 200 is led to the upper surface 106B of the housing 106 by the first contact 202. The first contact 202 transfers the heat to the heat sink 112 (via the interface material 114), and the heat sink 112 dissipates the heat. Since the first contact 202 is configured to propagate an electrical signal, the interface material 114 provides electrical shielding between the first contact 202 and the heat sink 112 to prevent the electrical signal from propagating to the heat sink 112.

[0040] The heat sink 112 can have any dimensions (e.g., width and length) with respect to the upper surface 106B of the housing 106 and / or the first contact 202. When the housing 106 includes a creepage extension structure 214 on the upper surface 106B of the housing 106, the heat sink 112 can have any width within the range of the dotted lines 216 and 218 (e.g., distance D). The dotted line 216 corresponds to the right edge of the trench 214G. The dotted line 218 corresponds to the right edge of the housing 106. In one non-limiting, non-exclusive example, the width of the heat sink 112 is equal to the width of the first contact 202. In another non-limiting, non-exclusive example, the width of the heat sink 112 is greater than the width of the first contact 202 but less than the distance D.

[0041] FIG. 3 shows a bottom view of the first semiconductor package 102 shown in FIG. 1 according to an embodiment of the present disclosure, where the housing 106 is shown as transparent for illustrative purposes. As described above, the first semiconductor package 102 includes a first contact 202, a second contact 204, and a semiconductor die 200. The first electrical connector 208 operably connects the second contact 204 to a second conductor pad 210 on the second surface 200B of the semiconductor die 200. The illustrated second conductor pad 210 is shown as a single conductor pad. However, in other embodiments, the second conductor pad 210 may be configured as two or more conductor pads to reduce or eliminate problems associated with current concentration. One or more jumper connectors may be used to operably connect the two or more conductor pads to each other. Additionally, or alternatively, an embodiment can include one or more first electrical connectors 208.

[0042] The semiconductor die 200 also includes a first conductor pad 206. The first conductor pad 206 is located on the first surface of the semiconductor die 200 (e.g., the first surface 200A in FIG. 2), and thus is shown in dashed lines because it is not visible in the bottom view of the first semiconductor package 102 shown in FIG. 3. The first conductor pad 206 is operably connected to the first contact 202 (e.g., physically contacted and electrically connected).

[0043] The first pins 108A, 108B, 108C, 108D, 108E, 108F are configured to provide an electrical signal to and / or receive an electrical signal from the second contact 204. The second pins 110A, 110B, 110C are configured to provide an electrical signal to and / or receive an electrical signal from the first contact 202. FIG. 3 shows six first pins 108A, 108B, 108C, 108D, 108E, 108F, and three second pins 110A, 110B, 110C, but other embodiments can include one or more first pins 108 and one or more second pins 110.

[0044] In one non-limiting and non-exclusive example, the semiconductor die 200 includes a diode such as a Schottky diode. Accordingly, the first conductor pad 206 is operatively connected to the first terminal (e.g., anode terminal) of the diode, and the second conductor pad 210 is operatively connected to the second terminal (e.g., cathode terminal) of the diode. The first conductor pad 206 may also be referred to as the first terminal conductor pad, and the second conductor pad 210 may be referred to as the second terminal conductor pad. The first pins 108A-108F are operatively connected to the second conductor pad 210 via the second contact 204 and the first electrical connector 208. The second pins 110A-110C are operatively connected to the first conductor pad 206 via the second electrical connector 212 (see FIG. 2) and the first contact 202.

[0045] In another non-limiting and non-exclusive example, the semiconductor die 200 includes a transistor (e.g., a MOSFET). Accordingly, the first conductor pad 206 (which may also be referred to as the first terminal conductor pad or the drain conductor pad) is operatively connected to the first terminal (e.g., drain) of the transistor, and the second conductor pad 210 (which may also be referred to as the second terminal conductor pad or the source conductor pad) is operatively connected to the second terminal (e.g., source terminal) of the transistor. Also in this case, the first pins 108A-108F are operatively connected to the second conductor pad 210 via the second contact 204 and the first electrical connector 208. The second pins 110A-110C are operatively connected to the first conductor pad 206 via the second electrical connector 212 (see FIG. 2) and the first contact 202.

[0046] If components of the semiconductor die 200 can use an additional conductor pad (e.g., similar to a transistor), the semiconductor die 200 further includes a third conductor pad 300 that is operably connected to a third terminal of the component (e.g., the gate of a transistor). A third electrical connector 302 operably connects the third conductor pad 300 to a third pin 304. The third conductor pad 300 may be referred to as a gate conductor pad or a third terminal conductor pad, and the third pin 304 may be referred to as a gate pin. An electrical signal can be transmitted to and / or received from the third conductor pad 300. For example, an electrical signal to be applied to the gate of a transistor is input to the first semiconductor package 102 at the third pin 304. The third electrical connector 302 transmits the electrical signal to the third conductor pad 300, and the electrical signal is applied to the third terminal (e.g., the gate of a transistor).

[0047] In certain embodiments, a Kelvin connection to the source of a transistor is used to improve the switching speed and / or switching efficiency of the transistor. FIG. 3 shows a Kelvin connection to a second conductor pad 210 (e.g., a source conductor pad). A fourth electrical connector 306 operably connects a fourth pin 308 (which may also be referred to as a Kelvin pin) to the second conductor pad 210. The third electrical connector 302 and the fourth electrical connector 306 are shown as wire bonds in FIG. 3. However, the third electrical connector 302 and the fourth electrical connector 306 may each be any suitable type of electrical connector, such as a wire bond, a conductive segment, or a conductive clip.

[0048] The components in the first semiconductor package 102 may vary depending on the components in the semiconductor die 200. For example, the third conductor pad 300, the third electrical connector 302, and the third pin 304 may be included in a particular embodiment (e.g., when the semiconductor die 200 includes transistors). Alternatively, the third conductor pad 300, the third electrical connector 302, and the third pin 304 may be omitted in other embodiments. Similarly, the Kelvin connection (the fourth pin 308 and the fourth electrical connector 306) may be included in a particular embodiment and omitted in other embodiments.

[0049] FIG. 4 shows a top view of the first semiconductor package 102 of FIG. 1 according to an embodiment of the present disclosure, where the housing 106 is shown as transparent for illustrative purposes. The exemplary first semiconductor package 102 includes a first contact 202, a second contact 204, first pins 108A - 108F, second pins 110A - 110C, a third pin 304, and a fourth pin 308. The first contact 202 is shown as a relatively large conductive contact, also known as a "tab", compared to the area of the second contact 204. However, other embodiments can include a first contact 202 and a second contact 204 each having any area.

[0050] The creepage extension structure 214 is formed on the top surface 106B of the housing 106. The creepage extension structure 214 has a first width W1. Accordingly, all of the trenches 214A - 214G (FIG. 2) in the creepage extension structure 214 have the same width W1. As discussed previously, at least one of the trenches 214A - 214G can have a width different from the widths of the other trenches 214A - 214G. In the exemplary embodiment, the width W1 is less than the width W2 of the housing 106.

[0051] FIG. 5 shows a side view of an exemplary second system 500 according to an embodiment of the present disclosure. The second system 500 is similar to the exemplary first system 100 shown in FIG. 1, but the interface material 114 is omitted. As will be described in more detail in connection with FIG. 6, the second semiconductor package 502 includes a built-in electrical shield for the semiconductor die within the second semiconductor package 502. Accordingly, the interface material 114 is not included in the exemplary second system 500.

[0052] In addition to the second semiconductor package 502, the exemplary second system 500 includes a heat sink 112 disposed to cover the upper surface 106B of the housing 106 and a circuit board 104 positioned to cover the bottom surface 106A of the housing 106. In FIG. 5, the heat sink 112 is in direct contact with the upper surface 106B of the housing 106 and the first surface 202A of the first contact 202 as a result of the built-in electrical shield.

[0053] The housing 106 can be formed by a molding process such that the housing 106 is provided around a semiconductor die (not shown in FIG. 5), a plurality of contacts (not shown in FIG. 5), a power substrate (not shown in FIG. 5), a portion of the first pin 108, and a portion of the second pin 110. The housing 106 can also be provided around one or more wire bonds, one or more conductive clips, and / or one or more conductive segments (not shown in FIG. 5). As described above, the material of the housing 106 can electrically isolate the components within the housing 106 from each other.

[0054] Similar to the first semiconductor package 102 (FIG. 1), the second semiconductor package 502 can be arranged as an SMT package such that the bottom surface 106A of the housing 106 is mounted on the first surface 104A of the circuit board 104. External electrical connections for the second semiconductor package 502 and the included semiconductor die can be provided by a structure including the first pins 108 and / or a structure including the second pins 110. In certain embodiments, the structure including the first pins 108 and / or the second pins 110 includes wire bonds, conductive segments, conductive clips, or other suitable electrical connectors.

[0055] In certain embodiments, one or more components can be operably attached to the second surface 104B of the circuit board 104. FIG. 5 shows four components 116, 118, 120, 122 operably attached to the second surface 104B of the circuit board 104, although any number of components can be operably attached to the second surface 104B of the circuit board 104. Non-limiting, non-exclusive examples of components are resistors, capacitors, inductors, sensors, diodes, transistors, or integrated circuits.

[0056] FIG. 6 shows a cross-sectional view of a first example of the second semiconductor package 502A shown in FIG. 5, according to an embodiment of the present disclosure. The second semiconductor package 502A is a leadless semiconductor package. The second semiconductor package 502A includes a semiconductor die 200, a first contact 202, a second contact 204, and a third contact 504. The first surface 202A of the first contact 202 can be exposed in that the first surface 202A is not covered by the upper surface 106B of the housing 106. In certain embodiments, the first surface 202A of the first contact 202 is coplanar with the upper surface 106B of the housing 106. The first surface 202A of the first contact 202 is positioned on the upper surface 106B of the housing 106. The second contact 204 and the third contact 504 are located on or near the bottom surface 106A of the housing 106. The first contact 202, the second contact 204, and the third contact 504 can be made of any suitable conductive material, such as metal.

[0057] The first surface 200A of the semiconductor die 200 is attached to the power substrate 506. The power substrate 506 is a thermally conductive substrate and an electrically insulating substrate. The power substrate 506 includes an insulating layer 508 sandwiched between a first conductive layer 510 and a second conductive layer 512. In a non-limiting and non-exclusive example, the insulating layer 508 is a ceramic layer, and the first conductive layer 510 and the second conductive layer 512 are copper layers. Thus, the power substrate 506 is a DBC substrate. The power substrate 506 may be mounted differently in other embodiments.

[0058] The first conductive layer 510 of the power substrate 506 is attached to the second surface 202B of the first contact 202. The power substrate 506, the first contact 202, and the heat sink 112 are included in the heat transfer path of the second semiconductor package 502A. The heat generated by the semiconductor die 200 is conducted to the upper surface 106B of the housing 106 by the power substrate 506 and the first contact 202. Since the first surface 202A of the first contact 202 is in thermal contact with the first surface 112A of the heat sink 112, the first contact 202 transfers heat to the heat sink 112, and the heat sink 112 dissipates the heat.

[0059] The first conductor pad 206 on the first surface 200A of the semiconductor die 200 is operably connected (e.g., electrically connected) to the second conductive layer 512 of the power substrate 506. A second electrical connector 514 operably connects the third contact 504 to the second conductive layer 512 of the power substrate 506. The third contact 504 is operably connected to the second pin 110. As shown in FIG. 5, the third contact 504 is in electrical contact with the second pin 110. Thus, an electrical signal (e.g., voltage or current) can be transmitted between the semiconductor die 200 and the second pin 110 via the third contact 504, the second electrical connector 514, the second conductive layer 512, and the first conductor pad 206.

[0060] The first electrical connector 208 operably connects the second contact 204 to the second conductor pad 210 on the second surface 200B of the semiconductor die 200. In the illustrated embodiment, the first electrical connector 208 and the second electrical connector 514 are wire bonds. The first electrical connector 208 and / or the second electrical connector 514 may be implemented differently in other embodiments. For example, the first electrical connector 208 and / or the second electrical connector 514 may each be a conductive segment, a conductive clip, or another type of electrical connector.

[0061] The first pin 108 and the second pin 110 are positioned on the bottom surface 106A of the housing 106. The first pin 108 and the second pin 110 may be made of any suitable conductive material such as metal.

[0062] The first surface 104A of the circuit board 104 is disposed to cover the bottom surface 106A of the housing 106 and may be operably connected to the second semiconductor package 502A. Although not shown in FIG. 6, one or more components may be operably connected to the second surface 104B of the circuit board 104.

[0063] The second semiconductor package 502A may also include a creepage extension structure 214. When the second semiconductor package 502A includes the creepage extension structure 214, the creepage extension structure 214 is formed as part of the upper surface 106B of the housing 106 at least at a location between at least the second pin 110 and the first contact 202. The creepage extension structure 214 effectively increases the creepage distance along the housing 106 between the second pin 110 and the first contact 202 without the need to position the second pin 110 and the first contact 202 further apart. In certain embodiments, the creepage distance may be in the range of 5 millimeters (mm) to 20 mm, or in the range of 5 mm to 15 mm, or in the range of 5 mm to 10 mm, or in the range of 10 mm to 20 mm, or in the range of 12 mm to 20 mm, or in the range of 12 mm to 15 mm, or in the range of 3 mm to 10 mm, depending on the power handling capability of the second semiconductor package 502A.

[0064] The creepage extension structure 214 may be formed simultaneously with the molding of the housing 106 around the second pin 110 and the first contact 202. In certain embodiments, the creepage extension structure 214 is disposed only as a part of the upper surface 106B of the housing 106B between the second pin 110 and the first contact 202. In other embodiments, the creepage extension structure 214 may be disposed as a part of the upper surface 106B of the housing 106, as a part of at least one peripheral surface of the housing 106, as a part of the bottom surface 106A of the housing 106, or in combinations thereof.

[0065] The heat sink 112 can have any dimensions (e.g., width and length) with respect to the upper surface 106B of the housing 106 and / or the first contact 202. When the housing 106 includes the creepage extension structure 214 on the upper surface 106B of the housing 106, the heat sink 112 can have any width within the range of the dotted lines 216 and 218 (e.g., distance D). The dotted line 216 corresponds to the right edge of the creepage extension structure 214. The dotted line 218 corresponds to the right edge of the housing 106. In one non-limiting, non-exclusive example, the width of the heat sink 112 is equal to the width of the first contact 202. In another non-limiting, non-exclusive example, the width of the heat sink 112 is greater than the width of the first contact 202 but less than the distance D.

[0066] FIG. 7 shows a bottom view of a first example of the second semiconductor package 502A shown in FIG. 6 according to an embodiment of the present disclosure, where the housing 106 is shown as transparent for illustrative purposes. As described above, the second semiconductor package 502A includes a first contact 202, a second contact 204, a third contact 504, and a semiconductor die 200. The first electrical connector 208 operably connects the second contact 204 to a second conductor pad 210 on the second surface 200B of the semiconductor die 200. The illustrated second conductor pad 210 is shown as a single conductor pad. However, as already described, the second conductor pad 210 may be configured as two or more conductor pads including a jumper connector that operably connects the two or more conductor pads to each other. Additionally, or alternatively, an embodiment can include one or more first electrical connectors 208.

[0067] The semiconductor die 200 also includes a first conductor pad 206. The first conductor pad 206 is located on the first surface of the semiconductor die 200 (e.g., the first surface 200A in FIG. 6), and thus is shown in dashed lines as it is not visible in the bottom view of the second semiconductor package 502A in FIG. 7. The first conductor pad 206 is operably connected (e.g., physically contacted and electrically connected) to the second conductive layer 512 of the power substrate 506. The second electrical connector 514 operably connects the third contact 504 to the second conductive layer 512 of the power substrate 506. FIG. 7 shows two second electrical connectors 514, but other embodiments can include one or more second electrical connectors 514.

[0068] The insulating layer 508 of the power substrate is also shown in FIG. 7. As described above, the first conductive layer 510 is positioned between the insulating layer 508 and the first contact 202. However, the first conductive layer 510 is not visible in the bottom view of the second semiconductor package 502A in FIG. 7.

[0069] The first pins 108A, 108B, 108C, 108D, 108E, 108F are configured to provide an electrical signal to and / or receive an electrical signal from the second contact 204. The second pins 110A, 110B, 110C, 110D, 110E, 110F, 110G, 110H are configured to provide an electrical signal to and / or receive an electrical signal from the third contact 504. FIG. 7 shows six first pins 108A-108F and eight second pins 110A-110H, although other embodiments can include one or more first pins 108 and one or more second pins 110.

[0070] In one non-limiting, non-exclusive example, the semiconductor die 200 includes a diode, such as a Schottky diode. Accordingly, the first conductor pad 206 is operatively connected to a first terminal (e.g., an anode terminal) of the diode, and the second conductor pad 210 is operatively connected to a second terminal (e.g., a cathode terminal) of the diode. The first pins 108A-108F are operatively connected to the second conductor pad 210 via the second contact 204 and the first electrical connector 208. The second pins 110A-110H are operatively connected to the first conductor pad 206 via the third contact 504, the second electrical connector 514, and the second conductive layer 512.

[0071] In another non-limiting, non-exclusive example, the semiconductor die 200 includes a transistor (e.g., a MOSFET). Accordingly, the first conductor pad 206 is operatively connected to a first terminal (e.g., a drain) of the transistor, and the second conductor pad 210 is operatively connected to a second terminal (e.g., a source terminal) of the transistor. Again, in this case, the first pins 108A-108F are operatively connected to the second conductor pad 210 via the second contact 204 and the first electrical connector 208. The second pins 110A-110H are operatively connected to the first conductor pad 206 via the third contact 504, the second electrical connector 514, and the second conductive layer 512.

[0072] If the components of the semiconductor die 200 can use additional conductor pads (e.g., similar to transistors), the semiconductor die 200 further includes a third conductor pad 300 operably connected to a third terminal of the component (e.g., the gate of a transistor). The third electrical connector 302 operably connects the third conductor pad 300 to a third pin 304 (e.g., a gate pin). An electrical signal can be transmitted to and / or received from the third conductor pad. For example, an electrical signal to be applied to the gate of a transistor is input to the second semiconductor package 502A at the third pin 304. The third electrical connector 302 transmits the electrical signal to the third conductor pad 300, and the electrical signal is applied to the third terminal (e.g., the gate of the transistor).

[0073] In certain embodiments, a Kelvin connection to the source of the transistor is included in the second semiconductor package 502A. The fourth electrical connector 306 operably connects a fourth pin 308 (e.g., a Kelvin pin) to the second conductor pad 210. The third electrical connector 302 and the fourth electrical connector 306 can each be any suitable type of electrical connector, such as a wire bond, a conductive segment, or a conductive clip.

[0074] The components in the second semiconductor package 502A can vary depending on the components in the semiconductor die 200. For example, the third conductor pad 300, the third electrical connector 302, and the third pin 304 can be included in certain embodiments (e.g., when the semiconductor die 200 includes transistors). Alternatively, the third conductor pad 300, the third electrical connector 302, and the third pin 304 can be omitted in other embodiments. Similarly, the Kelvin connection (the fourth pin 308 and the fourth electrical connector 306) can be included in certain embodiments and omitted in other embodiments.

[0075] FIG. 8 shows a cross-sectional view of a second example of the second semiconductor package 502B shown in FIG. 5 according to an embodiment of the present disclosure. The second semiconductor package 502B is similar to the second semiconductor package 502A shown in FIG. 6, except that the third contact 504 and the second electrical connector 514 are replaced by a first conductive clip 800, and the second contact 204 and the first electrical connector 208 are replaced by a second conductive clip 802. Further, the second pins 110 are replaced by one or more first leads (collectively, the first leads 804), and the first pins 108 are replaced by one or more second leads (collectively, the second leads 806). Accordingly, the second semiconductor package 502B is a leaded semiconductor package.

[0076] As described above, the first contact 202 is positioned on the upper surface 106B of the housing 106, and the first surface 202A of the first contact 202 may be coplanar with the upper surface 106B of the housing 106. The first conductive clip 800, the second conductive clip 802, the first leads 804, and the second leads 806 are positioned on or near the bottom surface A of the housing 106. The first conductive clip 800, the second conductive clip 802, the first leads 804, and the second leads 806 can each be made of any suitable conductive material such as metal.

[0077] The first conductive layer 510 of the power substrate 506 is attached to the second surface 202B of the first contact 202. Similar to the second semiconductor package 502A in FIG. 6, the power substrate 506, the first contact 202, and the heat sink 112 are included in the heat transfer path of the second semiconductor package 502A. The heat generated by the semiconductor die 200 is conducted to the upper surface 106B of the housing 106B by the power substrate 506 and the first contact 202. Since the first surface 202A of the first contact 202 is in thermal contact with the first surface 112A of the heat sink 112, the first contact 202 transfers and dissipates the heat to the heat sink 112.

[0078] The first conductive pad 206 on the first surface 200A of the semiconductor die 200 is operably connected (e.g., physically contacted and electrically connected) to the second conductive layer 512 of the power substrate 506. The second conductive clip 802 operably connects the second lead 806 to the second conductive layer 512 of the power substrate 506 (shown in FIG. 9). Thus, an electrical signal (e.g., voltage or current) can be transmitted between the semiconductor die 200 and the second lead 806 via the second conductive clip 802 and the first conductive pad 206.

[0079] The first conductive clip 800 is operably connected between the first lead 804 and the second conductive pad 210 on the second surface 200B of the semiconductor die 200. Thus, an electrical signal (e.g., voltage or current) can be transmitted between the semiconductor die 200 and the first lead 804 via the second conductive clip 802 and the second conductive pad 210. The first lead 804 and / or the second lead 806 may be implemented differently in other embodiments. For example, the first lead 804 and / or the second lead 806 may be a conductive segment, a wire bond, or another type of electrical connector.

[0080] The third conductive pad 808 and the fourth conductive pad 810 are positioned on the first surface 104A of the circuit board 104. The first lead 804 is operably connected to the third conductive pad 808. The second lead 806 is operably connected to the fourth conductive pad 810. The third conductive pad 808 and the fourth conductive pad 810 can be made of any suitable conductive material such as metal.

[0081] The first surface 104A of the circuit board 104 is disposed to cover the bottom surface 106A of the housing 106 and can be operably connected to the second semiconductor package 502B. Although not shown in FIG. 8, one or more components can be operably connected to the second surface 104B of the circuit board 104.

[0082] The second semiconductor package 502B may also include a creepage extension structure 214. When the second semiconductor package 502B includes the creepage extension structure 214, the creepage extension structure 214 is formed as part of the upper surface 106B of the housing 106 at least at a location between the first lead 804 and the first contact 202. The creepage extension structure 214 effectively increases the creepage distance along the housing 106 between the first lead 804 and the first contact 202 without the need to position the first lead 804 and the first contact 202 further apart. In certain embodiments, the creepage distance may be in the range of 5 millimeters (mm) to 20 mm, or in the range of 5 mm to 15 mm, or in the range of 5 mm to 10 mm, or in the range of 10 mm to 20 mm, or in the range of 12 mm to 20 mm, or in the range of 12 mm to 15 mm, or in the range of 3 mm to 10 mm, depending on the power handling capability of the second semiconductor package 502B.

[0083] The creepage extension structure 214 may be formed simultaneously with the shaping of the housing 106 around the first lead 804 and the first contact 202. In certain embodiments, the creepage extension structure 214 is disposed only as part of the upper surface B of the housing 106 between the first lead 804 and the first contact 202. In other embodiments, the creepage extension structure 214 may be disposed as part of a portion of at least one peripheral surface of the housing 106, as part of a portion of the bottom surface 106A of the housing 106, or a combination thereof, as part of the upper surface 106B.

[0084] The heat sink 112 can have any dimensions (e.g., width and length) with respect to the upper surface 106B of the housing 106 and / or the first contact 202. When the housing 106 includes a creepage extension structure 214 on the upper surface 106B of the housing 106, the heat sink 112 can have any width within the range of the dotted lines 216 and 218 (e.g., distance D). The dotted line 216 corresponds to the right edge of the creepage extension structure 214. The dotted line 218 corresponds to the right edge of the housing 106. In one non-limiting, non-exclusive example, the width of the heat sink 112 is equal to the width of the first contact 202. In another non-limiting, non-exclusive example, the width of the heat sink 112 is greater than the width of the first contact 202 but less than the distance D.

[0085] FIG. 9 shows a bottom view of a second example of the second semiconductor package 502B shown in FIG. 8 according to an embodiment of the present disclosure, with the housing 106 shown as transparent for illustrative purposes. As described above, the second semiconductor package 502B includes a first contact 202, a semiconductor die 200, a first conductive clip 800, and a second conductive clip 802. The first conductive clip 800 operably connects the first leads 804A, 804B, 804C, 804D, 804E to the second conductor pads 210 on the second surface 200B of the semiconductor die 200. The illustrated second conductor pads 210 are shown as a single conductor pad. However, in other embodiments, the second conductor pads 210 can be configured as two or more conductor pads including a jumper connector that operably connects the two or more conductor pads to each other.

[0086] The semiconductor die 200 also includes a first conductive pad 206. The first conductive pad 206 is located on a first surface of the semiconductor die 200 (e.g., the first surface 200A in FIG. 8), and thus is shown in dashed lines because it is not visible in the bottom view of the second semiconductor package 502B in FIG. 9. The first conductive pad 206 is operably connected (e.g., physically contacted and electrically connected) to a second conductive layer 512 of the power substrate 506. The second conductive clip 802 operably connects the second leads 806A, 806B, 806C, 806D, 806E, 806F, 806G to the second conductive layer 512 of the power substrate 506.

[0087] The insulating layer 508 of the power substrate is also shown in FIG. 9. As described above, the first conductive layer 510 is positioned between the insulating layer 508 and the first contact 202. However, the first conductive layer 510 is not visible in the bottom view of the second semiconductor package 502B in FIG. 9.

[0088] The first leads 804A - 804E are configured to provide an electrical signal to and / or receive an electrical signal from the first conductive clip 800. The second leads 806A - 806G are configured to provide an electrical signal to and / or receive an electrical signal from the second conductive clip 802. FIG. 9 shows five first leads 804A - 804E and seven second leads 806A - 806G, but other embodiments can include one or more first leads 804 and one or more second leads 806.

[0089] In one non-limiting and non-exclusive example, the semiconductor die 200 includes a diode such as a Schottky diode. Accordingly, the first conductive pad 206 is operatively connected to the first terminal (e.g., anode terminal) of the diode, and the second conductive pad 210 is operatively connected to the second terminal (e.g., cathode terminal) of the diode. The first leads 804A - 804E are operatively connected to the second conductive pad 210 via the first conductive clip 800. The second leads 806A - 806G are operatively connected to the first conductive pad 206 via the second conductive clip 802 and the second conductive layer 512 of the power substrate.

[0090] In another non-limiting and non-exclusive example, the semiconductor die 200 includes a transistor such as a MOSFET. Accordingly, the first conductive pad 206 is operatively connected to the first terminal (e.g., drain) of the transistor, and the second conductive pad 210 is operatively connected to the second terminal (e.g., source terminal) of the transistor. Also in this case, the first leads 804A - 804E are operatively connected to the second conductive pad 210 via the first conductive clip 800. The second leads 806A - 806G are operatively connected to the first conductive pad 206 via the second conductive clip 802 and the second conductive layer 512 of the power substrate.

[0091] If the components of the semiconductor die 200 can use an additional conductive pad (e.g., similar to a transistor), the semiconductor die 200 further includes a third conductive pad 300 that is operatively connected to a third terminal of the component (e.g., the gate of the transistor). The third electrical connector 302 operatively connects the third conductive pad 300 to a third pin 304 (e.g., gate pin). An electrical signal to be applied to the gate of the transistor is input to the second semiconductor package 502A at the third pin 304. The third electrical connector 302 transmits the electrical signal to the third conductive pad 300, and the electrical signal is applied to the gate of the transistor.

[0092] In certain embodiments, the Kelvin connection to the source of the transistor is included in the second semiconductor package 502B. The fourth electrical connector 306 operably connects the fourth pin 308 (e.g., a Kelvin pin) to the second conductor pad 210. The third electrical connector 302 and the fourth electrical connector 306 may be any suitable electrical connectors such as wire bonds, conductive segments, conductive clips, or any other type of electrical connector.

[0093] Similar to the second semiconductor package 502A shown in FIG. 7, the components in the second semiconductor package 502B may vary depending on the components in the semiconductor die 200. For example, the third conductor pad 300, the third electrical connector 302, and the third pin 304 may be included in certain embodiments (e.g., when the semiconductor die 200 includes a transistor). Alternatively, the third conductor pad 300, the third electrical connector 302, and the third pin 304 may be omitted in other embodiments. Similarly, the Kelvin connection (the fourth pin 308 and the fourth electrical connector 306) may be included in certain embodiments and omitted in other embodiments.

[0094] FIG. 10 shows a side view of a housing 106 for a semiconductor package showing a first exemplary creepage extension structure 1000 and a second exemplary creepage extension structure 1002 according to embodiments of the present disclosure. The first exemplary creepage extension structure 1000 includes trenches 1000A, 1000B, 1000C. Trenches 1000A, 1000C are formed in (and extend along) a top surface 106B of the housing 106 and a portion of a peripheral surface 1004 of the housing 106. Although not shown in FIG. 10, trenches 1000A, 1000C may also extend along a portion of another peripheral surface of the housing 106. The trench 1000B is formed only in the top surface 106B of the housing 106 and extends only along the top surface 106B. Thus, the trench 1000B is shown in dashed lines.

[0095] The second exemplary crepe page expansion structure 1002 includes trenches 1000D, 1000E, 1000F. Trenches 1000D, 1000E, 1000F are formed in (and extend along) the entire length of the upper surface 106B of the housing 106 and the circumferential surface 1004 of the housing 106. Although not shown in FIG. 10, trenches 1000D, 1000E, 1000F may also extend along at least a portion of another circumferential surface of the housing 106.

[0096] In other embodiments, the housing 106 can include any number of trenches. The trenches may be rectangular in shape or may have any other type of shape (e.g., "V" shape or "U" shape). The dimensions of the trenches (e.g., width and length) may be the same or at least one trench dimension may differ from the dimensions of the other trenches.

[0097] It is intended that any of the above-described aspects, and / or various separate aspects and features described herein, can be combined for further advantages. Any of the various embodiments disclosed herein can be combined with one or more other disclosed embodiments unless it is shown herein to the contrary.

[0098] Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered to be within the scope of the concepts disclosed herein and the scope of the appended claims.

Claims

Claim 1 An upper surface cooling semiconductor package, comprising: a housing; a first contact located within the housing on an upper surface of the housing, the first contact being included in a heat transfer path for the upper surface cooling semiconductor package; a semiconductor die located within the housing below the first contact, the semiconductor die having a conductor pad on a first surface of the semiconductor die; a second contact located within the housing on a bottom surface of the housing; an electrical connector operably connecting the second contact to the conductor pad of the semiconductor die; a creepage extension structure extending within a plane of the housing and including one or more trenches The upper surface cooling semiconductor package comprising the same. Claim 2 The conductor pad is a first conductor pad, The semiconductor die further includes a second conductor pad on a second surface of the semiconductor die, The upper surface cooling semiconductor package according to claim 1, wherein the first contact is operably connected to the second conductor pad of the semiconductor die. Claim 3 The semiconductor die includes a diode, The first conductor pad is a first terminal conductor pad operably connected to a first terminal of the diode, The upper surface cooling semiconductor package according to claim 2, wherein the second conductor pad is a second terminal conductor pad operably connected to a second terminal of the diode. Claim 4 The semiconductor die includes a transistor, The first conductor pad is a first terminal conductor pad operably connected to a first terminal of the transistor, The second conductor pad is a second terminal conductor pad operably connected to a second terminal of the transistor, The upper surface cooling semiconductor package according to claim 2, wherein the semiconductor die further includes a third terminal conductor pad on the first surface of the semiconductor die, and the third terminal conductor pad is operably connected to a third terminal of the transistor. Claim 5 The upper surface cooling semiconductor package according to any one of claims 1 to 4, further comprising a power substrate between the first contact and the semiconductor die. Claim 6 The upper surface cooling semiconductor package according to claim 5, wherein the power substrate includes an insulating layer between a top conductive layer and a bottom conductive layer. Claim 7 The upper surface cooling semiconductor package according to claim 6, wherein the power substrate is a direct bond copper substrate. Claim 8 The electrical connector is a first electrical connector, The conductor pad is a first conductor pad, The semiconductor die includes a second conductor pad on a second surface of the semiconductor die, and the second conductor pad is operably connected to the bottom conductive layer of the power substrate, The top-cooled semiconductor package, A third contact located on the bottom surface of the housing within the housing, And a second electrical connector that operably connects the third contact to the bottom conductive layer of the power substrate The top-cooled semiconductor package according to claim 6, further comprising.

9. The first electrical connector is one of a first wire bond, a first conductive segment, or a first conductive clip, The top-cooled semiconductor package according to claim 8, wherein the second electrical connector is one of a second wire bond, a second conductive segment, or a second conductive clip.

10. The semiconductor die includes a metal oxide semiconductor field effect transistor (MOSFET), The first conductor pad is a source conductor pad operably connected to the source of the MOSFET, The second conductor pad is a drain conductor pad operably connected to the drain of the MOSFET, The semiconductor die further includes a gate conductor pad on the first surface of the semiconductor die, and the gate conductor pad is operably connected to the gate of the MOSFET, The top-cooled semiconductor package according to claim 8, further comprising a third electrical connector that operably connects the gate conductor pad to a gate pin on the bottom surface of the housing.

11. The top-cooled semiconductor package according to claim 10, further comprising a fourth electrical connector that operably connects a Kelvin pin on the bottom surface of the housing to the source conductor pad of the semiconductor die.

12. The surface of the housing is the top surface of the housing, The top-cooled semiconductor package according to any one of claims 1 to 11, wherein the creepage extension structure provides a creepage distance within a range of 12 millimeters (mm) to 20 mm between the pin or lead and the first contact.

13. The top surface cooled semiconductor package according to claim 12, wherein the creepage extension structure includes at least one trench further extending into at least one circumferential surface of the housing.

14. The top surface cooled semiconductor package according to any one of claims 1 to 13, wherein the creepage extension structure provides a creepage distance within a range of 5 millimeters (mm) to 15 mm, or within a range of 3 mm to 10 mm.

15. The top surface cooled semiconductor package according to any one of claims 1 to 14, wherein the top surface cooled semiconductor package is a leadless top surface cooled semiconductor package.

16. A top surface cooled semiconductor package including a housing having a top surface and a bottom surface, a heat sink operably connected to the top surface of the housing, a circuit board operably connected to the bottom surface of the housing, A system comprising: wherein the top surface cooled semiconductor package a first contact located within the housing on the top surface of the housing, wherein the first contact and the heat sink are included in a heat transfer path for the top surface cooled semiconductor package; a semiconductor die located within the housing below the first contact, the semiconductor die having a conductor pad on a first surface of the semiconductor die; a second contact located within the housing on the bottom surface of the housing; an electrical connector operably connecting the second contact to the conductor pad of the semiconductor die; a creepage extension structure extending into at least one surface of the housing, the creepage extension structure comprising one or more trenches A system comprising.

17. The top surface cooled semiconductor package is operably connected to a first surface of the circuit board, The system according to claim 16, further comprising an electronic component operably attached to a second surface of the circuit board.

18. The conductor pad is a first conductor pad, the semiconductor die further includes a second conductor pad on a second surface of the semiconductor die, The system according to claim 16, wherein the first contact is operably connected to the second conductor pad of the semiconductor die.

19. The semiconductor die includes a diode, the first conductor pad is a first terminal conductor pad operably connected to a first terminal of the diode, The system according to claim 18, wherein the second conductor pad is a second terminal conductor pad operably connected to a second terminal of the diode.

20. The semiconductor die includes a transistor, the first conductor pad is a first terminal conductor pad operably connected to a first terminal of the transistor, the second conductor pad is a second terminal conductor pad operably connected to a second terminal of the transistor, the semiconductor die further includes a third terminal conductor pad on the first surface of the semiconductor die, and the third terminal conductor pad is operably connected to a third terminal of the transistor, the system according to claim 18.

21. The system according to any one of claims 16 to 20, wherein the top-cooled semiconductor package further includes a power substrate positioned between the first contact and the semiconductor die.

22. The system according to claim 21, wherein the power substrate includes an insulating layer between a first conductive layer and a second conductive layer.

23. The electrical connector is a first electrical connector, the conductor pad is a first conductor pad, the semiconductor die further includes a second conductor pad on a second surface of the semiconductor die, and the second conductor pad is operably connected to the second conductive layer of the power substrate, the top-cooled semiconductor package, a third contact located on the bottom surface of the housing within the housing, and a second electrical connector operably connecting the third contact to the second conductive layer of the power substrate The system according to claim 21, further comprising.

24. The first electrical connector is one of a first wire bond, a first conductive segment, or a first conductive clip, The system according to claim 23, wherein the second electrical connector is one of a second wire bond, a second conductive segment, or a second conductive clip.

25. The semiconductor die includes a metal oxide semiconductor field effect transistor (MOSFET), the first conductor pad is a source conductor pad operably connected to the source of the MOSFET, the second conductor pad is a drain conductor pad operably connected to the drain of the MOSFET. The semiconductor die further includes a gate conductor pad on the first surface of the semiconductor die, and the gate conductor pad is operably connected to the gate of the MOSFET. The system according to claim 23, wherein the top-cooled semiconductor package further includes a third electrical connector that operably connects the gate conductor pad to a gate pin on the bottom surface of the housing. **Claim 26** The system according to claim 25, wherein the top-cooled semiconductor package further includes a fourth electrical connector that operably connects a Kelvin pin on the bottom surface of the housing to the source conductor pad. **Claim 27** At least one surface of the housing is the top surface. The system according to any one of claims 16 to 20, wherein the creepage extension structure provides a creepage distance within a range of 5 millimeters (mm) to 20 mm between the pin or lead and the first contact. **Claim 28** At least one surface of the housing is the top surface and at least one peripheral surface of the housing. The system according to any one of claims 16 to 27, wherein the creepage extension structure includes at least one trench extending into the top surface of the housing and the at least one peripheral surface of the housing. **Claim 29** The system according to any one of claims 16 to 28, further comprising an interface material between the heat sink and the top surface of the housing. **Claim 30** The system according to any one of claims 16 to 29, wherein the top-cooled semiconductor package is a leadless top-cooled semiconductor package. **Claim 31** The system according to any one of claims 16 to 30, wherein the creepage extension structure provides a creepage distance within a range of 12 millimeters (mm) to 15 mm or within a range of 3 mm to 10 mm. **Claim 32** A top-cooled semiconductor package, comprising: a housing; a first contact located on the top surface of the housing within the housing; a semiconductor die located below the first contact within the housing, the semiconductor die including a conductor pad on a first surface of the semiconductor die; a power substrate located between the first contact and a second surface of the semiconductor die within the housing, the first contact and the power substrate being included in a heat transfer path of the top-cooled semiconductor package. a second contact located on the bottom surface of the housing within the housing and an electrical connector operably connecting the second contact to the conductor pad of the semiconductor die, A top surface cooled semiconductor package comprising:

33. The top surface cooled semiconductor package according to claim 32, wherein the power substrate includes an insulating layer between a first conductive layer and a second conductive layer.

34. wherein the electrical connector is a first electrical connector, the conductor pad is a first conductor pad, the semiconductor die includes a second conductor pad on the second surface of the semiconductor die, the second conductive layer is operably connected to the second conductor pad, the top surface cooled semiconductor package includes a third contact located on the bottom surface of the housing within the housing, and a second electrical connector operably connecting the third contact to the second conductive layer such that the third contact is operably connected to the second conductor pad of the semiconductor die The top surface cooled semiconductor package according to claim 33, further comprising:

35. The top surface cooled semiconductor package according to any one of claims 32 to 34, further comprising a creepage extension structure extending into the top surface of the housing, the creepage extension structure including one or more trenches.

36. The top surface cooled semiconductor package according to claim 35, wherein the creepage extension structure provides a creepage distance within a range of 5 millimeters (mm) to 20 mm between a pin or lead and the first contact.

37. The top surface cooled semiconductor package according to claim 35, wherein the creepage extension structure includes at least one trench further extending into at least one peripheral surface of the housing.

38. The top surface cooled semiconductor package according to any one of claims 32 to 37, wherein the top surface cooled semiconductor package is a leadless top surface cooled semiconductor package.

39. A top surface cooled semiconductor package, comprising a housing, and a first contact located on the top surface of the housing within the housing, the first contact being included in a heat transfer path of the top surface cooled semiconductor package. A semiconductor die located below the first contact within the housing, the semiconductor die having a first conductor pad on a first surface (upper surface) of the semiconductor die operably connected to the first contact, and a second conductor pad on a second surface (bottom surface) of the semiconductor die; A second contact located on the bottom surface of the housing within the housing; An electrical connector operably connecting the second contact to the second conductor pad of the semiconductor die Comprising an upper surface cooled semiconductor package.

40. The upper surface cooled semiconductor package according to claim 39, further comprising a creepage extension structure extending into the upper surface of the housing, the creepage extension structure comprising one or more trenches.

41. The upper surface cooled semiconductor package according to claim 40, wherein the creepage extension structure provides a creepage distance within a range of 5 millimeters (mm) to 20 mm between the pin or lead and the first contact.

42. The upper surface cooled semiconductor package according to claim 40, wherein the creepage extension structure includes at least one trench further extending into at least one peripheral surface of the housing.

43. The upper surface cooled semiconductor package according to any one of claims 39 to 42, further comprising a second electrical connector operably connected to the first contact.

44. The semiconductor die includes a diode, The first conductor pad is a first terminal conductor pad operably connected to the first terminal of the diode, The upper surface cooled semiconductor package according to any one of claims 39 to 42, wherein the second conductor pad is a second terminal conductor pad operably connected to the second terminal of the diode.

45. The semiconductor die includes a transistor, The first conductor pad is a first terminal conductor pad operably connected to the first terminal of the transistor, The second conductor pad is a second terminal conductor pad operably connected to the second terminal of the transistor, The upper surface cooled semiconductor package according to any one of claims 39 to 42, wherein the semiconductor die further comprises a third terminal conductor pad on the first surface of the semiconductor die, and the third terminal conductor pad is operably connected to the third terminal of the transistor.

46. The top surface cooled semiconductor package according to any one of claims 39 to 45, wherein the electrical connector is one of a wire bond, a conductive segment, or a conductive clip.

47. The top surface cooled semiconductor package according to any one of claims 39 to 46, further comprising an interface material between the heat sink and the top surface of the housing.

48. The top surface cooled semiconductor package according to any one of claims 39 to 47, wherein the top surface cooled semiconductor package is a leadless top surface cooled semiconductor package.

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