Hybrid Bonding of Semiconductor Structures to Advanced Substrate Panels

Abstract

A method for bonding a semiconductor surface enables a heterogeneous integration architecture using a hybrid bonding process. In some embodiments, these methods may include forming a semiconductor structure on a silicon-based substrate, the semiconductor structure having a first set of conductive connections exposed on the top surface of the semiconductor structure. The first set of exposed conductive connections having a pitch of less than about 10 μm. Forming an advanced rectangular substrate panel having a second set of exposed conductive connections. The second set of exposed conductive connections having a pitch of less than about 10 μm. Bonding the semiconductor structure to the advanced rectangular substrate panel by bonding the top surface of the semiconductor structure to the top surface of the advanced rectangular substrate panel using a hybrid bonding process.

Description

Technical Field

[0001] Embodiments of the principles of the present invention generally relate to semiconductor processing of semiconductor substrates.

Background Art

[0002] In conventional processes, semiconductor chips are fabricated in a front end of the line (FEOL) process, and redistribution layers (RDLs) are formed in a subsequent packaging process to enable electrical connections to the chips. However, since additional space is required to connect to the RDL, the RDL reduces the input / output (IO) density of the chip. In some examples, a fan-out method of providing connections may further reduce the IO density of the chip. To enable proper connections, similar low-IO density connections are formed on the substrate in a back end of the line (BEOL) process to align with the RDL connections on the chip. The chip is then bonded to the substrate using a thermocompression bonding process, and the RDL is connected to a printed circuit board (PCB) using solder bumps. The formation of the RDL and the reduced IO density increase the cost and number of components of the manufacturing process. In addition, the circular shape of the silicon substrate limits the effective area of the substrate on which rectangular chips can be bonded, further increasing the manufacturing cost per unit.

[0003] Accordingly, the inventors of the present invention have provided a method for increasing the IO density, which enables a much higher chip connection bandwidth while reducing the number of manufacturing components and costs.

Summary of the Invention

[0004] This specification describes an architecture and method for increasing the IO connection density by hybrid bonding of chips to advanced rectangular substrate panels.

[0005] In some embodiments, a method for bonding a semiconductor surface includes forming a first semiconductor structure on a silicon-based substrate, the first semiconductor structure having a first set of conductive connections exposed on a first top surface of the semiconductor structure, the first set of exposed conductive connections being dispersed within a first non-conductive material layer, the first set of exposed conductive connections having a pitch of less than about 10 μm; forming an advanced rectangular substrate panel, the advanced rectangular substrate panel having a second set of conductive connections exposed on a top surface of the advanced rectangular substrate panel, the second set of exposed conductive connections being dispersed within a second non-conductive material layer different from the first non-conductive material layer, the second set of exposed conductive connections having a pitch of less than about 10 μm; directly bonding the first non-conductive material layer to the second non-conductive material layer; and bonding the first top surface of the first semiconductor structure to the top surface of the advanced rectangular substrate panel using a hybrid bonding process to directly bond the first set of exposed conductive connections to the second set of exposed conductive connections.

[0006] In some embodiments, the method further includes that the second non-conductive material layer is polyimide, the hybrid bonding process is performed at a temperature of about 200 degrees Celsius or less, the advanced rectangular substrate panel has no core, has an organic core, or has a glass core, the first non-conductive material layer is a first dielectric material different from the second dielectric material of the second non-conductive material layer, the advanced rectangular substrate panel is chemically mechanical polished (CMP) to a surface roughness (RA) of about 0.5 nm or less before performing the hybrid bonding process, the advanced rectangular substrate panel is about 510 mm × about 515 mm, the advanced rectangular substrate panel is about 205 mm × about 257.5 mm, the first semiconductor structure is formed without a controlled collapse chip connection (C4) layer, the first semiconductor structure is a chip or chiplet formed using a front end of the line (FEOL) process, the advanced rectangular substrate panel is formed using a front end of the line (FEOL) process, and / or the method may further be used to form a heterogeneous integration architecture on both sides of the advanced rectangular substrate panel.

[0007] In some embodiments, the method is to form a second semiconductor structure on a silicon-based substrate, the second semiconductor structure having a third set of conductive connections exposed on a second top surface of the second semiconductor structure, the third set of exposed conductive connections being dispersed within a third non-conductive material layer, the third set of exposed conductive connections having a pitch of less than about 10 μm; to form an advanced rectangular substrate panel, the advanced rectangular substrate panel having a fourth set of conductive connections exposed on a bottom surface of the advanced rectangular substrate panel, the fourth set of exposed conductive connections being dispersed within a fourth non-conductive material layer different from the third non-conductive material layer; to directly bond the third non-conductive material layer to the fourth non-conductive material layer and to directly bond the third set of exposed conductive connections to the fourth set of exposed conductive connections by using a hybrid bonding process to bond the second top surface of the second semiconductor structure to the bottom surface of the advanced rectangular substrate panel; and to further include bonding such that the first semiconductor structure bonded to the top surface of the advanced rectangular substrate and the second semiconductor structure bonded to the bottom surface of the advanced rectangular substrate panel are in a high-bandwidth electrical communication state.

[0008] In some embodiments, a method for bonding a semiconductor surface includes forming a semiconductor structure on a silicon-based substrate, the semiconductor structure having a first set of conductive connections exposed on a top surface of the semiconductor structure, the first set of exposed conductive connections being dispersed within a first non-conductive material layer, the semiconductor structure being a chip or die formed without a controlled collapse chip connection (C4) layer using a front end of the line (FEOL) process; forming an advanced rectangular substrate panel, the advanced rectangular substrate panel having a second set of conductive connections exposed on a top surface of the advanced rectangular substrate panel, the second set of exposed conductive connections being dispersed within a second non-conductive material layer different from the first non-conductive material layer; and bonding the first non-conductive material layer directly to the second non-conductive material layer and bonding the top surface of the semiconductor structure to the top surface of the advanced rectangular substrate panel using a hybrid bonding process to directly bond the first set of exposed conductive connections to the second set of exposed conductive connections.

[0009] In some embodiments, the method further includes the first set of exposed conductive connections having a pitch of less than about 10 μm, the second set of exposed conductive connections having a pitch of less than about 10 μm, the hybrid bonding process being performed at a temperature of about 200 degrees Celsius or less, and / or the advanced rectangular substrate panel having no core, having an organic core, or having a glass core.

[0010] In some embodiments, a non-transitory computer-readable medium having instructions stored thereon, the instructions, when executed, cause a method for bonding a semiconductor surface to be performed, the method comprising forming a semiconductor structure on a silicon-based substrate, the semiconductor structure having a first set of conductive connections exposed on a top surface of the semiconductor structure, the first set of exposed conductive connections being dispersed within a first non-conductive material layer, the first set of exposed conductive connections having a pitch of less than about 10 μm; forming an advanced rectangular substrate panel, the advanced rectangular substrate panel having a second set of conductive connections exposed on a top surface of the advanced rectangular substrate panel, the second set of exposed conductive connections being dispersed within a second non-conductive material layer different from the first non-conductive material layer, the second set of exposed conductive connections having a pitch of less than about 10 μm; and bonding the first non-conductive material layer directly to the second non-conductive material layer and bonding the first set of exposed conductive connections directly to the second set of exposed conductive connections by bonding a top surface of the semiconductor structure to a top surface of the advanced rectangular substrate panel using a hybrid bonding process. The non-transitory computer-readable medium may include these steps.

[0011] In some embodiments, the method of the non-transitory computer-readable medium may further include chemical mechanical polishing (CMP) the advanced rectangular substrate panel to a surface roughness (RA) of about 0.5 nm or less, or activating a top surface of the advanced rectangular substrate panel using a plasma process, before performing the hybrid bonding process; the semiconductor structure being a chip or chiplet formed without a controlled collapse chip connection (C4) layer using a front end of the line (FEOL) process; and / or the advanced rectangular substrate panel being formed using a front end of the line (FEOL) process.

[0012] Other embodiments and additional embodiments are disclosed below.

[0013] The embodiments of the present principle, briefly outlined above and later discussed in more detail, can be understood by reference to the exemplary embodiments of the present principle shown in the accompanying drawings. However, the accompanying drawings show only typical embodiments of the present principle and, therefore, should not be regarded as limiting the scope, as the present principle may admit of other equally effective embodiments.

Brief Description of the Drawings

[0014]

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Figures 10A - 10J

Modes for Carrying Out the Invention

[0015] For ease of understanding, where possible, the same reference numerals have been used to denote the same elements common to these figures. These figures are not drawn to scale and may be simplified for clarity. Without additional recitation, elements and features of one embodiment may be beneficially incorporated in other embodiments.

[0016] The method is a high-quality hybrid bonding process for directly attaching individual chips or chiplets to a packaging substrate, such as an advanced rectangular substrate panel, at a very high density (e.g., a pitch of less than 10 μm), providing a high-quality hybrid bonding process that enables advanced architectures for semiconductor manufacturing. The principle enables ultra-fine pitch direct chip-substrate integration, eliminates the need to use interposers for chip-chip and chip-substrate in printed circuit board (PCB) interconnects, and enables multi-chip modules with high-bandwidth chip-chip and chip-substrate communication. Additionally, the method and architecture provide the benefits of smaller interconnect lengths, such as enhancing reliability and thermal efficiency, minimizing resistance / capacitance (RC) losses (i.e., minimizing interface materials), without underfill (UF) and / or interface materials. Maximizing the substrate area is enabled by the use of an advanced rectangular substrate panel (e.g., rectangular / square chip-rectangular / square substrate vs. rectangular / square chip-circular substrate, etc.). Such a panel further provides economies of scale when processing a larger area compared to a silicon wafer.

[0017] Conventional processes use a solder-assisted flip-chip process that attaches conventional chips at a much larger pitch using thermocompression bonding (TCB). In conventional processes, it is common to use underfill as a dielectric between solder bumps for mechanical stability. Conventional wirebond / flip-chip structures have long interconnect lengths, providing high impedance, joule heating, and RF interference, among other things, at a limited input / output (IO) density. The method of the present principle uses a direct molecular bonding process for non-conductive and conductive interfaces between a chip and an advanced rectangular substrate panel. The feasibility of such a bonding process is achieved by reducing surface roughness, design optimization, and material selection. The reduced interface length provided by the present principle provides better electrical performance and a significantly higher IO density. Since underfill is not required in hybrid bonding, mechanical reliability is significantly increased. This enhanced process further enables a potential reduction in the number of metal layers or redistribution layers (RDLs) on the chip (e.g., elimination of at least the "C4" layer or controlled collapse chip connection layer on the chip is possible). Similarly, the enhanced process has the potential to reduce the number of process steps in the packaging process and shorten the packaging time (i.e., improve the cycle time). The present principle further provides greater flexibility in design for chip-substrate integration and improved electrical performance (e.g., direct copper-copper bonding with minimal electro-metallurgical interference and direct copper-copper bonding without electro-metallurgical interference, etc.).

[0018] The architecture and method of this principle utilize advanced substrates and hybrid bonding to form high-bandwidth, high-reliability, and high-density semiconductor chip packages. Hybrid bonding is a process of directly bonding a chip to a substrate, for example, but not limited to, direct metal-to-metal interconnect bonding and direct non-conductive-to-non-conductive material bonding between the chip and the substrate. The non-conductive materials bonded together may be the same material or different materials. Then, an annealing process may be used to bond the metal-metal contacts. In some embodiments, the metal contacts may be recessed to be lower than the top surface of the non-conductive material, and the annealing process expands the metal of the metal contacts to overcome the recess and bond the contacts. In some embodiments, the metal contacts may be approximately at the same height as the top surface of the non-conductive material, and an annealing process after bonding may not be necessary.

[0019] This principle facilitates achieving high I / O density connections by utilizing the use of advanced rectangular substrate panels. High I / O density connections enable the advanced architecture disclosed herein. The advanced rectangular substrate panel has a non-silicon core formed in a rectangular panel. The connections of the advanced rectangular substrate panel may be formed using processes related to the front-end-of-the-line (FEOL) manufacturing process. Semiconductor structures used herein are typically structures formed during FEOL manufacturing, which requires high-precision and complex manufacturing, and then packaged together with other structures or chips in a back-end-of-the-line (BEOL) process that includes simpler processing with much lower precision.

[0020] In the industry, FEOL semiconductor manufacturers own machine tools for standard circular silicon substrates, and panel manufacturers do not have equipment for performing FEOL processing. The architecture described in this specification using this principle will require a significant investment in machine tool equipment and a dramatic change in the overall semiconductor manufacturing process flow to enable the manufacture of such high IO density, high bandwidth devices.

[0021] Figure 1 is a top view 100A of a semiconductor structure 104, such as a chip or chiplet, disposed on a silicon substrate 102 having a circular shape. Since the semiconductor structure 104 is rectangular and the silicon substrate 102 is circular, a significant amount of the surface area 106 of the silicon substrate 102 is wasted due to the shape mismatch. In addition, in order to enable the attachment of the semiconductor structure 104 to the silicon substrate 102 as shown in the cross-sectional view 100B of FIG. 1, the semiconductor structure 104 typically utilizes an interposer 108. The cross-sectional view 700 of FIG. 7 is an enlarged view of the connection between the semiconductor structure 104, the interposer 108, and the silicon substrate 102. The interposer 108 receives a higher density connection 702 of circuits from within the semiconductor structure 104 and expands (to make the connection less dense) to form an interposer substrate connection 704. The interposer substrate connection 704 is typically a solder ball connection. The interposer 108 is very expensive to manufacture, and the complexity of the interconnection between the semiconductor structure 104 and the silicon substrate 102 requires a high precision that is difficult to achieve and time-consuming to achieve.

[0022] In some embodiments of the method of the present principle, as shown in the top view 200A of FIG. 2, the complete substrate panel 202 may be utilized as an advanced rectangular substrate panel. In some embodiments, the complete substrate panel 202 may have a width 206 of about 510 mm and a length 208 of 515 mm, etc. In some embodiments, the complete substrate panel may have a width 206 greater than about 510 mm and a length greater than about 515 mm. The cross-section of the complete substrate panel 202 is shown in FIG. 200B. In some embodiments, the complete substrate panel 202 may be cut into quarter substrate panels 204 to enable easier handling and / or to fit the manufacturing equipment, etc. In some embodiments, the quarter substrate panel 204 may have a width 210 of about 255 mm and a length 212 of about 257.5 mm (depending on the dimensions of the complete substrate panel 202), etc. To show that the wasted surface area 216 of the planar substrate panel is significantly reduced in contrast to the silicon substrate 102, the top view 200C of FIG. 2 shows a quarter substrate panel 204 having four semiconductor structures 214. The cross-sectional view 200D shows a quarter substrate panel 204 with the semiconductor structures 214 directly mounted on the quarter substrate panel 204 without using an interposer, etc., which is commonly seen in silicon substrates, thereby dramatically reducing the material cost and manufacturing time.

[0023] In FIG. 300 of FIG. 3, the semiconductor structure 302 on the bulk silicon 304 includes a FEOL structure 306 and a C4 layer 308, and the C4 layer 308 includes RDL 312 and solder bumps 310. Underfill 326 is used between the solder bumps 310 to stabilize the solder bumps, and additional processing, time, and cost are required to form the underfill 326 on the semiconductor structure 302. To interface with the C4 layer 308 of the semiconductor structure 302, the silicon substrate 314 is formed to have an interface layer 316. The through-silicon vias (TSVs) 318 provide internal connections to the backside connection 320 that incorporates the RDL 324 and the solder bumps 322 to enable connectivity between the silicon substrate and a PCB (not shown), etc. The connectivity between the semiconductor structure 302 and the silicon substrate 314 is achieved by the solder bumps 310 and the RDL 312 on the semiconductor structure 302. To enable connection to the silicon substrate 314, the RDL 312 extends the connection to the FEOL structure 306, typically in a fan-out layout that increases the connection area (reduces the connection density), and the silicon substrate 314 also includes RDL in the interface layer 316 to enable connectivity with the semiconductor structure 302. Thus, both the semiconductor structure 302 and the silicon substrate 314 have an extended connection area and fewer connections (a low IO connection density that provides a low bandwidth).

[0024] The inventors of the present invention observed the low connection density of conventional semiconductor structures for silicon substrate attachment and found that using an advanced rectangular substrate panel instead of a silicon substrate would facilitate an increase in the available chip placement area compared to conventional silicon substrates and enable a new advanced architecture. Additionally, the inventors of the present invention further observed that the C4 layer of a conventionally formed semiconductor structure significantly reduces the IO connection density. In the cross-sectional view 400 of FIG. 4 according to this principle, the FEOL structure 406 of the semiconductor structure 402 is formed on the bulk silicon 404 without a C4 layer. The direct connection to the FEOL structure 406 remains exposed on the top surface 426 of the semiconductor structure 402. Since RDL and solder bumps are not required when using the method and architecture of this principle, eliminating the C4 layer eliminates the need for underfill or other supporting dielectrics. Eliminating the C4 layer reduces the process time and cost while enabling an increase in IO density. In some embodiments, the pitch may be less than about 10 μm at the top surface 426 of the semiconductor structure 402, thereby dramatically increasing the IO density of the semiconductor structure 402.

[0025] The inventors of the present invention found that the use of an advanced rectangular substrate panel 414 formed using an FEOL process would enable an IO density similar to that achievable using the semiconductor structure 402 and negate the need for an interposer between the semiconductor structure 402 and the printed circuit board. In some embodiments, the advanced rectangular substrate panel 414 can be FEOL processed to provide an IO density several orders of magnitude greater than that of conventional silicon-based substrates, such as the substrates used for BEOL packaging processes, including, but not limited to, non-silicon-based substrate panels such as organic-based substrate panels, glass-based substrate panels, and / or non-core substrate panels. The use of a very smooth core material within the advanced rectangular substrate panel 414 helps to further increase the IO density by reducing the pitch.

[0026] In some embodiments, the advanced rectangular substrate panel 414 has a core 418, which may include core through vias (TCVs) 430 for transmitting connections from the high IO density layer 416 to the PCB via a connection layer 420, and the connection layer 420 may include RDLs 424 and solder bumps 422. The panel top surface 428 has exposed connections having an IO density that matches or is greater than the IO density of the top surface 426 of the semiconductor structure 402. In some embodiments, the advanced rectangular substrate panel 414 may be formed using an organic material to electrically isolate the high density IO connections. For example, but not limited to, a polymer such as polyimide may be used. Thus, the inventors of the present invention have struggled to provide a process that would enable bonding an inorganic material such as a dielectric used in a semiconductor structure to an organic material such as polyimide used in the advanced rectangular substrate panel 414. In some embodiments, the dielectric material used for electrical isolation may be provided to the advanced rectangular substrate panel 414 by, for example, Ajinomoto Build-up Film (registered trademark) (ABF).

[0027] The inventors of the present invention have found that a new chip functional architecture based on heterogeneous integration, as shown in the cross-sectional view 600 of FIG. 6, can be achieved by the ultra-high IO density and high bandwidth achievable between the semiconductor structure 402 and the advanced rectangular substrate panel 414. The heterogeneous integration architecture enables the coordination of the functions of conventional chip devices among a plurality of chips interconnected by high-bandwidth connections 602 in the high IO density layer 416 of the advanced rectangular substrate panel 414. By using the method of this principle, the speed and bandwidth required for the heterogeneous integration architecture are made possible. The chips can be manufactured in different manufacturing facilities to enable the optimal manufacturing of different aspects of what is used as a single chip. The chips may have performance compromises (e.g., reduced space, thermal load, etc.) due to the need to generate all functions within a single chip. Considering the high IO density and high bandwidth, this principle solves the need to generate all functions with a single chip without the conventional disadvantages (such as low bandwidth and long latency). In some embodiments, the advanced rectangular substrate panel 414 provides both a high IO density layer 416 that may be used for high-bandwidth connections 602 between chips and a connection layer 420 that enables external IO connections 604 to allow the coordinated chips to connect to a PCB or the like.

[0028] FIG. 800 of FIG. 8 shows an exemplary architecture using the above-described basic principle. A first semiconductor structure, such as a graphics processing unit (GPU) 806, is hybrid bonded to an advanced rectangular substrate panel 804 together with a second semiconductor structure, such as a logic die 808 having stacked dynamic random access memory (DRAM) 810. The advanced rectangular substrate panel 804 enables high-bandwidth communication between the GPU 806, the logic die 808, and the stacked DRAM 810. In addition, the advanced rectangular substrate panel 804 enables communication with a PCB 802 via solder bumps 812 on the opposite side of the semiconductor structure. This architecture not only creates a dramatic increase in communication between semiconductor structures, but the overall process of manufacturing the device has fewer process steps and lower costs than using a conventional architecture process. One of the factors reducing costs is that the alignment of the rectangular substrate structure to the rectangular panel allows the rectangular panel to achieve a reduction of more than 50% of the waste of the substrate. In addition, with respect to circular silicon wafer processing, typically six or more additional processes are required during the manufacture of semiconductor devices compared to a single advanced rectangular substrate panel.

[0029] A method 500 for forming and hybrid bonding a semiconductor structure and an advanced rectangular substrate panel is shown in FIG. 5. The preparation for forming and hybrid bonding the semiconductor structure and the advanced rectangular substrate panel may be performed sequentially, in parallel, or as a combination in a previous process before hybrid bonding. In block 502, a semiconductor structure having direct connectivity to the underlying structure is formed, such as a semiconductor structure having direct connectivity to the underlying structure without, for example, a C4 layer that reduces IO density. In some embodiments, the semiconductor structure is 1 mm 2It may be formed to have an IO density of about 10,000 IO or more per hit. The semiconductor structure is usually formed using a FEOL process. The semiconductor structure may be formed on bulk silicon or the like, using a conductive material such as, but not limited to, copper and / or aluminum, and / or a non-conductive material (e.g., a dielectric material) such as, but not limited to, silicon dioxide (SiO2), silicon carbonitride (SiCN). In block 504, the semiconductor structure is wet-cleaned to reduce the fine particles resulting from the formation process.

[0030] In block 506, to enable high-density IO connectivity, the semiconductor structure is planarized using a chemical mechanical process (CMP). The planarization process enables a pitch of about 10 μm or less. In some embodiments, the semiconductor structure is planarized to a surface roughness or RA of about 01.0 nm or less per 10 mm × 10 mm area. In some embodiments, the semiconductor structure is planarized to a surface roughness or RA of about 0.5 nm or less per 10 mm × 10 mm area. In block 508, measurements are performed on the semiconductor structure to determine whether there are defects such as dishing and other defects. In block 510, a backgrinding tape is attached to the semiconductor structure for preparation for backgrinding. In block 512, a backgrinding process is performed on the semiconductor structure to reduce the thickness of the semiconductor structure by removing the portion of bulk silicon on which the semiconductor structure is formed. In block 514, dicing / separation / singulation of the semiconductor structure is performed to enable each of the semiconductor structures to be individually picked up, placed, and bonded. In block 516, the semiconductor structure is subjected to another cleaning process to remove the fine particles generated by the previous process. In block 518, the semiconductor structure is subjected to plasma activation for preparation for hybrid grinding. In block 520, the semiconductor structure is wetted with deionized water before being subjected to a hybrid bonding process with an advanced rectangular substrate panel.

[0031] As described above, processes 522 to 536 for the preparation of an advanced rectangular substrate panel for hybrid bonding may be executed in parallel with, before, or after processes 502 to 520 for the preparation of a semiconductor substrate. At block 522, an advanced rectangular substrate panel is formed. This formation generally consists of several processes that produce the final advanced rectangular substrate panel. The non-conductive material used on the bonding surface of the advanced rectangular substrate panel to be bonded to the bonding surface of the semiconductor structure may be the same as the non-conductive material on the bonding surface of the semiconductor structure, or may be different from the non-conductive material on the bonding surface of the semiconductor structure. Since packaging processes such as RDL and solder bumps are not required for the hybrid bonding of the advanced rectangular substrate panel to the semiconductor structure, the advanced rectangular substrate panel may be formed entirely or at least partially by the FEOL process. In some embodiments, the formation process may include forming a complete substrate panel and / or forming a complete substrate panel and then reducing the complete substrate panel to a smaller size, such as a quarter substrate panel. Thus, when used in method 500 herein, the advanced rectangular substrate panel may be a complete substrate panel or a portion of a complete substrate panel (e.g., a quarter panel, etc.).

[0032] In some embodiments, the size of the complete substrate panel may be about 510 mm × about 515 mm, or may be larger or smaller than that. In optional block 524, the complete substrate panel may be diced or cut into smaller parts such as quarter substrate panels. In some embodiments, the quarter substrate panel may be about 205 mm × about 257.5 mm based on the size of the complete substrate panel, or may be smaller or larger than that. In some embodiments, the complete substrate panel may be cut into more than four smaller panels (for example, one large panel may be cut into six, eight or more than ten smaller panels). In block 526, the advanced rectangular substrate panel is cleaned to remove residues and / or generated fine particles. In block 528, the advanced rectangular substrate panel is planarized. The planarization process of the rectangular substrate panel is different from that of a circular substrate such as a substrate used in the formation of a semiconductor structure during the FEOL process. The planarization of the rectangular substrate panel requires an advanced CMP process similar to the process that achieves a surface roughness or RA of about 1.0 nm or less to enable a pitch of about 10 μm or less for use in FEOL.

[0033] In some embodiments, the CMP process provides a surface roughness or RA of about 0.5 nm or less. Typically, this RA is achieved over the entire surface area of the advanced rectangular substrate panel related to the field of view of a reticle having a surface area of about 10 mm × 10 mm. In some embodiments, the variation in the total thickness of the advanced rectangular substrate panel after planarization may be 1 μm or less between the minimum and maximum thicknesses of the panel. Since semiconductor structures hybrid-bonded to the advanced rectangular panel usually have a surface area much smaller than the panel, for hybrid bonding, the limited surface roughness of the panel is more important than the overall wide-area surface quality of the panel. Since the advanced rectangular substrate panel is not circular, the polishing surface of the CMP is usually rotating, and care must be taken to protect the edges of the rectangular panel during the CMP process. A dedicated jig may be used to protect the edges and maintain the total thickness of the panel.

[0034] In block 530, measurements are performed on the substrate panel to detect defects such as dicing of an advanced rectangular substrate panel, although not limited thereto. In block 532, the advanced rectangular substrate panel is cleaned to remove residues and / or particles. In block 534, the advanced rectangular substrate panel is subjected to a plasma activation process to prepare it for hybrid bonding to a semiconductor structure. In some embodiments, since alternative materials such as polymers with higher temperature sensitivity are used, the advanced rectangular substrate panel may use a plasma activation process different from the process used for a semiconductor substrate. In some embodiments, the intensity of the plasma used in the activation process for the polymer-based material may be lower than the intensity of the activation process for the non-polymer-based material. The plasma activation process performs activation at a temperature of about 15 degrees Celsius to about 25 degrees Celsius, which is close to room temperature. In block 536, in some examples, the advanced rectangular substrate panel may be wetted with deionized water. In other examples, the advanced rectangular substrate panel may be wetted with another ionic solution so as not to passivate the materials used in the advanced rectangular substrate panel.

[0035] In block 538, in the hybrid bonding process between the semiconductor structure and the advanced rectangular substrate panel, the semiconductor structure is picked up and placed on the advanced rectangular substrate panel. In block 540, an annealing process is performed to complete the hybrid bonding process by expanding the metal surface connections on the semiconductor structure and on the advanced rectangular substrate panel until those surface connections are joined together. The linear coefficient of thermal expansion (CTE) of the metal materials used in the semiconductor substrate and in the advanced rectangular substrate panel may be used to determine the parameters required for the bonding of the metal materials. In some embodiments, the metal contacts may be at approximately the same height as the top (or bottom) surface of the non-conductive material, and an annealing process may not be required after hybrid bonding.

[0036] In advanced rectangular substrate panels, when organic materials such as polymers are used, although not limited, the hybrid bonding process temperature may be limited. In some embodiments, the annealing process may be limited to a process temperature of about 90 degrees Celsius to about 200 degrees Celsius in order to protect the integrity of some types of non-conductive materials (such as polymer-based materials). The inventors of the present invention have found that by using processes such as selective laser annealing, microwave annealing and / or high-pressure environments, a lower annealing temperature necessary to protect the materials used in advanced rectangular substrate panels can be achieved. At block 542, measurements regarding hybrid bonding are performed to detect defects such as misalignment and / or bonding voids.

[0037] To produce an advanced rectangular substrate panel having high IO density connections on both sides of the substrate panel, the architecture and method of the present principle described above may be further modified. Enabling high-bandwidth processing between semiconductor structures bonded on the same side and further high-bandwidth processing with semiconductor substructures bonded on the opposite side dramatically increases the possible chip density of a single advanced rectangular substrate panel. Therefore, FEOL processing is used to form high-density connections on both sides. Such high IO density and chip density with high-bandwidth connections enable an unheard-of enhancement of the performance of products such as advanced supercomputers. FEOL processing on both sides of an advanced rectangular substrate panel increases the production cost of the panel, and such processing may be more suitable for extremely high-performance low-volume products.

[0038] FIG. 9 shows a method 900 of forming a double-sided advanced rectangular substrate panel having interconnected semiconductor structures on both sides. FIGS. 1000A-1000J of FIG. 10 may be referred to during the discussion of method 900. At block 902, an advanced rectangular substrate panel 1002 (see FIG. 10A) having a first surface connection 1004 on a first surface 1014 (e.g., a top surface) and a second surface connection 1006 on a second surface 1016 (e.g., a bottom surface) is formed. The first surface connection 1004 and the second surface connection 1006 are high IO density connections that enable high bandwidth connections on each surface. Core through vias (TCVs) 1008 are formed to connect the first surface connection 1004 to the second surface connection 1006 through a core 1010 of the advanced rectangular substrate panel 1002. The first surface connection 1004 is formed using the FEOL process described above for a single-sided panel. The second surface connection 1006 is formed using the FEOL process described above for a single-sided panel. The first surface connection 1004 and the second surface connection 1006 may be formed to have an IO density of about 10,000 IOs or more and interconnected TCVs per 1 mm 2 or so.

[0039] At block 904, as shown in FIG. 1000B of FIG. 10B, at least one first semiconductor structure 1012 (e.g., a chip, a chiplet, etc.) is hybrid bonded to the first surface 1014 of the advanced rectangular substrate panel 1002. This hybrid bonding process was described above with respect to a single-sided advanced rectangular substrate and semiconductor structure. After performing the bonding, the IO connections of at least one first semiconductor structure 1012 are connected to the IO connections of the first surface connection 1004. The IO connections of at least one first semiconductor structure 1012 are available for high-bandwidth connections to other semiconductor structures on the first surface 1014 and are also available for high-bandwidth connections to the second surface 1016 through the TCV. At block 906, as shown in FIG. 1000C of FIG. 10C, at least one first semiconductor structure 1012 on the first surface 1014 is encapsulated using a first encapsulation material 1022. The first encapsulation material 1022 protects at least one first semiconductor structure 1012 during subsequent processing and may further provide a base for attaching a carrier (not shown) to the first surface 1014 of the advanced rectangular substrate panel 1002 to provide stability for additional processing. The first encapsulation material 1022 may be a molding-type material and / or a dielectric-type material, etc.

[0040] At optional block 908, as shown in FIG. 1000D of FIG. 10D, the top surface 1018 of the first encapsulation material 1022 may be planarized by a CMP process. In some embodiments, this planarization may be performed to make the top surface 1018 flat for applying carriers, etc. for subsequent handling and processing. In some embodiments, this planarization may remove the first encapsulation material 1022 to a level 1020 that exposes one or more top surfaces of at least one first semiconductor structure 1012 to enable the placement of thermal control devices, etc. (such as thermal pads, thermal tapes, heat sinks, etc.). At block 910, as shown in FIG. 1000E of FIG. 10E, the advanced rectangular substrate panel 1002 is flipped over so that the second surface 1016 becomes the top surface and the first surface 1014 becomes the bottom surface. At block 912, as shown in FIG. 1000F of FIG. 10F, at least one second semiconductor structure 1024 (such as a chip, chiplet, etc.) is hybrid bonded to the second surface 1016 of the advanced rectangular substrate panel 1002. This hybrid bonding process was described above with respect to a single-sided advanced rectangular substrate and semiconductor structures. After performing the bonding, the IO connections of at least one second semiconductor structure 1024 are connected to the IO connections of the second surface connection 1006. The IO connections of at least one second semiconductor structure 1024 are available for high-bandwidth connections to other semiconductor structures on the second surface 1016 and are also available for high-bandwidth connections to the first surface 1014 through the TCV.

[0041] In block 914, at least one second semiconductor structure 1024 on the second surface 1016 is encapsulated using a second encapsulation material 1026, as shown in FIG. 1000G of FIG. 10G. The second encapsulation material 1026 protects at least one second semiconductor structure 1024 during subsequent processing and may further provide a base for constructing external connections (such as vias, RDL, etc.) to the second surface 1016 of the advanced rectangular substrate panel 1002. In some embodiments, the first encapsulation material 1022 and the second encapsulation material 1026 may be the same material or different materials. The second encapsulation material 1026 may be a molding-type material and / or a dielectric-type material, etc. In block 916, an external connection 1028 is formed on the second surface 1016 of the advanced rectangular substrate 1002, as shown in FIG. 1000H of FIG. 10H. The external connection 1028 may include RDL and a through-mold via (TMV) 1030 that provides a connection to the second surface connection 1006 and subsequently provides a connection to the first surface connection 1004 through the TCV 1008. In some embodiments, the second encapsulation material 1026 may be planarized by a CMP process to enable the formation of fine-pitch RDL.

[0042] In block 918, a PCB connection 1032 (such as a solder ball, etc.) is formed on the second surface 1016 of the advanced rectangular substrate panel 1002, as shown in FIG. 1000I of FIG. 10I. The PCB connection 1032 enables external connections to be made to at least one first semiconductor structure 1012 and / or at least one second semiconductor structure 1024, etc. In FIG. 1000J of FIG. 10J, the advanced rectangular substrate panel 1002 is flipped over and mounted on the PCB 1034. The architecture of this principle enables the construction of an assembly with high-bandwidth capabilities between the semiconductor structures on each surface and between the surfaces of the advanced rectangular substrate panel 1002, while maintaining compatibility with PCB-type external connections and compatibility with fewer components (such as the absence of an interposer, etc.), increasing reliability and performance. In fact, this architecture will enable heterogeneous integration architectures and next-generation supercomputers.

[0043] Embodiments in accordance with this principle may be implemented in hardware, firmware, software, or any combination thereof. Embodiments may be implemented as instructions stored on one or more computer-readable media, which may be read and executed by one or more processors. A computer-readable media may include a mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing platform or a "virtual machine" running on one or more computing platforms). For example, a computer-readable media may include any suitable form of volatile or non-volatile memory. In some embodiments, a computer-readable media may include a non-transitory computer-readable media.

[0044] The foregoing description is directed to embodiments of this principle, but other and additional embodiments of this principle may be devised without departing from the basic scope of this principle.

Claims

1. A method for bonding a semiconductor surface, comprising: forming a first semiconductor structure on a silicon-based substrate, the first semiconductor structure having a first set of conductive connections exposed on a first top surface of the first semiconductor structure, the first set of exposed conductive connections being dispersed within a first non-conductive material layer, and the first set of exposed conductive connections having a pitch of less than about 10 μm; forming an advanced rectangular substrate panel, the advanced rectangular substrate panel having a second set of conductive connections exposed on a top surface of the advanced rectangular substrate panel, the second set of exposed conductive connections being dispersed within a second non-conductive material layer different from the first non-conductive material layer, and the second set of exposed conductive connections having a pitch of less than about 10 μm; bonding the first non-conductive material layer directly to the second non-conductive material layer and bonding the first set of exposed conductive connections directly to the second set of exposed conductive connections by using a hybrid bonding process to bond the first top surface of the first semiconductor structure to the top surface of the advanced rectangular substrate panel; A method comprising the above steps.

2. The method according to claim 1, wherein the second non-conductive material layer is polyimide.

3. The method according to claim 1, wherein the hybrid bonding process is performed at a temperature of about 200 °C or less.

4. The method according to claim 1, wherein the advanced rectangular substrate panel has no core, has an organic core, or has a glass core.

5. The method according to claim 1, wherein the first non-conductive material layer is a first dielectric material different from a second dielectric material of the second non-conductive material layer.

6. The method according to claim 1, further comprising chemical mechanical polishing (CMP) the advanced rectangular substrate panel to a surface roughness (RA) of about 0.5 nm or less before performing the hybrid bonding process. A method comprising the above steps.

7. Forming a second semiconductor structure on a silicon-based substrate, the second semiconductor structure having a third set of conductive connections exposed on a second top surface of the second semiconductor structure, the third set of exposed conductive connections being dispersed within a third non-conductive material layer, the third set of exposed conductive connections having a pitch of less than about 10 μm; Forming the advanced rectangular substrate panel, the advanced rectangular substrate panel having a fourth set of conductive connections exposed on a bottom surface of the advanced rectangular substrate panel, the fourth set of exposed conductive connections being dispersed within a fourth non-conductive material layer different from the third non-conductive material layer; Bonding the second top surface of the second semiconductor structure to the bottom surface of the advanced rectangular substrate panel using a hybrid bonding process to directly bond the third non-conductive material layer to the fourth non-conductive material layer and directly bond the third set of exposed conductive connections to the fourth set of exposed conductive connections, such that the first semiconductor structure bonded to the top surface of the advanced rectangular substrate panel and the second semiconductor structure bonded to the bottom surface of the advanced rectangular substrate panel are in a high-bandwidth electrical communication state; The method according to claim 1, further comprising.

8. The method according to claim 1, wherein the advanced rectangular substrate panel is about 510 mm × about 515 mm.

9. The method according to claim 1, wherein the advanced rectangular substrate panel is about 205 mm × about 257.5 mm.

10. The method according to claim 1, wherein the first semiconductor structure is formed without a controlled collapse chip connection (C4) layer.

11. The method according to claim 1, wherein the first semiconductor structure is a chip or chiplet formed using a front end of line (FEOL) process.

12. The method according to claim 1, wherein the advanced rectangular substrate panel is formed using a front end of line (FEOL) process.

13. The method according to claim 1, used for forming a heterogeneous integration architecture on both sides of the advanced rectangular substrate panel.

14. A method for bonding semiconductor surfaces, comprising: Forming a semiconductor structure on a silicon-based substrate, the semiconductor structure having a first set of conductive connections exposed on a top surface of the semiconductor structure, the first set of exposed conductive connections being dispersed within a first non-conductive material layer, and the semiconductor structure being a chip or die formed without a controlled collapse chip connection (C4) layer using a front end of line (FEOL) process; Forming an advanced rectangular substrate panel, the advanced rectangular substrate panel having a second set of conductive connections exposed on a top surface of the advanced rectangular substrate panel, the second set of exposed conductive connections being dispersed within a second non-conductive material layer different from the first non-conductive material layer; Bonding the top surface of the semiconductor structure to the top surface of the advanced rectangular substrate panel using a hybrid bonding process to directly bond the first non-conductive material layer to the second non-conductive material layer and to directly bond the first set of exposed conductive connections to the second set of exposed conductive connections; A method comprising.

15. The method of claim 14, wherein the first set of exposed conductive connections has a pitch of less than about 10 μm and the second set of exposed conductive connections has a pitch of less than about 10 μm.

16. The method of claim 14, wherein the hybrid bonding process is performed at a temperature of about 200 degrees Celsius or less.

17. The method of claim 14, wherein the advanced rectangular substrate panel has no core, has an organic core, or has a glass core.

18. A non-transitory computer-readable medium having instructions stored thereon, the instructions, when executed, causing a method for bonding semiconductor surfaces to be performed, the method comprising: Forming a semiconductor structure on a silicon-based substrate, the semiconductor structure having a first set of conductive connections exposed on a top surface of the semiconductor structure, the first set of exposed conductive connections being dispersed within a first non-conductive material layer, and the first set of exposed conductive connections having a pitch of less than about 10 μm; forming an advanced rectangular substrate panel, the advanced rectangular substrate panel having a second set of conductive connections exposed on a top surface of the advanced rectangular substrate panel, the second set of exposed conductive connections being dispersed within a second non-conductive material layer different from the first non-conductive material layer, the second set of exposed conductive connections having a pitch of less than about 10 μm, bonding the top surface of the semiconductor structure to the top surface of the advanced rectangular substrate panel using a hybrid bonding process to directly bond the first non-conductive material layer to the second non-conductive material layer and to directly bond the first set of exposed conductive connections to the second set of exposed conductive connections A non-transitory computer-readable medium comprising. Claims 19 The method is chemically mechanically polishing (CMP) the advanced rectangular substrate panel to a surface roughness (RA) of about 0.5 nm or less before performing the hybrid bonding process, or activating the top surface of the advanced rectangular substrate panel using a plasma process The non-transitory computer-readable medium according to claim 18, further comprising. Claims 20 the semiconductor structure is a chip or chiplet formed without a controlled collapse chip connection (C4) layer using a front end of line (FEOL) process, or the advanced rectangular substrate panel is formed using a front end of line (FEOL) process, The non-transitory computer-readable medium according to claim 18.

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