Dynamically controlling a secondary switch to achieve zero voltage switching

Abstract

Zero voltage switching using a secondary switch (e.g., synchronous rectifier) is described herein. The method enables a secondary side controller to calculate a secondary switch holding period that is required. By measuring a forward pin voltage when a primary switch is in a conducting state, the required secondary switch holding period can be determined without requiring communication from the primary side to the secondary side.

Description

Technical Field

[0001] Cross - reference to Related Applications

[0001] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 391,082, filed on July 21, 2022, the entire content of which is incorporated herein by reference.

[0002]

[0002] The present invention relates to zero - voltage switching using a secondary switch, and more particularly to using a secondary switch to enable zero - voltage switching in a flyback converter.

Background Art

[0003]

[0003] Many electronic devices, such as mobile phones, laptops, etc., are powered by direct - current (DC) power obtained from a power source. Conventional wall outlets generally transmit high - voltage alternating - current (AC) power that needs to be converted to regulated DC power for use as a power source for consumer - oriented electronic devices. Switch - mode power converters, also known as switching - mode power supplies (SMPS), are commonly used because of their high efficiency, small size, and light weight.

[0004]

[0004] Many electronic devices include multiple loads and require more than one DC power supply to operate. For example, an audio electronic device may include system components that operate at 5 volts and audio components that operate between 12 volts and 20 volts. In these applications, a multi-output power converter converts AC power into multiple DC power outputs to provide regulated DC power to each of the multiple loads, i.e., the system components and the audio components. In some applications, the regulated DC power output is a regulated constant current (CC) output and / or a regulated constant voltage (CV) output.

Summary of the Invention

[0005]

[0005] Non-limiting and non-exhaustive embodiments for dynamically controlling a secondary switch to achieve zero voltage switching are described with reference to the following figures, where like reference numerals indicate like parts throughout the various drawings unless otherwise specified.

Brief Description of the Drawings

[0006]

Figure 1A

[0006] FIG. 1A shows a power converter system according to a one-output embodiment.

Figure 1B

[0007] FIG. 1B shows a power converter system according to another embodiment.

Figure 1C

[0008] FIG. 1C shows a power converter system according to another embodiment.

Figure 1D

[0009] FIG. 1D shows a power converter system according to another embodiment.

Figure 1E

[0010] FIG. 1E shows a power converter system according to a multi-output embodiment.

Figure 1F

[0011] FIG. 1F shows a power converter system according to another embodiment.

Figure 1G

[0012] Figure 1G shows a power converter system according to another embodiment.

Figure 1H

[0013] Figure 1H shows a power converter system according to another embodiment.

Figure 2A

[0014] Figure 2A shows waveforms during a switching cycle.

Figure 2B

[0015] Figure 2B shows waveforms during a switching cycle according to an embodiment.

Figure 2C

[0016] Figure 2C shows waveforms during a switching cycle according to an embodiment.

Figure 2D

[0017] Figure 2D shows waveforms during a switching cycle according to another embodiment.

Figure 3A

[0018] Figure 3A shows a conceptual flowchart for zero voltage switching in a power converter system according to an embodiment.

Figure 3B

[0019] Figure 3B shows a conceptual flowchart for zero voltage switching in a power converter system according to another embodiment.

Figure 4

[0020] Figure 4 compares two switching cycles of a primary switch according to an embodiment.

Best Mode for Carrying Out the Invention

[0007]

[0021] Throughout the several views of the drawings, corresponding reference numerals indicate corresponding components. Those skilled in the art will appreciate that the elements in the figures are drawn to be simple and clear, and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to make the various embodiments of the teachings herein easier to understand. Further, commonly understood elements that are useful or necessary in a commercially suitable embodiment are often not shown so as not to obscure the figures of these various embodiments for dynamically controlling a secondary switch to achieve zero voltage switching.

[0008]

[0022] In the following description, numerous specific details are set forth in order to provide a thorough understanding of dynamically controlling a secondary switch to achieve zero voltage switching. However, it will be apparent to those skilled in the art that specific details are not necessarily used to practice the teachings herein. In other instances, well-known materials or methods have not been described in detail so as not to obscure the present disclosure.

[0009]

[0023] References herein to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment of the (multi-output) switching power converter system. Accordingly, the use of the phrases "in one embodiment," "in an embodiment," "an example," or "an example" in various places herein are not necessarily all referring to the same embodiment or example. Further, the particular features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples. The particular features, structures, or characteristics may be included in an integrated circuit, an electronic circuit, a logic circuit, or other suitable component that provides the described functionality. Additionally, it is understood that the figures provided herein are for the purpose of explanation to those skilled in the art and are not necessarily drawn to scale.

[0010]

[0024] In the context of the present application, when a transistor is "off" or "in the off state", the transistor blocks current and / or substantially no current flows. Conversely, when a transistor is "on" or "in the on state", the transistor can substantially conduct current. By way of example, in one embodiment, a high-voltage transistor comprises an N-channel metal-oxide-semiconductor (NMOS) field-effect transistor (FET) that supports a high voltage between a drain, which is a first terminal, and a source, which is a second terminal. In some embodiments, an integrated control device circuit may be used to drive a power switch when regulating the energy provided to a load. Further, for the purposes of the present disclosure, "ground" or "ground potential" represents a reference voltage or reference potential with respect to which all other voltages or potentials of an electronic circuit or integrated circuit (IC) are defined or measured. Further, according to power electronics theory, "power" transfer may be implied by "energy" transfer. Conversely, "energy" transfer may be implied by "power" transfer (i.e., power is related to the rate of change of energy).

[0011]

[0025] A multi-output power converter may be used to provide regulated DC power to a plurality of loads. The loads can be passive loads and / or active loads including discrete semiconductor devices, microprocessors, control devices, mixed-signal circuit components, and the like. In providing regulated DC power, the multi-output power converter can regulate the output current to a constant current (CC) output and / or regulate the output voltage to a constant voltage (CV) output. Further, the system voltage can be defined in relation to how the multi-output power converter provides power. For example, the multi-output power converter can provide a CC output operating at about 50 volts, a CV output regulated to 12 volts, and a CV output regulated to 5 volts.

[0012]

[0026] Electric power can be transferred from the primary side to the secondary side through an energy transfer element (e.g., a transformer) according to a switching cycle. For example, a primary switch can switch according to a switching cycle, in which case the primary winding receives input power over a part of the switching cycle, and one or more secondary windings provide power over another part of the switching cycle. When power is transferred such that the current in the secondary winding (i.e., the secondary current) is reduced to substantially zero before the completion of the switching cycle, the operating mode can be called the discontinuous conduction mode (DCM). Alternatively, when power (i.e., energy) is transferred such that the current in the secondary winding does not reduce to zero before the completion of the switching cycle, the operating mode can be called the continuous conduction mode (CCM).

[0013]

[0027] Furthermore, during one switching cycle (i.e., one switching period), power (i.e., energy) can be transferred to a selected one of the multiple outputs.

[0014]

[0028] In a power converter, a power converter system, a multi-output (multiple output) power converter, and a multi-output power converter system, the efficiency can be improved by reducing switching losses. For example, the switching losses can be improved (i.e., reduced) by switching the primary switch according to a zero voltage switching (ZVS) switching cycle.

[0015]

[0029] Zero Voltage Switching (ZVS) can beneficially reduce the voltage of the primary switch during switching. Ideally, ZVS can control the voltage across the primary switch such that it becomes substantially zero (e.g., approaches 0 volts) when the primary switch turns on. For example, when the primary switch is implemented as a Power Field Effect Transistor (FET), ZVS may be achieved by controlling the drain-to-source voltage of the FET such that it becomes substantially zero when the FET turns on.

[0016]

[0030] Attempts to switch the primary side switch according to the ZVS cycle are limited to systems that assume communication from the primary side to the secondary side. For example, a Synchronous Rectifier (SR) Field Effect Transistor (FET) can be switched strategically based on information related to the primary switch (e.g., state, primary voltage, primary current). Unfortunately, in modern conventional power converters and power converter systems, communication from the primary side to the secondary side may not be available.

[0017]

[0031] Therefore, there is a need to enable ZVS in power converters and power converter systems without the constraint of including communication from the primary side to the secondary side.

[0018]

[0032] Dynamically controlling a secondary switch (e.g., a synchronous rectifier and / or an SR FET) to achieve zero voltage switching is described herein. The method enables a secondary side controller to calculate the required secondary switch holding period (i.e., the secondary switch on period). By measuring the forward pin voltage when the primary switch is in the conduction state, the required secondary switch holding period can be determined without the need for communication from the primary side to the secondary side.

[0019]

[0033] Figure 1A shows a power converter system 100 according to an embodiment with one output. The power converter system 100 includes an energy transfer element 102, a secondary switch block 104, a load circuit 106, a secondary control device 108, a primary control device 109, a clamp 110, and a primary switch 152. The energy transfer element 102 includes a primary winding 112 and a secondary winding 99. The secondary switch block 104 includes an N-channel field effect transistor (NFET) 126.

[0020]

[0034] The output power converter system 100 converts input power derived from a rectified AC line voltage V IN and can provide output power with an output voltage V O1 and a secondary current I S1 . Alternatively, and additionally, the input power can be introduced from a high voltage power source. The load circuit 106 includes a feedback network 140, a filter capacitor C1, and a first load 142.

[0021]

[0035] As shown, the feedback network 140, the filter capacitor C1, and the first load 142 are electrically coupled. The feedback network 140 can provide a feedback signal FB to the secondary control device 108. In a steady state, the power converter system 100 of Figure 1A can be configured to regulate the power delivered to the first load 142 (e.g., the output voltage V O1 ). For example, the secondary control device 108 can regulate the output voltage V O1 based at least in part on the feedback signal FB.

[0022]

[0036] The primary control device 109 provides a primary control signal V CS to the control terminal (e.g., gate) of the primary switch 152. By this approach, the primary control device 109 controls a primary current I SW to supply energy to the primary winding 112. The primary detection element 54 is for the primary current I SWTo locally adjust the maximum value, a detection signal SENS may be provided to the primary control device. Further, the clamp 110 may be connected in parallel with the primary winding 112 to limit (i.e., clamp) the switch voltage V SW . As shown, the primary control device 109 may be configured to operate using signals referenced to the primary ground GND (e.g., the switch voltage V SW and the primary control signal V CS ).

[0023]

[0037] As described above, the secondary control device 108 may receive a feedback signal FB1 from the load circuit 106 (i.e., from the feedback network 140). Further, as shown, the secondary control device 108 may communicate with the primary control device 109 through the signal FL.

[0024]

[0038] The power converter system 100 may be configured as a flyback converter, in which case the primary switch 152 switches according to a switching cycle. Thus, during the switching cycle, energy may be transferred through the secondary current I S1 in the circuit path 115.

[0025]

[0039] According to the teachings herein, the secondary control device 108 may include a zero voltage switching (ZVS) on-time calculator 153. The secondary control device 108 may calculate a holding period (i.e., on-time) for controlling a secondary switch (e.g., a synchronous rectifier (SR)) during a switching cycle (i.e., the switching cycle of the primary switch 152).

[0026]

[0040] The operation and equation theory related to the ZVS on-period calculator 153 may be at least partially based on the oscillatory (i.e., ringing) behavior at the primary node NSW, where the primary switch 152 is electrically coupled to the primary winding 112. According to the theory of switched-mode power supplies, ringing (i.e., oscillation) may occur at the primary node NSW at least partially due to the primary capacitance Cpri and the primary inductance Lpri at the primary node NSW. The resonant oscillation period (i.e., ringing period) may often be referred to as the idle ringing period TIR.

[0027]

[0041] The primary capacitance Cpri may include the capacitance of the primary switch 152. For example, when the primary switch 152 is implemented using an N-channel field effect transistor (NFET), the primary capacitance Cpri may include the capacitance related to the NFET output capacitance.

[0028]

[0042] The primary inductance Lpri may include the inductance related to the primary winding 112. For example, it may include the magnetizing inductance of the primary winding.

[0029]

[0043] According to circuit theory, a simple approximation relating the idle ringing period TIR to the primary capacitance Cpri and the primary inductance Lpri may be given by Equation 1.

Equation

[0030]

[0044] According to the teachings of this specification, the secondary switch holding period T CHR_ZVS may be determined by considering energy storage. Alternatively, and additionally, the secondary switch holding period T CHR_ZVS may also be referred to as the secondary switch on-period T CHR_ZVS within the context of this application. In this context, either the synchronous rectifier (SR) and / or the secondary switch may be the secondary switch holding period TCHR_ZVS It can operate in the "on state" therein.

[0031]

[0045] Based at least in part on the principle of energy storage, inductance energy can be equated with capacitance energy to determine the peak inductor current Ipk.

Equation

[0032]

[0046] Next, based on Equation 1 and Equation 2, the approximation of the secondary switch holding period T CHR_ZVS can be determined by Equation 3.

Equation

[0033]

[0047] Here, Equation 3 introduces the turns ratio N of the winding and the output voltage Vout. In the case of a single-output flyback converter, as shown in Figure 1A, the output voltage Vout is the output voltage V O1 and the turns ratio N can be specified by the ratio of the number of turns of the primary winding 112 to the secondary winding 99.

[0034]

[0048] Equation 3 can be generalized by eliminating the dependence on the turns ratio N and introducing the concept of the reflected output voltage Vor. By introducing the reflected output voltage Vor and using Equation 1, Equation 3 can be recalculated as Equation 4.

Equation

[0035]

[0049] For comparison, a more exact relationship for the secondary switch holding period T CHR_ZVS can be given by Equation 5.

Equation

[0036]

[0050] Referring to FIG. 1A, the forward pin voltage V at node 123 FWD can be related to the input voltage V by Equation 6 IN , the output voltage Vout, and the turns ratio N of the winding. [Equation]

[0037]

[0051] As a result, the relationship of the ratio of the input voltage V to the reflected output voltage Vor can be determined by Equation 7 from the perspective of the forward pin voltage V at node 123 IN . FWD can be determined by Equation 7. [Equation]

[0038]

[0052] Further, as shown in FIG. 1A, the secondary winding 99 is electrically coupled to the resistor RW and to the drain of the NFET 126 at node 123 (i.e., the forward pin node 123).

[0039]

[0053] According to the teachings herein, the ZVS on-time calculator 153 can dynamically calculate (e.g., dynamically using the switching cycle of the primary switch 152) the secondary switch holding period T CHR_ZVS . According to Equation 7, the ZVS on-time calculator 153 can easily and dynamically measure quantities, namely, the forward pin voltage V at node 123 FWD and the output voltage Vout (e.g., the output voltage V O1 ) and use them.

[0040]

[0054] Thus, Equations 1 through 7 can also be time-dependent equations, in which case the values (e.g., the value of the forward pin voltage V at node 123 FWD and the value of the output voltage Vout) are values sampled in time. For example, the forward pin voltage V at node 123 FWDcan be sampled at discrete times during the switching cycle of the primary switch 152.

[0041]

[0055] Thus, as can be understood by those skilled in the art, the ZVS on-time calculator 153 can be implemented using digital, analog, and / or algorithm-based approaches. For example, the calculation results can be programmed into the control device 108.

[0042]

[0056] As shown, the NFET 126 can be configured to operate as a synchronous rectifier, and the secondary control device 108 can provide a control signal Vcr to gate (control) the NFET 126 (i.e., to gate the SR). According to the teachings herein, the NFET 126 may be configured to enable zero voltage switching (ZVS).

[0043]

[0057] The NFET 126 in FIG. 1A can be configured to operate as a synchronous rectifier, but other configurations are possible. For example, FIGS. 1B and 1C show a power converter system 100 according to another embodiment using a diode 126d in parallel with the secondary switch 127. The diode 126d can be configured to operate as a rectifier, and the secondary switch 127 can be configured to enable ZVS.

[0044]

[0058] As shown in FIG. 1C, the secondary switch 127 can be implemented using the NFET 127c. Further, the diode 126d can be distinguished from (e.g., independent of) the body diode of the NFET 127c, the diode 126d can be implemented to maintain a current similar to that of the NFET 126, and the NFET 127c can be implemented with a much lower current rating than that of the diode 126d. For example, the diode 126d can be implemented using a discrete high-current diode independent of the NFET 127c.

[0045]

[0059] Therefore, NFET127c can be beneficially implemented using a smaller device area (e.g., a smaller semiconductor chip area) than that of NFET126. Therefore, NFET127c can also be referred to as an auxiliary NFET127c without departing from the scope of the present disclosure. For example, the auxiliary NFET127c can be switched on only once during a switching cycle to enable zero voltage switching (ZVS).

[0046]

[0060] Further, according to the teachings herein, the secondary control device 108 can use information obtained from the forward pin voltage V at node 123 (i.e., the forward pin node 123). For example, the secondary control device 108 can receive a forward pin signal FW provided from a resistor RW coupled to node 123. The ZVS on-time calculator 153 can perform calculations based at least in part on the forward pin signal FW and / or the feedback signal FB1. FWD from. For example, the secondary control device 108 can receive a forward pin signal FW provided from a resistor RW coupled to node 123. The ZVS on-time calculator 153 can perform calculations based at least in part on the forward pin signal FW and / or the feedback signal FB1.

[0047]

[0061] As disclosed herein, the ZVS on-time calculator 153 and the secondary control device 108 can include digital and / or analog circuitry configured to calculate a secondary switch hold time T CHR_ZVS to achieve ZVS. For example, FIG. 1D shows a power converter system 100 using a secondary control device 108 having both digital and analog features.

[0048]

[0062] The secondary control device 108 of FIG. 1D includes a ZVS on-time calculator 153, an output control block 154, a comparator 155, an idle ringing period calculator 156, edge detection blocks 157-158, delay blocks 159-160, a sample and hold circuit 161, analog-to-digital converters 162-163, an AND gate 164, and an AND gate 165. The secondary control device 108 receives a forward pin signal FW and a feedback signal FB1. As shown, the feedback signal FB1 is the output voltage V O1can be obtained directly therefrom (e.g., equal to the output voltage V O1 ). In other embodiments (e.g., the embodiment of FIG. 1A), the feedback signal FB1 can be proportional to the output voltage V O1 (e.g., a scaled ratio of the output voltage V O1 ).

[0049]

[0063] As shown, the comparator 155 can compare the feedback signal FB1 (i.e., the output voltage V O1 ) with the forward pin signal FW. In response thereto, the comparator 155 can provide a comparator output signal L1, and as described herein with reference to FIGS. 2A-2D, the idle ringing period TIR can be calculated in response to a transition of the comparator output signal L1.

[0050]

[0064] The edge detection block 157 can receive the comparator output signal L1 and trigger the delay block 159 when the comparator output signal L1 transitions from high to low. According to the teachings herein, the delay block 159 can provide a delayed output signal L2 after one-fourth of the idle ringing period TIR has elapsed.

[0051]

[0065] Similarly, the edge detection block 158 can receive the comparator output signal L1 and trigger the delay block 160 when the comparator output signal L1 transitions from low to high. According to the teachings herein, the delay block 160 can provide a delayed output signal L3 after one-fourth of the idle ringing period TIR has elapsed.

[0052]

[0066] The output control block 154 can provide a request signal REQ based on the feedback signal FB1 and the delayed output signal L2. For example, the output control block 154 can identify a need for power transmission to the load 142 based on the feedback signal FB1 (e.g., the value of the feedback signal FB1 decreases). Further, the output control block 154 can assert the request signal REQ in response to the need and in response to the delayed output signal L2.

[0053]

[0067] The sample - hold circuit 161 may sample the forward pin signal FW and provide the sample to an analog - to - digital converter (ADC) 162. The ADC 162 may then provide a digital forward pin signal DFW (i.e., the digital representation of the forward pin signal FW).

[0054]

[0068] Similarly, the ADC 163 may convert the feedback signal FB1 and provide a digital output voltage signal DVO (i.e., the digital representation of the feedback signal FB1).

[0055]

[0069] As shown, the ZVS on - time calculator 153 may receive the digital output voltage signal DVO, the digital forward pin signal DFW, and the idle ringing period TIR. In response, the ZVS on - time calculator 153 may assert a ZVS calculator signal L4.

[0056]

[0070] According to the teachings herein, the ZVS on - time calculator 153 may perform calculations based at least in part on one or more of Equations 1 - 7. For example, the ZVS on - time calculator 153 may calculate the secondary switch hold - time T CHR_ZVS using Equation 8 derived from Equations 4 and 7.

Number

[0057]

[0071] Further shown, the AND gate 164 receives the request signal REQ, the ZVS calculator signal L4, and the delayed output signal L2. As shown, the control signal V CRcan be swung to drive the gate of NFET126 based on the logical AND function of the request signal REQ, the ZVS calculator signal L4, and the delayed output signal L2. As those skilled in the art can understand, additional components and / or buffer stages may exist between the output of AND gate 164 and the gate of NFET127c. Alternatively, and additionally, the secondary control device 108 of FIG. 1D can be used with an embodiment using NFET126 (e.g., the embodiment of FIG. 1A).

[0058]

[0072] Further, AND gate 165 receives the request signal REQ and the delayed output signal L3. As shown, the signal FL can be swung to close the primary switch 152 based at least in part on the logical AND function of the request signal REQ and the delayed output signal L3, and can be coupled to the primary control device 109.

[0059]

[0073] FIGS. 1A through 1D show a power converter system 100 according to a one-output embodiment, but other embodiments are possible.

[0060]

[0074] For example, FIG. 1E shows a power converter system 100 according to a multiple-output (i.e., multi-output) embodiment. The power converter system 100 of FIG. 1E can be configured similarly to that of FIG. 1A, except that the power converter system 100 of FIG. 1E has multiple outputs as described later.

[0061]

[0075] As shown, the power converter system 100 includes an energy transfer element 102, a secondary switch block 104, a load circuit 106, a secondary control device 108, a primary control device 109, a clamp 110, and a primary switch 152. The energy transfer element 102 includes a primary winding 112 and secondary windings 114, 116, 118. The secondary switch block 104 includes NFET126 and secondary switches 119, 122, 125.

[0062]

[0076] The multi-output power converter system 100 has a rectified AC line voltage VIN The input power derived from O1 ~V O3 and the secondary current I S1 ~I S3 can be converted into output power including. Alternatively, and additionally, the input power can be introduced from a high-voltage power source. The load circuit 106 includes a CC / CV3 port, a CC / CV2 port, a CC / CV1 port (which can be a regulated DC power port), and a secondary ground return port SRTN.

[0063]

[0077] Further, the CC / CV3 port can be a constant current (CC) port (i.e., the secondary current I S3 is controlled to be constant), and / or a constant voltage (CV) port (i.e., the output voltage V O3 is controlled to be constant), depending on the load state at the CC / CV3 port. The CC / CV2 port can be a constant current (CC) port (i.e., the secondary current I S2 is controlled to be constant), and / or a constant voltage (CV) port (i.e., the output voltage V O2 is controlled to be constant), depending on the load state at the CC / CV2 port, and the CC / CV1 port can be a constant current (CC) port (i.e., the secondary current I S1 is controlled to be constant), and / or a constant voltage (CV) port (i.e., the output voltage V O1 is controlled to be constant), depending on the load state at the CC / CV1 port.

[0064]

[0078] For example, in one embodiment, the CC / CV3 port can be a CC port, and the secondary current I S3 can be the regulated load current, while the output voltage V O3 is at least partially determined by the load at the CC / CV3 port. Further, the CC / CV1 port and the CC / CV2 port can be CV ports, in which case the output voltage V O1 and the output voltage V O2 are regulated. The secondary ground return port SRTN can be electrically coupled to the secondary ground RTN.

[0065]

[0079] In one embodiment, the output voltage V O1 ~V O3 can be at least partially determined by the energy transfer element 102. For example, the turns ratio and transformer configuration (e.g., stacked secondary windings) of the secondary windings 114, 116, 118 with respect to the primary winding 112 can be configured for the highest voltage CC / CV3 port (e.g., a voltage higher than 40 volts). The CC / CV1 port and the CC / CV2 port can be adjusted to a lower voltage (e.g., a voltage between 3 volts and 40 volts). In one embodiment, the CC / CV2 port can be a CV port with an output voltage V O2 adjusted to a lower voltage (e.g., 20 volts), and the CC / CV1 port can be a CV port with an output voltage V O1 adjusted to the lowest voltage (e.g., 5 volts).

[0066]

[0080] Alternatively, and additionally, the output voltage V O1 ~V O3 can be determined by the operation of the secondary switches 119, 122, 125. For example, the secondary switch 119 can be controlled so that the output voltage V O3 is higher than the output voltage V O2 .

[0067]

[0081] As shown, the secondary windings 114, 116, and 118 are electrically coupled by a stacked (i.e., in series) configuration according to the transformer "dot" notation. As shown, the secondary switch 119 is electrically coupled between the "dot" terminal of the secondary winding 118 and the CC / CV3 port in the circuit path 111. The secondary switch 122 is electrically coupled between the "dot" terminal of the secondary winding 116 and the CC / CV2 port in the circuit path 113, and the secondary switch 125 is electrically coupled between the "dot" terminal of the secondary winding 114 and the CC / CV1 port in the circuit path 115.

[0068]

[0082] The N-type FET (NFET) 126 is coupled between the secondary winding 114 and the secondary RTN in the circuit path 117 as shown. As already explained in connection with FIG. 1A, the NFET 126 is configured to operate as a synchronous rectifier and can be switched on and off by a control signal Vcr. Further, as already explained in connection with FIGS. 1B and 1C, the NFET 126 can be replaced by a diode 126d and a secondary switch 127 connected in parallel.

[0069]

[0083] Further shown, the primary winding 112 and the primary switch 152 can be connected between the input terminals 101 and 103 to receive an AC line voltage V IN rectified with respect to the primary ground GND. During a switching cycle (i.e., a switching period), the primary winding 112 can be energized by increasing (i.e., raising) the primary current I SW while the primary switch 152 is closed (i.e., conducting). According to magnetics and transformer theory, when the primary switch 152 is opened (i.e., during the transition from the conducting state to the non-conducting state), the energy in the primary winding 112 can be transferred to one or more of the secondary windings 114, 116, 118.

[0070]

[0084] The secondary control device 108 receives feedback signals FB1~FB3 from the load circuit 106, communicates with the primary control device 109 through the signal FL, and provides control signals SEL1~SEL3 to the secondary switch block 104. As shown, the secondary control device 108 can be configured to operate using signals (e.g., feedback signals FB1~FB3 and a plurality of output voltages V O1 ~V O3 ) referenced to the secondary ground RTN. Thus, the signal FL can be an optically coupled, magnetically coupled, and / or capacitively coupled signal FL to enable communication with the primary control device 109 referenced to the primary ground GND.

[0071]

[0085] As described herein, the secondary control device 108 may provide one or more control signals SEL1 to SEL3 to selectively control (i.e., switch) the transfer of energy (i.e., power) to the load circuit 106 by selecting a circuit path (e.g., circuit path 111, circuit path 113, and / or circuit path 115). As shown, the secondary control device 108 provides control signals SEL1, SEL2, SEL3 to the secondary switches 125, 122, 119, respectively. The control signals SEL1, SEL2, SEL3 may then gate the switches 125, 122, 119 to operate in an on state or an off state, respectively.

[0072]

[0086] During the switching cycle, when the secondary switch 119 is closed (i.e., operating in the on state) while both secondary switches 125, 122 are open (i.e., both operating in the off state), energy can be transferred through the secondary current I in the circuit path 111. S3 As shown, the circuit path 111 is a switching circuit path including the secondary switch 119 and is electrically coupled to the CC / CV3 port of the load circuit 106. Alternatively, when the secondary switch 122 is closed (i.e., operating in the on state) and the secondary switches 125, 119 are open (i.e., operating in the off state), energy can be transferred through the secondary current I in the circuit path 113. S2 As shown, the circuit path 113 is a switching circuit path including the secondary switch 122 and is electrically coupled to the CC / CV2 port of the load circuit 106. Alternatively, when the secondary switch 125 is closed (i.e., operating in the on state) and the secondary switches 122, 119 are open (i.e., operating in the off state), energy can be transferred through the secondary current I in the circuit path 115. S1 As shown, the circuit path 115 is a switching circuit path including the secondary switch 125 and is electrically coupled to the CC / CV1 port of the load circuit 106.

[0073]

[0087] As described above, the secondary control device 108 may include a zero voltage switching (ZVS) on-time calculator 153. According to the teachings herein, the secondary control device 108 is based at least in part on the forward pin signal FW and the selective output to control the synchronous rectifier (SR) during the switching cycle (i.e., the switching cycle of the primary switch 152), and may calculate a hold period (e.g., the secondary switch hold period T CHR_ZVS ).

[0074]

[0088] In the multi-output embodiment of FIG. 1E, the selective output may represent an output that is active and / or selected during the switching cycle. For example, during the switching cycle, when the secondary switch 125 is closed, the selective output corresponds to the output voltage V O1 . Alternatively, when the secondary switch 122 is closed, the selective output corresponds to the output voltage V O2 . Thus, Equation 7 may be reformulated by replacing the output voltage Vout with the selective output voltage Vo. For example, when the selective output corresponds to the output voltage V O2 , the selective output voltage Vo is the output voltage V O2 .

[0075]

[0089] FIG. 1F shows a multi-output (i.e., multi-output) power converter system 100 according to the embodiment of FIG. 1E. The primary switch 152 is implemented using an N-type field effect transistor (FET) 152b. The secondary switch 119 is replaced by a diode 120. As shown, the diode 120 is electrically coupled between the "dot" terminal of the secondary winding 118 and the CC / CV3 port in the circuit path 111. In applications where the output voltage V O3 is necessarily the highest of the plurality of output voltages V O1 to V O3 , the secondary switch 119 may be replaced by a diode 120 to beneficially simplify the switch block 104 and eliminate the need for the control signal SEL3.

[0076]

[0090] The secondary switch 122 is implemented using an N-type FET 122b, and as shown in the figure, the secondary switch 122 is electrically coupled to the diode 121 between the "dot" terminal of the secondary winding 116 and the CC / CV2 port in the circuit path 113. The secondary switch 125 is implemented using an N-type FET 125b, and the secondary switch 125b is electrically coupled between the "dot" terminal of the secondary winding 114 and the CC / CV1 port in the circuit path 115.

[0077]

[0091] The N-type FETs 152b, 122b, 125b, 126 can be integrated and / or discrete power FETs. In one embodiment, the N-type FETs 152b, 122b, 125b, 126 can be enhancement-mode FETs.

[0078]

[0092] The load circuit 106 includes feedback networks 140, 136, 132 that can each provide feedback signals FB1, FB2, FB3 to the secondary control device 108. Further, the load circuit 106 includes filter capacitors C1 to C3 electrically coupled to the first load 142, the second load 138, and the third load 148, respectively. In the steady state, the multi-output power converter system 100 of FIG. 1F can be configured to regulate the power delivered to the first load 142, the second load 138, and the third load 148.

[0079]

[0093] For example, the feedback networks 140, 136, 132 can each include a voltage divider network for providing feedback signals FB1, FB2, FB3 for closed-loop regulation of the output voltages V O1 、V O2 、V O3 . In the steady state, the feedback signals FB1, FB2, FB3 are each derived from the output voltages V O1 、V O2 、V O3 or are related to the output voltages V O1 、V O2, V O3 It can be the voltage sampled from O1 . By this method, the power delivered to the first load 142 can be regulated as the CV output (i.e., the regulated output voltage V O2 ). The power delivered to the second load 138 can be regulated as the CV output (i.e., the regulated output voltage V O3 ), and the power delivered to the third load 148 can be regulated as the CV output (i.e., the regulated output voltage V

[0080]

[0094] As described above, the secondary control device 108 can communicate with the primary control device 109 via a signal FL (e.g., a magnetically coupled signal FL). For example, using the signal FL, the primary control device 109 can send a handshake to the secondary control device 108 to indicate the power good state. Alternatively, and additionally, using the signal FL, the secondary control device 108 can send more energy transfer requests. In response to the request, the primary control device 109 can change the primary control signal V CS to close the primary switch 152 and supply energy to the primary winding 112.

[0081]

[0095] As shown, the secondary control device 108 can receive a forward pin signal FW and feedback signals FB1~FB3, and the secondary control device 108 can provide control signals SEL1, SEL2, and V Cr . As described herein, the control signals SEL1, SEL2 can be used to selectively control (i.e., switch) the transfer of energy (i.e., power) to the load circuit 106 by selecting circuit paths (e.g., circuit paths 111, 113, and / or circuit path 115). Further, the control signal V Cr can be used to drive the gate of the N-type FET 126 to operate as a synchronous rectifier.

[0082]

[0096] As described above, the feedback signals FB1 to FB3 can be sampled (i.e., measured) signals used within the secondary controller 108 for closed-loop control of the CV output. However, as will be appreciated by those skilled in the art, other configurations are possible. For example, as described herein, the secondary controller 108 can be further configured to provide closed-loop control of the CC output.

[0083]

[0097] As shown, the forward pin voltage V FWD can be present at node 123, and an optional passive component (i.e., resistor R W ) can be electrically coupled at node 123 to the secondary winding 114 to provide a forward pin signal FW to the secondary controller 108. In some embodiments, the forward pin signal FW can be equal to the forward pin voltage V FWD , whereas in other embodiments, the forward pin signal FW can be attenuated with respect to the forward pin voltage V FWD .

[0084]

[0098] FIG. 1G shows a multi-output power converter system 100 according to another embodiment of FIG. 1E. The embodiment of FIG. 1G is similar to the embodiment of FIG. 1F except that the load 148 is replaced by LED strings 183-184, and the current sensing element 182 samples the load current I L3 to provide the feedback signal FB3. In the steady state, the multi-output power converter system 100 of FIG. 1G can be configured to regulate the power transmitted to the LED strings 183-184 as a CC output (i.e., regulated load current I L3 ).

[0085]

[0099] Further, the load circuit 106 includes a plurality of parallel-connected light emitting diode (LED) strings 183-184, a first load 142, and a second load 138. As shown, the LED strings 183-184 carry the load current I L3is required (i.e., received). The feedback signal FB3 directly samples the load current I L3 is shown as directly sampling, but other configurations are possible. For example, instead of directly sampling the load current I L3 the load current I L3 can be adjusted by sampling the LED string current I L3A ~I L3B and the LED string current I L3A ~I L3B can be used by the secondary control device 108 to adjust the total load current I L3 .

[0086]

[0100] In one embodiment, the LED string current I L3A ~I L3B can be used by the secondary control device 108 to adjust the output voltage V L3 as a means of controlling the total load current I O3 . Further, although the load circuit 106 is shown as including two LED strings 183, 184, other configurations including more or fewer than two LED strings 183, 184 are possible.

[0087]

[0101] As described above, the NFET 126 can be replaced by a diode 126d and a secondary switch 127 connected in parallel. For example, FIG. 1H shows a multi-output power converter system 100 according to another embodiment of FIGS. 1G and 1D. The embodiment of FIG. 1H is similar to the embodiment of FIG. 1G except that, as in FIG. 1D, the NFET 126 can be replaced by a diode 126d and a secondary switch 127 connected in parallel. As shown, the secondary switch 127 includes an auxiliary NFET 127c.

[0088]

[0102] Furthermore, as can be understood by those skilled in the art, the embodiments of FIGS. 1A-1H are non-limiting, and other configurations may be implemented using integrated and / or discrete semiconductor components including bipolar junction transistors (BJTs), insulated gate bipolar transistors (IGBTs), and / or reverse polarity FETs (e.g., P-channel FETs). Further, the active devices may be realized using material processing based on materials such as silicon, silicon germanium, gallium nitride, and the like.

[0089]

[0103] FIG. 2A shows waveforms 202-205 during discontinuous mode (DCM) over the switching cycle of period T1. Waveform 202 may correspond to the forward pin voltage V FWD and / or the forward pin signal FW as a function of time. Waveform 203 may correspond to the switch voltage V SW as a function of time. Waveform 204 may correspond to the primary control signal V CS as a function of time, and waveform 205 may correspond to the control signal Vcr as a function of time.

[0090]

[0104] As shown by waveform 204, the primary control signal V CS that drives the primary switch (e.g., primary switch 152) may be periodic in units of period T1. For example, as shown at time point 211, the primary control signal V CS may transition from high to low to turn off the primary switch 152. At time point 213, the primary control signal V CS may transition from low to high to turn on the primary switch 152, and at time point 214, the control signal may transition from high to low again to turn off the primary switch 152.

[0091]

[0105] As shown by waveform 205, after the turn-off transition of the primary switch 152, the signal Vcr that drives the SR (e.g., NFET126) gate may transition. For example, as shown at time point 211, the signal VCR It can transition from low to high at time point 211 and remain high until time point 212. At time point 212, the signal Vcr transitions from high to low and can remain low until a new cycle begins at time point 214.

[0092]

[0106] As shown by waveform 202 in relation to waveforms 204 - 205, the forward pin voltage V at node 123 FWD can vary periodically according to the switching transitions of the primary switch 152 and the SR (e.g., according to the switching transition of NFET126). For example, from time point 211 to time point 212, the SR (NFET126) can be in a conducting state, and the forward pin voltage V FWD can be less than 0 volts (0V) and / or equal to 0 volts (0V). Time point 212 can represent the time when the energy from the secondary windings 114, 116, 118 and / or winding 99 becomes depleted to the extent that ringing can occur at node 123. For example, as shown by waveform 202, there is ringing (i.e., oscillation) between time point 212 and time point 213.

[0093]

[0107] As further shown, ringing occurs with peaks (i.e., offsets) higher and lower than the output voltage V OUT According to the teachings herein, the output voltage V OUT can correspond to the output V of FIG. 1A O1 and / or the output voltages V of FIGS. 1E - 1H O1 ~V O3

[0094]

[0108] As shown by waveform 203 in relation to waveforms 202, 204, 205, the switch voltage V SW can also vary periodically according to the switching transitions of the primary switch 152 and the SR (e.g., NFET126). For example, from time point 211 to time point 212, while the forward pin voltage V FWD is made less than 0 volts (0V) and / or equal to 0 volts (0V), the switch voltage V SW is the rectified AC line voltage VIN reach a higher plateau and / or clamped voltage. Further, after the time point 212 when the energy from the secondary windings 114, 116, 118 and / or the winding 99 becomes depleted, the switch node voltage V SW may ring, at least in part, due to capacitance (e.g., the parasitic capacitance of the primary switch 152) and inductance (e.g., the inductance of the primary winding 112). According to the theory of the switching power converter, and as shown in waveforms 202, 203, the ringing of waveforms 202 and 203 can be out of phase. At the time point 213 when the primary control signal V CS switches the primary switch 152 on, the ringing may end.

[0095]

[0109] According to the teachings herein, the information from the forward pin voltage V FWD can beneficially provide information without requiring further communication from the primary side to the secondary side.

[0096]

[0110] FIG. 2B shows waveforms 222 - 225 during a switching cycle according to the teachings herein. Waveform 222 may correspond to the forward pin voltage V FWD and / or the forward pin signal FW as a function of time. Waveform 223 may correspond to the control signal Vcr as a function of time. Waveform 224 may correspond to the signal FL transmitted by the secondary controller 108 as an energy requirement, and waveform 225 may correspond to the primary control signal V CS as a function of time.

[0097]

[0111] In contrast to waveform 204, waveform 223 shows a low - to - high transition at time point 241 and a high - to - low transition at time point 242. According to the teachings herein, by switching on the SR (e.g., NFET 126) during the interval T2 (i.e., from time point 241 to time point 242), the primary switch 152 can experience ZVS, and, as described herein, during the holding period (e.g., the secondary switch holding period T CHR_ZVS) The duration of the interval T2, also referred to as, can be calculated using information available to the secondary control device 108.

[0098]

[0112] As shown in waveforms 223 to 225, after the interval T2, the signal FL transitions from low to high at time point 244, and then transitions from high to low at time point 245. Next, in response to the signal FL, the primary control signal V CS may transition to high to turn on the primary switch 152 at time point 246. At time point 247, when the primary control signal V CS transitions from high to low, the primary switch 152 switches off.

[0099]

[0113] For waveforms 223 to 225, waveform 222 shows how the forward pin voltage V FWD changes. For example, during the interval T3 from time point 242 to time point 243, the forward pin voltage V FWD transitions from 0 volts (0V) to a value determined by the output voltage Vout and / or the selective output voltage Vo. During the interval T4 from time point 243 to time point 246, the forward pin voltage V FWD transitions from a value determined by the output voltage Vout and / or the selective output voltage Vo to the value V FON . As shown, the value V FON may correspond to the value of the forward pin voltage V FWD and / or the forward pin signal FW while the primary switch 152 is switched on.

[0100]

[0114] Waveform 222 shows the forward pin voltage V FON as changing up to the value V FWD , but other variations are possible. For example, as those skilled in the art can understand, in other configurations, the forward pin voltage V FWD may not reach the value V FON (i.e., the value V FONThose that do not ring or do not transition (up to) can be such.)

[0101]

[0115] As described herein, the duration of interval T2, also referred to as holding period T2 (i.e., the secondary switch holding period T CHR_ZVS ) can be related to value V FON and output voltage V OUT and / or the selective output voltage Vo. Thus, Equation 7 can be recalculated by substituting the sampled value of the forward pin voltage V FWD with a value V FON that can be that value.

[0102]

[0116] FIG. 2C shows waveforms 252-255 during the switching cycle from time 270 to time 279 according to an embodiment. Waveform 252 can correspond to the forward pin voltage V FWD and / or the forward pin signal FW as a function of time. Waveform 253 can correspond to the control signal Vcr as a function of time. Waveform 254 can correspond to the signal FL transmitted by the secondary control device 108 as an energy requirement at time 275, and waveform 255 can correspond to the primary control signal V CS as a function of time.

[0103]

[0117] Referring to waveform 255, the switching cycle can be measured from time 270 when the primary control signal V CS transitions low to time 279 when the control signal V CS transitions low again. Further, as shown in waveform 254, during the switching cycle from time 270 to time 279, the signal FL transmits an energy requirement between time 276 and time 277.

[0104]

[0118] As shown by waveform 252 in relation to waveforms 253-255, the forward pin voltage V at node 123 FWDcan vary periodically according to the switching transitions of the primary switch 152 and the SR switch (e.g., NFET 126). For example, from time point 270 to time point 272, the SR (NFET 126) can be in a conducting state, and the forward pin voltage V FWD can be less than and / or equal to 0 volts (0V). Time point 272 can represent the time when the energy from the secondary windings 114, 116, 118 and / or winding 99 becomes depleted to the extent that ringing can occur at node 123. For example, as shown by waveform 252, an initial occurrence of ringing (i.e., oscillation) can exist during interval T5 from time point 272 to time point 273.

[0105]

[0119] According to the teachings herein, the SR switch (NFET 126) can be switched on at time point 273. Further, according to the teachings herein, the output voltage V OUT can correspond to the output V of FIG. 1A O1 and / or the output voltage V of FIGS. 1E - 1H O1 ~V O3 .

[0106]

[0120] As described herein, the control signal V CR can remain high during interval T6 (i.e., from time point 273 to time point 274). Interval T6 can also be referred to as the secondary switch hold time T CHR_ZVS . Referring to waveforms 252 - 255, the secondary switch hold time T CHR_ZVS can be determined (i.e., calculated) as a function of the forward pin voltage V FWD sampled at time point 269 (e.g., value V FON ).

[0107]

[0121] Further, as described above, the value V FON can correspond to the value of the forward pin voltage V FWD and / or the forward pin signal FW while the primary switch 152 is switched on.

[0108]

[0122] As described herein, the interval T6 (e.g., the secondary switch holding period T CHR_ZVS ) can be further determined (i.e., calculated) as a function of the output voltage V OUT . According to the teachings herein, the output voltage V OUT can also be the selectable output voltage V O readily available to the secondary control device 108. For example, referring to FIG. 1H, the selectable output voltage V O can be provided to the secondary control device 108 from any one of the feedback signals FB1 to FB3.

[0109]

[0123] Referring to waveforms 253 to 255, waveform 252 further shows how the forward pin voltage V FWD changes after the interval T6. For example, during the interval T7 from time point 274 to time point 275, the forward pin voltage V FWD transitions from 0 volts (0V) to a value determined by the output voltage and / or the selectable output voltage Vo. Later, during the interval T8 from time point 275 to time point 278, the forward pin voltage V FWD transitions from the value determined by the output voltage and / or the selectable output voltage Vo to the value V FON . According to the teachings herein, the interval T8 can be one-fourth (i.e., 1 / 4) of the idle ringing period TIR given by Equation 9.

Equation

[0110]

[0124] Further, according to the teachings herein, Equation 8 can be reformulated by Equation 10 in terms of the sampled value V FON and the selectable output voltage Vo.

Equation

[0111]

[0125] Figure 2D shows waveforms 252-255 during the switching cycle from time point 270 to time point 279 according to another embodiment. The embodiment of Figure 2D may be similar to that of Figure 2C, except that waveform 253 does not transition high between time points 270 and 272, and waveform 253 also does not transition high at time point 279. Alternatively, waveform 253 transitions high only from time point 273 to time point 274 during interval T6.

[0112]

[0126] For example, waveform 253 of Figure 2D may correspond to the power converter system 100 of Figures 1C and / or 1H using NFET127c, and the embodiment of Figure 2C may correspond to the power converter system 100 of Figure 1A using NFET126.

[0113]

[0127] Figure 3A shows a conceptual flow diagram 300 for zero voltage switching in the power converter system 100 according to an embodiment.

[0114]

[0128] Step 301 may correspond to closing (i.e., switching on) the primary switch 152 at time point 278.

[0115]

[0129] Step 302 may correspond to sampling the forward pin voltage V FWD Referring to waveform 252, the forward pin voltage V FWD at time point 269 may provide the value V FON of the forward pin signal when the primary switch 152 is switched on (i.e., conducting).

[0116]

[0130] Step 304 may correspond to opening (i.e., switching off) the primary switch at time point 270.

[0117]

[0131] Step 306 may correspond to closing the SR switch (e.g., NFET 126) at time point 270, and step 308 may correspond to opening the SR switch (e.g., NFET 126) at time point 272.

[0118]

[0132] Step 310 may correspond to calculating the SR hold duration T6 (e.g., calculating interval T6). The SR hold duration T6 may be given by the secondary switch hold duration T CHR_ZVS derived herein.

[0119]

[0133] Step 312 may correspond to closing the synchronous rectifier over the hold duration T6. For example, step 312 may correspond to closing the SR switch (e.g., NFET 126) over interval T6 (i.e., the hold duration T6) from time point 273 to time point 274.

[0120]

[0134] Step 313 may correspond to opening the synchronous rectifier after the hold duration T6 and before time point 278.

[0121]

[0135] FIG. 3B shows a conceptual flowchart 350 for zero voltage switching in the power converter system 100 according to another embodiment. The conceptual flowchart 350 is similar to the conceptual flowchart 300 except that the conceptual flowchart 350 does not include steps 306 to 308, and steps 312 to 313 are replaced by steps 352 to 353, respectively.

[0122]

[0136] Step 352 may correspond to closing the secondary switch (e.g., NFET 127c) over the hold duration T6. Step 352 may correspond to opening the secondary switch (e.g., NFET 127c) after the hold duration T6 and before time point 278.

[0123] Dynamic operation during the switching cycle

[0124]

[0137] Figure 4 compares waveforms 403 - 407 during two switching cycles 401 - 402 of primary switch 152. For comparison during switching cycle 401, control signal Vcr can be deactivated, whereas during switching cycle 402, control signal Vcr can be activated.

[0125]

[0138] Waveform 405 may correspond to the forward pin voltage V FWD and / or the forward pin signal FW as a function of time. Waveform 407 may correspond to the switch voltage V SW as a function of time. Waveform 403 may correspond to the primary control signal V CS as a function of time, and waveform 404 may correspond to the control signal Vcr as a function of time. Further, waveform 406 may correspond to the output voltage V OUT (e.g., the output voltage V of FIG. 1D O1 ).

[0126]

[0139] The primary switch 152 may operate in the “on” state in response to the primary control signal V CS . As shown in FIG. 4, the primary switch 152 closes (i.e., switches “on”) at time points 410, 411, and 421. Switching cycle 401 (i.e., switching period 401) is represented from time point 410 to time point 411, whereas switching period 402 is represented from time point 411 to time point 421. As described above, switching cycle 402 may correspond to that of the primary switch 152 in the embodiment of FIG. 1D.

[0127]

[0140] At time point 412, the sample - hold circuit 161 may sample the forward pin signal FW and / or the forward pin voltage V FWD . For example, the sample - hold circuit 161 may sample the forward pin voltage V FWD at point 427 in waveform 405. Thus, the ADC162 may then provide, as the digital representation of waveform 405 at time point 412, a digital forward pin signal DFW (e.g., value V FON) can be provided.

[0128]

[0141] At time point 413, the primary switch 152 can open (i.e., switch to “off”). From time point 413 to time point 414, the diode 126d can conduct according to the embodiment of FIG. 1D. Therefore, the waveform 404 (i.e., the control signal Vcr) remains low from time point 413 to time point 414. However, as those skilled in the art can understand, in other embodiments (e.g., the embodiment of FIG. 1A), the waveform 404 (i.e., the control signal Vcr) can transition high at time point 413 to drive the gate of the NFET 126, and then can transition low at time point 414.

[0129]

[0142] At time point 414, the power converter system 100 can enter the discontinuous conduction mode (DCM). Therefore, the waveforms 405 and 407 show ringing. The comparator 155 can be used to distinguish the intersection (i.e., crossing) points 433 to 436 where the waveform 405 (i.e., the forward pin voltage V FWD and / or the forward pin signal FW) crosses the waveform 406 (i.e., the output voltage V OUT ). Referring to FIG. 1D, the comparator output signal L1 can thus change (i.e., transition) according to the ringing of the waveform 405, and then the idle ringing period calculator 156 can calculate the idle ringing period TIR according to the transition of the comparator output signal L1. Further, the edge detection blocks 157 to 158 can be triggered in response to the transition edges of the comparator output signal L1.

[0130]

[0143] During the switching cycle 402, the ZVS on period calculator 153 calculates the hold period (e.g., the secondary switch hold period T CHR_ZVS) can be calculated dynamically. As shown in FIG. 1D, the holding period can be provided via the ZVS calculator signal L4, and in response to the AND gate 165, the waveform 404 (i.e., the control signal Vcr) transitions high at time point 415 and transitions low at time point 416. According to the teachings herein, the period from time point 415 to time point 416 can be at least partially determined by the ZVS on-period calculator 153.

[0131]

[0144] Further, the comparator output signal L1 can further transition at the point 437 where the waveform 405 (i.e., the forward pin voltage V FWD and / or the forward pin signal FW) crosses (i.e., intersects) the waveform 406 (i.e., the output voltage V OUT ). Next, at time point 421, the delay block 159 can transition to turn on the primary control signal V CS (i.e., waveform 403) to turn on the primary switch 152. The delay from point 437 to the time point 421 when the primary switch 152 is turned on can be referred to as the "open ring duration".

[0132]

[0145] According to the teachings herein, the open ring duration can be one quarter of the idle ringing period TIR. For example, referring to FIG. 1D, the delay block 160 can provide the delayed output signal L3 after one quarter of the idle ringing period TIR has elapsed. This can then result in a delay of one quarter of the idle ringing period TIR such that the duration from time point 416 to time point 421 is substantially equal to one quarter of the idle ringing period TIR.

[0133]

[0146] When the control signal Vcr is activated during the switching cycle 402, the switching becomes relatively "soft" (i.e., improved) at time point 421. As shown in waveform 407, at time point 421, the switch voltage V SW reaches approximately 0 volts at point 438. In comparison, at time point 411 after the switching cycle 401, the switch voltage V SWIt transitions from a point 431 having a relatively high voltage compared to the point 438.

[0134]

[0147] The multi-output power converter system 100 shows a switching configuration (e.g., flyback configuration) for providing a plurality of selectable output voltages V O1 ~V O3 and secondary currents I S1 ~I S3 Although it shows a switching configuration (e.g., flyback configuration) for providing them, other configurations with more or fewer multi-outputs are also possible. For example, the teachings herein may also be applicable to forward converters and / or other converter topologies using transformers including a plurality of secondary windings.

[0135]

[0148] In the description and exemplary drawings, it is understood that the concept of independently controlled CC / CV multi-outputs is mainly shown together with the series connection of secondary windings in an energy transfer element (e.g., transformer). However, this should not be considered as a limitation, and based on the load power requirements for each application and multi-output, independently regulated CV / CC outputs can be configured by any combination of series windings, parallel windings, or both series and parallel windings using a common return line for all of the independently controlled and regulated outputs according to the teachings herein.

[0136]

[0149] The proposed converter topology is an example of a single-stage multi-output flyback converter for applications with a plurality of separately regulated constant voltage and / or constant current outputs. Exemplary targets for such products include, for example, a CC-controlled output for a parallel string (e.g., array) of backlight LEDs that require a regulated adjustable (e.g., dimmable) constant current output with a voltage drop of 40 - 50V, and one or more CV-controlled outputs for powering a logic section, a universal serial bus (USB), and audio, which must meet strict regulation accuracy requirements for each output, and may include monitor and TV applications.

[0137] Conclusion

[0138]

[0150] The foregoing description of the illustrated examples of the present disclosure, including the matters set forth in the abstract, is not intended to be exhaustive or to limit the disclosure to the forms disclosed. Specific embodiments and examples of dynamically controlling a secondary switch to achieve zero voltage switching are illustrated herein for purposes of example, but various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it is understood that specific and exemplary voltages, currents, frequencies, output range values, times, etc. are presented for purposes of illustration and that other values may be used in other embodiments and examples in accordance with the teachings of this specification.

[0139]

[0151] The foregoing description may refer to elements or features as being “connected,” “electrically connected,” and / or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element / feature is directly or indirectly connected to another element / feature and does not necessarily mean mechanically connected. Similarly, unless expressly stated otherwise, “coupled” means that one element / feature is directly or indirectly coupled to another element / feature and does not necessarily mean mechanically connected. Thus, while the various schematic diagrams shown in the figures illustrate exemplary configurations of elements and components, additional intervening elements, devices, features, or components may exist in actual embodiments (assuming the functionality of the circuits shown is not adversely affected).

[0140]

[0152] Furthermore, for example, among others, expressions of conditions used in this specification such as "can ~", "be able to ~", "may ~", "may be ~", "for example", "as an example", "etc.", generally, unless explicitly stated otherwise or understood differently in the context in which they are used, are intended to convey that while a particular embodiment includes a particular feature, element, and / or state, other embodiments do not include the particular feature, element, and / or state. Thus, such expressions of conditions generally do not imply that a feature, element, and / or state is required in any way by one or more embodiments, and that one or more embodiments necessarily include the logic for determining whether these features, elements, and / or states are included in, or implemented in, any particular embodiment.

[0141]

[0153] Particular embodiments have been described, but these embodiments are presented by way of example only and are not intended to limit the scope of the present disclosure. In fact, the novel devices, methods, and systems described herein may be embodied in various other forms, and furthermore, various omissions, substitutions, and changes in the forms of the methods and systems described herein may be made without departing from the spirit of the present disclosure. For example, although the disclosed embodiments are shown with a given configuration, alternative embodiments may implement similar functions using different components and / or circuit topologies, and some elements may be deleted, moved, added, re-divided, combined, and / or changed. Each of these elements may be realized in various different ways. Any suitable combination of the elements and operations of the various embodiments described above may also be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.

[0142]

[0154] The claims presented in this application are in a form that is subordinate to one for filing in the USPTO, but it is understood that any claim may be subordinate to any one of the preceding claims of the same kind, except when it is clearly not technically feasible.

Claims

1. A method of dynamically switching during a switching cycle of a primary switch in a power converter, the method comprising: starting the switching cycle by closing the primary switch; receiving a forward pin voltage at a forward pin node; opening the primary switch; receiving a selective output voltage; identifying an idle ringing period; calculating a hold duration related to the forward pin voltage, the selective output voltage, and the idle ringing period; closing a secondary switch over the hold duration; A method comprising the above steps.

2. The method according to claim 1, wherein the secondary switch is a synchronous rectifier. The method according to claim 1.

3. The method according to claim 1, wherein the secondary switch is an auxiliary N-channel field effect transistor (NFET). The method according to claim 1.

4. The method according to claim 1, wherein the secondary switch is an auxiliary bipolar junction transistor (BJT). The method according to claim 1.

5. The method according to claim 1, wherein the power converter is a flyback converter. The method according to claim 1.

6. The method according to claim 1, wherein the power converter is a multi-output flyback converter. The method according to claim 1.

7. The method according to claim 1, further comprising transferring energy to a selective output to maintain the selective output voltage. The method according to claim 1.

8. The method according to claim 1, further comprising identifying the idle ringing period using a comparison unit. The method according to claim 1.

9. identifying an open ringing duration related to the idle ringing period; completing the switching cycle after the open ringing duration; The method according to claim 1, further comprising the above steps.

10. The method according to claim 9, wherein the open ringing duration is substantially equal to one quarter of the idle ringing period. The method according to claim 9.

11. An energy transfer element comprising a primary winding configured to receive energy from a first power source and at least one secondary winding configured to transfer energy to a selective output; a primary switch electrically coupled to the primary winding and configured to switch according to a switching cycle; a secondary control device, the secondary control device comprising: an idle ringing period calculator configured to calculate an idle ringing period during the switching cycle; A zero voltage switching (ZVS) calculator configured to calculate a holding duration based at least in part on the idle ringing period; The secondary control device comprising; A secondary switch electrically coupled to the at least one secondary winding and configured to close over the holding duration in response to a control signal from the secondary control device; A multi-output power converter comprising. **Claim 12** The multi-output power converter, wherein the multi-output power converter is a multi-output flyback converter; The multi-output power converter according to claim 11. **Claim 13** The multi-output power converter according to claim 11, wherein the selective output is a constant current (CC) output; The multi-output power converter according to claim 11. **Claim 14** The multi-output power converter according to claim 11, wherein the selective output is a constant voltage (CV) output; The multi-output power converter according to claim 11. **Claim 15** The multi-output power converter according to claim 11, wherein the idle ringing period depends at least in part on a primary capacitance and a primary inductance; The multi-output power converter according to claim 11. **Claim 16** The multi-output power converter according to claim 11, wherein the selective output is configured to provide a selective output voltage; The multi-output power converter according to claim 11, wherein the holding duration depends at least in part on the selective output voltage; The multi-output power converter according to claim 11. **Claim 17** The multi-output power converter according to claim 11, wherein the secondary switch is a synchronous rectifier; The multi-output power converter according to claim 11. **Claim 18** The multi-output power converter according to claim 11, wherein the secondary switch is an auxiliary N-channel field effect transistor (NFET); The multi-output power converter according to claim 11. **Claim 19** The multi-output power converter according to claim 18, further comprising a diode connected in parallel with the auxiliary NFET and independent of the auxiliary NFET; The multi-output power converter according to claim 18. **Claim 20** A primary switch electrically coupled to the primary winding and configured to switch during a first switching cycle; A selective output configured to provide a selective output voltage during the first switching cycle; A forward pin node electrically coupled to the secondary winding and configured to provide a forward pin voltage; A secondary switch electrically coupled to the forward pin node and configured to conduct current during a holding duration of the first switching cycle; A secondary control device, wherein the secondary control device... An idle ringing period calculator configured to provide an idle ringing period of the first switching cycle; A zero voltage switching (ZVS) calculator configured to calculate the hold duration related to the idle ringing period of the first switching cycle so that the primary switch is zero voltage switched during a second switching cycle; The secondary control device comprising the same; A multi-output power converter system comprising the same.

21. The multi-output power converter system is a multi-output flyback power converter system. The multi-output power converter system according to claim 20.

22. The secondary switch is a synchronous rectifier (SR). The multi-output power converter system according to claim 20.

23. The secondary switch is an auxiliary N-channel field effect transistor (NFET). The multi-output power converter system according to claim 20.

24. The selective output is a constant current (CC) output. The multi-output power converter system according to claim 20.

25. The selective output is a constant voltage (CV) output. The multi-output power converter system according to claim 20.

26. The secondary control device further comprises a sample and hold circuit configured to sample a value of the forward pin voltage while the primary switch is operating in an on state. The multi-output power converter system according to claim 20.

27. The ZVS calculator is further configured to calculate the hold duration related to the selective output voltage and the value of the forward pin voltage so that the primary switch is zero voltage switched during the second switching cycle. The multi-output power converter system according to claim 26.

28. A method of dynamically switching a primary switch in a power converter, the method comprising: Starting a first switching cycle by closing the primary switch; Receiving a forward pin voltage at a forward pin node; Opening the primary switch; Receiving a selective output voltage; Identifying an idle ringing period; Calculating a holding duration related to the forward pin voltage, the selective output voltage, and the idle ringing period; Closing the secondary switch over the holding duration such that the primary switch is zero-voltage switched during a second switching cycle; A method comprising the above. **Claim 29** The secondary switch is a synchronous rectifier. The method according to claim 28. **Claim 30** The secondary switch is an auxiliary N-channel field effect transistor (NFET). The method according to claim 28. **Claim 31** The secondary switch is an auxiliary bipolar junction transistor (BJT). The method according to claim 28. **Claim 32** The power converter is a flyback converter. The method according to claim 28. **Claim 33** The power converter is a multi-output flyback converter. The method according to claim 28. **Claim 34** Further comprising transferring energy to a selective output to maintain the selective output voltage. The method according to claim 28. **Claim 35** Further comprising using a comparison unit to identify the idle ringing period. The method according to claim 28. **Claim 36** Identifying an open-ring duration related to the idle ringing period; Completing the first switching cycle after the open-ring duration; The method according to claim 28, further comprising the above. **Claim 37** The open-ring duration is substantially equal to one quarter of the idle ringing period. The method according to claim 36.

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