Complementary FET (CFET) and method of manufacturing the same

Abstract

A stacked gate-all-around (GAA) complementary field-effect transistor (CFET) includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA FET includes at least one three-dimensional (3D) semiconductor slab having a channel region and a first surface. A first gate structure surrounds the channel region within the first GAA FET, and a second gate structure surrounds the channel region within the second GAA FET. The first gate structure is stacked opposite the second gate structure in a direction orthogonal to the first surface. In some embodiments, the first crystal structure of the 3D semiconductor slab within the first GAA FET has a first orientation, and the second crystal structure of the 3D semiconductor slab within the second GAA FET has a different orientation for improving carrier mobility.

Description

Technical Field

[0001] Priority Application This application claims priority to U.S. Patent Application No. 17 / 812,300, filed Jul. 13, 2022, entitled "STACKED COMPLEMENTARY FIELD EFFECT TRANSISTOR (CFET) AND METHOD OF MANUFACTURE", which is hereby incorporated by reference in its entirety.

Background Art

[0002] I. Field of the Disclosure The technology of the present disclosure generally relates to complementary metal-oxide semiconductor (CMOS) field-effect transistors (FETs) (CFETs), and more specifically, to stacked FETs.

[0003] II. Background Integrated circuits (ICs) play a role in performing a wide variety of functions with high-level performance in electronic devices. There is always market pressure to minimize the size of electronic devices, which provides the motivation to reduce the size of ICs. Complementary metal-oxide-semiconductor (CMOS) technology is commonly adopted in ICs due to its low power consumption, improved performance, and better noise tolerance compared to circuits that employ only N-type MOS (NMOS) or P-type MOS (PMOS) technology. However, each CMOS transistor includes both a PMOS transistor such as a P-type field effect transistor (PFET) and an NMOS transistor (e.g., NFET). Regardless of whether the PFET and NFET of a CFET are vertically stacked, fin-type, or gate-all-around (GAA) FETs, each CFET in a circuit includes the area occupied by at least one PFET and at least one NFET. Since there can be millions of circuit instances within an IC, the circuit area can significantly affect the area of the IC. Additionally, since the carrier mobility of NFETs is significantly higher than that of PFETs, PFETs are often sized up to compensate for this difference and provide more balanced performance, further increasing the cell area of CMOS transistor circuits. Therefore, there is a desire for CMOS devices with reduced circuit cell area while maintaining balanced performance. SUMMARY OF THE INVENTION

[0004] The aspects disclosed in the detailed description include a stacked complementary field effect transistor (FET) (CFET). Related methods for manufacturing the stacked CFET are also disclosed. The stacked gate all around (GAA) CFET includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA FET includes at least one three-dimensional (3D) semiconductor slab having a channel region and a first surface. A first gate structure surrounds the channel region within the first GAA FET, and a second gate structure surrounds the channel region within the second GAA FET. The first gate structure is stacked opposite the second gate structure in a direction orthogonal to the first surface. In some embodiments, the stacked GAA CFET is a hybrid CFET, and the first crystal structure of the 3D semiconductor slab within the first GAA FET has a first orientation, and the second crystal structure of the 3D semiconductor slab within the second GAA FET has a second orientation different from the first orientation for improving carrier mobility.

[0005] In an exemplary aspect, a stacked CFET is disclosed. The stacked CFET includes a first GAA FET of a first type. The first GAA FET includes a first channel region having a first crystal structure with a first orientation. The first GAA FET includes a first gate structure surrounding the first channel region. The stacked CFET includes a second GAA FET of a second type, and the second GAA FET includes a second channel region having a second crystal structure with a second orientation different from the first orientation. The second GAA FET includes a second gate structure surrounding the second channel region.

[0006] In another exemplary aspect, a method of manufacturing a stacked CFET is disclosed. The method includes forming a first GAA FET of a first type, the first GAA FET comprising a first channel region. The method includes forming a first gate structure surrounding the first channel region. The method includes forming a second GAA FET of a second type, the second GAA FET comprising a second channel region. The method includes forming a second gate structure surrounding the second channel region. The first channel region has a first crystal structure having a first orientation, and the second channel region has a second crystal structure having a second orientation different from the first orientation.

Brief Description of the Drawings

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[0008] Next, with reference to the drawings, some exemplary aspects of the present disclosure will be described. The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" should not necessarily be construed as preferred or advantageous over other aspects.

[0009] Aspects disclosed in the detailed description include stacked complementary field effect transistors (FETs) (CFETs). Related methods of manufacturing stacked CFETs are also disclosed. A stacked gate all around (GAA) CFET includes a first GAA FET of a first type and a second GAA FET of a second type. Each of the first GAA FET and the second GAA FET includes at least one three-dimensional (3D) semiconductor slab having a channel region and a first surface. A first gate structure surrounds the channel region of the 3D semiconductor slab in the first GAA FET, and a second gate structure surrounds the channel region of the 3D semiconductor slab in the second GAA FET. The first gate structure is stacked opposite the second gate structure in a third direction orthogonal to the surface. In some embodiments, the stacked GAA CFET is a hybrid CFET, and the first crystal structure of the 3D semiconductor slab in the first GAA FET has a first orientation, and the second crystal structure of the 3D semiconductor slab in the second GAA FET has a second orientation different from the first orientation for improving carrier mobility.

[0010] FIG. 1 is a side cross-sectional view of a stacked GAA CFET circuit 100 (“CFET100”) including a first GAA FET 102 of a first type stacked opposite a second GAA FET 104 of a second type. In one aspect, CFET100 is an example of a complementary metal-oxide-semiconductor (CMOS) inverter that occupies the substrate area of the first GAA FET 102 and has a reduced area compared to a conventional CMOS inverter arranged adjacent to each other on a substrate. In another aspect, CFET100 is a hybrid CFET in which the 3D semiconductor slab 106 of the first GAA FET 102 has a different surface orientation from the 3D semiconductor slab 108 of the second GAA FET 104, as further described below, to improve performance. GAA CFET100 may be a cell circuit having a layout according to a cell design that can be placed within a die layout by a designer.

[0011] A CMOS circuit provides improved performance, reduced power consumption, and better noise immunity compared to a circuit having only one type of FET, but may include twice the number of transistors. By stacking the first GAA FET 102 and the second GAA FET 104 opposite each other, the area of the CMOS circuit can be significantly reduced (e.g., by up to 50%) compared to a circuit having only one type of FET. In this example, the first GAA FET 102 is of a first type that provides a good reference voltage source (e.g., ground or V SS ), and the second GAA FET 104 is of a second type that provides a good supply voltage source (e.g., 1.8 volts or V DD ).

[0012] The terms "first type" and "second type" refer to one of N-type and P-type, which may also be called N-channel and P-channel. In an N-type device, the semiconductor source and drain are doped with pentavalent dopants, and the voltage applied to the gate within the channel region generates an N-channel in which electrons are the majority carriers. In a P-type or P-channel device, the semiconductor source and drain are doped with trivalent dopants, and the applied gate voltage generates a P-channel in the channel region, where holes are the majority carriers. The 3D semiconductor slabs 106, 108 in a P-type device can include silicon (Si), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), or compounds thereof. The 3D semiconductor slabs 106, 108 in an N-type device can include Si, GaAs, or compounds thereof.

[0013] The first GAA FET 102 includes three 3D semiconductor slabs 106, but may have fewer or more numbers. The first gate structure 110 surrounds the 3D semiconductor slab 106 in the channel region 112 (e.g., on all sides). The first GAA FET 102 also includes epitaxial source / drains 114A and 114B coupled to both ends of the 3D semiconductor slab 106. The second GAA FET 104 includes three 3D semiconductor slabs 108, but may have fewer or more numbers. The 3D semiconductor slab 106 includes a surface 116 extending in the X-axis and Y-axis directions. The second gate structure 118 surrounds the 3D semiconductor slab 108 in the channel region 120. The first gate structure 110 is stacked opposite the second gate structure 118 in the Z-axis direction. The second GAA FET 104 also includes epitaxial regions 122A and 122B, also referred to herein as epitaxial source / drains 122A and 122B, coupled to both ends of the 3D semiconductor slab 108. The first gate structure 110 is insulated from the 3D semiconductor slab 106 by an insulator layer 124, and the second gate structure 118 is insulated from the 3D semiconductor slab 108 by an insulator layer 126.

[0014] The first GAA FET 102 is disposed within a first layer 128 that includes a layer fill material 130 that is an insulator or a dielectric material. The first layer 128 is disposed adjacent to a first base layer 132, which is also an electrical insulator and / or a dielectric material. The second GAA FET 104 is disposed within a second layer 134 that can also include the fill material 130. The second layer 134 is disposed adjacent to a second base layer 136. The first base layer 132 and the second base layer 136 may be insulator layers that can include an oxide material. The CFET 100 includes a third layer 138 between the first layer 128 and the second layer 134. In some embodiments, as described below, the third layer 138 is a bonding layer for bonding the second layer 134 to the first layer 128. In other embodiments, the third layer 138 may be a base layer formed on the first layer 128 before the second layer 134 is formed.

[0015] The CFET 100 also includes a first contact layer 140 and a second contact layer 142 that include contacts CON(1) to CON(7), and the contacts CON(1) to CON(7) are electrically coupled by vias VIA(1) to VIA(9) to one or both of the first GAA FET 102 and the second GAA FET 104. The contacts CON(1) to CON(7) couple the first GAA FET 102 to the second GAA FET 104 and can provide a connection to an external circuit. The number of contacts CON(1) to CON(7) and vias VIA(1) to VIA(9) can vary depending on the configuration of the CFET 100.

[0016] The first gate structure 110 and the second gate structure 118 are electrically coupled to each other. Such an electrical coupling may be internal via a via VIA(5) that extends from the first gate structure 110 to the second gate structure 118 through the third layer 138. In other embodiments, the first gate structure 110 and the second gate structure 118 may be electrically coupled to each other internally or externally by a means other than the via VIA(5). By the first gate structure 110 being electrically coupled to the second gate structure 118, the binary input IN 100 can be supplied to the CFET100 by either one of the contacts CON(3) or CON(6). In an embodiment where the first GAA FET102 is an N-type FET and the second GAA FET104 is a P-type FET, the source / drain 114A is coupled to the reference voltage V SS by a via VIA(2), and the contacts CON(2) and the source / drain 122A are coupled to the supply voltage V DD by vias VIA(7) and VIA(1) and contacts CON(5) and CON(1). The binary output OUT 100 having a binary state that is the inversion of the binary input IN 100 is provided to contacts CON(4) and CON(7) coupled by vias VIA(4), VIA(6), and VIA(8) through one of the source / drains 114B or 122B. The channel direction CD 100 through the 3D semiconductor slab 106 and the channel direction CD 100 through the 3D semiconductor slab 108 is in the X-axis direction (e.g., from left to right) of FIG. 1. In this configuration, the CFET100 can be coupled to an external circuit via the contacts CON(1)-CON(4) in the first contact layer 140, but in an alternative arrangement of the contacts, the CFET100 can be coupled to the external circuit via the second contact layer 142.

[0017] As will be further described below with reference to FIGS. 2 to 6H, the first GAA FET 102 and the second GAA FET 104 can be manufactured separately as silicon-on-insulator (SOI) devices or bulk semiconductor devices. After being manufactured separately, the first GAA FET 102 and the second GAA FET 104 can be joined to each other by using a layer transfer and stacking process to form the CFET 100. Alternatively, the second GAA FET 104 can be manufactured separately on the first GAA FET 102.

[0018] Since the first GAA FET 102 and the second GAA FET 104 are manufactured separately, as will be disclosed in detail below, the 3D semiconductor slab 106 of the first GAA FET 102 is manufactured separately from the 3D semiconductor slab 108 of the second GAA FET 104. Therefore, the crystal structure 144 of the 3D semiconductor slab 106 can be formed with an orientation different from the orientation of the crystal structure 146 of the 3D semiconductor slab 108. In particular, in an embodiment where the first GAA FET 102 is an N-type FET, the crystal structure 144 may have a (100) surface orientation, and the channel direction D of <110> 100 provides high electron mobility. For example, in the second GAA FET 104, the crystal structure 146 has a (110) surface orientation and a channel direction D of <110> 100A P-type FET having a hole mobility in it, and its performance is superior to that of a P-type FET having the same surface orientation in crystal structure as an N-type FET. In the conventional structure, P-type FETs and N-type FETs formed on the same substrate have a common orientation (for example, (100)), which thus hindered the performance of the P-type FET. By separately forming a crystal structure 146 having a surface orientation of (110), the performance of the second GAA FET 104 of P-type is increased by up to 15%. In addition, by forming the P-type FET (for example, the second GAA FET 104) separately from or after forming the N-type FET (for example, the first GAA FET 102), the P-type FET does not need to undergo a high-temperature process (for example, annealing) used in the manufacture of the N-type FET that can cause deterioration of the P-type FET.

[0019] FIG. 2 is a diagram of a first GAA FET 202 formed on a first insulator layer 204 and a second GAA FET 206 formed on a second insulator layer 208. The first GAA FET 202 and the second GAA FET 206 may be the first GAA FET 102 and the second GAA FET 104 in FIG. 1. In the embodiment of FIG. 2, the first GAA FET 202 is an N-type FET including a 3D semiconductor slab 210 and a first gate structure 212. The first GAA FET 202 can be formed on the first insulator layer 204 after the first insulator layer 204 is formed on a substrate (not shown). The first insulator layer 204 can be formed of an oxide such as silicon dioxide (SiO2) or another suitable insulator material, and the substrate may be a semiconductor substrate (for example, silicon). Thereafter, the substrate can be removed from the first insulator layer 204. In this embodiment, the second GAA FET 206 is a P-type FET including a 3D semiconductor slab 218 and a second gate structure 220.

[0020] The first GAA FET 202 and the second GAA FET 206 in FIG. 2 are shown in a perspective view before epitaxial regions (epitaxial source / drain) are formed at both ends of the 3D semiconductor slabs 210 and 218 to more clearly show the features of the cross-sectional view of FIG. 1. Here, it can be seen that the first gate structure 212 is formed on the first insulator layer 204, and the second gate structure 220 is formed on the second insulator layer 208.

[0021] As described above, the first GAA FET 102 is formed in the first layer 128 including the filling material 130, but such filling material is not included in FIG. 2 to simplify the description of FIG. 2. In the stacking process, the second GAA FET 206 may be inverted to stack facing the first GAA FET 202. A bonding layer (not shown) corresponding to the third layer 138 in FIG. 1 may be included to bond the first GAA FET 202 to the second GAA FET 206. In an alternative embodiment, the second GAA FET 206 can be stacked as shown to perform a face-to-back bonding to the first GAA FET 202.

[0022] FIG. 3 is a flowchart of a method 300 for manufacturing the stacked GAA CFET 100 of FIG. 1. This method includes forming a first GAA FET 102 of a first type (block 302), and forming the first GAA FET 102 of the first type includes forming a first channel region 112 having a first crystal structure having a first orientation (block 304). The method of forming the first GAA FET 102 includes forming a first gate structure 110 surrounding the first channel region 112 (block 306). This method includes forming a second GAA FET 104 (308), and forming the second GAA FET 104 (308) includes forming a second channel region 120 having a second crystal structure having a second orientation different from the first orientation (block 310). The method of forming the second GAA FET includes forming a second gate structure 118 surrounding the second channel region 120 (block 312).

[0023] Figures 4A - 4F are cross - sectional side views of stages 400A(1) - 400F in manufacturing the CFET100 of FIG. 1, and FIGS. 5A - 5F are flowcharts of a method 500 corresponding to the manufacturing stages of the CFET100 of FIGS. 4A - 4F. FIG. 4A includes manufacturing stage 400A(1) of the first GAA FET102 of FIG. 1. This method includes forming a first base layer 132 on a lower substrate 402 (block 502), and forming a first type of first GAA FET102 including a 3D semiconductor slab 106, source / drains 114A, 114B, and a first gate structure 110 on the first base layer 132 (block 504). In this embodiment, the first GAA FET102 is a silicon - on - insulator (SOI) transistor formed on the lower substrate 402. The lower substrate 402 is an insulator layer, and the insulator layer may be an oxide layer (e.g., SiO2). The lower substrate 402 can be formed on a support substrate (not shown) such as a semiconductor substrate before forming the first GAA FET102, and the semiconductor substrate is removed later. Alternatively, in some embodiments, the first GAA FET102 may be a bulk silicon transistor, the lower substrate 402 is a semiconductor (e.g., silicon) substrate, and the first GAA FET102 is formed on a shallow trench isolation (STI) layer. Whether SOI or bulk, the first GAA FET102 is formed within a first layer 128 including a filling material 130 such as an inter - layer dielectric (ILD). After forming the first GAA FET102 on the lower substrate 402, this method includes polishing the first layer 128 and forming a third layer 138 on the first layer 128 (block 506). The polishing may be chemical, mechanical polish (CMP), or other known methods. The third layer 138 in this embodiment is a bonding layer for bonding the first layer 128 to a second layer 134. The third layer 138 can include a bond oxide such as SiO2. This method further includes forming vias VIA(5), VIA(6) that penetrate the third layer (138) (block 508).

[0024] FIG. 4A also includes manufacturing stage 400A(2) of the second GAA FET 104. The second GAA FET 104 in this embodiment may also be a SOI having an upper substrate 406 which is an insulator layer, or alternatively a bulk transistor, in which case the upper substrate 406 is a semiconductor substrate. The method 500 further includes forming a second base layer 136 on the upper substrate 406 (block 510). The method includes forming a second layer 134 including the second GAA FET 104 on the second base layer 136 (block 512), and the second GAA FET 104 further includes a 3D semiconductor slab 108, source / drains 122A, 122B, and a second gate structure 118. The method includes polishing the second layer 134 (e.g., by CMP) (block 514) and forming a via VIA(6) in the second layer 134 (block 516).

[0025] FIG. 4B includes manufacturing stage 400B of the CFET 100 in the method 500, and the manufacturing stage 400B includes bonding and annealing the second layer 134 to the third layer 138 with the second gate structure 118 facing the first gate structure 110 (block 518). In this regard, the term "facing" indicates that the first gate structure 110 and the second gate structure 118 directly face each other on both sides of the third layer 138 in a direction orthogonal to the third layer 138. The annealing process can be used in the bonding process to ensure an oxide-to-oxide bond between the third layer 138 and the second layer 134.

[0026] FIG. 4C includes stage 400C in the manufacture of CFET 100. The method of FIG. 5C includes removing the upper substrate 406 from the second GAA FET 104 (block 520). Removing the upper substrate 406 can include chemically and / or mechanically removing the upper substrate 406 from the second base layer 136. FIG. 4D includes stage 400D in the manufacture of CFET 100. According to stage 400D, method 500 includes forming vias (VIA(1), VIA(7)-VIA(9)) in the second layer 134 (block 522) and forming a second contact layer 142 including contacts CON(5)-CON(7) on the second base layer 136 (block 524). Forming vias VIA(1), VIA(7)-VIA(9) includes forming vias that penetrate the second base layer 136 of the second GAA FET 104 (e.g., etching and filling with a conductive metal). Forming the second contact layer 142 can include first forming contacts CON(5)-CON(7) on the second base layer 136 and disposing a dielectric on the second base layer 136 and on contacts CON(5)-CON(7). Alternatively, contacts CON(5)-CON(7) can be formed within the second base layer 136.

[0027] FIG. 4E includes stage 400E in the manufacture of CFET100. The method of FIG. 5E includes inverting CFET100 and removing the lower substrate 402 from the first GAA FET102 (block 526). Removing the lower substrate 402 can include chemically and / or mechanically removing the lower substrate 402 from the first base layer 132. FIG. 4F includes stage 400F in the manufacture of CFET100, and the method of FIG. 5F includes forming vias VIA(1)-VIA(4) in the first GAA FET102 (block 528) and adding a first contact layer 140 including contacts CON(1)-CON(4) (block 530). The CFET100 of FIG. 4F can be coupled to an external circuit from either the first contact layer 140 or the second contact layer 142, which may include thinning the dielectric on one of the first contact layer (140) and the second contact layer (142) to expose either contacts (CON(1)-CON(4)) or (CON(1) and CON(5)-CON(7)).

[0028] In the CFET100 manufactured by the above method, the first GAA FET102 of the first type can be either an N-type or a P-type transistor and can be formed as either a SOI or a bulk-type transistor. In the above manufacturing method, the first GAA FET102 and the second GAA FET104 are manufactured separately, and thus, the 3D semiconductor slabs 106 and 108 can be formed to have crystal structures 144, 146 with different surface orientations for improving carrier mobility performance. In this regard, for more balanced performance, the performance improvement can include improving the performance of the P-type FET without adversely affecting the performance of the N-type FET. The relative improvement in the performance of the P-type FET can avoid the need to upsizing the P-type FET to achieve more balanced performance. In this way, the size of the CFET100 can be reduced.

[0029] Figures 6 to 8 are side cross-sectional views of other embodiments of a stacked GAA CFET circuit having SOI transistors.

[0030] Figure 6 is a side cross-sectional view of a CFET 600 in which a first GAA FET 602, which is a first type of SOI transistor, is stacked face-to-face with a second GAA FET 604, which is a second type of SOI transistor. The first GAA FET 602 includes a 3D semiconductor slab 606 having a channel direction D extending in the X-axis direction between epitaxial source / drains (regions of epitaxially grown material) 608A and 608B. 606 The channel region 610 of the 3D semiconductor slab 606 is surrounded by a first gate structure 612. The second GAA FET 604 includes a 3D semiconductor slab 614 having a channel direction D extending between epitaxial source / drains 616A and 616B. 606 The channel region 618 of the 3D semiconductor slab 614 is surrounded by a second gate structure 620. The first GAA FET 602 is formed in a first layer 622. The second GAA FET 604 is formed in a second layer 624. A third layer 626 between the first layer 622 and the second layer 624 may be in direct contact with the first layer 622 and the second layer 624. In this regard, the third layer 626 may be a bonding layer that bonds the first layer 622 to the second layer 624. The CFET 600 also includes a lower base layer 628 on the first layer 622 and an upper base layer 630 on the second layer 624. The CFET 600 also includes contact layers 632 and 634 formed on the lower base layer 628 and the upper base layer 630, respectively.

[0031] In the above aspect, the first GAA FET 602 corresponds to the first GAA FET 102 in FIG. 1, and the second GAA FET 604 corresponds to the second GAA FET 104. However, the CFET 600 is different from the CFET 100 in FIG. 1 with respect to vias VIA(1) to VIA(8) and contacts CON(1) to CON(7). It should be noted that the electrical coupling between the first gate structure 612 and the second gate structure 620 is not shown in FIG. 6, but can be provided within different cross-sections (not shown) of the CFET 600 or outside the CFET 600.

[0032] FIG. 700 is a cross-sectional view of a CFET 700 having a first GAA FET 702 in a first layer 704 and a second GAA FET 706 in a second layer 708. The CFET 700 includes a third layer 710 between the first layer 704 and the second layer 708. The first GAA FET 702 and the second GAA FET 706 are formed as SOI transistors. Generally, the CFET 700 corresponds to the CFET 100 in FIG. 1. However, in the CFET 700, the second GAA FET 706 is stacked back-to-back with the first GAA FET 702 facing each other. That is, the third layer 710 in the CFET 700 is an insulating layer on which the second GAA FET 706 is formed in an SOI process. The first layer 704 is formed on an insulator layer 712. The second layer 708 is formed on the third layer 710, and the third layer 710 is joined to the first layer 704. A base layer 714 and a contact layer 716 are formed on the second layer 708, and a contact layer 718 is formed on the insulator layer 712. Vias VIA(1) to VIA(9) and contacts CON(1) to CON(7) correspond to the same labeled features in FIG. 1.

[0033] FIG. 8 is a cross-sectional view of a CFET 800 including a first GAA FET 802 formed on a first insulator layer 804 and a second GAA FET 806 formed on a second insulator layer 808. The CFET 800 corresponds to the CFET 600 of FIG. 6, except that the second GAA FET 806 is laminated surface-to-back surface with a second insulator layer 808 joined to a first layer 810 including the first GAA FET 802, as described with respect to the CFET 700.

[0034] FIG. 9 is a diagram of a first GAA FET 902 on a first semiconductor substrate 904 and a diagram of a second GAA FET 906 on a second semiconductor substrate 908. Since the first GAA FET 902 and the second GAA FET 906 are formed on different semiconductor substrates, the orientation of the crystal structure 910 of one or more 3D semiconductor slabs 912 in the first GAA FET 902 can be different from the orientation of the crystal structure 914 of one or more 3D semiconductor slabs 916 of the second GAA FET 906. As an example of an embodiment, for example, the first GAA FET 902 may be a P-type FET in which at least one 3D semiconductor slab 912 has a (110) surface orientation, and the second GAA FET 906 may be an N-type FET in which at least one 3D semiconductor slab 916 has a (100) surface orientation. It should be understood that since the crystal structures 910 and 914 are separately formed on different semiconductor substrates 904 and 908, other surface orientations are possible. Both the 3D semiconductor slabs 912 and 916 can have a channel direction D of <100> corresponding to the X-axis direction in FIG. 9. 900 The first GAA FET 902 and the second GAA FET 906 are formed as bulk transistors and are shown in perspective view without epitaxial source / drain at both ends of the 3D semiconductor slabs 912 and 916 to provide a clearer view of specific features. Here, it can be seen that the first gate structure 918 is formed on the STI layer 920 so as to be electrically separated from the first semiconductor substrate 904. The second gate structure 922 is formed on the STI layer 924 on the second semiconductor substrate 908.

[0035] The first GAA FET 902 includes a well 926 between the 3D semiconductor slab 912 and the first semiconductor substrate 904. The well 926 reduces or avoids the leakage current path in the channel direction D passing through the first semiconductor substrate 904 when the first GAA FET 902 is inactive. By reducing the leakage current, the performance of the first GAA FET 902 can be improved and the power consumption can be reduced. 900 By reducing the leakage current, the performance of the first GAA FET 902 can be improved and the power consumption can be reduced.

[0036] In an embodiment where the first GAA FET 902 is a P-type FET, the well 926 may be an N+ well doped with a high concentration of N-type dopant. In an embodiment where the first GAA FET 902 is an N-type FET, the well 926 may be a P+ well doped with a high concentration of P-type dopant. In this regard, the second GAA FET 906 also has a well 928 between the 3D semiconductor slab 916 and the second semiconductor substrate 908. The wells corresponding to the well 926 and the well 928 may not be visible in FIGS. 10 to 12. This is because vias are formed penetrating these wells at the positions of the illustrated cross sections.

[0037] FIGS. 10 to 12 are side cross-sectional views of an embodiment of a stacked GAA CFET circuit formed on a semiconductor substrate. The features of FIGS. 10 to 12 corresponding to the features of the previously presented figures may not be labeled and may not be described separately to avoid redundancy. FIG. 10 is a side cross-sectional view of a CFET 1000. The CFET 1000 includes a first GAA FET 1002 and a second GAA FET 1004 stacked in a surface-to-surface configuration. The CFET 1000 corresponds to the first GAA FET 102 and the second GAA FET 104 in FIG. 1, except that the first GAA FET 1002 and the second GAA FET 1004 are bulk-type transistors formed on the first semiconductor substrate 1006 and the second semiconductor substrate 1008, respectively, instead of on the first insulator layer 204 and the second insulator layer 208.

[0038] The first GAA FET 1002 includes a 3D semiconductor slab 1010 that can be formed from a first semiconductor substrate 1006. The second GAA FET 1004 includes a 3D semiconductor slab 1012 that can be formed from a second semiconductor substrate 1008. The first GAA FET 1002 is included in a first layer 1014, and the second GAA FET 1004 is within a second layer 1016. The CFET 1000 includes a third layer 1018 that may be a bonding layer including an oxide or other bonding material 1020. The CFET 1000 includes a first semiconductor substrate 1006 and a STI layer adjacent to the first layer 1014. The CFET 1000 further includes a first contact layer 1024 including contacts 1026. Due to the conductivity of the first semiconductor substrate 1006, an insulating wall 1028 is provided between each via 1030 and the first semiconductor substrate 1006. The CFET 1000 further includes a STI layer 1032 between the second layer 1016 and the second semiconductor substrate 1008. A second contact layer 1034 is formed on the second semiconductor substrate 1008 and includes contacts 1036.

[0039] FIG. 11 is a cross-sectional view of a CFET 1100 in which a first GAA FET 1102 and a second GAA FET 1104 are stacked facing each other in a surface-to-surface configuration, corresponding to the CFET 600 of FIG. 6, except that the CFET 1100 is a bulk device rather than a SOI device. Differences between the CFET 1100 and the CFET 600 include having a first semiconductor substrate 1106 and a STI layer 1108 where the CFET 600 includes a lower base layer 628, and having a second semiconductor substrate 1110 and a STI layer 1112 instead of the upper base layer 630 of FIG. 6.

[0040] FIG. 12 is a cross-sectional view of a CFET 1200 in which a first GAA FET 1202 and a second GAA FET 1204 are stacked back-to-back, corresponding to the CFET 800 of FIG. 8. However, since the CFET 1200 is a bulk transistor, there are differences between the CFET 1200 and the CFET 800. The differences include that the CFET 1200 has a first semiconductor substrate 1206 and an STI layer 1208 instead of the CFET 800 including a first insulator layer 804, and that the CFET 1200 includes a second semiconductor substrate 1210 and an STI layer 1212 instead of the second insulator layer 808 of FIG. 8.

[0041] Since each of the CFETs 1000 - 1200 in FIGS. 10 - 12 is formed according to the method described above, it should be noted that the 3D semiconductor slabs of the first GAA FET and the 3D semiconductor slabs of the second GAA FET can be formed with different crystal structure orientations in order to improve the performance of the P-type device without degrading the performance of the N-type device. In this context, the term "3D semiconductor slab" refers to a thin layer of semiconductor material having a crystal structure.

[0042] According to the aspects disclosed in this specification, the stacked GAA CFET can be provided in or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed-position data units, mobile-position data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (such as smartwatches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0043] FIG. 13 shows an exemplary wireless communication device 1300 that includes radio-frequency (RF) components formed from one or more integrated circuits (ICs) 1302, where the IC 1302 can include an exemplary stacked GAA CFET in which a gate structure of a first GAA FET and a gate structure of a second GAA FET are stacked facing each other, in accordance with any of the aspects disclosed herein, as shown in FIGS. 1, 6-8, and 10-12. The wireless communication device 1300 can include, or can be provided within, any of the devices mentioned above by way of example. As shown in FIG. 8, the wireless communication device 1300 includes a transceiver 1304 and a data processor 1306. The data processor 1306 can include memory for storing data and program code. The transceiver 1304 includes a transmitter 1308 and a receiver 1310 that support two-way communication. In general, the wireless communication device 1300 can include any number of transmitters 1308 and / or receivers 1310 for any number of communication systems and frequency bands. All or part of the transceiver 1304 can be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.

[0044] The transmitter 1308 or the receiver 1310 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal is frequency-converted between RF and baseband in multiple stages, for example, from RF to an intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is frequency-converted between RF and baseband in one stage. The superheterodyne architecture and the direct conversion architecture may use different circuit blocks and / or have different requirements. In the wireless communication device 1300 of FIG. 13, the transmitter 1308 and the receiver 1310 are implemented using a direct conversion architecture.

[0045] In the transmission path, the data processor 1306 processes the data to be transmitted and provides an I analog output signal and a Q analog output signal to the transmitter 1308. In the exemplary wireless communication device 1300, the data processor 1306 includes digital-to-analog converters (DACs) 1312(1), 1312(2) for converting the digital signal generated by the data processor 1306 into an I analog output signal and a Q analog output signal, for example, an I output current and a Q output current, for further processing.

[0046] Within the transmitter 1308, low-pass filters 1314(1) and 1314(2) filter the I analog output signal and the Q analog output signal, respectively, to remove unwanted signals generated by previous digital-to-analog conversions. Amplifiers (AMPs) 1316(1) and 1316(2) amplify the signals from low-pass filters 1314(1) and 1314(2), respectively, to provide an I baseband signal and a Q baseband signal. The upconverter 1318 upconverts the I baseband signal and the Q baseband signal using the I TX LO signal and the Q TX LO signal from the transmit (TX) local oscillator (LO) signal generator 1322 through mixers 1320(1) and 1320(2) to provide the upconverted signal 1324. The filter 1326 filters the upconverted signal 1324 to remove unwanted signals generated by frequency upconversion and noise within the receive frequency band. The power amplifier (PA) 1328 amplifies the upconverted signal 1324 from the filter 1326 to obtain a desired output power level and provides a transmitted RF signal. The transmitted RF signal is routed through a duplexer or switch 1330 and transmitted via an antenna 1332.

[0047] In the receiving path, antenna 1332 receives the signal transmitted by the base station to provide a received RF signal, which is routed through duplexer or switch 1330 and provided to low noise amplifier (LNA) 1334. Duplexer or switch 830 is designed to operate using specific RX-TX duplexer frequency separation so that the receive (RX) signal is separated from the TX signal. To obtain the desired RF input signal, the received RF signal is amplified by LNA 1334 and filtered by filter 1336. Downconversion mixers 1338(1), 1338(2) mix the output of filter 1336 with the I RX LO signal and Q RX LO signal (i.e., LO_I and LO_Q) from RX LO signal generator 1340 to generate an I baseband signal and a Q baseband signal. The I baseband signal and Q baseband signal are amplified by AMPs 1342(1), 1342(2) and further filtered by low pass filters 1344(1), 1344(2) to obtain an I analog input signal and a Q analog input signal, and those analog input signals are provided to data processor 1306. In this embodiment, data processor 1306 includes analog-to-digital converters (ADCs) 1346(1), 1346(2) for converting the analog input signals into digital signals to be further processed by data processor 1306.

[0048] In the wireless communication device 1300 of FIG. 13, the TX LO signal generator 1322 generates the I TX LO signal and the Q TX LO signal used for frequency up-conversion, while the RX LO signal generator 1340 generates the I RX LO signal and the Q RX LO signal used for frequency down-conversion. Each LO signal is a periodic signal having a specific fundamental frequency. The TX phase-locked loop (PLL) circuit 1348 receives timing information from the data processor 1306 and generates a control signal used to adjust the frequency and / or phase of the TX LO signal from the TX LO signal generator 1322. Similarly, the RX PLL circuit 1350 receives timing information from the data processor 1306 and generates a control signal used to adjust the frequency and / or phase of the RX LO signal from the RX LO signal generator 1340.

[0049] As shown in FIGS. 1, 6-8, and 10-12, the wireless communication device 1300 can include an exemplary stacked GAA CFET circuit in which the gate structure of the first GAA FET and the gate structure of the second GAA FET are stacked facing each other according to any of the aspects disclosed herein, and can be provided within or integrated into any processor-based device. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed position data units, mobile position data units, global positioning system (GPS) devices, mobile phones, cellular phones, smartphones, session initiation protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, eyewear, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

[0050] FIG. 14 shows an example of a processor-based system 1400 including a circuit that includes a circuit including an exemplary stacked GAA CFET circuit in which a gate structure of a first GAA FET and a gate structure of a second GAA FET are stacked facing each other according to any aspect disclosed herein, as shown in FIGS. 1, 6-8, and 10-12. In this example, the processor-based system 1400 includes one or more central processor units (CPUs) 1402, sometimes referred to as a CPU or a processor core, each including one or more processors 1404. The CPU 1402 may have a cache memory 1406 coupled to the processor 1404 to provide rapid access to temporarily stored data. The CPU(s) 1402 is coupled to a system bus 1408 and can interconnect master and slave devices included in the processor-based system 1400. As is well known, the CPU 1402 communicates with these other devices by exchanging address information, control information, and data information via the system bus 1408. For example, the CPU(s) 1402 can communicate a bus transaction request to a memory controller 1410 as an example of a slave device. Although not shown in FIG. 14, multiple system buses 1408 can be provided, and each system bus 1408 can constitute a different fabric.

[0051] Other master devices and slave devices can be connected to the system bus 1408. As shown in FIG. 14, these devices can include, by way of example, a memory system 1412 including memory controllers 1410 and one or more memory arrays 1414, one or more input devices 1416, one or more output devices 1418, one or more network interface devices 1420, and one or more display controllers 1422. The input device(s) 1416 can include any type of input device, including but not limited to input keys, switches, voice processors, etc. The output device(s) 1418 can include any type of output device, including but not limited to audio, video, other visual indicators, etc. The network interface device(s) 1420 can be any device configured to enable data exchange with a network 1424. The network 1424 can be any type of network, including but not limited to a wired or wireless network, a private or public network, a local area network (LAN), a wireless local area network (WLAN), a wide area network (WAN), a BLUETOOTH (registered trademark) network, and the Internet. The network interface device(s) 1420 can be configured to support any desired type of communication protocol.

[0052] The CPU(s) 1402 can also be configured to access a display controller(s) 1422 via a system bus 1408 to control information sent to one or more displays 1426. The display controller(s) 1422 sends information to be displayed to the display(s) 1426 via one or more video processors 1428, and the one or more video processors 1428 process the information to be displayed into a format suitable for the display(s) 1426. The display(s) 1426 can include any type of display, including but not limited to a cathode ray tube (CRT), a liquid crystal display (LCD), a plasma display, or a light-emitting diode (LED) display.

[0053] One of ordinary skill in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory or on another computer-readable medium and executed by a processor or other processing device, or combinations of both. The master and slave devices described herein can be employed, by way of example, in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be any type and size of memory and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative components, blocks, modules, circuits, and steps have been generally described above in terms of their functionality. How such functionality is implemented depends upon the particular application, design choices, and / or design constraints imposed on the overall system. One of ordinary skill in the art may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0054] Various illustrative logical blocks, modules, and circuits described in connection with the aspects disclosed herein can be implemented or performed using a processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate logic or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor can be a microprocessor, but in the alternative, the processor can be any conventional processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in association with a DSP core, or any other such configuration).

[0055] Aspects disclosed herein can be embodied in hardware and stored within hardware, for example, in instructions embodied in any other form of computer-readable medium known in the art, such as random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, removable disk, CD-ROM, or the like. An exemplary storage medium is coupled to the processor such that the processor can read information from, and write information to, the storage medium. Alternatively, the storage medium can be integral with the processor. The processor and the storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and the storage medium can exist as discrete components in a remote station, base station, or server.

[0056] Also, note that the operation steps described in any of the exemplary aspects of this specification are also noted in terms of providing examples and explanations. The described operations can also be implemented in many different sequences other than the illustrated sequence. Further, the operations described in a single operation step can actually be implemented in a plurality of different steps. Furthermore, one or more operation steps described in the exemplary aspects can also be combined. It should be understood that many various modifications can be made to the operation steps shown in the flowchart diagrams, as will be readily apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using various technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof.

[0057] The above description of the present disclosure is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can also be applied to other variations. Therefore, the present disclosure is not intended to be limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

[0058] In the following numbered clauses, implementation examples are described. 1. A first gate-all-around (GAA) FET of a first type, comprising: a first channel region having a first crystal structure with a first orientation; a first gate structure surrounding the first channel region; and a first GAA FET of the first type. A second GAA FET of a second type, comprising: A second channel region having a second crystal structure with a second orientation different from the first orientation, A second gate structure surrounding the second channel region, A second GAA FET of a second type, comprising: A stacked complementary field effect transistor (CFET) comprising: 2. The first orientation of the first crystal structure is (100), The second orientation of the second crystal structure is (110), The stacked CFET according to clause 1. 3. The first GAA FET of the first type is an N-type FET, The second GAA FET of the second type is a P-type FET, The stacked CFET according to clause 1 or clause 2. 4. A first layer including the first GAA FET, A second layer including the second GAA FET, A third layer between the second layer and the first layer, The stacked CFET according to any one of clauses 1 to 3, further comprising: 5. The stacked CFET according to clause 4, wherein the third layer includes a bonding layer that bonds the first layer to the second layer. 6. The stacked CFET according to clause 5, wherein the bonding layer includes an oxide layer. 7. The stacked CFET according to any one of clauses 4 to 6, wherein the third layer includes a semiconductor substrate. 8. The stacked CFET according to any one of clauses 4 to 7, further comprising a via extending from the first gate structure to the second gate structure through the third layer. 9. A first dielectric layer on the first layer, the first dielectric layer comprising a first contact coupled to the first GAA FET, A second dielectric layer on the second layer, the second dielectric layer comprising a second contact coupled to the second GAA FET, The stacked CFET according to any one of clauses 4 to 8, further comprising: 10. The stacked CFET according to clause 9, further comprising a via extending from the first contact to the second contact through the first layer, the third layer, and the second layer. 11. The stacked CFET according to clause 9 or clause 10, further comprising a first semiconductor substrate between the first layer and the first dielectric layer. 12. The stacked CFET according to clause 11, further comprising a second semiconductor substrate between the second layer and the second dielectric layer. 13. The stacked CFET according to any one of clauses 1 to 12, wherein a first epitaxial region coupled to the first channel region of the first GAA FET is coupled to a second epitaxial region coupled to the second channel region of the second GAA FET. 14. The stacked CFET according to any one of clauses 1 to 13, integrated into an integrated circuit (IC). 15. The stacked CFET according to any one of clauses 1 to 14, integrated into a device selected from the group consisting of a set-top box, an entertainment unit, a navigation device, a communication device, a fixed-position data unit, a mobile-position data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smartphone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device, a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, a portable digital video player, an automobile, vehicle components, an avionics system, a drone, and a multicopter. 16. A method of manufacturing a stacked complementary field-effect transistor (CFET), comprising: a first gate-all-around (GAA) FET of a first type, comprising: a first channel region having a first crystal structure having a first orientation; and A first gate structure surrounding a first channel region, forming a first GAA FET of a first type, comprising: A second GAA FET of a second type, having a second channel region having a second crystal structure with a second orientation different from the first orientation, a second gate structure surrounding the second channel region, forming a second GAA FET of a second type, comprising: A method comprising. 17. Forming the first GAA FET further comprises forming the first GAA FET in a first layer on a first oxide layer on a first substrate, Forming the second GAA FET further comprises forming the second GAA FET in a second layer on a second oxide layer on a second substrate, The method according to clause 16. 18. The first orientation is a (100) orientation, The second orientation is a (110) orientation, The method according to clause 16 or clause 17. 19. Forming a bonding layer on one of the first layer and the second layer, Stacking the second layer on the first layer, The method according to clause 17 or clause 18, further comprising: 20. The method according to clause 19, further comprising forming a via extending through the bonding layer and coupling the first gate structure to the second gate structure.

Claims

1. A first gate-all-around (GAA) FET of the first type, A first channel region having a first crystal structure having a first orientation, A first gate structure surrounding the first channel region, A first type of first GAA FET comprising, A second type of second GAA FET, A second channel region having a second crystal structure having a second orientation different from the first orientation, A second gate structure surrounding the second channel region, A second type of second GAA FET comprising, A stacked complementary field-effect transistor (CFET) equipped with this feature.

2. The first orientation of the first crystal structure is (100), The second orientation of the second crystal structure is (110), or The first type of the first GAA FET is an N-type FET, The second type of the second GAA FET is a P-type FET. The multilayer CFET according to claim 1.

3. The first layer including the first GAA FET, The second layer includes the second GAA FET, A third layer between the second layer and the first layer, The multilayer CFET according to claim 1, further comprising the above.

4. The multilayer CFET according to claim 3, wherein the third layer includes a bonding layer that bonds the first layer to the second layer, and preferably the bonding layer includes an oxide layer.

5. The stacked CFET according to claim 3, wherein the third layer further comprises vias including a semiconductor substrate or extending through the third layer from the first gate structure to the second gate structure.

6. A first dielectric layer on the first layer, comprising a first contact coupled to the first GAA FET, A second dielectric layer on the second layer, comprising a second contact coupled to the second GAA FET, The multilayer CFET according to claim 3, further comprising the above.

7. The multilayer CFET according to claim 6, further comprising vias extending from the first contact to the second contact, penetrating the first layer, the third layer, and the second layer.

8. The stacked CFET according to claim 6, further comprising a first semiconductor substrate between the first layer and the first dielectric layer, and preferably further comprising a second semiconductor substrate between the second layer and the second dielectric layer.

9. The stacked CFET according to claim 1, wherein a first epitaxial region coupled to the first channel region of the first GAA FET is coupled to a second epitaxial region coupled to the second channel region of the second GAA FET.

10. Integrated into an integrated circuit (IC), or The stacked CFET according to claim 1, integrated into a device selected from the group consisting of set-top boxes, entertainment units, navigation devices, communication devices, fixed-location data units, mobile-location data units, Global Positioning System (GPS) devices, mobile phones, cell phones, smartphones, Session Initiation Protocol (SIP) phones, tablets, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices, desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multicopters.

11. A method for manufacturing a stacked complementary field-effect transistor (CFET), A first gate-all-around (GAA) FET of the first type, A first channel region having a first crystal structure having a first orientation, A first gate structure surrounding the first channel region, To form a first GAA FET of a first type, A second type of second GAA FET, A second channel region having a second crystal structure having a second orientation different from the first orientation, A second gate structure surrounding the second channel region, To form a second type of second GAA FET comprising, Methods that include...

12. Forming the first GAA FET further includes forming the first GAA FET in a first layer on a first oxide layer on a first substrate, Forming the second GAA FET further includes forming the second GAA FET within a second layer on a second oxide layer on a second substrate. The method according to claim 11.

13. The first orientation is the (100) orientation, The second orientation is the (110) orientation. The method according to claim 11.

14. Forming a bonding layer on one of the first layer and the second layer, Laminating the second layer on the first layer, The method according to claim 12, further comprising:

15. The method according to claim 14, further comprising forming vias that extend through the bonding layer and connect the first gate structure to the second gate structure.

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