High-Voltage III-n Devices and Structures with Reduced Current Degradation

Abstract

Horizontal III-N devices such as AlGaN / GaN HEMTs can have structures that help improve performance and reduce current degradation. The III-N device can include a conductive substrate and a III-N material structure including a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, with a composition difference inducing a 2DEG channel therein. A first portion is in ohmic contact with the 2DEG channel, and a second portion extends above the upper surface of the III-N barrier layer and is in direct contact with the upper surface of the III-N barrier layer. The device further has a drain-substrate pinch-off voltage and a maximum rated drain-source operating voltage greater than the drain-substrate pinch-off voltage, and when the III-N device is biased above the maximum rated drain-source operating voltage, the charge below the second portion of the drain electrode is completely depleted in the 2DEG channel.

Description

Technical Field

[0001] The disclosed technology relates to semiconductor devices, particularly group-III nitride transistors and switches.

Background Art

[0002] Currently, typical power semiconductor devices including devices such as transistors, diodes, power MOSFETs, and insulated gate bipolar transistors (IGBTs) are manufactured using silicon (Si) semiconductor materials. More recently, wide bandgap materials (SiC, III-N, III-O, diamond) have been considered as power devices due to their excellent properties. Group-III nitride or III-N semiconductor devices such as gallium nitride (GaN) devices or AlGaN / GaN HEMT transistors have emerged as attractive candidates for carrying high currents, supporting high voltages, and providing very low on-resistance and fast switching times.

[0003] Although high-voltage GaN HEMT transistors have begun to be commercialized, it has been found that the design and manufacture of III-N transistors with high performance figures of merit have been difficult so far. To accelerate market adoption, design improvements are needed to improve the device size, efficiency, reliability, and output characteristics.

Summary of the Invention

[0004] This specification describes lateral III-N devices such as AlGaN / GaN HEMTs having a structure that functions to improve performance and reduce current degradation.

[0005] In a first aspect, a III-N device is described. The III-N device can include a conductive substrate and a III-N material structure. The III-N material structure includes a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, and a composition difference therein induces a 2DEG channel. The device further includes a source electrode, a gate electrode electrically connected to the conductive substrate, and a drain electrode, and the drain electrode includes a first portion and a second portion. The first portion makes an ohmic contact with the 2DEG channel, and the second portion extends across the upper surface of the III-N barrier layer and is in direct contact with the upper surface of the III-N barrier layer. The device further includes a drain-substrate pinch-off voltage and a maximum rated drain-source operating voltage, and the maximum rated drain-source operating voltage is greater than the drain-substrate pinch-off voltage, and when the III-N device is biased at or above the maximum rated drain-source operating voltage, the charge below the second portion of the drain electrode is completely depleted in the 2DEG channel.

[0006] In a second aspect, a III-N device is described. The device includes a conductive substrate and a III-N material structure. The III-N material structure includes a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, and a composition difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein. The device further includes a source, a gate, and a drain electrode, and the drain comprises a first portion and a second portion. The first portion of the drain electrode makes an ohmic contact with the 2DEG channel, and the second portion of the drain electrode extends on and makes direct contact with the upper surface of the III-N barrier layer. The III-N device has a drain-substrate pinch-off voltage and a maximum rated drain-source operating voltage, and the maximum rated drain-source operating voltage is at least 50 V greater than the drain-substrate pinch-off voltage. The device has a first on-state resistance when the drain-source voltage is held constant at a low voltage, and the device has a second on-state resistance when the drain-substrate voltage is swept from a low voltage to the maximum rated drain-source voltage, held at said voltage for at least 2 minutes, and swept back to the low voltage, and the first on-state resistance is within 25% of the second on-state resistance.

[0007] In a third aspect, a III-N device is described. The device includes a conductive substrate and a III-N material structure. The III-N material structure includes a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, and a composition difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein. The III-N buffer layer includes at least five separate layers that continuously increase from a first side of the III-N buffer layer adjacent to the substrate to a second side of the III-N buffer layer adjacent to the III-N channel layer. The first layer is an AlN nucleation layer, and the second layer is Al X Ga 1-X N, where 70% < x < 90% and the thickness is 0.2 μm to 1.0 μm, the third layer is Al X Ga 1-X N, where 40% < x < 70% and the thickness is 0.2 μm to 1.0 μm, the fourth layer has a thickness of 0.5 μm to 1.5 μm, and AlN / Al X Ga1-X Including N-layer repetitions, the AlN layer has a thickness of 0.5 nm to 5 nm, and Al X Ga 1-X The N layer has a thickness of 10 nm to 50 nm, 5% < x < 20%, and the fifth layer has a thickness of 0.5 μm to 1.5 μm. The device has a source electrode, a gate electrode, and a drain electrode. The gate electrode is electrically connected to the conductive substrate. When the III-N device is biased at the maximum rated drain-source operating voltage, the 2DEG channel is not completely depleted of charge.

[0008] Each of the electronic devices, transistors, and methods described herein can include one or more of the following features. The device has a maximum rated drain-source operating voltage exceeding 600 V and a drain-substrate pinch-off voltage less than 600 V, or the device has a maximum rated drain-source operating voltage of at least 650 V and a drain-substrate pinch-off voltage of 600 V or less. When the III-N device is biased at the maximum rated drain-source pinch-off voltage, the 2DEG channel is completely depleted of charge below the second portion of the drain electrode. The device does not intentionally include any dielectric or insulating material between the drain electrode and the III-N material structure. The device can include a gate dielectric layer formed between the upper surface of the III-N barrier layer and the gate electrode. The gate dielectric layer includes a first end extending toward the drain electrode and a second end extending toward the source electrode. The separation between the first end and the drain electrode is 0.1 μm to 2 μm, and the separation portion is filled with an insulating material having a composition different from that of the gate dielectric layer. The source electrode includes a first portion and a second portion. The first portion makes an ohmic contact with the 2DEG channel, and the second portion extends on the upper surface of the III-N barrier layer and is in direct contact with the upper surface. When the drain-source voltage is at the maximum rated operating voltage, the 2DEG channel under the second portion of the drain electrode is depleted by the vertical electric field between the drain electrode and the conductive substrate. The I of the first ON-state resistance DS is the I of the second ON-state resistance DSIt is within 20% of. The III-N material structure has a thickness of less than 6 μm, and the III-N material structure has a breakdown voltage exceeding 750 V. The III-N material structure is formed on a conductive silicon substrate, and the first surface of the III-N buffer layer is adjacent to the conductive silicon substrate.

[0009] As used herein, the terms III-nitride or group-III N material, layer, device, etc. refer to a material or device composed of a compound semiconductor material of the chemical formula B w Al x In y Ga z N, where w + x + y + z is approximately 1, 0 ≤ w ≤ 1, 0 ≤ x ≤ 1, 0 ≤ y ≤ 1, and 0 ≤ z ≤ 1. The III-N material, layer, or device can be formed or prepared by any of directly growing on a suitable substrate (e.g., by metalorganic chemical vapor deposition), growing on a suitable substrate, peeling from the original substrate, and bonding to another substrate.

[0010] As used herein, two or more contacts or other items, such as a conductive channel or component, are said to be "electrically connected" when they are connected by a material that is sufficiently conductive to ensure that the potential at each of the contacts or other items is the same, e.g., always substantially the same under any bias conditions.

[0011] As used herein, "blocking voltage" refers to the ability of a transistor, device, or component to prevent a significant current, such as a current exceeding 0.001 times the operating current during normal conduction, from flowing through the transistor, device, or component when a voltage is applied across the two ends of the transistor, device, or component. In other words, when the transistor, device, or component is blocking the voltage applied thereto, the total current passing through the transistor, device, or component does not exceed 0.001 times the operating current during normal conduction. Devices having an off-current greater than this value exhibit high losses and low efficiency and are typically not suitable for many applications, particularly power switching applications.

[0012] As used herein, "depletion mode device" refers to a transistor having a negative threshold voltage and considered to be in the "on" state when the gate of the depletion mode transistor is biased at a voltage greater than the negative threshold voltage, such that the device turns on when the gate is biased at zero volts. "Enhancement mode device" refers to a transistor having a positive threshold voltage and considered to be in the "off" state when the gate of the enhancement mode transistor is biased at zero volts. The "on-resistance" of a transistor refers to the resistance between the source contact and the drain contact of the transistor when the transistor is biased in the on state (i.e., R DS(ON) ). As used herein, the on-resistance is measured when the device is considered to be in the saturation mode.

[0013] As used herein, "high voltage device", such as a high voltage switching transistor, HEMT, bidirectional switch, or four quadrant switch (FQS), is an electronic device optimized for high voltage applications. That is, when the device is off, it is capable of blocking a high voltage, such as about 300 V or more, about 600 V or more, or about 1200 V or more, and when the device is on, it has a sufficiently low on-resistance (R ON) and has, for example, a sufficiently low conduction loss when a substantial current passes through the device. A high-voltage device can at least block a voltage equal to the high-voltage source or the maximum voltage in the circuit in which it is used. A high-voltage device can block 300V, 600V, 1200V, 1700V, 2500V, 3300V, or other suitable blocking voltages required by the application. In other words, a high-voltage device can block all voltages between 0V and at least V max and, where V max is the highest voltage that can be supplied by the circuit or power source, and V max is, for example, 300V, 600V, 1200V, 1700V, 2500V, 3300V, or other suitable blocking voltages required by the application. In the case of a bidirectional switch or a four-quadrant switch, the blocked voltage is of any polarity less than a certain maximum value when the switch is off (±V max , for example, ±300V or ±600V, ±1200V, etc.), and the current is in either direction when the switch is on.

[0014] As used herein, an electrode refers to a metal layer within a device or transistor that is connected to either the source, gate, or drain of the device. A "pad" such as a "source pad, drain pad, or gate pad" refers to the uppermost non-passivated portion of an electrode that is used to electrically connect a device or transistor to a package, for example, using solder, epoxy resin, wire bonding, and / or metal clips.

[0015] As used herein, an “III-N device” is a device based on or essentially comprising III-N material including an III-N heterostructure. The III-N device can be designed to operate as a transistor or switch whose state is controlled by a gate terminal, or as a two-terminal device that blocks current in one direction and conducts in the other direction without a gate terminal. The III-N device can be a high-voltage device suitable for high-voltage applications. In such a high-voltage device, when the device is biased off (e.g., when the voltage on the gate relative to the source is less than the device threshold voltage), the device can support at least all source-drain voltages below the high voltage in the application for which the device is used, such as 100V, 300V, 600V, 1200V, 1700V, 2500V, or more. When the high-voltage device is biased (e.g., when the voltage on the gate relative to the source or the associated power terminal is greater than the device threshold voltage), the high-voltage device can conduct a substantial current at a low on-voltage (i.e., a low voltage between the source and drain terminals or between opposite power terminals). The maximum allowable on-voltage is the maximum on-state voltage that can be maintained in the application for which the device is used.

[0016] As used herein, a “III-polarity” or “Group-III-polarity” III-N material is a III-N material in which the Group-III plane (i.e., the

[0001] plane) is on the side opposite to the substrate on which the material is grown. In a “III-polarity” or “Group-III-polarity” lateral III-N device, at least some of the device contacts (e.g., source and / or drain contacts) are typically formed on the

[0001] side of the III-N material (e.g., on the side opposite to the [000-1] plane).

[0017] As used herein, a "N-polarity" III-N material is a III-N material in which the nitrogen plane (i.e., the [000-1] plane) is on the side opposite to the substrate on which the material grows. In a "N-polarity" lateral III-N device, at least some of the device contacts (e.g., source and / or drain contacts) are typically formed on the [000-1] plane of the III-N material (e.g., on the side opposite to the

[0001] plane).

[0018] As used herein, a "regrown" III-N layer structure or III-N material structure refers to an additional material film-forming method that is performed after a previous material film-forming method. Between the subsequent growth process and the regrowth process, the device can be removed from the deposition tool and the vacuum environment can be interrupted. Thus, a regrown III-N material structure may require a separate insertion of the III-N material structure into the deposition apparatus from the initial insertion of the III-N material structure. For example, a regrown III-N layer can be deposited after removal of at least a portion of the initial III-N material structure. Removal of a portion of the initial III-N material structure is typically performed in an environment external to the primary III-N material structure deposition apparatus.

[0019] As used herein, the terms "above", "below", "between", and "on" refer to the relative position of one layer with respect to another layer. Thus, for example, one layer disposed above or below another layer may or may not be in direct contact with the other layer and may have one or more intervening layers. Further, one layer disposed between two layers may or may not be in direct contact with the two layers and may have one or more intervening layers. In contrast, a first layer that is "on" a second layer is in contact with that second layer. Additionally, the relative position of one layer with respect to another layer is provided assuming that operations are performed with respect to the substrate without considering the absolute orientation of the substrate.

[0020] The details of one or more disclosed implementations of the subject matter described in this specification are set forth in the accompanying drawings and the description below. Additional features and modifications may also be included within the implementations. Other features, aspects, and advantages will be apparent from the description, drawings, and claims.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0037] This specification describes lateral III-N devices such as AlGaN / GaN HEMTs. These devices have a structure that serves to improve performance and reduce current degradation, particularly when the device operates at or near the maximum rated voltage of the device. III-N power devices can have superior performance compared to their silicon counterparts due to the very high conductivity of the two-dimensional electron gas (2DEG) channel inherent in lateral III-N devices such as AlGaN / GaN HEMT devices. However, the performance and reliability of these devices can be further improved by eliminating or reducing a phenomenon known as current collapse during power switching operation. Current collapse can be caused by electron traps that can occur within / on the device layer or be embedded within the III-N material structure. When the gate of the device is biased in the off state, electrons can be trapped. These trapped electrons cannot be rapidly removed when the gate voltage rapidly changes to the on state. These trapped electrons deplete an equal portion of the 2DEG channel charge. This increases the device channel on-state resistance under switching conditions and an overall reduction in the current level is observed.

[0038] A cross-sectional view of a high-voltage III-N device 101, such as an AlGaN / GaN HEMT device, is shown in FIG. 1A. The III-N device 101 can be an enhancement-mode device (i.e., normally off) or a depletion-mode device (i.e., normally on). When the device 101 is a depletion-mode device (D-mode), the device 101 can be configured in a cascode configuration having a low-voltage enhancement-mode device 21 (e.g., a silicon FET) to form a normally-off hybrid device 100 that can operate in a manner similar to a single enhancement-mode III-N device.

[0039] The III-N device 101 of FIG. 1A includes a III-N material structure 20 grown on a suitable substrate 10, which is a conductive semiconductor such as silicon (e.g., p-type or n-type Si), GaN, or any other sufficiently conductive substrate, for example, a combination of GaN and AlGaN. For example, the substrate can be doped p-type with a hole concentration exceeding 1×10 19 holes / cm 3 , or the substrate can be doped n-type with an electron concentration exceeding 1×10 19 electrons / cm -3 . The substrate can have a high or low thermal conductivity. In the case of a substrate with low thermal conductivity, the substrate can be thinned to improve heat dissipation. The substrate can have a lattice constant and / or a coefficient of thermal expansion that is the same as or different from that of any material layer of the III-N material structure 20.

[0040] The III-N material structure 20 can include a III-N buffer layer 11 grown on the substrate 10, for example, GaN or AlGaN. The buffer layer 11 can be made insulating by including dislocations or point defects in the layer, or by doping the layer with compensating elements such as Fe, C, and / or Mg, or can be made substantially free of unintentional n-type mobile carriers. The buffer layer can have a substantially uniform composition throughout, or the composition can vary. For example, in some embodiments, the buffer layer is compositionally graded, such as by grading the aluminum composition in the buffer layer (e.g., the substrate is Al x G 1-x(which can be N). In other embodiments, the buffer layer is formed from a "superlattice" structure including alternating layers of GaN and Al(x)Ga(1-x)N. The thickness and composition of the buffer layer 11 can be optimized for high-voltage applications. That is, the buffer layer can block a high-voltage source or a voltage above the maximum voltage in the circuit to which it is supplied. For example, the buffer layer 11 can block a vertical voltage exceeding 600V, 900V, 1200V between the drain electrode 17 and the substrate 10. The thickness of the buffer layer 10 can exceed 4μm. For example, the III-N buffer layer can have a thickness of 5μm to 8μm.

[0041] The III-N material structure can further include a III-N channel layer 12 (e.g., GaN) on the III-N buffer layer 11 and a III-N barrier layer 13 (e.g., AlGaN, AlInN, or AlGaInN) on the III-N channel layer 12. The bandgap of the III-N barrier layer 13 is larger than the bandgap of the III-N channel layer 12. The III-N channel layer 12 has a different composition from the III-N barrier layer 13, and the thickness and composition of the III-N barrier layer 12 are selected such that a two-dimensional electron gas (2DEG) channel 19 (shown by a dashed line in FIG. 1A) is induced in the III-N channel layer 12 adjacent to the interface between the layer 13 and the layer 12. When the device 101 is a depletion-mode device, when a zero-voltage bias is applied to the device, the 2DEG channel 19 extends continuously between the source electrode 16 and the drain electrode 17. The III-N barrier layer 13 can have a first side and a second side, the first side being adjacent to the III-N channel layer 12 and the second side being opposite to the first side.

[0042] Typically, a III-N high electron mobility transistor (HEMT) is formed from an epitaxial (i.e., epi) III-N material structure grown in a reactor by molecular beam epitaxy (MBE) or metalorganic chemical vapor deposition (MOCVD) or by other techniques. The III-N material structure can be grown in a group III polar (e.g., gas polar) orientation such as the

[0001] (C-plane) orientation as shown in FIG. 1A. That is, the source, gate, and drain electrodes of the HEMT are formed on the group III plane (e.g., the

[0001] plane) of the III-N material structure, which is typically on the opposite side of the III-N material structure as seen from the substrate on which the III-N layer is formed.

[0043] Alternatively, the III-N HEMT can be formed on a III-N material structure grown in an N-polar (i.e., N-plane) orientation such as the [000-1] orientation. In this case, the source, gate, and drain electrodes of the HEMT are formed on the N-plane (e.g., the [000-1] plane) of the III-N material structure. Here, the III-N material structure can include a III-N barrier layer on a III-N buffer layer and a III-N channel layer on the III-N barrier layer 13. The bandgap of the III-N barrier layer 13 is larger than the bandgap of the III-N channel layer 12, and the thickness and composition of the III-N barrier layer 13 are selected such that a two-dimensional electron gas (2DEG) channel 19 is induced in the III-N channel layer 12 adjacent to the interface between the III-N channel layer 12 and the III-N barrier layer 13. The N-polar III-N material has a polarization field in the opposite direction to the group III polar III-N material and can thus enable the implementation of III-N devices that cannot be fabricated using group III polar structures.

[0044] The gate dielectric layer 14 is grown or deposited on the upper surface of the III-N material structure 20 and is formed in direct contact with the second surface of the III-N barrier layer 14. The gate dielectric 14 is, for example, aluminum oxide (Al2O3), silicon dioxide (SiO2), Si x N y 、Al 1-x Si x N、Al1-x Si x O, Al 1-x Si x It can be formed from or can include ON, or any other wide bandgap insulator.

[0045] The source electrode 16 and the drain electrode 17 are formed on the side opposite to the substrate 10 of the device 101, whereby the device 101 is characterized as a lateral III-N device (i.e., the source and the drain are on the same side of the device, and the current flows laterally through the device between the source 16 and the drain 17). The source electrode 16 and the drain electrode 17 are in ohmic contact and are electrically connected to the device 2DEG channel 19 formed in the layer 12. The source and drain electrodes 16, 17, for example, the source and drain electrodes, can be formed by a metal stack. A recess can be formed in the III-N barrier layer 13 to enable an improved ohmic contact between the source electrode 16 and the drain electrode 17 and the 2DEG channel 19. The metal stack can be Ti / Al / Ni / Au, Ti / Al, or other suitable metals. The source and drain electrodes 16, 17 can be formed by sputtering and dry etching methods, or other techniques such as metal evaporation and annealing after film formation.

[0046] The insulating layer 15 can be formed on the gate dielectric layer 14 shown as a single layer. Alternatively, it can be formed from several layers deposited during different processing steps to form a single composite insulator layer 15. The insulating layer 15 can be formed from SiN, SiON, SiO2, or other suitable insulating materials.

[0047]

[0048] Within the insulating layer 15, a gate recess is formed to expose the upper surface of the gate insulating layer 14. The gate electrode 18 (for example, a gate contact) can be formed at least partially within the recess where a portion 18a of the gate electrode 18 is in direct contact with the upper surface of the gate dielectric layer 14. The gate recess can have a plurality of steps extending towards the drain electrode 17 where the gate metal is formed on the steps to form the field plate 18b; the field plate 18b is vertically separated from the gate dielectric layer 14 by a portion of the insulating layer 15, for example, a stepped portion. The field plate 18b can help manage the electric field within the drain side access region. Effective electric field management may require a plurality of field plates. For example, the field plate 18b includes at least three different step heights (i.e., FP1, FP2, FP3), each increasing in height as the field plate extends towards the drain 17. The gate electrode 18 can be formed from a metal stack, for example, a suitable conductive material such as titanium / aluminum (Ti / Al) or nickel / gold (Ni / Au), and can be deposited by metal evaporation or sputtering or chemical vapor deposition or various atomic layer depositions (ALD). Alternatively, the gate electrode 18 can be another conductive material or material stack including one or more materials with a high work function, such as a semiconductor material with a high work function (e.g., p-type polysilicon, indium tin oxide, tungsten nitride, indium nitride, or titanium nitride).

[0049] When the device 101 is a depletion mode device, the dielectric layer 14 is formed between the gate electrode 18 and the III-N barrier layer 13. The thickness of the dielectric layer 14 determines the threshold voltage of the device (i.e., V TH ) such that as the thickness of the dielectric layer 14 increases, the threshold voltage of the device 101 becomes more negative. Alternatively, the gate recess can extend through the gate dielectric layer 14 such that the gate electrode 18 contacts or recesses within the III-N material structure 24 (not shown) to create an enhancement mode device.

[0050] As described above, when device 101 is a depletion mode device, it can be arranged in a cascode configuration with a low voltage enhancement mode FET device 21 to form a hybrid device 100. The hybrid device 100 can be arranged and assembled into an individual electronic component package 102. The electronic component package 102 can have at least three terminals. The first terminal 25 is electrically connected to the drain electrode 17. The second terminal 23 is electrically connected to the source of the FET element 21 and the gate electrode 18 of the element 101. The third terminal 22 of the device is electrically connected to the gate of the FET device 21.

[0051] The source electrode 16 and the drain electrode 17 can be formed on the III-N device 101 by various techniques. One common method is to deposit a continuous layer of ohmic metal (e.g., by sputter deposition) on the upper surface of the device 101. Next, the ohmic metal layer is patterned with photoresist to cover and protect the source and drain electrode areas, and the remaining unprotected metal layer is etched away (e.g., by a dry etching process) to form the source and drain electrodes 16 and 17.

[0052] Due to the tolerances of photolithography and the limitations in etching techniques, typically, the extended portions of the source and drain electrodes remain above the gate dielectric layer 14 and / or the insulating layer 15. As seen in FIG. 1A, the extended drain electrode portion 17' extends towards the gate electrode 18 into the drain-side access region 27, and the extended source electrode portion 16' extends towards the gate electrode 18 into the source-side access region 26. In the case of power devices typically fabricated in a conventional CMOS fab, the extended portions 16' and 17' can be in the range of 0.25 μm to 1 μm in length (along the channel length). As shown in FIG. 1A, between the drain electrode extension 17' and the III-N barrier layer 12, a part of the gate dielectric layer 14 and a part of the insulating layer 15 are formed. Also, between the source electrode extension 16' and the III-N barrier layer 12, a part of the gate dielectric layer 14 and a part of the insulating layer 15 are formed.

[0053] In some configurations, a portion of the insulating layer 15 may not need to be present under the extended electrode portions 16' or 17'. In such a configuration, the bottom surface of the extended portion can be in direct contact with the top surface of the dielectric layer 14. For example, when the dielectric layer 14 is formed by in-situ MOCVD SiN, the thickness of the SiN under the drain overhang 17' is approximately equal to the thickness of the MOCVD SiN layer 14. However, maintaining the high integrity of the MOCVD SiN layer is an important factor in device performance. One way to maintain the integrity of the gate dielectric is to deposit a sacrificial etch-stop SiN layer on the gate dielectric layer 14. One manufacturing technique is to use an etch-stop layer that is approximately equal to the step height of the first field plate (i.e., FP1) of the multiple field plate system 18b. In this scenario, the thickness of the portion of the insulating layer 15 and the dielectric layer 14 under the drain overhang 17' is approximately equal to the thickness of the SiN under FP1 plus the thickness of the gate dielectric 14. The thickness of the portion of the insulating layer 15 and the dielectric layer 14 under the drain overhang 17' can be 200 nm, 100 nm or less.

[0054] For the purposes of this specification, the source-side access region 26 is defined as the region measured in the plane of the upper surface of the dielectric layer 14 between the portion of the source electrode 16 that contacts the 2DEG channel 19 and the portion of the gate electrode 18a that contacts the gate dielectric layer 14, as shown in FIG. 1A. Similarly, the drain-side access region 27 is defined as the region measured in the plane of the upper surface of the dielectric layer 14 between the portion of the gate electrode 18a that contacts the gate dielectric layer and the portion of the drain electrode 17 that contacts the 2DEG channel 19, as shown in FIG. 1A.

[0055] Referring to FIG. 1B, when the III-N device 101 is a depletion-mode device, the gate electrode 18 and the substrate 10 are electrically connected to circuit ground. The source electrode 16 is biased above the gate-source threshold (V TH ) of the III-N device 101, the 2DEG channel 19 is depleted, and a depletion layer 19a is formed under the gate electrode 18. The 2DEG channel 19 is no longer continuous between the source electrode 16 and the drain electrode 17, and the device is considered to be "off". When a positive drain-source voltage (i.e., V DS ) is applied and the drain-source voltage is further increased, the 2DEG channel 19 is further depleted in the drain-side access region 27. As seen in FIG. 1B, a portion 19' of the 2DEG channel can remain within the drain-side access region 27 proximal to the drain electrode 17, and a portion 19'' can remain within the source-side access region 26 proximal to the source electrode 16.

[0056] When the drain-source voltage is high enough, the 2DEG channel is fully depleted, i.e., the depletion region 19a reaches the drain electrode. The drain voltage at which the 2DEG is fully depleted depends on at least three of the following factors: (1) the higher the 2DEG charge density, the higher the drain voltage required to reach full depletion; (2) the accumulation of the lateral electric field due to the capacitive coupling between the drain electrode 17 and the gate electrode 18 determined by the field plate 18’ design, and the length of the drain-side access region 27; (3) the accumulation of the longitudinal electric field due to the capacitive coupling between the drain electrode 17 and the conductive substrate 10, a phenomenon hereinafter referred to as “back-gating”. The amount of 2DEG depletion caused by the back-gating effect is determined by the applied drain-substrate potential (V D-SUB ), the thickness and resistivity uniformity of the III-N buffer layer 11. For a given applied V D-SUB and a given thickness of the III-N buffer layer 11, the back-gating effect is stronger. That is, when the lower part of the III-N buffer layer 11 is less insulating and has a lower resistance than the upper part of the III-N buffer layer 11, more 2DEG depletion occurs. In this case, charge redistribution occurs within the III-N buffer layer 11, and the stronger capacitive coupling between the drain electrode 17 and the substrate 10 results in more 2DEG depletion for a given applied V D-SUB . This effect is known in the literature as the Maxwell-Wagner effect (see Digital Object Identifier 10.1109 / TED.2017.2706090 and Digital Object Identifier 10.1109 / TED.2006.877700). The drain-substrate voltage (V D-SUB ) at which the 2DEG is fully depleted is then referred to as the drain-substrate pinch-off voltage (V D-SUBpinch-off ).

[0057] The drain-substrate pinch-off voltage (V D-SUBpinch-off ) is the maximum rated source-drain operating voltage (V TR(DSS)When the III-N device 101 (specifically, the III-N buffer layer 11) is designed to be less than V DS and V D-SUBpinch-off is biased at a voltage greater than V, the 2DEG channels 19 / 19' (shown in FIG. 1B) are completely depleted up to the drain electrode 17. V TR(DSS is V D-SUBpinch-off can be made 50 V or more higher than V. When this operating condition occurs (see FIG. 1C), the dielectric layer 14 and the insulating layer 15 are forward-biased, and negative charges 28 are injected into the dielectric layer 14 and / or the insulating layer 15 under the drain electrode extension 17' as shown in the dashed region 30. A portion of the negative charges 28 is "trapped" within the insulating layer and is not easily removed. Next, when the III-N device 101 is switched "on", the 2DEG channel charge under the extension 17' decreases, and the on-resistance of the device 101 increases overall. Significant current collapse can be observed under high-voltage switching operations at or near the maximum drain-source voltage rating of the device.

[0058] A possible solution to prevent complete 2DEG depletion (pinch-off) and to mitigate charge trapping under the drain electrode extension 17' is to increase the 2DEG charge density. However, this solution causes other reliability issues related to the increased electric field due to the higher 2DEG charge, and can cause premature failure of the gate electrode 18 during operation over time. Thus, other solutions may be desirable.

[0059] Figure 2A shows a cross-sectional view of a III-N device 201 similar to the III-N device 101 of Figure 1A. The III-N device 201 can be an enhancement-mode device (i.e., normally-off) or a depletion-mode device (i.e., normally-on). When the device 201 is a depletion-mode device (D-mode), the device 201 can be configured in a cascode configuration having a low-voltage enhancement-mode device 21 (e.g., a silicon FET), forming a normally-off hybrid device 200 that can operate in a manner similar to a single enhancement-mode III-N device.

[0060] The III-N device 201 of Figure 2A includes a III-N buffer structure 220 in which the III-N device 201 is designed, and is different from the III-N device 101 of Figure 1A in that the drain-substrate pinch-off voltage is made larger than the maximum rated operating voltage of the device. The engineered III-N buffer structure 220 can include a nucleation layer 221 such as AlN grown at low temperature, high temperature, or a stack thereof. The III-N buffer structure 220 can, in the future, include a high aluminum composition III-N layer 222 (such as Al 80% Ga 20% N, etc.) and a medium aluminum composition III-N layer 223 (such as Al 60% Ga 40% N, etc.). For example, the layer 222 can have an Al X Ga 1-X N ratio of 70% < x < 90%, and the layer 223 can have an Al X Ga 1-X N ratio of 40% < x < 70%. The layers 222 and 223 can have a thickness of 0.2 μm to 1.0 μm. For example, the high aluminum composition III-N layer 222 can have a thickness of ~0.5 μm, and the medium aluminum composition III-N layer 223 can have a thickness of ~0.6 μm. The III-N buffer structure 220 can further include a III-N stack 224 / 225, and the stack 224 / 225 is AlN / GaN, AlN / Al x Ga 1-x N, or Al x Ga 1-xIt is a structure including a repetitive stack of N / GaN or any combination thereof. For example, the III-stack 224 can have a thickness of 0.5 μm to 1.5 μm, and AlN / Al X Ga 1-X The repetition of the stack can be included, the AlN layer can have a thickness of 0.5 nm to 5 nm, and Al X Ga 1-X The N layer can have a thickness of 10 nm to 50 nm, and the x composition can be 5% to 20%. The III-N stack 225 can have a thickness of 0.5 μm to 1.5 μm, can include the repetition of the AlN / GaN stack, the AlN layer can have a thickness of 0.5 nm to 5 nm, and the GaN layer can have a thickness of 10 nm to 50 nm. The III-N stack 224 / 225 is AlN / GaN, AlN / Al x Ga 1-X N, or Al x Ga 1-X In order to prevent the generation of parasitic 2DEG and 2DHG at the interface between the AlN / GaN layers, it can be doped with iron, carbon, or other deep donor or deep acceptor agents.

[0061] The designed III-N buffer structure 220 can increase the drain-substrate pinch-off voltage compared to the standard III-N buffer layer 11 described in FIG. 1A. For example, the drain-substrate pinch-off voltage can be greater than 750 V, and the maximum rated drain-source operating voltage can be less than 750 V. The implementation of the buffer structure 220 prevents the overall depletion of the 2DEG channel 19' in the region under the drain electrode extension 17', and can prevent the forward bias of the gate dielectric layer 14 and / or the insulating layer 15 to reduce negative charge trapping and current degradation. The designed III-N buffer structure 220 can have a thickness of less than 6 μm. The designed III-N material structure can have a breakdown voltage exceeding 750 V.

[0062] As shown in FIG. 2B, the influence of 2DEG depletion and current collapse due to the back gate effect can be measured, and then a test circuit can be used to capture electrons in the dielectric layer 14 and / or the insulating layer 15 under the drain electrode extension 17'. A simplified circuit diagram 210 (not shown in FIG. 2B for simplicity) that does not require connecting the gate electrode 18 is used. Also, for simplicity, the designed III-N buffer structure 220 is not shown. The drain-source potential is set to a low voltage (e.g., 1V), the first drain-source current is measured, and the first on-resistance is calculated. The magnitude of the drain-source current gives an indication of the 2DEG channel density. The voltage between the drain electrode 17 and the substrate 10 is swept (sweep1) from 0V to the maximum drain-source operating voltage (V TR(DSS) ) of the device, while the current between the drain and the source is measured (I DS ). The speed of the voltage sweep can be greater than 1V / s. Since V DS is held constant, the voltage of the substrate 10 is swept to a negative value with respect to the voltage of the drain electrode 17 to increase the drain-substrate potential during the test. The drain-substrate voltage can be held at V TR(DSS) for at least 2 minutes. This holding time is for ensuring sufficient operating stress on the device. Next, the substrate voltage is swept (sweep2) to 0V, the second drain-source current is measured, and the second on-state resistance is calculated. For the purposes of this specification, it is assumed that the first drain-source current measurement and the second drain-source current measurement are completed within 1 hour of each other.

[0063] FIGS. 2C and 2D show graph data comparing the measurement results of actual back-gating measurements between a device manufactured according to the device 101 of FIG. 1A and a device manufactured according to the device 201 of FIG. 2A. Specifically, referring to FIG. 2C, the drain-substrate voltage gradually increases (forward sweep 250) from 0V to the maximum rated voltage 252 (V TR(DSS) = e.g., 725 V), and V TR(DSS)It gradually decreases from 0 V (reverse sweep 251). The drain-source current is recorded during both the forward sweep 250 and the reverse sweep 251. During the forward sweep 250, the drain-source current reaches 0 A near 600 V, and before V D-SUB reaches V TR(DSS) , it shows back-gating pinch-off 253 and complete 2DEG depletion. This situation results in a forward bias of the dielectric layer 14 and the insulating layer 15 under the drain electrode extension 17, as well as charge trapping in the dielectric layer 14 and / or the insulating layer 15 under the drain electrode extension 17', leading to severe current degradation as observed in the reverse sweep 251. As seen in Figure 2C, the starting Id is ~0.05 A / mm and the ending Id is ~0.015 A / mm, indicating a current reduction of more than 50% and an on-state resistance increase of more than 100%.

[0064] Figure 2D shows the back-gating test results of a device fabricated according to the designed III-N buffer structure 220 of device 201. As seen in Figure 2D, when the voltage sweep reaches 252, the 2DEG is not completely depleted, as indicated by a current >0 A (V D-SUBpinch-off >V TR(DSS) ). The charge trapping mechanism is prevented, and substantially no current degradation is observed in device 201. However, a designed III-N buffer structure such as structure 220 can be costly and time-consuming to develop. In addition, a designed III-N buffer structure such as structure 220 does not prevent the charge trapping problem under the drain electrode extension 17' when the 2DEG is completely depleted due to the accumulation of a lateral electric field caused by capacitive coupling between the drain electrode 17 and the gate electrode 18. This scenario can occur in devices with an aggressive design having a highly scaled gate-drain side access region 27 aimed at reducing a specific on-state resistance and the overall chip size. Therefore, other solutions may be desirable.

[0065] Figure 2E shows box plot data of additional test results indicating the performance of devices manufactured according to device 201. Figure 2E shows the increase in on-resistance (i.e., Ron) over time for a specific stress test. Devices manufactured according to device 201 were subjected to a high temperature reverse bias (i.e., HTRB) test. The test conditions were as follows: while the gate-source voltage was biased below the threshold voltage, the source-drain voltage was biased at 750V; the temperature was maintained at 175°C; the voltage was held for 1,000 hours. The test was conducted as follows. The on-resistance of the device was measured before HRB (time = 0), then the HTRB stress was executed, and the on-resistance of the device was measured again at 250-hour, 500-hour, and 1,000-hour intervals. The on-resistance (Ron) is plotted in Figure 2E. As seen in Figure 2E, the median increase in the on-resistance of the device at time 0 is ~30 mΩ. After 250 hours of HTRB stress, the median on-resistance increases but remains less than 35 mΩ and less than a 20% increase in on-resistance. After 500 hours and 1,000 hours of stress respectively, the median on-resistance remains less than 35 mΩ, and all of the tested devices had an on-resistance increase of less than 20% after HTRB stress under the aforementioned conditions. These results demonstrate the effectiveness of the present invention.

[0066] Figure 3A shows a cross-sectional view of a III-N device 301 similar to the III-N device 101 of Figure 1A. The III-N device 301 can be an enhancement mode device (i.e., normally off) or a depletion mode device (i.e., normally on). When device 301 is a depletion mode device (D mode), device 301 can be configured in a cascode configuration having a low voltage enhancement mode device 21 (e.g., a silicon FET) to form a normally off hybrid device 300 that can operate in a manner similar to a single enhancement mode III-N device.

[0067] The III-N device 301 in FIG. 3A is different from the III-N device 101 in FIG. 1A in that the III-N device 301 does not include a gate dielectric layer 14 and / or an insulating layer 15 formed under the drain electrode extension portion 17' as shown in the dashed region 30. Instead, the drain electrode extension 17' is formed "above" the second side of the III-N barrier layer 13 and is in direct contact. Further, the III-N device 301 may optionally not include a gate dielectric layer 14 and / or an insulating layer 15 formed under the source electrode extension portion 16'. Instead, the source electrode extension 16' is formed in direct contact on the second surface of the III-N barrier layer 13. By removing the gate dielectric layer 14 and / or the insulating layer 15 below the extensions 16' / 17', negative charges are no longer trapped, thereby eliminating or reducing current degradation. Since there is no insulating material that causes charge trapping in FIG. 1A, the 2DEG channel can be completely depleted by the substrate up to the drain electrode without causing current degradation. Therefore, a device having a substrate-drain pinch-off voltage lower than the maximum operating voltage of the device can be manufactured without causing performance problems.

[0068] Although not shown for simplicity, the device 301 can also include a conductive intermediate layer formed between the drain and / or source extension portions 16' / 17' and the III-N barrier layer 13. The layer can be an etch stop layer to assist in the manufacturing process of the source and / or drain electrodes. The etch stop layer can have an etch rate smaller than the etch rate of the source and / or drain electrodes when etched under similar conditions. The etch stop layer should be a conductive material that allows a path for charges to move between the drain electrode and the III-N barrier layer. The etch stop layer can be, for example, TiN, TiW, Ni, or silicon (e.g., sputtered silicon). The etch stop layer can have a thickness of 5 nm to 100 nm. The etch stop layer can have a thickness of less than 100 nm.

[0069] Figure 3B shows the back-gating test results on device 301 having the modified drain electrode region 17'. The drain-substrate voltage is gradually increased from 0 V to the maximum rated voltage 352 (V TR(DSS) = for example 1100 V) (forward sweep 350), and gradually decreased from V TR(DSS) to 0 V (reverse sweep 351). The drain-source current is recorded during both the forward sweep 350 and the reverse sweep 351. During the forward sweep 350, the drain-source current reaches 0 A near 650 V, and shows a back-gating pinch-off 353 and complete 2DEG depletion until V D-SUB reaches V TR(DSS) . As seen in Figure 3B, V TR(DSS) 352 is more than 100 V away from V D-SUB 353. However, since there is no dielectric layer 14 and / or insulating layer 15 below the drain electrode extension 17', the charge trapping mechanism is prevented and the current degradation is significantly reduced. As seen in Figure 3B, the starting Id is ~0.155 A / mm and the ending Id is ~0.125 A / mm, which shows a current decrease of less than 20% and an on-state resistance increase of less than 25%. This result shows a significant improvement in performance compared to the result of device 101 shown in Figure 2C.

[0070] This result was unexpected. As described above, the drain electrode extension 17 is typically 0.5 μm in length and can be in the range of 0.25 μm to 1.0 μm. In a high-voltage III-N power device such as device 101, this represents less than 2% of the total source-drain spacing. At the time of the present invention, it was not clear that such a small overlapping area of the drain / insulator could contribute to such a large current degradation. However, the results shown in Figure 3B clearly show that the current collapse can be reduced.

[0071] Figure 3C shows a box plot of test results showing the performance benefits of devices manufactured according to device 301 of FIG. 3A as compared to devices manufactured according to device 100 of FIG. 1A. Figure 3C shows the rate of increase in on-resistance (i.e., Ron) after a specific stress test. Devices 301 and 100 were subjected to a high temperature reverse bias (i.e., HTRB) test. The test conditions were as follows: the source-drain voltage was biased to 750 V, the gate-source voltage was biased below the threshold voltage, the temperature was held at 175° C., and the voltage bias was held for 1,000 hours. The test was conducted as follows. The on-resistance of the device was measured before HTRB stress, then the HTRB test was performed, and the on-resistance of the device was measured again (post-HTRB). As seen in FIG. 3C, the median of the on-resistance increase of device 100 is greater than 70%. However, when device 301 was tested under the same conditions, the median of the on-resistance increase was less than 20%, and all of the devices showed a post-HTRB on-resistance increase of less than 30%. These results demonstrate the effectiveness of the present invention.

[0072] FIG. 4A shows a cross-sectional view of a III-N device 401 similar to the III-N device 301 of FIG. 3A. The III-N device 401 can be an enhancement mode device (i.e., normally off) or a depletion mode device (i.e., normally on). When the device 401 is a depletion mode device (D-mode), the device 401 can be configured in a cascode configuration with a low voltage enhancement mode device 21 (e.g., a silicon FET) to form a normally off hybrid device 400 that can operate in a manner similar to a single enhancement mode III-N device. The III-N device 401 differs from the III-N device 301 in that it includes an n-type III-N contact layer 40 formed under the drain electrode 17 and an n-type III-N contact layer 40' formed under the source electrode 16. The n-type III-N contact layers 40 / 40' can be formed by implantation or by regrowth using a dopant such as silicon. The source and drain electrodes 16 and 17 form an ohmic contact with the n-type III-N contact layers 40 / 40', which can be a high-quality ohmic contact having a very low electrical resistance. The length of the n-type contact layer 40 can be made longer than the length of the drain electrode 17 (both measured along the channel length). The n-type contact layer 40 can have a first portion that is immediately under the drain electrode 17 and makes an ohmic contact, and a second portion that extends into the drain side access region 27, thereby eliminating the presence of a drain electrode extension 17' within the device 401. When the n-type III-N contact layer 40 extends into the drain side access region and the drain electrode extension is eliminated, as shown in FIG. 4A, charge trapping near the drain electrode can be eliminated and current collapse can be reduced.

[0073] FIG. 4B shows a cross-sectional view of a III-N device 402 similar to the III-N device 101 of FIG. 1A. However, the III-N device 402 has a drain extension 17' and a source electrode extension 16'. The N-type III-N contact layer has a first end that extends into the drain-side access region 27 toward the gate electrode 18. The first end of the n-type III-N layer 40 extends into the drain-side access region beyond the drain electrode extension 17'. The first end of the n-type III-N layer 40' extends toward the gate 18 beyond the source electrode extension 16'. The 2DEG channel 19 extends between the first end of the n-type III-N layer 40' and the first end of the n-type III-N layer 40. Thus, a portion of the 2DEG channel 19 is not formed under either the source electrode extension 16' or the drain electrode extension 17'. As seen in FIG. 4B, the insulator layer 15 can be formed between the drain electrode extension 17' and the n-type III-N layer 40. Since the device design does not include the 2DEG channel under the extension, negative charges trapped in the insulator layer 15 under the portion 17' are prevented, and current degradation is prevented.

[0074] FIG. 5 shows a cross-sectional view of a III-N device 501 similar to the III-N device 101 of FIG. 1A. The III-N device 501 can be an enhancement-mode device (i.e., normally-off) or a depletion-mode device (i.e., normally-on). When the device 501 is a depletion-mode device (D-mode), the device 501 can be configured in a cascode configuration with a low-voltage enhancement-mode device 21 (e.g., a silicon FET) to form a normally-off hybrid device 500 that can operate in a manner similar to a single enhancement-mode III-N device. The III-N device 501 differs from the III-N device 101 in that it includes a second 2DEG channel under the drain electrode extension 17' and optionally includes a second 2DEG channel under the source electrode extension 16'. The second 2DEG channel is induced from the compositional mismatch between the second III-N channel layer 52 and the second III-N barrier layer 51. The layer 51 and the layer 52 can first be formed or grown continuously on the first III-N barrier layer 13 and extend between the drain electrode 17 and the source electrode 16. Then, the second channel layer 52 and the second barrier layer 51 can be removed or etched away in a region inserted from the source extension 16' and the drain extension 17' such that the remaining ends of the layer 51 / 52 approach the gate electrode 18 more closely than the extension portions 16' / 17'. The gate dielectric 14 can be formed in the insertion region. By forming a second 2DEG channel under the extension, the portion of the insulating layer 15 under the drain electrode extension 17' is shielded from becoming forward-biased when the primary 2DEG channel 19 is fully depleted. Further, the second 2DEG channel formed within the second channel layer substantially increases the drain-substrate pinch-off voltage. This prevents the primary 2DEG channel 19 from being fully depleted under the drain extension 17' when the device 501 operates at the maximum rated drain-source voltage.

[0075] FIG. 6 shows a cross-sectional view of a III-N device 601 similar to the III-N device 101 of FIG. 1A. The III-N device 601 can be an enhancement mode device (i.e., normally off) or a depletion mode device (i.e., normally on). When the device 601 is a depletion mode device (D-mode), the device 601 can be configured in a cascode configuration with a low voltage enhancement mode device 21 (e.g., a silicon FET) to form a normally off hybrid device 600 that can operate in a manner similar to a single enhancement mode III-N device. The III-N device 601 differs from the III-N device 101 in that it includes a III-N spacer layer 61 (e.g., UID GaN) and a p-type III-N layer 62 formed on the III-N channel layer 13. A portion of the p-type III-N layer 61 can be etched away in the source and drain access regions. The remaining portion 62 is directly under and in contact with the drain extension 17'. Portion 62' is directly under and in contact with the gate electrode 18. Portion 62'' is directly under and in contact with the source electrode extension 61'. The first end of the remaining portion 62 extends further towards the gate electrode 18 in the drain side access region 27 than the drain extension 17', and the first end of the remaining portion 62'' extends further towards the gate electrode 18 than the source side extension 16'. The III-N spacer layer 61 acts as a diffusion barrier that prevents / limits the p-type dopant in the III-N layer 62 from reducing the 2DEG channel charge. The device may not include the gate dielectric layer 14 as shown in the device 101 of FIG. 1A. Forming the gate dielectric 14 is typically grown in-situ in a MOCVD reactor and also causes significant maintenance and throughput issues for MOCVD. Having a device without a gate dielectric can significantly reduce the cost and time of the manufacturing process. The device 601 is a JFET type device.

[0076] FIG. 7 shows a cross-sectional view of a III-N device 701 similar to the III-N device 301 of FIG. 3A. The III-N device 701 can be an enhancement-mode device (i.e., normally-off) or a depletion-mode device (i.e., normally-on). When the device 701 is a depletion-mode device (D-mode), the device 701 can be configured in a cascode configuration having a low-voltage enhancement-mode device 21 (e.g., a silicon FET), forming a normally-off hybrid device 700 that can operate in a manner similar to a single enhancement-mode III-N device. The III-N device 701 is different from the III-N device 301 in that the III-N material structure 20 is formed on an insulating substrate 70 (e.g., a sapphire or SiC substrate) instead of the conductive silicon substrate 10 described in FIG. 3A. The device 101 of FIG. 1A can be fabricated on an insulating substrate such as the substrate 70, but significant current degradation can occur. The insulating substrate reduces the electric field in the buffer layer and is beneficial for realizing a high-voltage lateral GaN HEMT device with a rated voltage > 650V, e.g., exceeding 1200V, without the need for growing a thick epitaxial III-N buffer layer (such as the buffer layer 11). However, such a device requires a lateral high-voltage blocking region that increases the die size and thus the die cost. One way to reduce the die size is to increase the 2DEG channel charge density, but this can cause reliability problems due to an increase in the electric field. Another way is to shorten the length of the drain-side access region 27 (measured along the channel length). This increases the capacitive coupling between the gate electrode 18 and the drain electrode 17. As a result of this increased coupling, when a high voltage is applied to the drain terminal, the 2DEG can be completely depleted, and negative charges can be trapped in the layers 14 and / or 15 under the drain electrode extension 17'. This can increase the Ron of the device and thus increase the current degradation during operation.The device 701 shown in FIG. 7 can address this potential problem by removing layer 14 and / or 15 under the drain electrode extension 17', and helps to realize a reliable and low-cost high-voltage lateral GaN device on an insulating substrate.

[0077] Figures 8(a)-(d) show a method of manufacturing the device 301 of FIG. 3A. As shown in FIG. 8(a), an III-N material structure is formed on a substrate (not shown). The III-N material structure includes an III-N buffer layer 11 (e.g., AlGaN / GaN), an III-N channel layer 12 (e.g., UID GaN), and an III-N barrier layer 13 (e.g., AlGaN). A gate dielectric layer 14 is continuously formed on the upper surface of the III-N material structure. As shown in FIG. 8(b), the gate dielectric layer is removed or etched (e.g., dry etched in the regions where the source and drain electrodes are to be formed), and as shown in FIG. 8(c), a part of the III-N barrier layer can be removed or etched away to form a recess. The remaining part of the gate dielectric layer 14 is smaller than the remaining part of the III-N channel layer 13. The recess formed in the III-N barrier layer can help to improve the ohmic contact for source / drain connection to the 2DEG. As shown in FIG. 8(d), source electrode 16 and drain electrode 17 are formed in the removed part of the III-N barrier 13. Drain extensions 17' and source extensions 16' are formed on the upper surface of the III-N barrier layer 13. The device can be further annealed at a high temperature (e.g., above 500 °C) to form an ohmic contact to the 2DEG. The isolation part 81 is between the end of the extension 17' and the end of the gate dielectric layer 14 closest to the drain electrode 17. The isolation part 81 can be 0.1 - 2 μm, but ideally should be kept as small as possible.

[0078] Figures 9(a) to 9(d) illustrate a method 901 for manufacturing a drain electrode 91 that does not include the drain electrode extension 17' shown in FIG. 1A. As shown in FIG. 9(a), an III-N material structure is formed on a substrate (not shown). The III-N material structure includes an III-N buffer layer 11 (e.g., AlGaN / GaN), an III-N channel layer 12 (e.g., UID GaN), and an III-N barrier layer 13 (e.g., AlGaN). A gate dielectric layer 14 is continuously formed on the upper surface of the III-N material structure 20. An insulating layer 15 is continuously formed on the upper surface of the gate dielectric layer 14.

[0079] As shown in FIG. 9(b), recesses are formed in the insulating layer 15, the dielectric layer 14, and the III-N barrier layer 13 (e.g., by dry etching). A metal contact layer (e.g., Ti / Al) is continuously deposited in the recesses and on the upper surface of the insulating layer 15. Next, the metal contact layer is patterned and etched to form a drain electrode 91 having a drain electrode extension 91'. The drain electrode 19 is patterned such that the top width of the drain is larger than the width of the recess, ensuring good metal coverage within the recess and high-quality ohmic contact of the drain electrode to the 2DEG channel 19. The insulating layer 15 is used to protect the gate dielectric layer 14 during the metal etching process for forming the drain electrode 91.

[0080] However, as described above, having an insulating material between the drain electrode extension 91' and the 2DEG channel 19 can cause negative charge trapping and current degradation. Another way to reduce this current degradation is to remove the drain extension 19'. As can be seen in FIG. 9(c), a photoresist layer 93 is patterned on the drain electrode 91 and inserted from the drain electrode extension portion 91'.

[0081] Next, as seen in FIG. 9(d), the device undergoes an isotropic chemical wet etching process that is selective to the drain electrode metal stack. The corners of the drain extension portion 19' are etched at a faster rate than the sidewalls that form the re-entrant profile under the photoresist layer 93. The photoresist layer 93 is then removed to form the drain electrode without overhangs, reducing current degradation. The process 901 shown in FIGS. 9(a)-(c) describes a method of forming the drain electrode, but the same process can be used simultaneously to form a source electrode without an extension portion.

[0082] Alternatively, using another embodiment and manufacturing method, performance improvements similar to those described for the device 301 can be achieved. The device 301 of FIG. 3A shows a drain extension portion 17' in direct contact with the III-N barrier layer 13, but an improved on-resistance is also shown by substantially increasing the thickness of the insulating portion 15 formed under the drain extension portion 17'.

[0083] FIG. 10A shows a cross-sectional view of a III-N device 110 similar to the III-N device 100 of FIG. 1A. The III-N device 110 can be an enhancement-mode device (i.e., normally-off) or a depletion-mode device (i.e., normally-on). When the device 110 is a depletion-mode device (D-mode), the device 110 can be configured in a cascode with a low-voltage enhancement-mode device 21 (e.g., a silicon FET) to form a normally-off hybrid device 700 that can operate in a manner similar to a single enhancement-mode III-N device. The III-N device 110 differs from the III-N device 100 in that the thickness of the insulating portion 15 and / or 14 formed under the drain extension 17'' is substantially increased compared to the device 100 of FIG. 1A. For example, the total thickness of the insulating material (i.e., layer 14 + layer 15) formed under the drain extension portion of the device 100 can be less than 100 nm. However, in the device 110, the total thickness of the insulating material formed under the drain extension 17' can exceed 500% compared to the device 100. The overall thickness of the insulating material can be greater than 300 nm, greater than 500 nm, for example, 500 nm to 1,000 nm.

[0084] As shown in FIG. 10A, device 110 includes a multi-field plate structure 18b. The field plate structure 18b includes a first portion c' (i.e., the first field plate), a second portion d' (i.e., the second field plate), and a third portion e' (i.e., the third field plate). Each field plate has a step height that increases between each field plate and the top of the III-N barrier layer 13 as the field plate extends towards the drain electrode. The third field plate e' has a step height h' above the barrier layer 13. The step height h'' of the drain overhang 17' of device 110 is at least as high as the step height h' of the third field plate. Device 110 can also have three or more field plates. For example, device 110 can have four field plates (not shown), and the step height h'' can be less than the step height of the fourth field plate, but can also be greater than the step height of the third field plate.

[0085] FIG. 10B shows the back-gating test results on device 110. The drain-substrate voltage is gradually increased from 0 V to the maximum rated voltage 452 (V TR(DSS) =e.g., 1000 V) (forward sweep 450), and gradually decreased from V TR(DSS) to 0 V (reverse sweep 451). The drain-source current is recorded during both the forward sweep 450 and the reverse sweep 451. During the forward sweep 450, the drain-source current reaches 0 A near 650 V and shows a back-gating pinch-off 453 and complete 2DEG depletion until V D-SUB reaches V TR(DSS) . As seen in FIG. 10B, V TR(DSS) 452 is V D-SUBIt is separated from 453 by 100V or more. However, below the drain electrode extension portion 17', since the dielectric layer 14 and / or the insulating layer 15 are relatively thick, the charge trapping mechanism becomes small and the current degradation is significantly improved. As seen in FIG. 10B, the starting normalized Id is 1 and the ending Id is ~0.9, which indicates a current reduction of less than 20% and an increase in the on-state resistance of less than 25%. This result demonstrates a significant improvement in performance compared to the result of the device 101 shown in FIG. 2C.

[0086] Some embodiments have been described. Nevertheless, it will be understood that various modifications can be made without departing from the spirit and scope of the technologies and devices described herein.

Claims

1. An III-N device comprising: A conductive substrate; An III-N material structure comprising an III-N buffer layer, an III-N channel layer, and an III-N barrier layer, wherein a composition difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein; A source electrode, a gate electrode, and a drain electrode; Wherein: The gate electrode is electrically connected to the conductive substrate, and the drain electrode comprises a first portion and a second portion, The first portion of the drain electrode makes an ohmic contact with the 2DEG channel, and the second portion of the drain electrode extends on and is in direct contact with the upper surface of the III-N barrier layer, The device has a drain-substrate pinch-off voltage and a maximum rated drain-source operating voltage, and the maximum rated drain-source operating voltage is greater than the drain-substrate pinch-off voltage, When the III-N device is biased at the maximum rated drain-source operating voltage, the 2DEG channel is completely depleted of charge below the second portion of the drain electrode, An III-N device.

2. The device further comprises a gate dielectric layer formed between the upper surface of the III-N barrier layer and the gate electrode, the gate dielectric layer comprising a first end extending towards the drain electrode and a second end extending towards the source electrode, and a separation between the first end and the drain electrode is between 0.1 μm and 2 μm and the separation is filled with an insulating material having a composition different from that of the gate dielectric layer. The III-N device according to claim 1.

3. The device intentionally does not include any dielectric or insulating material between the drain electrode and the III-N material structure. The III-N device according to claim 2.

4. The device has a maximum rated drain-source operating voltage exceeding 600 V and a drain-substrate pinch-off voltage less than 600 V. The III-N device according to claim 1.

5. The device has a first on-state resistance when the drain-source voltage is held constant at a low voltage, and the device has a second on-state resistance when the drain-substrate voltage is swept from the low voltage to the maximum rated drain-source voltage and back to the low voltage, and the first on-state resistance is within 25% of the second on-state resistance. The III-N device according to claim 4.

6. The I of the first on-state resistance ＤＳ is within 20% of the I of the second on-state resistance ＤＳ The III-N device according to claim 4

7. The source electrode includes a first portion and a second portion, the first portion makes an ohmic contact with the 2DEG channel, and the second portion extends above the upper surface of the III-N barrier layer and is in direct contact with the upper surface. The III-N device according to claim 1.

8. The device is a depletion-mode device, and an enhancement-mode low-voltage Si-FET is arranged in a cascode configuration to form a hybrid enhancement-mode III-N device. The III-N device according to claim 7.

9. When the drain-source voltage is the maximum rated operating voltage, the 2DEG channel below the second portion of the drain electrode is depleted by the vertical electric field between the drain electrode and the conductive substrate. The III-N device according to claim 1.

10. A III-N device, a conductive substrate; a III-N material structure including a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, wherein a composition difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein, the III-N material structure; a source electrode, a gate electrode, and a drain electrode; comprising the drain electrode includes a first portion and a second portion, the first portion of the drain electrode makes an ohmic contact with the 2DEG channel, and the second portion of the drain electrode extends on the upper surface of the III-N barrier layer and is in direct contact with the upper surface, the device has a drain-substrate pinch-off voltage and a maximum rated drain-source operating voltage, and the maximum rated drain-source operating voltage is at least 50 V greater than the drain-substrate pinch-off voltage. The device has a first on-state resistance when the drain-source voltage is held constant at a low voltage, and the device has a second on-state resistance when the drain-substrate voltage is swept from the low voltage to the maximum rated drain-source voltage, held at the maximum rated voltage for at least two minutes, and then swept back to the low voltage, and the first on-state resistance is within 25% of the second on-state resistance. III-N device. **Claim 11** The III-N device according to claim 10, wherein the device has a maximum rated drain-source operating voltage of at least 650 V and a drain-substrate pinch-off voltage of 600 V or less. **Claim 12** The I of the first on-state resistance ＤＳ is within 20% of the I of the second on-state resistance ＤＳ The device according to claim 10 **Claim 13** The device according to claim 10, wherein when the III-N device is biased at the maximum rated drain-source pinch-off voltage, the charge below the second portion of the drain electrode in the 2DEG channel is completely depleted. **Claim 14** A III-N device, a conductive substrate; a III-N material structure comprising a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, wherein a compositional difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein; comprising the III-N buffer layer comprises at least five separate layers that increase continuously from a first side of the III-N buffer layer adjacent to the substrate to a second side of the III-N buffer layer adjacent to the III-N channel layer, the first layer is an AlN nucleation layer, The second layer is Al Ｘ Ga １－Ｘ N, where 70% < x < 90%, and the thickness is 0.2 μm to 1.0 μm The third layer is Al Ｘ Ga １－Ｘ N, where 40% < x < 70% and the thickness is 0.2 μm to 1.0 μm The fourth layer has a thickness of 0.5 μm to 1.5 μm and includes repetitions of an AlN / Al Ｘ Ga １－Ｘ N stack. The AlN layer has a thickness of 0.5 nm to 5 nm, and the Al Ｘ Ga １－Ｘ N layer has a thickness of 10 nm to 50 nm, and 5% < x < 20%, the fifth layer has a thickness of 0.5 μm to 1.5 μm and includes a repetition of an AlN / GaN stack, the AlN layer has a thickness of 0.5 nm to 5 nm, and the GaN layer has a thickness of 10 nm to 50 nm, the III-N device further comprises a source electrode, a gate electrode, and a drain electrode, the gate electrode is electrically connected to the conductive substrate, when the III-N device is biased at the maximum rated drain-source operating voltage, the charge in the 2DEG channel is not completely depleted. III-N device. **Claim 15** The III-N device according to claim 14, wherein the device further has a drain-source pinch-off voltage, and the drain-source pinch-off voltage is greater than the maximum rated drain-source operating voltage. **Claim 16** The device further includes a gate dielectric layer, the drain electrode includes a first portion and a second portion, the first portion of the drain electrode makes an ohmic contact with the 2DEG channel, and the second portion of the drain electrode extends above the upper surface of the gate dielectric layer. The III-N device according to claim 15.

17. The III-N device according to claim 14, wherein the III-N material structure is less than 6 μm, and the drain-substrate pinch-off voltage is greater than 750 V.

18. A III-N material structure, comprising a III-N buffer layer, a III-N channel layer, and a III-N barrier layer, wherein the composition difference between the III-N channel layer and the III-N barrier layer induces a 2DEG channel therein, the III-N buffer layer includes at least five separate layers sequentially increasing from a first side of the III-N buffer layer to a second side of the III-N buffer layer, the first layer is an AlN nucleation layer, The second layer is Al Ｘ Ga １－Ｘ N, where 70% < x < 90%, and the thickness is 0.2 μm to 1.0 μm The third layer is Al Ｘ Ga １－Ｘ N, where 40% < x < 70% and the thickness is 0.2 μm to 1.0 μm The fourth layer has a thickness of 0.5 μm to 1.5 μm and includes repetitions of an AlN / Al Ｘ Ga １－Ｘ N stack, where the AlN layer has a thickness of 0.5 nm to 5 nm and the Al Ｘ Ga １－Ｘ N layer has a thickness of 10 nm to 50 nm, and 5% < x < 20%, the fifth layer has a thickness of 0.5 μm to 1.5 μm and includes a repetition of an AlN / GaN stack, the AlN layer has a thickness of 0.5 nm to 5 nm, and the GaN layer has a thickness of 10 nm to 50 nm, the III-N channel layer is formed above the fifth layer, A III-N device.

19. The III-N device according to claim 18, wherein the III-N material structure has a thickness of less than 6 μm, and the III-N material structure has a breakdown voltage exceeding 750 V.

20. The III-N device according to claim 19, wherein the III-N material structure is formed on a conductive silicon substrate, and the first surface of the III-N buffer layer is adjacent to the conductive silicon substrate.

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