A method for constructing a package substrate having high density

Abstract

The disclosed method may include: (i) positioning a first surface of a component of a semiconductor device over a first through-hole via; (ii) covering at least a second surface of the component, which is opposite to the first surface of the component, with a layer of a dielectric material; (iii) removing a portion of the layer of the dielectric material covering the second surface of the component to form at least one cavity; and (iv) depositing a conductive material within the cavity to form a second through-hole via over the second surface of the component. Various other devices, systems and methods are also disclosed.

Description

Background Art

[0001] To meet the increasing power supply requirements of semiconductor device products, individual components such as voltage regulators and capacitors can be embedded within a package substrate. As will be described in more detail below, the present application discloses both problems associated with the embedding of individual components and corresponding solutions.

[0002] The accompanying drawings illustrate several exemplary embodiments and are a part of this specification. Together with the following specification, these drawings demonstrate and explain the various principles of the present disclosure.

Brief Description of the Drawings

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Detailed Description of the Invention

[0004] Throughout the drawings, like reference numerals and descriptions indicate like but not necessarily identical elements. The exemplary embodiments described herein have many modifications and alternative forms, but a particular embodiment is shown by way of example in the drawings and is described in detail herein. However, the exemplary embodiments described herein are not intended to be limited to the particular forms disclosed. Rather, the present disclosure covers all modifications, equivalents, and alternatives falling within the scope of the appended claims.

[0005] The present disclosure describes various methods for embedding components at high density within a substrate. To meet the increasing power supply requirements of semiconductor products, individual components such as voltage regulators and capacitors can be embedded within a package substrate in closer proximity to the die. The present application describes the generation of a package substrate structure capable of embedding one or more components within a high density configuration of plated through holes.

[0006] The technology of the present application can solve several different problems. Related power supply solutions in the field of package substrates may not have flexibility or scalability. In addition, the approach of using an air core inductor may depend on the thickness of the package. In the case of a thin package, the inductance value is generally too low to be implemented. Another approach of including a magnetic material in the plated through hole may make the plated through hole pitch very coarse, which may make it impossible to achieve the scaling of the plated through hole density. Also, this last approach may involve very high manufacturing complexity due to the leaching of the magnetic filler into various wet chemistries in the process flow. In contrast, the technology of the present application can be highly scalable with an effective doubling of the plated through hole density compared to related or conventional package structures. Also, the technology of the present application can be very flexible with respect to embedding components of various dimensions within the package core. In summary, related technologies involving air core inductors, magnetic core inductors and / or multilayer ceramic capacitors have significant limitations with respect to flexibility and scalability.

[0007] In view of the above, the technology of the present application can introduce various improvements to the related methodologies. For example, the technology of the present application can achieve a high plated two-hole density due to a lower plated through hole pitch. In addition, the technology of the present application can enable the embedding of components of various thicknesses. Also, the technology of the present application can enable the embedding of components without using a cavity drill and without the overhead of associated spacing (e.g., spacing along the X and Y coordinates of the plan view of the corresponding semiconductor device).

[0008] In addition, the technology of the present application can enable embedding components of different dimensions (e.g., varying along each of the X, Y, and / or Z dimensions) without creating process complexity and / or yield issues. In related embedding techniques, the thickness of the component has to be close to the thickness of the substrate core. Due to this constraint, embedding components in a thick core with a thickness exceeding 800 microns may become impractical. Thus, the exemplary techniques disclosed in the present application can enable a significant increase in the through-hole plating density. In addition, the technology of the present application can facilitate the efficient design of semiconductor device packages.

[0009] The technology of the present application can include several prominent features. In some examples, a high through-hole plating density with a pitch of 250 - 300 microns can constitute one prominent feature. In a further example, components embedded in various layers of the core are another prominent feature, because related methodologies can only embed such components within a single layer (e.g., a single composite layer formed by joining the topmost and bottommost layers, while the technology of the present application can result in any number of layers until the target thickness is reached). Similarly, in a further example, another prominent feature of the present application can be that different types of components with different thicknesses can be embedded in the core.

[0010] As will be described in more detail below, the present disclosure is generally related to a method for constructing a package substrate having a high density. An exemplary method can include: (i) positioning a first surface of a component of a semiconductor device over a first through-hole plating; (ii) covering at least a second surface of the component, which is on the opposite side of the first surface of the component, with a layer of dielectric material; (iii) removing a portion of the layer of dielectric material covering the second surface of the component to form at least one cavity; and (iv) depositing a conductive material within the cavity to form a second through-hole plating on the second surface of the component.

[0011] In some examples, the first plated through hole is positioned such that the pitch of the plated through hole pattern is less than about 500 microns.

[0012] In some examples, the first plated through hole is positioned such that the pitch of the plated through hole is less than about 350 microns.

[0013] In some examples, the first plated through hole is positioned such that the pitch of the plated through hole pattern is about 250 microns.

[0014] In some examples, the thickness of the layer of dielectric material is about 50 to 100 microns.

[0015] In some examples, the first surface of the component of the semiconductor device is positioned such that a cavity drill is not used to form the space in which the component is disposed before the second surface of the component is covered with a layer of dielectric material.

[0016] In some examples, the method further includes adding a contact formed from a conductive material to the second surface of the component of the semiconductor device before the second surface of the component is covered with a layer of dielectric material.

[0017] In some examples, the method further includes repeating at least a portion of the method to form a second layer of dielectric material.

[0018] In some examples, a portion of the method is repeated until a defined thickness of the substrate core for the semiconductor device is achieved.

[0019] In some examples, the components of the semiconductor device include at least one of a capacitor or a voltage regulator.

[0020] An exemplary semiconductor substrate can include components embedded within a dielectric layer, a first plated through-hole electrically connected to a first surface of the component, and a second plated through-hole electrically connected to a second surface of the component on the side opposite the first surface. In these examples, the pitch of the plated through-hole pattern within the semiconductor substrate is less than about 550 microns.

[0021] Similarly, an exemplary semiconductor device can include components embedded within a dielectric layer, a first plated through-hole electrically connected to a first surface of the component, and a second plated through-hole electrically connected to a second surface of the component on the side opposite the first surface. In these examples, the pitch of the plated through-hole pattern within the corresponding semiconductor substrate is less than about 550 microns.

[0022] FIG. 1 shows an exemplary workflow 100 that can include workflow step 110, workflow step 112, workflow step 114, and workflow step 116. Workflow 100 can correspond to a methodology of a related art that can be improved by the technology of the present application. Workflow 100 can start at workflow step 110, at which point a substrate core formed from a suitable dielectric is obtained or generated. As one exemplary example, a pre-preg can form the substrate 102 shown in workflow step 110, although in other examples, different suitable dielectric materials can be used.

[0023] As further shown in this figure, the substrate core can have a plurality of plated through holes 104. Further, the plated through holes 104 can have a specific pitch, which can refer to the distance between the centers of two plated through holes within the pattern of the plated through holes when not obstructed by other components otherwise. In the example of workflow step 110, the two left plated through holes 104 can have a specific pitch of about 550 microns (see workflow step 214 in FIG. 2), but the right plated through hole in workflow step 110 does not necessarily define or correspond to this specific pitch due to the obstruction of component 108, as further described below.

[0024] In workflow step 112, a cavity drill can be used to form a cavity within the substrate 102. A cavity drill can be used to form a cavity for later placement of components within the cavity. The components can correspond to, for example, a capacitor or a voltage regulator. In one specific example, the capacitor can correspond to a silicon capacitor. In other examples, any other suitable or appropriate individual component or integrated passive device can be used and embedded within the cavity formed in workflow step 112 using a cavity drill.

[0025] In workflow step 114, after the generation of the cavity, a tape lamination procedure can be performed to laminate a tape layer 107 on the bottom of the remaining portion of the substrate 102. Then, in workflow step 116, components 108 such as a silicon capacitor can be properly placed within the previously formed cavity. According to the methodology of workflow 100, the component 108 can be constrained with respect to its thickness such that its thickness is substantially the same as the thickness of the substrate 102.

[0026] From FIG. 1, workflow 100 can proceed in the form of workflow 200 shown in FIG. 2. Workflow 200 can include workflow step 210, workflow step 212, and workflow step 214. In workflow step 210, component 108 can be encapsulated within another dielectric material. As one exemplary example, the second individual dielectric material can correspond to an Ajinomoto Build-up Film. Thus, it is desirable to use the same or a similar dielectric material as in workflow 100, such as a prepreg as described above, although the prepreg may not have sufficient fluidity or other material properties to properly flow into the cavities formed by the cavity drill in workflow step 112. Thus, in workflow step 210, a second individual dielectric material (e.g., an Ajinomoto Build-up Film) can be used. Similarly, in workflow step 212, a second layer 250 of the second individual dielectric material can be formed on both the top and bottom surfaces of substrate 102 (e.g., a second layer of Ajinomoto Build-up Film on a previous Ajinomoto Build-up Film).

[0027] Finally, in workflow step 214, vias corresponding to the plated through holes can be formed using a suitable procedure such as a laser processing procedure. The laser processing procedure can electrically connect the plated through holes 104 to external and / or components 108 such as silicon capacitors. In addition, a metallization procedure can be performed to ensure that the metal or other conductive material forming the plated through holes achieves electrical connectivity.

[0028] Further, as further shown in FIG. 2, workflow step 214 further emphasizes how the through - hole plating of this methodology has a relatively large pitch corresponding to about 550 microns together. Similarly, workflow step 214 further emphasizes how the height or thickness of the original substrate 102, which is constrained to substantially match the height or thickness of component 108 by this methodology, is relatively large and inflexible at about 800 - 1200 microns.

[0029] Further, as described above, the methodologies of FIGS. 1 and 2 may have several defects, undesirable characteristics, or sub - optimizations. A pitch of about 550 microns is relatively large, which results in a lower component density or functionality per square millimeter of mounting area on the corresponding substrate. Also, the relatively large pitch results in very large through - hole plating, which must contain no voids within their centers. Additionally, the size of the components (e.g., along each of the three - dimensional X, Y, and / or Z) is relatively inflexible and is further constrained to substantially match the height or thickness of the original substrate, which is 800 - 1200 microns. As another example, the methodologies of FIGS. 1 and 2 involve the use of cavity drills. Further, this methodology may be essentially constrained to a single layer (e.g., a composite layer formed by merging an upper sub - layer and a lower sub - layer), as further shown in FIGS. 1 and 2.

[0030] In view of the above, FIG. 3 shows an exemplary flowchart of a method 300 for embedding components within a substrate. Method 300 can address one or more of the drawbacks outlined above and, for example, can improve the methodologies of FIGS. 1 and 2. In step 302, one or more of the systems described herein (e.g., semiconductor manufacturing equipment) can position a first surface of a component of a semiconductor device over a first through - hole plating.

[0031] Step 302 can be executed in various ways. As an illustrative example, FIGS. 4-7 show a sequence of workflows highlighting more detailed embodiments of method 300. In particular, the methodologies of FIGS. 4-7 can include a plurality of preparatory steps prior to the execution of step 302. These preparatory steps can prepare the corresponding substrate and / or prepare one or more plated-through hole layers for placing components such as silicon capacitors according to step 302.

[0032] FIG. 4 shows an exemplary workflow 400 that can further include workflow step 410, workflow step 412, workflow step 414, and workflow step 416. In workflow step 410, an original semiconductor substrate can be generated or obtained. The semiconductor substrate can include a layer of dielectric material 404 having thinner conductive metal layers 402 both on the upper side and the lower side of the dielectric material 404. One exemplary example of a dielectric material can include a prepreg. Similarly, an exemplary example of a conductive material for the metal layer 402 can include copper. However, in other examples, any different suitable dielectric material and / or metal or other conductive material can be used for the dielectric material 404 and the metal layer 402. In particular, in workflow step 410, as further shown in FIG. 4, copper foils can be placed on the upper and lower surfaces of the base portion of the prepreg. Additionally, in workflow step 410, an acid cleaning procedure can be performed to remove particles or obstacles or otherwise ensure a clean surface for the remainder of the workflows of FIGS. 4-7.

[0033] From workflow step 410, workflow 400 can proceed to workflow step 412, at which point a plating through hole pad patterning procedure can be performed by excluding a selected portion from the metal layer 402 at the bottom of the dielectric material 404. After excluding, removing, or cutting out the selected portion from the metal layer 402, the remaining portion (as shown in workflow step 412 of FIG. 4) can form the upper surface of the corresponding plating through hole, as will be further described below in connection with FIGS. 5-7.

[0034] From workflow step 412, workflow 400 can proceed to workflow step 414, at which point a polyethylene terephthalate lamination procedure can be performed. Performing the polyethylene terephthalate lamination procedure can effectively laminate the bottom surface of the dielectric material 404, which includes the remaining portion of the metal layer 402 at the bottom, with a layer of polyethylene terephthalate 406.

[0035] From workflow step 414, workflow 400 can proceed to workflow step 416, at which point an upper etching procedure can be performed. Performing the etching procedure of workflow step 414 can substantially or completely remove the metal layer 402 on the upper surface of the dielectric material 404. Thus, in workflow step 416, FIG. 4 shows how this particular instance of the metal layer 402 was removed.

[0036] From FIG. 4, workflow 400 proceeds in the form of workflow 500 shown in FIG. 5. Workflow 500 can further include workflow step 502, workflow step 504, workflow step 506, and workflow step 508. In workflow step 502, the polyethylene terephthalate 406 previously placed in workflow step 414 can be removed. Thus, in workflow step 502, FIG. 5 further shows how the layer of polyethylene terephthalate 406 was removed.

[0037] From workflow step 502, workflow 500 can proceed to workflow step 504, at which point one or more cavities can be generated within dielectric material 404. Thus, at workflow step 504, FIG. 5 further shows how a plurality of cavities of substantially trapezoidal shape are effectively generated or cut out within dielectric material 404. In some exemplary examples, the generation of these trapezoidal-shaped cavities can be performed at least in part using a laser drill. Thus, the use of a laser drill can be contrasted with the use of a cavity drill described above in connection with FIGS. 1 and 2, since the methodologies of FIGS. 4-7 can omit any use of a cavity drill. Additionally, at workflow step 504, after performing laser drilling to generate the corresponding cavities, a desmearing operation can be performed to effectively clean the corresponding vias or plated through holes.

[0038] From workflow step 504, workflow 500 can proceed to workflow step 506, at which point a copper seeding procedure can be performed. Due to scale, although not necessarily shown in FIG. 5, after generating cavities using a laser drill at workflow step 504, a thin layer of copper can be disposed over the remaining portion of dielectric material 404. In some examples, the copper seeding procedure can correspond to an electroless copper seeding procedure.

[0039] From workflow step 506, workflow 500 can proceed to workflow step 508, at which point the copper electroplating procedure can be executed to deposit or fill copper within the cavities generated in workflow step 504. In addition to filling these cavities, as further shown in workflow step 508 of FIG. 5, a horizontal layer of copper can be formed over the cavities and branched between the cavities.

[0040] From FIG. 5, workflow 500 can proceed in the form of workflow 600 shown in FIG. 6. Workflow 600 can include workflow step 602, workflow step 604, workflow step 606, and workflow step 610. In workflow step 602, the dry film resist lamination procedure can be executed to laminate a dry film resist layer 608 on the upper surface of copper 402 disposed through copper electroplating in workflow step 508 as further described above. Additionally, after laminating the dry film resist layer 608 on the upper surface of copper 402, an exposure procedure can be executed where the dry film resist layer 608 can be exposed, for example, by removing a protective film.

[0041] From workflow step 602, workflow 600 can proceed to workflow step 604, at which point the combination of copper 402 and dielectric material 404 can be appropriately developed, trimmed, and stripped. These procedures in workflow step 604 can effectively remove the dry film resist layer 608 laminated on the upper surface of dielectric material 402 in workflow step 602.

[0042] From workflow step 604, workflow 600 can proceed to workflow step 606, which can also correspond to step 302 of method 300, as further described above. In workflow step 606, component 602 can be placed on the upper surface of copper 402 to form a plated through hole. Placing the component on the upper surface can electrically connect the component through the plated through hole to the outside and / or one or more layers of the corresponding stack below component 602. Further, in workflow step 606, additional instances of copper 402 in the form of conductive contacts can be placed on the upper surface of component 602. FIG. 6 shows an exemplary example of three individual instances of copper 402 placed on the upper surface of component 602, but in other examples, any other arbitrary or suitable number of conductive contacts can be placed on the upper surface.

[0043] In addition, workflow 600 can include workflow step 608, at which point a small adhesion promoter can be applied to the surfaces of copper 402 at the top and bottom of the plated through hole, as well as to the contacts on the component. The adhesion promoter can be applied, for example, by the Czochralski method. The adhesion promoter can promote the adhesion of a second layer of dielectric material that can be placed on the plated through hole, as further described below in connection with workflow step 702 of FIG. 7.

[0044] Returning to FIG. 3, at step 304 of method 300, one or more of the systems described herein can cover at least a second surface of a component on the side opposite the first surface of the component with a layer of dielectric material. Similarly, from workflow step 606, workflow 600 can proceed in the form of workflow 700 shown in FIG. 7. Workflow 700 can further include workflow step 702, workflow step 704, and workflow step 706, as further shown in this figure. In particular, workflow step 702 can correspond to step 304 of method 300, at which point a second layer of dielectric material 404 can be disposed over component 408 and over copper 402 that forms conductive contacts on the upper surface of component 408. Thus, the entire layer filling the voids between the plated-through holes within the component between the original layer of dielectric material 404 and the second layer of dielectric material 404 laminated at workflow step 702 can be substantially uniform (e.g., can be substantially the same dielectric material such as a prepreg), although the methodologies of FIGS. 1 and 2 have resulted in a mixed non-uniform layer of dielectrics (e.g., characterized by both a MSG build-up film and a prepreg).

[0045] Returning to FIG. 3, at step 306 of method 300, one or more of the systems herein can remove a portion of the layer of dielectric material covering the second surface of the component to form at least one cavity. Similarly, at workflow step 704, workflow 700 can proceed to a drilling procedure for forming one or more vias or plated-through holes, as further shown in FIG. 7. Thus, the use of a drilling procedure such as a laser drilling procedure can form a substantially trapezoidal cavity that is substantially parallel to those underlying trapezoidal-shaped plated-through holes (previously filled with copper 402 in the copper electroplating procedure of workflow step 508).

[0046] Returning again to FIG. 3, at step 308, one or more of the systems described herein can deposit a conductive material within the cavity to form a second plated through hole on a second surface of the component. Similarly, at workflow step 706, one or more of the previous steps of methods 300 and workflows 400-700 can be repeated as necessary until a defined or target thickness of the corresponding substrate core is achieved. Thus, in the example of workflow step 706, three substantially uniform layers of dielectric material (e.g., prepreg) can be laminated on top of each other, thereby encapsulating the component, component contacts, and plated through holes, as further described above. Further, at workflow step 706, FIG. 7 further shows how the corresponding pitch of the pattern of plated through holes formed by the corresponding ones of plated through holes 402 can be substantially about 250 microns. Similarly, the height or thickness of the dielectric layer encapsulating the component is substantially or about 50-100 microns.

[0047] To summarize, FIG. 8 shows a comparison diagram 800 that compares, at the top, the repetition of the final results of the methodologies of FIGS. 1 and 2 (see workflow step 214), and, at the bottom, the final results of the methods of FIGS. 3-7 (see workflow step 706). As further shown in FIG. 8, the solution shown at the bottom achieves a substantially narrower and more desirable pitch of the plated through hole pattern, at about 250-300 microns, compared to a substantially larger and less desirable pitch of about 550 microns by the methodology shown at the top. Similarly, the components of workflow step 214 are substantially constrained with respect to height or thickness so as to match the height or thickness of the corresponding dielectric material forming the substrate, which is about 800-1200 microns, while the components of workflow step 706 can be flexible with respect to size along one or more of the three individual dimensions. Similarly, the height of the dialectical layer encapsulating the components in workflow step 706 can be made substantially smaller, at about 50-100 microns. Further, the solution of workflow step 706 can be effectively repeated, as further explained above, thereby generating two, three or more layers as part of a stack for forming the substrate. Further, the bottom of FIG. 8 shows only a single component embedded within an intermediate layer, while the solution of workflow step 706 and / or method 300 can be substantially or partially repeated to embed a plurality of different components of various shapes, sizes and types in one or more (or all) of a plurality of layers stacked on top of each other. In contrast, the solution of workflow step 214 is substantially constrained to a single layer (although it can be formed as a composite of an upper sublayer and a bottom sublayer, and for example, it cannot necessarily achieve the 3+ layer configuration shown in workflow step 706). Additionally, as further explained above, the solution corresponding to workflow step 706 can effectively eliminate the use of cavity drills and the use of mixed dielectrics (e.g., both prepregs and flavor build-up films), resulting in a more uniform and easier-to-manage dielectric layer (e.g., a uniform prepreg) as shown in workflow step 706.Accordingly, as shown in the lower part of FIG. 8, the component 408, the upper surface of the first plated-through hole under the component 408, and the bottom surface of the second plated-through hole above the component 408 are embedded within a dielectric layer formed from a substantially uniform dielectric material. Finally, the solution corresponding to workflow step 706 can eliminate the voids within the plated-through holes previously described in relation to FIGS. 1 and 2.

[0048] For completeness, the above description relates to semiconductor devices including computer processors. Such a processor can include and / or represent any type or form of hardware-implemented device capable of interpreting and / or executing computer-readable instructions. In one example, a processor can include and / or represent one or more semiconductor devices implemented and / or deployed as part of a computing system. Examples of a processor include a Central Processing Unit (CPU) and a microprocessor. Other examples can include, depending on the context, a microprocessor, a microcontroller, a field-programmable gate array (FPGA) implementing a softcore processor, an application-specific integrated circuit (ASIC), a system on a chip (SoC), one or more portions of these, one or more variations or combinations of these, and / or any other suitable processor.

[0049] The processor can implement any of a variety of different architectures and / or microarchitectures, and / or can be configured using them. For example, the processor can be implemented and / or configured as a reduced instruction set computer (RISC) architecture, or the processor can be implemented and / or configured as a complex instruction set computer (CISC) architecture. Additional examples of such architectures and / or microarchitectures include, without limitation, 16-bit computer architecture, 32-bit computer architecture, 64-bit computer architecture, x86 computer architecture, advanced RISC machine (ARM) architecture, microprocessor without interlocked pipelined stage (MIPS) architecture, scalable processor architecture (SPARC), load-store architecture, one or more portions of these, one or more combinations or variations of these, and / or any other suitable architecture or microarchitecture.

[0050] In some examples, the processor can include and / or incorporate one or more additional components not explicitly represented and / or shown in the figure. Examples of such components include, without limitation, registers, memory devices, circuits, transistors, resistors, capacitors, diodes, connections, traces, buses, semiconductor (e.g., silicon) devices and / or structures, one or more combinations or variations of these, and / or any other suitable components.

[0051] In the foregoing disclosure, various embodiments have been described using specific block diagrams, flowcharts, and examples. However, the components of each block diagram, the steps, operations, and / or components of the flowchart described and / or illustrated herein can be implemented individually and / or collectively using a wide variety of hardware, software, or firmware (or any combination thereof) configurations. Additionally, since many other architectures can be implemented to achieve the same functionality, any disclosure of components included within other components should be considered to be exemplary in nature.

[0052] The apparatuses, systems, and methods described herein can employ any number of software, firmware, and / or hardware configurations. For example, one or more of the exemplary embodiments disclosed herein can be encoded as a computer program (also referred to as computer software, software applications, computer-readable instructions, and / or computer control logic) on a computer-readable medium. The term "computer-readable medium" generally refers to any form of device, carrier, or medium that can store or transport computer-readable instructions. Examples of computer-readable media include, but are not limited to, transmission-type media such as carrier waves, as well as magnetic storage media (e.g., hard disk drives and floppy (registered trademark) disks), optical storage media (e.g., Compact Disk (CD) and Digital Video Disk (DVD)), electronic storage media (e.g., solid state drives and flash media), and / or non-transitory media such as other delivery systems.

[0053] In addition, one or more of the modules, instructions, and / or micro-operations described herein can transform data, physical devices, and / or representations of physical devices from one form to another. Additionally or alternatively, one or more of the modules, instructions, and / or micro-operations described herein can transform a processor, volatile memory, non-volatile memory, and / or any other part of a physical computing device from one form to another by performing on a computing device, storing data on a computing device, and / or otherwise interacting with a computing device.

[0054] The order of process parameters and steps described and / or illustrated herein are provided by way of example only and can be changed as desired. For example, the steps illustrated and / or described herein can be illustrated or described in a particular order, but such steps need not necessarily be performed in the order illustrated or described. The various exemplary methods described and / or illustrated herein can omit one or more of the steps described or illustrated herein, or can include additional steps in addition to those disclosed.

[0055] Various embodiments are described herein in sufficient detail to enable those skilled in the art to practice the disclosure. It is to be understood that the various embodiments of the disclosure are different but not necessarily mutually exclusive, and that they can be combined differently in order to show new features. For example, the particular features, structures, manufacturing steps, or characteristics described in connection with one embodiment can be implemented in other embodiments without departing from the spirit and scope of the disclosure. In addition, it is to be understood that the location and arrangement of individual elements, such as geometric parameters within each disclosed embodiment, can be modified without departing from the spirit and scope of the disclosure. Other variations will be recognized by those skilled in the art. Accordingly, the following detailed description should not necessarily be construed in a limiting sense.

[0056] The foregoing description is provided to enable those skilled in the art to make the best use of the various aspects of the exemplary embodiments disclosed herein. This exemplary description is not intended to be exhaustive or to be limited to any precise form disclosed. Many modifications and variations are possible without departing from the spirit and scope of the present disclosure. The embodiments disclosed herein should be considered exemplary in all respects and not restrictive. When determining the scope of the present disclosure, reference should be made to the appended claims and their equivalents.

[0057] Unless otherwise specified, the terms "connected to" and "coupled to" (and their derivatives) as used in this specification and the claims are to be construed as allowing both direct and indirect (i.e., via other elements or components) connections. Additionally, the term "a" or "an" as used in this specification and the claims is to be construed as meaning "at least one of". Finally, for ease of use, the terms "including" and "having" (and their derivatives) as used in this specification and the claims are interchangeable with the term "comprising" and have the same meaning.

Claims

1. A method comprising: positioning a first surface of a component of a semiconductor device over a first through-hole plating; covering at least a second surface of the component, which is on the opposite side of the first surface of the component, with a layer of dielectric material; removing a part of the layer of dielectric material covering the second surface of the component to form at least one cavity; depositing a conductive material within the cavity to form a second through-hole plating on the second surface of the component. A method.

2. The method according to claim 1, wherein the first through-hole plating is positioned such that the pitch of the through-hole plating pattern is less than 500 microns. The method of claim 1.

3. The method according to claim 1, wherein the first through-hole plating is positioned such that the pitch of the through-hole plating pattern is less than 350 microns. The method of claim 1.

4. The method according to claim 1, wherein the first through-hole plating is positioned such that the pitch of the through-hole plating pattern is 250 microns. The method of claim 1.

5. The method according to claim 1, wherein the thickness of the layer of dielectric material is 50 to 100 microns. The method of claim 1.

6. The method according to claim 1, wherein the first surface of the component of the semiconductor device is positioned before covering the second surface of the component with the layer of dielectric material such that a cavity drill is not used to form the space in which the component is disposed. The method of claim 1.

7. The method according to claim 1, further comprising adding a contact formed from the conductive material to the second surface of the component of the semiconductor device before covering the second surface of the component with the layer of dielectric material. The method of claim 1.

8. The method according to claim 1, further comprising repeating at least a part of the method to form a second layer of dielectric material. The method of claim 1.

9. The method according to claim 8, wherein the part of the method is repeated until a predetermined thickness of a substrate core of the semiconductor device is achieved. The method of claim 8.

10. The method according to claim 1, wherein the component of the semiconductor device includes at least one of a capacitor or a voltage regulator. The method of claim 1.

11. A semiconductor substrate comprising: a component; a first through-hole plating electrically connected to a first surface of the component; and a second through-hole plating electrically connected to a second surface of the component on the opposite side of the first surface. The component, the upper surface of the first plated through hole, and the bottom surface of the second plated through hole are embedded in a dielectric layer formed from a uniform dielectric material. Semiconductor substrate. **Claim 12** The dielectric material is a prepreg. The semiconductor substrate of claim 11. **Claim 13** The first plated through hole is positioned such that the pitch of the plated through hole pattern is less than 350 microns. The semiconductor substrate of claim 11. **Claim 14** The first plated through hole is positioned such that the pitch of the plated through hole pattern is 250 microns. The semiconductor substrate of claim 11. **Claim 15** The thickness of the dielectric layer is 50 to 100 microns. The semiconductor substrate of claim 11. **Claim 16** The first surface of the component of the semiconductor substrate is positioned before covering the second surface of the component with the dielectric layer so that a cavity drill is not used to form a space in which the component is disposed. The semiconductor substrate of claim 11. **Claim 17** Comprising a contact formed of a conductive material on the second surface of the component of the semiconductor substrate. The semiconductor substrate of claim 11. **Claim 18** The semiconductor substrate is formed from at least three layers of the dielectric material. The semiconductor substrate of claim 11. **Claim 19** At least three layers of the dielectric material are formed from prepregs. The semiconductor substrate of claim 18. **Claim 20** A method comprising: Positioning a first surface of a first component of a semiconductor device over a first plated through hole; Covering at least a second surface of the first component, which is on the opposite side of the first surface of the first component, with a first layer of a dielectric material; Removing a portion of the first layer of the dielectric material covering the second surface of the first component to form at least one first cavity; Depositing a conductive material in the first cavity to form a second plated through hole on the second surface of the first component; Repeating a portion of the method for a second component to form a second cavity in a second layer of the dielectric material and embed the second component in the second layer of the dielectric material over the first layer of the dielectric material. Method.

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