Wafer processing and hybrid bonding separation of layers formed on different wafers of a semiconductor assembly

Abstract

A method for forming a semiconductor assembly, comprising forming a first set of layers on a first wafer, wherein one or more layers of the first set comprise one or more devices of the semiconductor assembly. The method further comprises forming a second set of layers on a second wafer, wherein the one or more layers of the second set comprise connections between one or more of the devices of the semiconductor assembly. The method further comprises bonding the first set of layers to the second set of layers using metal-to-metal hybrid bonds.

Description

[Background technology]

[0001] As the number of components, such as transistors, in a semiconductor assembly increases, the number of layers for interconnecting the components of the semiconductor assembly also increases. Forming an increased number of layers increases the cycle time for manufacturing the semiconductor assembly. In addition to increasing the overall time to manufacture the semiconductor assembly, increasing the number of layers for interconnecting the components of the semiconductor assembly increases the likelihood of manufacturing defects when manufacturing the semiconductor assembly. [Brief explanation of the drawings]

[0002] [Figure 1] 1A-1C are cross-sectional views of a conventional manufacturing process for a semiconductor assembly. [Figure 2] 1 is a portion of a process flow for manufacturing a semiconductor assembly including layers connected by hybrid metal-to-metal bonds, according to some embodiments. [Figure 3] 1 is a portion of a process flow for manufacturing a semiconductor assembly including layers connected by hybrid metal-to-metal bonds, according to some embodiments. [Figure 4] 1 is a portion of a process flow for manufacturing a semiconductor assembly including a layer and a transition layer connected by a hybrid metal-to-metal bond, according to some embodiments. [Figure 5] 10A-10C are cross-sectional views of exemplary couplings of conductive traces in different layers to conductive traces in a transition layer according to some embodiments. [Figure 6] 1 is an exemplary semiconductor assembly including layers connected by hybrid metal-to-metal bonds, according to some embodiments. [Figure 7] 1 is another exemplary semiconductor assembly including layers connected by hybrid metal-to-metallic bonds, according to some embodiments. [Figure 8] 1 is a cross-sectional view of an exemplary integrated circuit device including a semiconductor assembly including layers connected by hybrid metal-to-metal bonds according to some embodiments. [Figure 9] FIG. 1 illustrates an exemplary computing device, according to some embodiments. [Figure 10] 1 is a flowchart illustrating an exemplary method for manufacturing an integrated circuit device assembly including layers connected by hybrid metal-to-metal bonds, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0003] As the number of components, such as transistors, included in a semiconductor assembly increases, the semiconductor assembly includes an increasing number of layers to connect the various components. For example, a semiconductor assembly includes various metal interconnect layers to connect the different components. With an increasing number of components, an increasing number of metal layers are included in the semiconductor assembly to connect the different components.

[0004] While an increasing number of interconnect layers, such as metal interconnect layers, allows for increased power or performance of the semiconductor assembly, increasing the number of interconnect layers increases the cycle time for manufacturing the semiconductor assembly. Furthermore, increasing the number of interconnect layers increases the likelihood of manufacturing defects from the fabrication of the interconnect layers. Additionally, conventional methods for fabricating interconnect layers expose components of the semiconductor assembly to heat, and therefore, increasing the number of interconnect layers increases the amount of thermal exposure of the components of the semiconductor assembly, which can affect the subsequent performance of the components of the semiconductor assembly.

[0005] FIG. 1 is a cross-sectional view of a conventional manufacturing process for semiconductor assemblies. As shown in FIG. 1, layers 105-125 are applied to wafer 100. In various embodiments, first wafer 100 includes a material such as silicon, silicon dioxide, gallium arsenide, aluminum oxide, or other suitable material. A subset of layers 105-125 are layers in which devices, such as transistors, capacitors, and resistors, that form the semiconductor assembly are formed. For example, layers 105 and 110 are layers in which devices that comprise the semiconductor assembly are formed. Other layers applied to wafer 100 include connections between devices that make up the semiconductor assembly. In the example of FIG. 1, layers 115-125 include connections between devices within the semiconductor assembly. Layers 115-125 include conductive materials, such as metals, for forming connections and conductive paths between devices. In FIG. 1, each layer is applied individually; the layers are applied sequentially. For example, layer 110 is not applied until layer 105 is completely applied to wafer 100. Similarly, layer 115 is not applied until layer 110 is completely applied. This sequential application of layers to wafer 100 increases the overall time to fabricate the semiconductor assembly as the number of layers 105-125 increases. Thus, increasing the number of connections between devices increases the number of layers 115-125 that comprise the connections between the devices, resulting in an increase in the time to fabricate the semiconductor assembly. Furthermore, the formation of layers 115-125 exposes the existing layers of the semiconductor assembly to heat, and as a result, increasing the number of interconnect layers increases the amount of heat exposure to the devices in the semiconductor assembly. Such increased heat exposure increases the likelihood of device performance degradation.

[0006] To that end, this specification describes various embodiments of methods in which a first set of layers of a semiconductor assembly is formed on a first wafer and a second set of layers of the semiconductor assembly is formed on a second wafer. The second set of layers is bonded to the first set of layers by hybrid bonding to form the semiconductor assembly. Forming different sets of layers on different wafers allows the methods described herein to reduce overall manufacturing time by allowing different sets of layers to be formed in parallel, rather than individually forming the layers sequentially on a single wafer, as further described herein. Furthermore, forming different sets of layers on different wafers allows heat applied to device-containing layers of a semiconductor assembly to be reduced by forming the device-containing layers on a wafer separate from the wafer on which one or more layers containing inter-device connections are formed.

[0007] This specification describes various embodiments for forming a semiconductor assembly, including forming a first set of layers on a first wafer, where one or more of the first set of layers include one or more devices of the semiconductor assembly. The method further includes forming a second set of layers on a second wafer, where one or more of the second set of layers include connections between one or more of the devices of the semiconductor assembly. The method further includes bonding the first set of layers to the second set of layers using metal-to-metal hybrid bonds.

[0008] In some embodiments, the first set of layers are bonded to one or more conductive traces included in the transition layer using a metal-to-metal hybrid bond. The second set of layers are bonded to one or more conductive traces included in the transition layer using a metal-to-metal hybrid bond. In some embodiments, the pitch of the one or more conductive traces included in the transition layer is different from the pitch of the conductive traces included in the first set of layers. Additionally, in some embodiments, the pitch of the one or more conductive traces included in the transition layer is different from the pitch of the conductive traces included in the second set of layers.

[0009] In some embodiments, the first set includes a subset of layers that include connections between devices of the semiconductor assembly. In some embodiments, the first set of layers comprises any layer of a subset of layers that includes connections between one or more of the devices of the semiconductor assembly.

[0010] In some embodiments, the second set of layers includes at least one passive component. In some embodiments, the passive component comprises a capacitor. In some embodiments, the capacitor is a super high density metal-insulator-metal capacitor. In some embodiments, the passive component comprises an inductor.

[0011] This specification further describes a semiconductor device including a first set of layers, where one or more of the first set of layers include one or more devices. The semiconductor device further includes a second set of layers, where the second set of layers are coupled to the first set of layers using metal-to-metal hybrid bonds. One or more of the second set of layers includes a connection between one or more of the devices.

[0012] In some embodiments, the semiconductor device further includes a transition layer including one or more conductive traces, wherein the first set of layers is coupled to the one or more conductive traces using a metal-to-metal hybrid bond and the coupled second set of layers is coupled to the one or more conductive traces using a metal-to-metal hybrid bond. In some embodiments, the pitch of the one or more conductive traces included in the transition layer is different from the pitch of the conductive traces included in the first set of layers. Additionally, in some embodiments, the pitch of the one or more conductive traces included in the transition layer is different from the pitch of the conductive traces included in the second set of layers.

[0013] In some embodiments, the layers of the first set include a subset of layers having connections between one or more of the devices. The layers of the first set coupled to the second set using a metal-to-metal hybrid bond are, in some embodiments, any layers of the subset that include connections between one or more of the devices.

[0014] In some embodiments, any layer in the second set of layers includes at least one passive component. In some embodiments, the passive component is a capacitor. In some embodiments, the capacitor is an ultra-high density metal-insulator-metal capacitor. In some embodiments, the passive component comprises an inductor.

[0015] The following disclosure provides many different embodiments or examples for implementing different features of the provided invention. To simplify the disclosure, specific examples of components and configurations are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, a first feature formed above or on a second feature includes embodiments in which the first and second features are formed in direct contact, and also includes embodiments in which an additional feature is formed between the first and second features such that the first and second features are in direct contact. Furthermore, spatially relative terms such as "beneath," "below," "lower," "above," "upper," "back," "front," "top," "bottom," etc. are used herein to facilitate descriptions that describe the relationship of one element or feature to another, as shown in the figures. Similarly, terms such as "front" and "back" or "top" and "back" are used herein to more easily identify various components and identify those components as being on opposite sides of another component, for example. Spatially relative terms are intended to encompass different orientations of the device during use or processing in addition to the orientation shown in the figures.

[0016] 2-4 illustrate steps in an exemplary manufacturing process for a semiconductor assembly including layers connected by hybrid metal-to-metal bonds. Beginning with FIG. 2, layers 205, 210, and 215 are applied to a first wafer 200. In various embodiments, first wafer 200 includes a material such as silicon, silicon dioxide, gallium arsenide, aluminum oxide, or other suitable material. Layers 205, 210, and 215 are referred to herein as a first set of layers 220, and thus, first set of layers 220 are formed on first wafer 200. One or more of first set of layers 220 include devices of the semiconductor assembly. Exemplary components included in layers of first set 220 include transistors, resistors, capacitors, or other suitable devices. Thus, one or more layers in first set 220 include "front end of line" (FEOL) layers of a semiconductor assembly that correspond to layers in a manufacturing process that occur before the formation of interconnect layers, such as metal interconnect layers, and are layers during which devices comprising the semiconductor assembly are fabricated. Thus, the FEOL layers of a semiconductor assembly correspond to layers in a manufacturing process at which devices (e.g., transistors, capacitors, resistors, etc.) comprising the semiconductor assembly are formed.

[0017] In some embodiments, one or more layers of first set 220 are optionally “middle of line” (MOL) layers that include local connections between devices of the semiconductor assembly (e.g., devices formed in one or more FEOL layers) and one or more interconnect layers between different layers of the semiconductor assembly. For example, the MOL layers include gate contacts for transistors in one or more FEOL layers and interconnects between different layers. In some embodiments, the MOL layers provide connections between devices contained within the FEOL layers, and the one or more MOL layers also enable connections between conductive elements in “back end of line” (BEOL) layers, described further below, allowing for a tighter pitch between conductive elements in the BEOL layers.

[0018] In some embodiments, a subset of first set of layers 220 includes connections between devices, also referred to as “back-end-of-line” (BEOL) layers. Thus, the BEOL layers are formed in the manufacturing process after the layers in which the devices comprising the semiconductor assembly are formed (the FEOL layers described further above), and the BEOL layers include one or more connections between the devices comprising the semiconductor assembly. In various embodiments, the BEOL layers begin with a first layer that includes connections between devices and include subsequent layers that include connections between devices. For example, one or more of first set of layers 220 include metal connections that couple the devices of the semiconductor assembly to one another. In different embodiments, first set of layers 220 includes a different number of layers that include connections between the devices of the semiconductor assembly. For example, layer 205 in the example of FIG. 2 is a FEOL layer that includes the devices of the semiconductor assembly, layer 210 in the example of FIG. 2 is a MOL layer, and layer 215 in the example of FIG. 2 is a BEOL layer that includes connections between the devices in layer 205. In another example, layer 205 of the example of FIG. 2 includes devices of a semiconductor assembly, and layers 210 and 215 include connections between the devices included in layer 205.

[0019] 2, a second wafer 230 is used in the manufacturing process. The second wafer 230 is separate and different from the first wafer 200. In various embodiments, the second wafer 230 comprises a material such as silicon, silicon dioxide, gallium arsenide, aluminum oxide, or other suitable material. In some embodiments, the second wafer 230 and the first wafer 200 are a common material, while in other embodiments, the second wafer 230 and the first wafer 200 are different materials.

[0020] Layers 235, 240, 245 are formed on second wafer 230, and layers 235, 240, 245 form a second set of layers 250 on second wafer 230. In various embodiments, one or more layers 235, 240, 245 of second set 250 include connections between devices included in one or more layers 205, 210, 215 of first set 220. Thus, in various embodiments, second set 250 includes one or more BEOL layers. In other embodiments, each layer 205, 210, 215 of second set 250 is a BEOL layer that includes one or more connections between devices of a semiconductor assembly.

[0021] In various embodiments, the first set of layers 220 is applied to the first wafer 200 in parallel with the application of the second set of layers 250 to the second wafer 230. Such parallel formation of the first set of layers 220 on the first wafer 200 and the second set of layers 250 on the second wafer 230 reduces the time to form the different layers 205, 210, 215, 235, 240, 245 compared to a process in which the layers are formed sequentially on top of each other on a single wafer.

[0022] In some embodiments, the number of layers included in second set 250 is determined to increase the parallel formation of layers on second wafer 230 and layers on first wafer 200. For example, first set of layers 220 includes some BEOL layers including connections between devices of a semiconductor assembly, and second set of layers 250 also includes some BEOL layers including connections between devices of a semiconductor assembly. This allows layers including connections between devices of a semiconductor assembly to be formed in parallel on first wafer 200 and second wafer 230, allowing the total number of layers including connections between devices to be increased while reducing the time to form the total number of layers including connections compared to techniques in which each layer including connections is formed in series on a single wafer, as further described above. In other embodiments, FEOL layers in which devices comprising a semiconductor assembly are formed are formed on first wafer 200, and BEOL layers including connections between devices in the FEOL layers are formed on second wafer 230. Such formation of connections between devices on the first wafer 200 and devices on the second layer 230 reduces the heat applied to the devices during formation of the connections between the devices, preventing degradation of device performance from heat exposure.

[0023] In some embodiments, the layers in the second set of layers 250 include a subset of layers that include connections between devices of the semiconductor assembly, and the layers in the first set of layers 230 include another subset of layers that include connections between devices of the semiconductor assembly. In some embodiments, the subset of layers that include connections between devices of the semiconductor assembly include connections of a different pitch than the other subset of layers. Thus, in various embodiments, the first set of layers 230 includes layers having one or more pitches of connections that meet one or more criteria, and the second set of layers 250 includes layers having one or more pitches of connections that meet one or more alternative criteria. However, in other embodiments, the inclusion of layers that include connections between devices in the first set of layers 230 in the second set of layers 250 is based on other criteria.

[0024] In FIG. 3 , a layer of the second set of layers 250 formed on the second wafer 230 is bonded to a layer of the first set of layers 220 formed on the first wafer 200. For illustrative purposes, FIG. 3 shows layer 245 of the second set of layers 250 bonded to layer 215 of the first set of layers 220. Thus, in some embodiments, the most recently formed layer of the second set of layers 250 is bonded to the most recently formed layer of the first set of layers 220. In various embodiments, layer 245 of the second set of layers 250 includes a connection between devices of the semiconductor assembly, and layer 215 of the first set of layers 220 includes an additional connection between devices of the semiconductor assembly. Thus, in some embodiments, layer 245 and layer 215 are both BEOL layers. The layers of the second set 250 and the first set 220 are bonded via a metal-to-metal hybrid bond. For example, a hybrid metal-to-metal bond may include a dielectric bond having an embedded connecting material (e.g., metal) that is bonded to one or more connecting traces in a layer of the first set 220 and to one or more connecting traces in a layer of the second set 250. To illustrate, Figure 3 shows a hybrid metal-to-metal bond 300 that bonds layer 245 of second set 250 to layer 215 of the first set of layers.

[0025] 4 illustrates an alternative bonding in which a layer of the second set 250 of layers formed on the second wafer 230 is bonded to a layer of the first set 220 of layers formed on the first wafer 200. In the example of FIG. 4, a transition layer 400 is formed between a layer of the second set 250 of layers formed on the second wafer 230 and a layer of the first set 220 of layers formed on the first wafer 200. A surface of the transition layer 400 is bonded to a layer of the second set 250, while an opposite surface of the transition layer 400 is bonded to a layer of the first set 220, the surfaces being parallel to each other and separated by a distance. The transition layer 400 includes conductive traces 405 including a conductive material (e.g., copper) contained in another material, such as a dielectric material. Conductive traces or other connections in the layers of the first set 220 are coupled to conductive traces 405 in the transition layer 400, which are coupled to other conductive traces or other connections in the layers of the second set 250. In various embodiments, the transition layer 400 includes multiple conductive traces 405, allowing different conductive traces in the layers of the first set 220 to be coupled to different conductive traces in the layers of the second set 250. The conductive traces 405 in the transition layer 400 are coupled to the conductive traces in the layers of the first set 220 using hybrid metal-to-metal bonds, as further described above. Similarly, the conductive traces 405 in the transition layer 400 are coupled to the conductive traces 405 in the layers of the second set 250 using hybrid metal-to-metal bonds, coupling the conductive traces in the layers of the first set 220 to the conductive traces in the layers of the second set 250 via the conductive traces 405 in the transition layer 400.

[0026] FIG. 5 shows a cross section of an exemplary bonding of conductive traces in different layers to conductive traces in transition layer 400. For illustration purposes, FIG. 5 shows layer 215 from first set of layers 220 bonded to transition layer 400 and layer 245 from second set of layers 250 bonded to transition layer 400. As shown in FIG. 5, layer 215 includes conductive trace 500. Similarly, transition layer 400 includes a conductive trace, and layer 245 includes conductive trace 510. In the embodiment illustrated by FIG. 5, the pitch between conductive traces 505 in transition layer 400 is different from the pitch between conductive traces 500 in layer 215 and different from the pitch between conductive traces 510 in layer 245. In other embodiments, the pitch between conductive traces 500 in layer 215 is different from at least one of the pitch between conductive traces 500 in layer 215 and the pitch between conductive traces 510 in layer 245. For example, the pitch between conductive traces 500 in transition layer 400 is smaller than the pitch between conductive traces 500 in layer 215 and the pitch between conductive traces 510 in layer 245. In the example described above, the reduced pitch between conductive traces 500 in layer 215 allows transition layer 400 to fan out the pitch between conductive traces on either layer 215 or layer 245 to facilitate hybrid metal-to-metal bonding, and then transition back to a pitch corresponding to the pitch between conductive traces in layer 215 or layer 245.

[0027] Referring to FIG. 6 , an exemplary semiconductor assembly 600 is shown including layers connected by hybrid inter-metallic bonds. In the example illustrated by FIG. 6 , the semiconductor assembly includes a first wafer 200 and a first set of layers 220 formed on the first wafer 200. In the example of FIG. 6 , layer 215 of the first set of layers is bonded to transition layer 400, which is bonded to layer 245 of a second set of layers 250 formed on a second wafer 230, as shown in FIG. 2 . Conductive traces in layer 215 are bonded to conductive traces in transition layer 400 using hybrid inter-metallic bonds, and conductive traces in transition layer 400 are bonded to conductive traces in layer 245 using hybrid inter-metallic bonds. However, in other embodiments, conductive traces in layer 215 are bonded directly to conductive traces in layer 245 using hybrid inter-metallic bonds, and thus layer 215 is bonded directly to layer 245 without transition layer 400. The remaining layers in second set of layers 250 are also included in semiconductor assembly 600 as a result of bonding layer 215 to layer 245. As shown in FIG. 6 , second wafer 230 on which second set of layers 250 was formed is removed when semiconductor assembly 600 after layer 215 is bonded to layer 245.

[0028] FIG. 7 illustrates another exemplary semiconductor assembly 700 including layers connected by hybrid metal-to-metal junctions. In FIG. 7 , one or more devices 705 comprising the semiconductor assembly 700 are illustrated within a layer 205 of the first set of layers 220. For example, the devices 705 include one or more transistors. However, one or more of the devices 705 are other components (e.g., resistors, capacitors, etc.) in various embodiments. In various embodiments, at least one of the devices 705 is an active device (e.g., a transistor, a diode, etc.). In various embodiments, different devices 705 are connected to each other through one or more of the layers in the first set of layers 220, through one or more of the layers in the second set of layers 250, or through a combination of layers in the first set of layers 220 and the second set of layers 250. Thus, one or more layers in the second set of layers 250 include conductive traces configured to couple to one or more devices 705. In some embodiments, a subset of the first set of layers 220 includes conductive traces configured to couple to one or more devices 705.

[0029] In the example semiconductor assembly 700 shown in FIG. 7 , one or more layers of the second set of layers 250 include, for illustrative purposes, one or more passive components 710. Exemplary passive components 710 include capacitors, resistors, inductors, or other suitable devices. For example, in some embodiments, the passive components 710 are capacitors. In a more specific example, the passive components 710 are ultra-high density metal-insulator-metal capacitors. However, in different embodiments, different passive components 710 or combinations of passive components 710 are included in one or more layers of the second set of layers 250. In various embodiments, the passive components 710 are connected to each other or to the devices 705 through one or more of the layers in the second set of layers 250 or through combinations of layers in the first set of layers 220 and the second set of layers 250. Thus, one or more layers of the second set of layers 250 include conductive traces configured to be coupled to one or more devices 705 or one or more passive components 710. In some embodiments, a subset of first set of layers 220 includes conductive traces configured to be coupled to one or more devices 705 or to one or more passive components 710. Inclusion of passive components 710 in one or more layers of second set 250 is optional in different embodiments. Inclusion of one or more passive components 710 in one or more layers of second set 250 allows passive components to be included without increasing the cycle time for manufacturing semiconductor assembly 700 because passive components 710 can be included in a layer formed on a wafer separate from the wafer on which devices 705 and layers in first set of layers 220 are formed, as opposed to sequential formation of layers on a single wafer, in which passive components 710 are formed in the last layer containing the interconnections between devices in the semiconductor assembly, which increases the overall time to complete manufacturing of the semiconductor assembly.

[0030] FIG. 8 is a cross-sectional view of an exemplary integrated circuit device 800 including a semiconductor assembly including layers connected by hybrid metal-to-metal bonds, in accordance with some embodiments of the present disclosure. The exemplary integrated circuit device 800 can be implemented in various computing devices, including mobile devices (as shown in FIG. 9), personal computers, peripheral hardware components, gaming devices, set-top boxes, smartphones, etc. The exemplary integrated circuit device 800 of FIG. 8 includes a die 805. The die 805 is a block of semiconductor material, such as silicon, on which a functional integrated circuit is fabricated. By way of example, the die 805 includes a processor, such as a central processing unit (CPU), a graphics processing unit (GPU), or other processor, as can be appreciated. In various embodiments, the die 805 includes a semiconductor assembly including layers connected by hybrid metal-to-metal bonds, as further described above in connection with FIGS. 2-6.

[0031] As an example, die 805 includes a processor 905 of a computing device 900, as shown in Figure 9. Computing device 900 may be implemented as, for example, a desktop computer, a laptop computer, a server, a game console, a smartphone, a tablet, etc. In addition to one or more processors 905, computing device 900 includes memory 910. Memory 910 may include random access memory (RAM) or other volatile memory. Memory 910 may also include non-volatile memory, such as disk storage or solid-state storage.

[0032] In some embodiments, computing device 900 includes one or more network interfaces 915. In some embodiments, network interface 915 includes a wired network interface 915, such as an Ethernet or another wired network connection, as may be appreciated. In some embodiments, network interface 915 includes a wireless network interface 915, such as a WiFi, BLUETOOTH, cellular, or other wireless network interface 915, as may be appreciated. In some embodiments, computing device 900 includes one or more input devices 920 that accept user input. Exemplary input devices 920 include a keyboard, a touchpad, a touchscreen interface, etc. Those skilled in the art will understand that in some embodiments, input device 920 includes peripheral devices such as an external keyboard, a mouse, etc.

[0033] In some embodiments, computing device 900 includes a display 925. In some embodiments, display 925 includes an external display connected via a video or display port. In some embodiments, display 925 is housed within the housing of computing device 900. For example, display 925 includes the screen of a tablet, laptop, smartphone, or other mobile device. In embodiments in which display 925 includes a touchscreen, display 925 also functions as input device 920.

[0034] Die 805 is coupled to substrate 810. Substrate 810 is a piece of material that provides mechanical support for coupled components, such as die 805. In some embodiments, substrate 810 electrically couples various components mounted to substrate 810 via conductive traces, tracks, pads, etc. For example, substrate 810 electrically couples components of die 805 to one or more other components via connecting traces and solder joints formed from solder balls coupled to conductive pads. In some embodiments, substrate 810 includes a printed circuit board (PCB), while in other embodiments, substrate 810 is another semiconductor device, such as die 805 (which may include active components therein). In some embodiments, die 805 is coupled to substrate 810 via a socket (not shown), to which die 805 is soldered or otherwise attached. In other embodiments, as shown in FIG. 8 , die 805 is directly coupled to substrate 810 via a direct solder connection or other connection, as can be appreciated. In some embodiments, die 805 is coupled to substrate 810 using a land grid array (LGA), a pin grid array (PGA), or other packaging technology as can be appreciated.

[0035] For further explanation, FIG. 10 sets forth a flowchart illustrating an exemplary method for fabricating an integrated circuit device assembly including layers connected by hybrid metal-to-metal bonds. The method illustrated in FIG. 10 includes forming 1005 a first set 220 of layers on a first wafer 200, as described above in connection with FIG. 2. One or more layers of the first set 220 include devices that comprise the integrated circuit device assembly. For example, a layer of the first set 220 includes one or more transistors. In various embodiments, other devices, such as resistors, capacitors, diodes, inductors, or other devices, are included in the layers of the first set. In various embodiments, different devices or combinations of devices that make up the integrated circuit device assembly are included in the layers 1005 formed on the first wafer 200. In various embodiments, a different number of layers of the first set 220 include devices that comprise the integrated circuit device assembly. In some embodiments, a subset of the layers of the first set 220 includes connections between devices that comprise the integrated circuit device assembly.

[0036] A second set of layers 250 is formed (1010) on the second wafer 230, with one or more layers of the second set 250 including connections between devices that comprise the integrated circuit device assembly. The second wafer 230 is different from the first wafer 200, and thus the first set of layers and the second set of layers are each formed on different wafers. For example, one or more layers of the second set 250 include conductive traces configured to couple connections of devices comprising the integrated circuit device assembly in a layer of the first set 220 to another device included in the layer of the first set 220 (or to another device in a different layer of the first set 220). In some embodiments, the layers of the second set 250 include connections for coupling devices in the layers of the first set 220 to components within the layers of the second set 250. The formation of the second set of layers 250 is further described above in connection with FIG. 2 .

[0037] In some embodiments, one or more layers of second set 250 include one or more passive components, as further described above in connection with FIG. 7 . Exemplary passive components include capacitors, resistors, inductors, or other suitable devices. For example, in some embodiments, the passive components are capacitors. In a more specific example, the passive components are ultra-high density metal-insulator-metal capacitors. However, in different embodiments, different passive components or combinations of passive components are included in one or more layers of second set 250. In various embodiments, one or more layers of second set 250 include connections between passive components or between passive components and one or more devices included in one or more layers of first set 220. In some embodiments, passive components are included in multiple layers of second set 250.

[0038] The layers of the second set 250 are bonded 1015 to the layers of the first set 220 using inter-metallic hybrid bonds. For example, the inter-metallic hybrid bonds include a dielectric bond with an embedded interconnect material (e.g., metal) that is bonded to one or more connection traces in the layers of the first set 220 and to one or more connection traces in the layers of the second set 250. In some embodiments, the layers of the first set 220 are bonded directly to the layers of the second set 250 using inter-metallic hybrid bonds. In other embodiments, the conductive traces in the layers of the first set 220 are bonded to one or more conductive traces included in the transition layer 400 using inter-metallic hybrid bonds, and the conductive traces in the layers of the second set 250 are bonded to one or more conductive traces included in the transition layer 400 using inter-metallic hybrid bonds. In such embodiments, the layers of the first set 220 are bonded to the transition layer 400, which is also bonded to the layers of the second set 250, as shown above in connection with FIG. 4. In various embodiments, the pitch of the conductive traces in transition layer 400 is different from the pitch of the conductive traces in the layers of first set 220 or different from the pitch of the conductive traces in the layers of second set 250. In some embodiments, the pitch of the conductive traces included in transition layer 400 is different from the pitch of the conductive traces included in the layers of first set 220 and different from the pitch of the conductive traces included in the layers of second set 250, as further described above in connection with FIG.

[0039] In embodiments in which first set of layers 220 includes a subset of layers that include connections between devices that comprise the integrated circuit device assembly, the layers of first set 220 that are coupled (1015) to layers of second set 250 are layers of the subset that include connections between devices that comprise the integrated circuit device assembly. Such embodiments allow a subset of connections between devices that comprise the integrated circuit device assembly to be established through first set of layers 220, while using layers of second set of layers 250 to establish additional connections between c devices that comprise the integrated circuit device assembly. This allows an increased number of connections between devices that comprise the integrated circuit device assembly to be established without increasing the time to manufacture the integrated circuit device assembly by forming first set of layers 220 on first wafer 200 while forming second set of layers 250 on a different second wafer 230.

[0040] In light of the above discussion, the reader will appreciate that fabricating an integrated circuit device assembly including layers from a first set formed on a first wafer bonded to layers from a second set formed on a second wafer using metal-to-metal hybrid bonding allows an increased number of connections to be made between devices comprising the integrated circuit device assembly without significantly increasing the manufacturing time for the integrated circuit device assembly. Such fabrication allows different layers of the integrated circuit device assembly to be formed in parallel on different wafers, and allows the layers formed on the different wafers to be bonded to one another using metal-to-metal hybrid bonding. Additionally, forming different sets of layers on different wafers prevents degradation of the devices comprising the integrated circuit device assembly by reducing the amount of time the devices are exposed to heat when forming layers having interconnections between the devices, since one or more of the layers having interconnections between the devices are formed on a wafer separate from the wafer containing the devices comprising the integrated circuit device assembly.

[0041] It will be understood from the foregoing description that modifications and variations can be made in various embodiments of the present disclosure. The description herein is for illustrative purposes only and should not be construed in a limiting sense. The scope of the present disclosure is limited only by the language of the following claims.

Claims

1. 1. A method for forming a semiconductor assembly, comprising: forming a first set of layers on a first wafer, one or more layers of the first set including one or more devices of the semiconductor assembly; forming a second set of layers on a second wafer, one or more layers of the second set including connections between one or more of the devices of the semiconductor assembly; and bonding the first set of layers to the second set of layers using metal-to-metal hybrid bonds. method.

2. forming the first set of layers on the first wafer and forming the second set of layers on the second wafer are performed in parallel.

10. The method of claim 1.

3. Bonding the first set of layers to the second set of layers using metal-to-metal hybrid bonds includes: coupling the first set of layers to one or more conductive traces included in a transition layer using a metal-to-metal hybrid bond; and bonding the second set of layers to the one or more conductive traces included in the transition layer using a metal-to-metal hybrid bond.

10. The method of claim 1.

4. the pitch of the one or more conductive traces in the transition layer is different from the pitch of the conductive traces in the first set of layers; The method of claim 3.

5. the pitch of the one or more conductive traces in the transition layer is different from the pitch of the conductive traces in the second set of layers; The method of claim 4.

6. the first set of layers includes a subset of layers that includes connections between one or more of the devices of the semiconductor assembly; 10. The method of claim 1.

7. the first set of layers comprises any layer of the subset of layers that includes connections between one or more of the devices of the semiconductor assembly; The method of claim 6.

8. any layer of the second set of layers on the second wafer includes at least one passive component; 10. The method of claim 1.

9. The passive components include capacitors.

9. The method of claim 8.

10. the capacitor comprises an ultra-high density metal-insulator-metal capacitor; 10. The method of claim 9.

11. The passive components include an inductor; 9. The method of claim 8.

12. A semiconductor device comprising: a first set of layers, wherein one or more layers of the first set include one or more devices; a second set of layers, the second set of layers being coupled to the first set of layers using metal-to-metal hybrid bonds, and one or more layers of the second set comprising connections between one or more of the devices; Semiconductor devices.

13. a transition layer including one or more conductive traces; the first set of layers are coupled to the one or more conductive traces using metal-to-metal hybrid bonds; the second set of layers are coupled to the one or more conductive traces using metal-to-metal hybrid bonds; The semiconductor device of claim 12.

14. the pitch of the one or more conductive traces in the transition layer is different from the pitch of the conductive traces in the first set of layers; The semiconductor device of claim 13.

15. the pitch of the one or more conductive traces in the transition layer is different from the pitch of the conductive traces in the second set of layers; 15. The semiconductor device of claim 14.

16. the first set of layers includes a subset of layers that includes connections between one or more of the devices; The semiconductor device of claim 12.

17. the first set of layers comprises any layer of the subset of layers that includes a connection between one or more of the devices; 17. The semiconductor device of claim 16.

18. any layer of the second set of layers includes at least one passive component; The semiconductor device of claim 12.

19. The passive components include capacitors.

20. The semiconductor device of claim 18.

20. The passive components include an inductor; 20. The semiconductor device of claim 18.

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