Display device and manufacturing method thereof

Abstract

According to one embodiment, the display device includes at least a substrate including a flat region and a trench region recessed from the flat region, an electrode pattern disposed on the substrate and including a recess bent along a profile of the trench region of the substrate, a planarization layer inserted in the recess, a first insulating layer covering the substrate, the electrode pattern, and the planarization layer, and a light emitting element disposed on the first insulating layer, wherein the planarization layer may include an organic / inorganic composite material.

Description

[Technical Field]

[0001] The present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] Display devices have become increasingly important with the development of multimedia, and various types of display devices, such as organic light emitting displays (OLEDs) and liquid crystal displays (LCDs), are now being used.

[0003] Display devices include display panels, such as light-emitting display panels and liquid crystal display panels, that display images. Light-emitting display panels include light-emitting elements. Examples of light-emitting elements include light-emitting diodes (LEDs). Light-emitting diodes include organic light-emitting diodes (OLEDs) that use organic materials as fluorescent materials and inorganic light-emitting diodes that use inorganic materials as fluorescent materials. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device that prevents a decrease in device reliability due to the thickness of wiring or electrodes.

[0005] Another object of the present invention is to provide a method for manufacturing a display device that prevents a decrease in device reliability due to the thickness of wiring or electrodes.

[0006] The problems to be solved by the present invention are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0007] According to one embodiment of the present invention, a display device includes at least a substrate including a flat region and a trench region recessed from the flat region, an electrode pattern disposed on the substrate and including a recess bent along a profile of the trench region of the substrate, a planarization layer inserted into the recess, a first insulating layer covering the substrate, the electrode pattern, and the planarization layer, and a light-emitting element disposed on the first insulating layer, wherein the planarization layer may include an organic / inorganic composite material.

[0008] According to another embodiment of the present invention, a display device includes at least a first insulating layer disposed on a substrate and including a flat region and a trench region recessed from the flat region; an electrode pattern disposed on the substrate and including a recess bent along a profile of the trench region; a planarization layer inserted into the recess; a second insulating layer covering the first insulating layer, the electrode pattern, and the planarization layer; and a light-emitting element disposed on the second insulating layer, wherein the planarization layer may include an organic / inorganic composite material.

[0009] According to one embodiment of the present invention, a method for manufacturing a display device may include at least the steps of: preparing a substrate; forming a flat region and a trench region recessed from the flat region on the substrate; forming an electrode material layer on the substrate, the electrode material layer being partially curved along a profile of the trench region; forming an organic / inorganic composite material layer on the electrode material layer; etching the organic / inorganic composite material layer to form a planarization layer on a portion of the electrode material layer; selectively etching a portion of the electrode material layer that is not covered by the planarization layer; and forming a first insulating layer on the flat region of the substrate, the planarization layer, and the electrode material layer. [Effects of the Invention]

[0010] In the display device according to the embodiment, the reliability of the device can be improved.

[0011] A method for manufacturing a display device according to an embodiment can provide a display device with improved device reliability.

[0012] The effects of the embodiments are not limited to the above examples, and a wider variety of effects are included in this specification. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a schematic perspective view of an electronic device according to an embodiment. [Figure 2] 1 is a perspective view illustrating a display device included in an electronic device according to an embodiment. [Figure 3] 1 is a plan view illustrating a display panel of a display device according to an embodiment. [Figure 4] 1 is a cross-sectional view showing a schematic structure of one pixel of a display device according to an embodiment. [Figure 5] FIG. 5 is an enlarged view of region A1 in FIG. 4. [Figure 6] 1A to 1C are diagrams illustrating a process for manufacturing a display device according to an embodiment. [Figure 7] 1A to 1C are diagrams illustrating a process for manufacturing a display device according to an embodiment. [Figure 8] 1A to 1C are diagrams illustrating a process for manufacturing a display device according to an embodiment. [Figure 9] 1A to 1C are diagrams illustrating a process for manufacturing a display device according to an embodiment. [Figure 10] 1A to 1C are diagrams illustrating a process for manufacturing a display device according to an embodiment. [Figure 11] 1A to 1C are diagrams illustrating a process for manufacturing a display device according to an embodiment. [Figure 12] 1A to 1C are diagrams illustrating a process for manufacturing a display device according to an embodiment. [Figure 13] 1A to 1C are diagrams illustrating a process for manufacturing a display device according to an embodiment. [Figure 14] FIG. 10 is a cross-sectional view showing a schematic structure of one pixel of a display device according to another embodiment. [Figure 15] FIG. 10 is a cross-sectional view showing a schematic structure of one pixel of a display device according to still another embodiment. [Figure 16] FIG. 10 is a cross-sectional view showing a schematic structure of one pixel of a display device according to still another embodiment. [Figure 17] FIG. 17 is an enlarged view of the A2 region in FIG. [Figure 18] 17A to 17C are diagrams for explaining the steps of manufacturing the display device according to the embodiment of FIG. 16. [Figure 19] 17A to 17C are diagrams for explaining the steps of manufacturing the display device according to the embodiment of FIG. 16. [Figure 20] 17A to 17C are diagrams for explaining the steps of manufacturing the display device according to the embodiment of FIG. 16. [Figure 21] FIG. 10 is a cross-sectional view showing a schematic structure of one pixel of a display device according to still another embodiment. [Figure 22] FIG. 10 is a cross-sectional view showing a schematic structure of one pixel of a display device according to still another embodiment. [Figure 23] FIG. 10 is a cross-sectional view showing a schematic structure of one pixel of a display device according to still another embodiment. [Figure 24] FIG. 10 is a cross-sectional view showing a schematic structure of one pixel of a display device according to still another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0014] The advantages and features of the present invention, as well as methods for achieving them, will become clearer with reference to the following detailed embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be realized in various different forms. The present embodiments are provided solely for the purpose of complete disclosure of the present invention and to fully convey the scope of the invention to those skilled in the art to which the present invention pertains. The present invention is defined solely by the scope of the claims.

[0015] When an element or layer is referred to as "above" another element or layer, this includes either being directly above or having intervening layers or elements. Similarly, when references are made to "below," "left," and "right," this includes either being directly adjacent to or having intervening layers or elements. Like reference numbers refer to like elements throughout the specification.

[0016] Although terms such as "first" and "second" are used to describe various components, it is understood that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it is understood that a "first" component referred to below may be a "second" component within the technical concept of the present invention.

[0017] The features of the various embodiments of the present invention may be partially or wholly combined or combined with one another, and may be technically interlocked and driven in various ways, and each embodiment may be implemented independently of the others or in conjunction with one another.

[0018] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0019] FIG. 1 is a schematic perspective view of an electronic device according to an embodiment.

[0020] 1, an electronic device 1 displays moving or still images. The electronic device 1 refers to any electronic device that provides or includes a display screen. Examples of electronic devices that provide a display screen include televisions, laptops, monitors, billboards, the Internet of Things, mobile phones, smartphones, tablet PCs (Personal Computers), electronic watches, smart watches, watch phones, head-mounted displays, mobile communication terminals, electronic organizers, e-books, PMPs (Portable Multimedia Players), navigation systems, game consoles, digital cameras, and camcorders.

[0021] FIG. 1 defines a first direction DR1, a second direction DR2, and a third direction DR3. The first direction DR1 and the second direction DR2 are perpendicular to each other, and the first direction DR1 and the third direction DR3 may be perpendicular to each other. The first direction DR1 refers to the horizontal direction in the drawing, the second direction DR2 refers to the vertical direction in the drawing, and the third direction DR3 refers to the top and bottom direction in the drawing, i.e., the thickness direction. In the following description, unless otherwise specified, a "direction" refers to both directions extending along that direction. Furthermore, when it is necessary to distinguish between "directions" extending along both sides, one side will be referred to as the "first direction" and the other side as the "second direction." Referring to FIG. 1, the direction indicated by an arrow pointing in a direction will be referred to as one side, and the opposite direction will be referred to as the other side.

[0022] Hereinafter, for convenience of explanation, when referring to the surfaces of the electronic device 1 or each component constituting the electronic device 1, the surface facing the direction in which an image is displayed, i.e., one side in the third direction DR3, will be referred to as the top surface, and the surface opposite to the top surface will be referred to as the bottom surface. However, without being limited thereto, the one surface and the other surface of the component will also be referred to as the front surface and the back surface, respectively, and also as the first surface and the second surface. Furthermore, when describing the relative positions of each component of the electronic device 1, one side in the third direction DR3 will be referred to as the top surface, and the other side in the third direction DR3 will be referred to as the bottom surface.

[0023] The electronic device 1 may include a display device ('10' in FIG. 2) that provides a display screen. Examples of the display device include an inorganic light emitting diode display device, an organic light emitting display device, a quantum dot light emitting display device, a plasma display device, and a field emission display device. Hereinafter, a case where an organic light emitting display device is applied as an example of the display device will be described, but the present invention is not limited thereto, and may be applied to other display devices as long as the same technical concept is applicable.

[0024] The shape of the electronic device 1 can be varied in various ways. For example, the electronic device 1 can have a horizontally long rectangle, a vertically long rectangle, a square, a rectangle with rounded corners (vertices), other polygonal shapes, a circle, or the like. The shape of the display area DA of the electronic device 1 is also similar to the overall shape of the electronic device 1. FIG. 1 illustrates an example of an electronic device 1 having a rectangular shape with a long length in the second direction DR2.

[0025] The electronic device 1 may include a display area DA and a non-display area NDA. The display area DA is the area where the screen is displayed, and the non-display area NDA is the area where the screen is not displayed. The display area DA is also called the active area, and the non-display area NDA is also called the inactive area. The display area DA generally occupies the center of the electronic device 1.

[0026] FIG. 2 is a perspective view showing a display device included in an electronic device according to an embodiment.

[0027] 1 and 2 , an electronic device 1 according to an embodiment may include a display device 10. The display device 10 provides a display screen for the electronic device 1. The display device 10 may have a planar shape similar to that of the electronic device 1. For example, the display device 10 may have a shape similar to a rectangle having a short side in a first direction DR1 and a long side in a second direction DR2. The corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be rounded to have a curvature, but is not limited thereto and may also be a right angle. The planar shape of the display device 10 is not limited to a rectangle and may be formed in various shapes such as a polygon, a circle, or an ellipse.

[0028] The display device 10 may include a display panel 100, a display driver 200, and a circuit board 300. In one embodiment, the display device 10 may further include a touch driver.

[0029] The display panel 100 may include a main area MA and a sub-area SBA.

[0030] The main area MA may include a display area DA including pixels for displaying images and a non-display area NDA arranged around the display area DA. The display area DA emits light from a plurality of light-emitting areas or a plurality of aperture areas, which will be described later. For example, the display panel 100 may include pixel circuits including switching elements, pixel defining layers that define the light-emitting areas or aperture areas, and self-light-emitting elements.

[0031] For example, the self-luminous element may include, but is not limited to, at least one of an organic light-emitting diode (OLED) including an organic light-emitting layer, a quantum dot LED including a quantum dot emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED. In the following embodiments, the self-luminous element is exemplified as an organic light-emitting diode.

[0032] The non-display area NDA may be an area outside the display area DA. The non-display area NDA is defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver (not shown) that supplies gate signals to the gate lines and fan-out lines (not shown) that connect the display driver 200 to the display area DA.

[0033] In this specification, the term "connection" means not only that a component is connected to another component through physical contact, but also that the component is connected via another component. This can also be understood as a single, integrated component, where one part and another part are interconnected by the integrated component. Furthermore, the connection between one component and another component can be interpreted to include not only a direct contact connection, but also an electrical connection via another component.

[0034] The sub-region SBA may be an area extending from one side of the main region MA. The sub-region SBA may include a flexible material that allows bending, folding, rolling, etc. For example, when the sub-region SBA is bent, the sub-region SBA overlaps the main region MA in the thickness direction (third direction DR3). The sub-region SBA may include the display driver 200 and a pad unit connected to the circuit board 300. In other embodiments, the sub-region SBA may be omitted, and the display driver 200 and the pad unit may be disposed in the non-display region NDA.

[0035] The display driver 200 outputs signals and voltages for driving the display panel 100. The display driver 200 supplies data voltages to data lines. The display driver 200 supplies power supply voltages to power lines and gate control signals to the gate driver. The display driver 200 may be formed as an integrated circuit (IC) and mounted on the display panel 100 using a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic bonding method. For example, the display driver 200 may be disposed in the sub-area SBA and may overlap the main area MA in the thickness direction by bending the sub-area SBA. As another example, the display driver 200 may be mounted on a circuit board 300.

[0036] The circuit board 300 is attached onto the pads of the display panel 100 using an anisotropic conductive film (ACF). Lead wires of the circuit board 300 can be electrically connected to the pads of the display panel 100. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0037] FIG. 3 is a plan view showing a display panel of a display device according to an embodiment.

[0038] Referring to FIG. 3, the display panel 100 may include a display area DA and a non-display area NDA.

[0039] The display area DA is disposed in the center of the display panel 100. A plurality of pixels PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power supply lines VL are disposed in the display area DA. Each of the plurality of pixels PX can be defined as a minimum unit or basic unit that emits light.

[0040] The gate lines GL supply gate signals received from the gate driver 210 to the pixels PX. The gate lines GL extend in a first direction DR1 and are spaced apart from each other in a second direction DR2 that intersects with the first direction DR1.

[0041] The plurality of data lines DL supplies the plurality of pixels PX with data voltages received from the display driver 200. The plurality of data lines DL extend in the second direction DR2 and are spaced apart from each other in the first direction DR1.

[0042] The power supply lines VL supply power supply voltages received from the display driver 200 to the pixels PX. Here, the power supply voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a low potential voltage. The power supply lines VL extend in the second direction DR2 and are spaced apart from each other in the first direction DR1.

[0043] The non-display area NDA may surround the display area DA. The non-display area NDA includes a gate driver 210, a fan-out line FOL, and a gate control line GCL. The gate driver 210 generates a plurality of gate signals based on the gate control signal and sequentially supplies the gate signals to the plurality of gate lines GL in a set order.

[0044] The fan-out lines FOL may extend from the display driver 200 to the display area DA. The fan-out lines FOL supply the data voltages received from the display driver 200 to the plurality of data lines DL.

[0045] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL supplies the gate control signal received from the display driver 200 to the gate driver 210.

[0046] The sub-area SBA may include a display driver 200 and a pad area PA.

[0047] The display driver 200 outputs signals and voltages to the fan-out lines FOL to drive the display panel 100. For example, the display driver 200 supplies data voltages to the data lines DL via the fan-out lines FOL. The data voltages can be supplied to a plurality of pixels PX to control the brightness of the plurality of pixels PX. The display driver 200 supplies gate control signals to the gate driver 210 via the gate control lines GCL.

[0048] The pad area PA is disposed on the edge of the sub-area SBA and can be electrically connected to the circuit board 300 using a material such as anisotropic conductive film or SAP (Self Assembly Anisotropic Conductive Paste).

[0049] The pad area PA may include a plurality of display pad units DP, which may be connected to an external system (e.g., a graphic system) via the circuit board 300. The display pad units DP are connected to the circuit board 300 to receive digital video data and provide the digital video data to the display driver 200.

[0050] As described above, a plurality of wires (or electrodes) are arranged on the display panel 100. Since the efficiency of the display device 10 decreases as the resistance acting on the plurality of wires increases, the thickness of the plurality of wires (i.e., the width in the third direction DR3) can be increased to reduce the resistance acting on the plurality of wires.

[0051] However, when the thickness of the wirings (or electrodes) is increased, a step due to the thickness of the wirings occurs when forming other wirings disposed on top of the wirings, which may reduce device reliability. Therefore, in one embodiment, a trench (or trench region) is formed in a substrate or an insulating layer, and the wirings (or electrodes) are disposed in the trench, thereby reducing the step due to the thickness of the wirings (or electrodes).

[0052] 4 is a cross-sectional view showing a schematic structure of one pixel of a display device according to an embodiment, and FIG. 5 is an enlarged view of an A1 region of FIG.

[0053] The cross-sectional structure of the display device 10 according to one embodiment will be described with reference to FIGS.

[0054] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that allows bending, folding, rolling, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate SUB may include a glass material or a metal material.

[0055] The substrate SUB may include a flat region SUBa and a trench region SUBb. The trench region SUBb of the substrate SUB may have a shape recessed from the flat region SUBa of the substrate SUB toward the inside of the substrate SUB, i.e., toward the other side in the third direction DR3. An electrode pattern may be disposed on the trench region SUBb of the substrate so as not to protrude from the flat region SUBa of the substrate SUB. This will be described in detail later.

[0056] A lower metal layer BML is disposed as an electrode pattern on the trench region SUBb of the substrate SUB. The lower metal layer BML can protect the semiconductor layer ACT of the thin film transistor TFT (described later) or block external light.

[0057] The lower metal layer BML is disposed on the trench region SUBb of the substrate SUB, and may be bent along the profile of the trench region SUBb with substantially the same thickness to form a U-shape or other shape. For example, the lower metal layer BML may be bent over the trench region SUBb of the substrate SUB to form a recess (DN,dent portion, see FIG. 9) (or groove) that can accommodate an organic / inorganic composite layer CPXL (described later). This is because the lower metal layer BML is formed by a process such as sputtering in the display device manufacturing process (described later).

[0058] In some embodiments, the bottom metal layer BML is formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto. For convenience of explanation, the following description will focus on the bottom metal layer BML containing molybdenum (Mo).

[0059] The lower metal layer BML may include an exposed surface BMLa exposed between the flat region SUBa of the substrate SUB and an upper surface CPXLa of the organic / inorganic composite layer CPXL (described later). The exposed surface BMLa may be disposed substantially flush with one side surface of the flat region SUBa of the substrate SUB in the third direction DR3. For example, the lower metal layer BML may be disposed only on the trench region SUBb of the substrate SUB, and not on the flat region SUBa. As an example, the lower metal layer BML may not protrude from the substrate SUB to one side of the third direction DR3.

[0060] The organic / inorganic composite layer CPXL is disposed on a depression DN formed by bending the lower metal layer BML. The organic / inorganic composite layer CPXL may serve as a planarizing layer that fills and planarizes the depression DN formed by the lower metal layer BML. For example, the upper surface CPXLa of the organic / inorganic composite layer CPXL may be disposed substantially flush with the flat region SUBa of the substrate SUB and the exposed surface BMLa of the lower metal layer BML.

[0061] The organic / inorganic composite layer CPXL (also referred to as the "planarization layer") can include both organic and inorganic materials. For example, the organic / inorganic composite layer CPXL is a mixture of an organic material and an inorganic material. In some embodiments, the organic material included in the organic / inorganic composite layer CPXL can be a siloxane-based organic material, and the inorganic material can be silicon oxide (SiO2), but is not limited thereto.

[0062] The organic material contained in the organic / inorganic composite layer CPXL can fill and planarize the depression DN formed by the lower metal layer BML with the organic / inorganic composite layer CPXL. Also, the inorganic material contained in the organic / inorganic composite layer CPXL can improve the heat resistance of the organic / inorganic composite layer CPXL under high temperature conditions in the range of 350°C to 400°C, which are process conditions required in the manufacturing process of the display device described below.

[0063] If the organic / inorganic composite layer CPXL contains only organic materials, it can easily fill and planarize the depressions DN formed by the lower metal layer BML, but its heat resistance will be reduced, resulting in relatively large amounts of outgassing under the high temperatures of 350°C to 400°C required in subsequent processes, which may result in cracks. On the other hand, if the organic / inorganic composite layer CPXL contains only inorganic materials, it will have improved heat resistance and emit relatively little outgassing under the high temperatures of 350°C to 400°C required in subsequent processes, but it may not be easy to fill the depressions DN formed by the lower metal layer BML. Therefore, in one embodiment, the organic / inorganic composite layer CPXL may contain both organic and inorganic materials to a certain extent.

[0064] In some embodiments, the organic / inorganic composite layer CPXL may have a higher inorganic material content than the organic material content. For example, the organic / inorganic composite layer CPXL may have an inorganic material content of 60% and an organic material content of 40%, but is not limited to these. This is because a relatively low organic material content can easily fill the depression DN formed by the lower metal layer BML, and increasing the inorganic material content improves the heat resistance of the organic / inorganic composite layer CPXL itself.

[0065] According to the configuration of the above-described embodiment, even if the lower metal layer BML is formed on the substrate SUB, other elements disposed on the substrate SUB are formed on a substantially flat surface, so that steps are not generated, and heat resistance capable of withstanding high temperature processes required in subsequent processes is improved, thereby improving the reliability of the display device 10. Furthermore, according to the above-described embodiment, the organic / inorganic composite layer CPXL disposed on the lower metal layer BML further separates the various elements in the third direction DR3, so that it is possible to prevent parasitic capacitance from occurring between the lower metal layer BML and the organic / inorganic composite layer CPXL without increasing the thickness of the panel.

[0066] The buffer layer BF is disposed on the flat region SUBa of the substrate SUB, the exposed surface BMLa of the lower metal layer BML, and the upper surface CPXLa of the organic / inorganic composite layer CPXL. As described above, in the embodiment, the flat region SUBa of the substrate SUB, the exposed surface BMLa of the lower metal layer BML, and the upper surface CPXLa of the organic / inorganic composite layer CPXL are disposed on substantially the same plane, so that the buffer layer BF can be disposed flat without any steps.

[0067] The buffer layer BF may include an inorganic film that can prevent the penetration of air or moisture. For example, the buffer layer BF may include a plurality of inorganic films that are alternately stacked.

[0068] The thin film transistor TFT is disposed on the buffer layer BF and forms a pixel circuit for each of the pixels. For example, the thin film transistor TFT may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0069] The semiconductor layer ACT is disposed on the buffer layer BF. The semiconductor layer ACT overlaps the lower metal layer BML and the gate electrode GE in the thickness direction (or the third direction DR3), and can be insulated from the gate electrode GE by the gate insulating layer GI.

[0070] The gate electrode GE is disposed on the gate insulating layer GI. In plan view, the gate electrode GE can overlap the semiconductor layer ACT with the gate insulating layer GI therebetween.

[0071] The gate insulating layer GI is disposed on the semiconductor layer ACT. For example, the gate insulating layer GI covers the semiconductor layer ACT and the buffer layer BF and insulates the semiconductor layer ACT from the gate electrode GE. The gate insulating layer GI may include contact holes through which the source electrode SE and the drain electrode DE pass.

[0072] The interlayer insulating layer ILD covers the gate electrode GE and the gate insulating layer GI. The interlayer insulating layer ILD may include contact holes through which the source electrode SE and the drain electrode DE pass. The contact holes in the interlayer insulating layer ILD may be connected to the contact holes in the gate insulating layer GI and the contact holes in the first via insulating layer VIA1.

[0073] A capacitor electrode (not shown) is disposed on the interlayer insulating layer ILD. The capacitor electrode may overlap the gate electrode GE in the third direction DR3. The capacitor electrode and the gate electrode GE may form a capacitance.

[0074] The first via insulating layer VIA1 covers the interlayer insulating layer ILD. The first via insulating layer VIA1 may include contact holes through which the source electrode SE and the drain electrode DE penetrate. The contact holes of the first via insulating layer VIA1 may be connected to the contact holes of the interlayer insulating layer ILD and the contact holes of the gate insulating layer GI.

[0075] The source electrode SE and the drain electrode DE are disposed on the first via insulating layer VIA1. The source electrode SE and the drain electrode DE can be electrically connected to the semiconductor layer ACT of the thin film transistor TFT. For example, the source electrode SE and the drain electrode DE can be inserted into contact holes formed in the first via insulating layer VIA1, the interlayer insulating layer ILD, and the gate insulating layer GI, and can be in contact with the semiconductor layer ACT of the thin film transistor TFT, respectively.

[0076] The second via insulating layer VIA2 covers the source electrode SE, the drain electrode DE, and the first via insulating layer VIA1. The second via insulating layer VIA2 can protect the thin film transistor TFT. The second via insulating layer VIA2 can include a contact hole through which the connection electrode CNE passes.

[0077] The connection electrode CNE is disposed on the second via insulating layer VIA2. The connection electrode CNE can electrically connect the pixel electrode AE ​​of the light-emitting element ED (described later) to the drain electrode DE of the thin-film transistor TFT. The connection electrode CNE can be inserted into a contact hole formed in the second via insulating layer VIA2 and contact the drain electrode DE.

[0078] The third via insulating layer VIA3 covers the connection electrode CNE and the second via insulating layer VIA2. The third via insulating layer VIA3 may include a contact hole through which the pixel electrode AE ​​of the light-emitting element ED passes.

[0079] The light-emitting element ED may include a pixel electrode AE, a light-emitting layer EL, and a common electrode CE.

[0080] The pixel electrode AE ​​is disposed on the third via insulating layer VIA3. The pixel electrode AE ​​is disposed to overlap the opening of the pixel defining layer PDL. The pixel electrode AE ​​can be electrically connected to the drain electrode DE of the thin film transistor TFT via the connection electrode CNE.

[0081] The pixel defining film PDL includes an opening and is disposed on the third via insulating layer VIA3 and a part of the pixel electrode AE. The opening of the pixel defining film PDL can expose a part of the pixel electrode AE.

[0082] The pixel defining layer PDL separates and insulates the pixel electrodes AE of the light emitting elements ED. The pixel defining layer PDL can include a light absorbing material to prevent light reflection. For example, the pixel defining layer PDL can include a polyimide (PI)-based binder and a mixture of red, green, and blue pigments. Alternatively, the pixel defining layer PDL can include a cardo-based binder resin and a mixture of lactam black pigment and blue pigment. Alternatively, the pixel defining layer PDL can include carbon black.

[0083] The light-emitting layer EL is disposed on the pixel electrode AE ​​and a part of the pixel defining film PDL. For example, the light-emitting layer EL may be disposed on one surface of the pixel electrode AE ​​exposed by the opening formed by the pixel defining film PDL and a part of the pixel defining film PDL.

[0084] The light-emitting layer EL may be an organic light-emitting layer made of an organic material. When the light-emitting layer EL is an organic light-emitting layer, when the thin film transistor TFT applies a predetermined voltage to the pixel electrode AE ​​of the light-emitting element ED and the common electrode CE of the light-emitting element ED receives a common voltage or a cathode voltage, holes and electrons may move to the light-emitting layer EL via the hole transport layer and the electron transport layer, respectively, and combine with each other in the light-emitting layer EL to emit light.

[0085] The common electrode CE is disposed on the light-emitting layer EL and the pixel defining film PDL. For example, the common electrode CE may be disposed on the light-emitting layer EL and a portion of the pixel defining film PDL where the light-emitting layer EL is not disposed. Furthermore, the common electrode CE may be mounted over the entire display area DA as an electrode common to all pixels, without being separated for each pixel PX.

[0086] The common electrode CE receives a common voltage or a low potential voltage, and when the pixel electrode AE ​​receives a voltage corresponding to the data voltage and the common electrode CE receives a low potential voltage, a potential difference is formed between the pixel electrode AE ​​and the common electrode CE, causing the light-emitting layer EL to emit light.

[0087] The encapsulation layer TFEL is disposed on the common electrode CE and covers the light-emitting elements ED. In some embodiments, the encapsulation layer TFEL includes at least one inorganic film and at least one organic film, and can prevent foreign substances such as oxygen, moisture, or dust from penetrating into the light-emitting elements EM.

[0088] In an exemplary embodiment, the encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3 stacked in sequence in the third direction DR3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed therebetween may be an organic encapsulation layer.

[0089] The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may each include one or more inorganic insulators, such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0090] The second encapsulating layer TFE2 may include a polymer-based material. Examples of polymer-based materials include acrylic resin, epoxy resin, polyimide, and polyethylene. For example, the second encapsulating layer TFE2 may include an acrylic resin, such as polymethyl methacrylate or polyacrylic acid. The second encapsulating layer TFE2 may be formed by curing a monomer or applying a polymer.

[0091] Hereinafter, an embodiment of a process for forming a lower metal layer BML and an organic / inorganic composite layer CPXL on a substrate SUB will be described.

[0092] 6 to 13 are diagrams illustrating a process for manufacturing a display device according to an embodiment.

[0093] Referring to FIG. 6, a method for manufacturing a display device according to an embodiment may include the steps of: forming a flat region SUBa and a trench region SUBb (or trench) on a substrate SUB (S100); forming a lower metal material layer BML′ on the substrate SUB (S200); forming an organic / inorganic composite material layer CPXL′ on the lower metal material layer BML′ (S300); etching the organic / inorganic composite material layer CPXL′ to form an organic / inorganic composite layer CPXL remaining on the trench region SUBb (S400); etching the lower metal material layer BML′ to form a lower metal layer BML (S500); and forming a first insulating layer, for example, a buffer layer BF, on the lower metal layer BML, the organic / inorganic composite layer CPXL, and the substrate SUB (S600).

[0094] 7 and 8, a flat region SUBa and a trench region SUBb are formed in a substrate SUB (S100). The step of forming the flat region SUBa and the trench region SUBb can be performed using, for example, a mask.

[0095] The trench region SUBb may be a region recessed from the flat region SUBa, as described above. The trench region SUBb does not penetrate the substrate SUB in the third direction DR3.

[0096] 9, a lower metal material layer BML' is formed on the substrate SUB (S200). The process of forming the lower metal material layer BML' is performed by, for example, a sputtering method, but is not limited thereto.

[0097] The lower metal material layer BML' may bend along the profile of the trench region SUBb of the substrate SUB in the trench region SUBb to form a depression DN. For example, the lower metal material layer BML' may have a substantially constant thickness and bend along the profile of the trench region SUBb of the substrate SUB in the trench region SUBb, and therefore the lower metal material layer BML' may include the depression DN.

[0098] The lower metal material layer BML′ is a layer that will become the lower metal layer BML through a subsequent etching process and includes the same material as the lower metal layer BML. In some embodiments, the lower metal material layer BML′ may include, but is not limited to, molybdenum (Mo).

[0099] 10, an organic / inorganic composite layer CPXL' is formed on the lower metal layer BML' (S300), and the organic / inorganic composite layer CPXL' is etched to form an organic / inorganic composite layer CPXL remaining on the trench region SUBb (S400). The process of etching the organic / inorganic composite layer CPXL' is performed by a dry etching method, but is not limited thereto.

[0100] The organic / inorganic composite layer CPXL' is a layer that becomes the organic / inorganic composite layer CPXL after an etching process and contains the same material as the organic / inorganic composite layer CPXL. That is, the organic / inorganic composite layer CPXL' may be a mixture of organic and inorganic materials. In some embodiments, the organic material contained in the organic / inorganic composite layer CPXL' may be a siloxane-based organic material, and the inorganic material may be silicon oxide (SiO2), but is not limited thereto.

[0101] As described above, since the organic / inorganic composite material layer CPXL′ contains both organic and inorganic materials, it can fill the depression DN formed by the lower metal material layer BML′ and reduce or planarize the step formed by the lower metal material layer BML′.

[0102] The process of etching the organic / inorganic composite material layer CPXL′ is performed by dry etching using a first etching gas. The first etching gas is chlorine (Cl) gas, which does not react with the lower metal material layer BML′. Therefore, only the organic / inorganic composite material layer CPXL′ is etched, and as shown in FIG. 11, an organic / inorganic composite material layer CPXL is formed in the depression DN formed by the lower metal material layer BML′.

[0103] That is, the organic / inorganic composite material layer CPXL' is not completely etched, which further simplifies the process.

[0104] 11 and 12, the lower metal layer BML' is etched to form the lower metal layer BML (S500). The process of etching the lower metal layer BML' may be performed by dry etching, but is not limited thereto.

[0105] The process of etching the lower metal layer BML' is performed by dry etching using a second etching gas. The second etching gas is argon (Ar) gas, which does not react with the organic / inorganic composite layer CPXL. Therefore, the region of the lower metal layer BML' that is not covered by the organic / inorganic composite layer CPXL is etched by the second etching gas, while the region that is covered by the organic / inorganic composite layer CPXL is not etched because the organic / inorganic composite layer CPXL acts as an etch stopper.

[0106] 10 to 12 illustrate the use of different etching gases to etch the organic / inorganic composite layer CPXL' and the lower metal layer BML', respectively, but the method for etching the organic / inorganic composite layer CPXL' and the lower metal layer BML' is not limited thereto. For example, the organic / inorganic composite layer CPXL' and the lower metal layer BML' may be simultaneously etched using the same third etching gas. In this case, the etching ratio of the organic / inorganic composite layer CPXL' and the lower metal layer BML' to the third etching gas may be the same.

[0107] 13, a first insulating film, for example, a buffer layer BF, is formed on the lower metal layer BML, the organic / inorganic composite layer CPXL, and the substrate SUB (S600). As described above, the flat region SUBa of the substrate SUB, the exposed surface BMLa of the lower metal layer BML, and the upper surface CPXLa of the organic / inorganic composite layer CPXL are arranged on substantially the same plane, so that the buffer layer BF can be formed flat with substantially no steps.

[0108] Thereafter, the display device 10 can be manufactured by the subsequent processes of forming the semiconductor layer ACT, the gate insulating layer GI, and the like.

[0109] The following describes other embodiments of the display device 10. In the following embodiments, the same components as those in the above-described embodiments are given the same reference numerals, and overlapping or repetitive descriptions are omitted or simplified, with differences being mainly described.

[0110] FIG. 14 is a cross-sectional view showing a schematic structure of one pixel of a display device according to another embodiment.

[0111] Referring to FIG. 14, the lower metal layer BML of the display device 10_1 according to this embodiment is disposed in a trench region formed in a first buffer layer BF1_1 as an insulating layer disposed on a substrate SUB_1.

[0112] The substrate SUB_1 according to an embodiment may have a generally flat surface, for example, the substrate SUB_1 may not have a separate recessed portion formed thereon.

[0113] A first buffer layer BF1_1 and a second buffer layer BF2_1 are sequentially disposed on the substrate SUB_1.

[0114] The first buffer layer BF1_1 is disposed on the substrate SUB_1 and forms a flat region and a trench region. The trench region may be a region recessed from the flat region. In some embodiments, the trench region of the first buffer layer BF1_1 penetrates the first buffer layer BF1_1. For example, the trench region of the first buffer layer BF1_1 may be formed or defined by an opening formed in the first buffer layer BF1_1. However, embodiments are not limited thereto. For example, the trench region of the first buffer layer BF1_1 may not penetrate the first buffer layer BF1_1. FIG. 14 illustrates the trench region of the first buffer layer BF1_1 penetrating the first buffer layer BF1_1. For example, the trench region of the first buffer layer BF1_1 may be formed or defined by a removed portion of the first buffer layer BF1_1. Since the trench region is formed on the first buffer layer BF1_1, the manufacturing process becomes easier.

[0115] The lower metal layer BML is bent along the profile of the trench region of the first buffer layer BF1_1 to form a recess that accommodates the organic / inorganic composite layer CPXL. The lower metal layer BML, the first buffer layer BF1_1, and the organic / inorganic composite layer CPXL provide flat surfaces.

[0116] The second buffer layer BF2_1 is disposed on the first buffer layer BF1_1 and has a flat profile, and serves to electrically insulate the lower metal layer BML from the thin film transistor TFT.

[0117] The first buffer layer BF1_1 and the second buffer layer BF2_1 may include an inorganic film that can prevent the penetration of air or moisture. For example, the first buffer layer BF1_1 and the second buffer layer BF2_1 may include a plurality of inorganic films that are alternately stacked.

[0118] FIG. 15 is a cross-sectional view showing a schematic structure of one pixel of a display device according to still another embodiment.

[0119] Referring to FIG. 15, a display device 10_2 according to one embodiment may include a recess formed by bending the gate electrode GE_2 of the thin film transistor TFT_2, and an organic / inorganic composite layer CPXL_2 that fills the recess (for example, inserted into the recess).

[0120] In one embodiment, the interlayer insulating layer ILD_2 forms a trench region in a region overlapping with the semiconductor layer ACT, and the gate electrode GE_2 of the thin film transistor TFT_2 can be bent along the profile of the trench region of the interlayer insulating layer ILD_2 to form a recess that forms the organic / inorganic composite layer CPXL_2. In this embodiment, the above-mentioned capacitor electrode can also be disposed on the organic / inorganic composite layer CPXL_2.

[0121] The organic / inorganic composite layer CPXL_2 is substantially the same as the organic / inorganic composite layer CPXL of the display device 10 according to the above-described embodiment, and therefore a repeated description thereof will be omitted.

[0122] In some embodiments, the substrate SUB_1 may have a generally flat profile, but is not limited thereto. For example, the substrate SUB_1 may have a trench region formed thereon, similar to the substrate of the display device 10 according to one embodiment, and a lower metal layer may be further disposed thereon.

[0123] 16 is a cross-sectional view showing a schematic structure of one pixel of a display device according to another embodiment. FIG. 17 is an enlarged view of region A2 of FIG.

[0124] 16 and 17, in a display device 10_3 according to an embodiment, a lower metal layer BML_3, which is an electrode pattern disposed in a trench region of a substrate SUB, may be electrically connected to a pixel electrode AE_3.

[0125] The thin film transistor TFT_3 is disposed on the buffer layer BF and constitutes a pixel circuit for each of the pixels. For example, the thin film transistor TFT_3 may be a driving transistor or a switching transistor of the pixel circuit. The thin film transistor TFT_3 may include a semiconductor layer ACT, a source electrode SE_3, a drain electrode DE_3, and a gate electrode GE.

[0126] The semiconductor layer ACT is disposed on the buffer layer BF. The semiconductor layer ACT overlaps the gate electrode GE in the thickness direction and can be insulated from the gate electrode GE by the gate insulating layer GI. Part of the semiconductor layer ACT can be made conductive to form the source electrode SE_3 and the drain electrode DE_3. In this embodiment, the semiconductor layer ACT can include an oxide semiconductor such as ITO or IGZO.

[0127] The light-emitting element ED_3 is disposed on the second via insulating layer VIA2. In this embodiment, the third via insulating layer VIA3 of the display device 10 according to the embodiment can be omitted, but is not limited thereto. Figure 16 illustrates an example in which the third via insulating layer VIA3 of the display device 10 according to the embodiment is omitted.

[0128] The pixel electrode AE_3 of the light emitting element ED_3 can be electrically connected to the drain electrode DE_3 of the thin film transistor TFT_3 via a contact hole that penetrates the gate insulating layer GI, the interlayer insulating layer ILD, the first via insulating layer VIA1, and the second via insulating layer VIA2.

[0129] Furthermore, the pixel electrode AE_3 may be electrically connected to the lower metal layer BML_3 disposed in the trench region of the substrate SUB through a contact hole that penetrates the second via insulating layer VIA2, the first via insulating layer VIA1, the interlayer insulating layer ILD, the gate insulating layer GI, and the buffer layer BF. For example, the pixel electrode AE_3 may be electrically connected to an exposed surface RA of the lower metal layer BML_3 exposed by the substrate SUB and the organic / inorganic composite layer CPXL through a contact hole that penetrates the second via insulating layer VIA2, the first via insulating layer VIA1, the interlayer insulating layer ILD, the gate insulating layer GI, and the buffer layer BF.

[0130] In some embodiments, the lower metal layer BML_3 is formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof, but is not limited thereto. For convenience of explanation, the following description will focus on the case where the lower metal layer BML_3 contains copper (Cu).

[0131] The exposed surface RA of the lower metal layer BML_3 is curved. For example, the exposed surface RA may have a recessed shape on the other side in the third direction DR3. This is due to the manufacturing process for forming the lower metal layer BML_3.

[0132] The process of forming the lower metal layer BML_3 of the display device 10_3 according to the embodiment of FIG. 16 will be described below.

[0133] 18 to 20 are diagrams for explaining the process of manufacturing the display device according to the embodiment of FIG.

[0134] Referring to Figures 18 to 20, a lower metal material layer BML_3' and an organic / inorganic composite material layer CPXL' are sequentially formed on a substrate SUB having a trench region formed therein, the organic / inorganic composite material layer CPXL' is etched to form an organic / inorganic composite layer CPXL, and the lower metal material layer BML_3' is etched to form a lower metal layer BML_3.

[0135] In an embodiment in which the lower metal layer BML_3 includes copper (Cu), the process of forming the lower metal layer BML_3 is difficult to perform using dry etching, and therefore is performed using wet etching using an etching solution. In this embodiment, the lower metal layer BML_3 is etched using wet etching, so the exposed surface RA is curved. For example, the exposed surface RA may have a concave shape on the other side of the third direction DR3. The organic / inorganic composite layer CPXL serves as an etching prevention layer and can prevent the portion of the lower metal layer BML_3 covered by the organic / inorganic composite layer CPXL from being etched.

[0136] FIG. 21 is a cross-sectional view showing a schematic structure of one pixel of a display device according to still another embodiment.

[0137] Referring to Figure 21, the display device 10_4 according to this embodiment differs from the display device 10_3 according to the embodiment of Figure 16 in that the pixel electrode AE_3 penetrates the organic / inorganic composite layer CPXL_4 and is electrically connected to the lower metal layer BML_3, but the other configurations are substantially the same or similar.

[0138] For example, the pixel electrode AE_3 can be electrically connected to the lower metal layer BML_3 through a contact hole that penetrates the second via insulating layer VIA2, the first via insulating layer VIA1, the interlayer insulating layer ILD, the gate insulating layer GI, the buffer layer BF and the organic / inorganic composite layer CPXL_4.

[0139] In this embodiment, the pixel electrode AE_3 is electrically connected to the unetched portion of the lower metal layer BML_3 that overlaps with the organic / inorganic composite layer CPXL_4, instead of the exposed surface of the lower metal layer BML_3, so that the lower metal layer BML_3 and the pixel electrode AE_3 can be electrically connected over a wider area.

[0140] FIG. 22 is a cross-sectional view showing a schematic structure of one pixel of a display device according to still another embodiment.

[0141] Referring to Figure 22, the display device 10_5 according to this embodiment differs from the display device 10_3 according to the embodiment of Figure 16 in that the lower metal layer BML_3 is arranged on the trench region formed by the first buffer layer BF1_1, but the other configurations are substantially the same or similar.

[0142] The substrate SUB_1 according to this embodiment may have a flat surface as a whole, for example, the substrate SUB_1 may not have a separate recessed portion formed thereon.

[0143] A first buffer layer BF1_1 and a second buffer layer BF2_1 are sequentially disposed on the substrate SUB_1. The first buffer layer BF1_1 and the second buffer layer BF2_1 have been described above, and therefore detailed description thereof will be omitted below.

[0144] FIG. 23 is a cross-sectional view showing a schematic structure of one pixel of a display device according to still another embodiment.

[0145] Referring to Figure 23, the display device 10_6 of this embodiment differs from the display device 10 of the embodiment of Figure 4 in that the drain electrode DE_6 of the thin film transistor TFT_6 electrically connects the semiconductor layer ACT and the lower metal layer BML, but the other configurations are substantially the same or similar.

[0146] 23 illustrates an example in which the drain electrode DE_6 electrically connects the semiconductor layer ACT and the lower metal layer BML, but the present invention is not limited to this. For example, the source electrode SE_6 may electrically connect the semiconductor layer ACT and the lower metal layer BML.

[0147] 23 illustrates the gate insulating layer GI covering the semiconductor layer ACT and the buffer layer BF, but the present invention is not limited to this. For example, the gate insulating layer GI may have substantially the same profile as the gate electrode GE disposed thereon. In other words, the gate insulating layer GI may be etched together with the gate electrode GE during the formation of the gate electrode GE, so that the gate insulating layer GI has substantially the same profile as the gate electrode GE and exposes a portion of the semiconductor layer ACT.

[0148] FIG. 24 is a cross-sectional view showing a schematic structure of one pixel of a display device according to still another embodiment.

[0149] Referring to Figure 24, the display device 10_7 according to this embodiment differs from the display device 10_6 according to the embodiment of Figure 23 in that the lower metal layer BML is arranged on the trench region formed by the first buffer layer BF1_1, but the other configurations are substantially the same or similar.

[0150] Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art will understand that the present invention can be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not limiting.

Claims

1. a substrate including a flat region and a trench region recessed from the flat region; an electrode pattern disposed on the substrate and including a recessed portion bent along a profile of the trench region of the substrate; a planarization layer inserted in the recess; a first insulating layer covering the substrate, the electrode pattern, and the planarization layer; a light emitting element disposed on the first insulating layer; The planarization layer comprises an organic / inorganic composite material.

2. The organic / inorganic composite material includes an organic material and an inorganic material, The display device according to claim 1 , wherein the proportion of the inorganic material is greater than the proportion of the organic material.

3. The organic material includes siloxane, The inorganic material is silicon oxide (SiO ２ 3. The display device of claim 2, comprising:

4. the electrode pattern includes the flat area of ​​the substrate and an exposed surface exposed by the planarization layer; The display device according to claim 1 , wherein the upper surface of the flat region, the exposed surface, and the upper surface of the planarization layer are arranged on the same plane.

5. further comprising a thin film transistor disposed between the first insulating layer and the light emitting element; The display device according to claim 4 , wherein a semiconductor layer of the thin film transistor overlaps with the electrode pattern.

6. The light-emitting element is A first electrode; a light-emitting layer disposed on the first electrode; a second electrode disposed on the light-emitting layer; The light-emitting element further includes a thin film transistor disposed between the first insulating layer and the light-emitting element, The display device according to claim 4 , wherein the first electrode of the light-emitting element and the thin film transistor are electrically connected to each other.

7. The display device according to claim 6 , wherein the first electrode is in direct contact with the exposed surface of the electrode pattern through a contact hole that penetrates the first insulating layer.

8. The display device according to claim 6 , wherein the first electrode is in direct contact with the electrode pattern through a contact hole that penetrates the first insulating layer and the planarizing layer.

9. the electrode pattern includes the flat area of ​​the substrate and an exposed surface exposed by the planarization layer; The display device according to claim 1 , wherein the exposed surface has a curved shape.

10. The display device according to claim 9 , wherein the electrode pattern includes copper (Cu).

11. a first insulating layer disposed on the substrate and including a planar region and a trench region recessed from the planar region; an electrode pattern disposed on the substrate and including a recessed portion bent along a profile of the trench region; a planarization layer inserted in the recess; a second insulating layer covering the first insulating layer, the electrode pattern, and the planarizing layer; a light emitting element disposed on the second insulating layer; The planarization layer comprises an organic / inorganic composite material.

12. The organic / inorganic composite material includes an organic material and an inorganic material, The display device of claim 11 , wherein the proportion of the inorganic material is greater than the proportion of the organic material.

13. The organic material includes siloxane, and the inorganic material includes silicon oxide (SiO ２ 13. The display device of claim 12, comprising:

14. the electrode pattern includes the flat region of the first insulating layer and an exposed surface exposed by the planarization layer; The display device according to claim 11 , wherein the upper surface of the flat region, the exposed surface, and the upper surface of the planarization layer are arranged on the same plane.

15. further comprising a thin film transistor disposed between the first insulating layer and the light emitting element; The display device according to claim 14 , wherein a semiconductor layer of the thin film transistor overlaps with the electrode pattern.

16. The light-emitting element is A first electrode; a light-emitting layer disposed on the first electrode; a second electrode disposed on the light-emitting layer; The light-emitting element further includes a thin film transistor disposed between the first insulating layer and the light-emitting element, The display device according to claim 14 , wherein the first electrode of the light-emitting element and the thin film transistor are electrically connected to each other.

17. The display device according to claim 14 , further comprising a thin film transistor disposed between the substrate and the light emitting element, wherein the electrode pattern is a gate electrode of the thin film transistor.

18. providing a substrate; forming a flat region and a trench region recessed from the flat region in the substrate; forming an electrode material layer on the substrate, the electrode material layer being partially curved along a profile of the trench region; forming an organic / inorganic composite material layer on the electrode material layer; etching the organic / inorganic composite material layer to form an organic / inorganic composite layer on a portion of the electrode material layer; selectively etching a portion of the electrode material layer that is not covered by the organic / inorganic composite layer to form an electrode layer; A method for manufacturing a display device, comprising forming a first insulating layer on the flat area of ​​the substrate, the organic / inorganic composite layer, and the electrode layer.

19. the organic / inorganic composite material layer and the organic / inorganic composite layer each contain an organic material and an inorganic material; The method of claim 18 , wherein the ratio of the inorganic material is greater than the ratio of the organic material. Request 20 The organic material includes siloxane, and the inorganic material includes silicon oxide (SiO ２ 20. The method for manufacturing a display device according to claim 19, comprising:

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