Backside contact for semiconductor devices

Abstract

A semiconductor device is provided having a backside contact. The backside contact surrounds the periphery of the source / drain regions, providing increased contact area for electrical connection between the field effect transistor and the metallization layer. Cavities formed in the device layers expose the sidewalls of selected source / drain regions. The backside contact extends into such cavities and is adjacent to the sidewall and bottom surfaces of the selected source / drain regions. [Representative image] Figure 17A

Description

[Technical Field]

[0001] The present invention relates generally to electrical, electronic and computer technologies, and more particularly to FET architectures having backside contacts and methods for forming such backside contacts. [Background technology]

[0002] Due to the shrinking dimensions of various integrated circuit components, transistors such as field-effect transistors (FETs) have seen dramatic improvements in both performance and power consumption. These improvements can be largely attributed to the shrinking dimensions of components used in integrated circuits, which generally leads to reduced capacitance, resistance, and increased throughput current from the transistors. Metal oxide semiconductor field-effect transistors (MOSFETs) are suitable for use in high-density integrated circuits. As the size of MOSFETs and other devices decreases, the dimensions of the device's source / drain regions, channel region, and gate electrode also decrease.

[0003] FinFETs, nanosheet, and vertical transport FETs are under development for use in narrow-pitch applications. Nanosheet FETs contain multiple channel layers, each separated by a gate stack containing a conductive gate material layer and a gate dielectric layer. The gate stack surrounds the channel layer on all sides, thereby forming a gate-all-around (GAA) structure. Epitaxial regions at the edges of the nanosheet channel layer form the source / drain regions of the nanosheet FET.

[0004] The use of both front and backside contacts facilitates the fabrication and performance of integrated circuits. Having contacts on both sides of the chip allows for greater contact spacing than if all of the FET's contacts were on only one side (e.g., the front side). The backside power rail can be electrically connected to the backside source / drain contacts. Summary of the Invention

[0005] A monolithic semiconductor structure according to one aspect of the present invention includes a device layer having a front surface and a back surface, an interlayer dielectric layer, and a field effect transistor. The field effect transistor includes a channel region and first and second source / drain regions in the interlayer dielectric layer and extending laterally from the channel region. A back end layer on the front surface of the device layer is electrically connected to the field effect transistor. A back contact extends from the back surface of the device layer, the back contact having a width greater than a bottom surface of the first source / drain region. The back contact is electrically connected to the first source / drain region and contacts a first sidewall surface and a second sidewall surface of the first source / drain region.

[0006] A monolithic semiconductor structure according to a second aspect includes a device layer having a front surface and a back surface. The device layer includes an nFET region including an nFET transistor, a pFET region including a pFET transistor, and an interlayer dielectric layer. The nFET transistor and the pFET transistor are disposed within the interlayer dielectric layer. A back-end layer on the front surface of the device layer is electrically connected to one or more of the nFET transistor and the pFET transistor. One or more back surface contacts extend from the back surface of the device layer. Each of the one or more back surface contacts is electrically connected to a first source / drain region of one of the nFET transistor and the pFET transistor, respectively. Each of the one or more back surface contacts has a width wider than a bottom surface of the first source / drain region and contacts first and second sidewall surfaces of the first source / drain region.

[0007] A method for fabricating a semiconductor structure including a backside contact includes forming a sacrificial placeholder in a substrate and forming a device layer over the substrate, the device layer having a front surface and a backside, the device layer including an interlayer dielectric layer, a semiconductor channel region, and first and second source / drain regions in the interlayer dielectric layer and extending laterally from the channel region. The first source / drain region and portions of the interlayer dielectric layer adjacent to the first source / drain region are formed directly above the sacrificial placeholder. The method further includes forming a back-end interconnect layer over the front side of the device layer, removing the sacrificial placeholder to thereby expose a bottom surface of the first source / drain region and portions of the interlayer dielectric layer adjacent to the first source / drain region, forming a recess in the interlayer dielectric layer to thereby expose a first sidewall and a second sidewall of the first source / drain region, and forming a backside contact on the bottom surface, the first sidewall, and the second sidewall of the first source / drain region, extending from the backside of the device layer.

[0008] The techniques and structures disclosed herein can provide substantial beneficial technical effects. By way of example only and not limitation, one or more embodiments may provide one or more of the following advantages: · Manufacturing flexibility; Advantages of rear power supply network technology; Increased backside contact area; Wrap-around back contact.

[0009] These and other features and advantages will become apparent from the following detailed description of illustrative embodiments of the invention when read in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0010] The following drawings are presented by way of example only and not by way of limitation, and (when used) like reference numerals indicate corresponding elements throughout the several views.

[0011] [Figure 1]FIG. 10 is a top view of a layout including a sacrificial gate on a nanosheet stack, showing the x, y-1, and y-2 cross sections, according to an exemplary embodiment.

[0012] [Figure 1A] FIG. 2 is a schematic cross-sectional view taken along the y-1 cross section of FIG.

[0013] [Figure 1B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0014] [Figure 1C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0015] [Figure 2A] FIG. 1B is a schematic cross-sectional view along the y-1 section showing the structure shown in FIG. 1A after removing the bottom layer of the nanosheet stack.

[0016] [Figure 2B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0017] [Figure 2C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0018] [Figure 3A] 2B is a schematic cross-sectional view of the structure shown in FIG. 2A after formation of a spacer layer.

[0019] [Figure 3B] FIG. 3B is a schematic cross-sectional view of the structure shown in FIG. 3A taken along the y-2 cross section.

[0020] [Figure 3C] 3B is a schematic cross-sectional view of the structure shown in FIG. 3A taken along the x-section.

[0021] [Figure 4A] FIG. 3B is a schematic cross-sectional view of the structure shown in FIG. 3A after depositing and recessing an organic planarizing layer.

[0022] [Figure 4B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0023] [Figure 4C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0024] [Figure 5A] 4B is a schematic cross-sectional view showing the structure of FIG. 4A after partial removal of the spacer layer and formation of protective gate spacers.

[0025] [Figure 5B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0026] [Figure 5C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0027] [Figure 6A] FIG. 5B is a schematic cross-sectional view of the structure shown in FIG. 5A after further recessing the organic planarization layer and removing the spacer material from the sidewalls of the nanosheet stacks.

[0028] [Figure 6B] FIG. 10 is a schematic cross-sectional view along the y-2 cross section after the sacrificial layer is exposed.

[0029] [Figure 6C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0030] [Figure 7A] FIG. 6B is a schematic cross-sectional view of the structure shown in FIG. 6A after forming an inner spacer.

[0031] [Figure 7B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0032] [Figure 7C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0033] [Figure 8A] 7B is a schematic cross-sectional view of the structure shown in FIG. 7A after further deposition of an organic planarization layer and formation of a placeholder trench patterning.

[0034] [Figure 8B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0035] [Figure 8C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0036] [Figure 9A] 8B is a schematic cross-sectional view along the y-1 cross section of the structure shown in FIG. 8A after depositing and recessing a placeholder material.

[0037] [Figure 9B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0038] [Figure 9C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0039] [Figure 10A] FIG. 9B is a schematic cross-sectional view of the structure shown in FIG. 9A after source / drain epitaxy and deposition of an interlevel dielectric layer.

[0040] [Figure 10B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0041] [Figure 10C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0042] [Figure 11A] FIG. 10B is a schematic cross-sectional view of the structure shown in FIG. 10A after replacement gate formation, contact and interconnect formation, and carrier wafer bonding.

[0043] [Figure 11B]FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0044] [Figure 11C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0045] [Figure 12A] FIG. 11B is a schematic cross-sectional view of the structure shown in FIG. 11A after wafer flipping and semiconductor substrate removal.

[0046] [Figure 12B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0047] [Figure 12C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0048] [Figure 13A] FIG. 12B is a schematic cross-sectional view of the structure shown in FIG. 12A after deposition of a capping layer and planarization.

[0049] [Figure 13B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0050] [Figure 13C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0051] [Figure 14A] FIG. 13B is a schematic cross-sectional view of the structure shown in FIG. 13A after selective removal of the sacrificial placeholder.

[0052] [Figure 14B] FIG. 14B is a schematic cross-sectional view of the structure shown in FIG. 14A along the y-2 cross section.

[0053] [Figure 14C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0054] [Figure 15A]FIG. 14B is a schematic cross-sectional view of the structure shown in FIG. 14A after exposing selected source / drain regions.

[0055] [Figure 15B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0056] [Figure 15C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0057] [Figure 16A] FIG. 15B is a schematic cross-sectional view of the structure shown in FIG. 15A after back contact metallization.

[0058] [Figure 16B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0059] [Figure 16C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0060] [Figure 17A] FIG. 16B is a schematic cross-sectional view of the structure shown in FIG. 16A after forming a backside power rail and a backside power distribution network (BS-PDN).

[0061] [Figure 17B] FIG. 1 is a schematic cross-sectional view taken along the y-2 cross section.

[0062] [Figure 17C] FIG. 1 is a schematic cross-sectional view taken along the x-section.

[0063] It should be understood that elements in the figures are shown for simplicity and clarity, and that common but well-understood elements that may be useful or necessary in a commercially viable embodiment may not be shown in order to lessen obstruction to the view of the illustrated embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0064] The principles of the present invention are described herein in the context of exemplary embodiments. It should be understood, however, that the specific embodiments and / or methods illustratively shown and described herein are to be considered exemplary, and not restrictive. Moreover, it will be apparent to those skilled in the art in light of the teachings herein that numerous modifications to the illustrated embodiments may be made within the scope of the claims. Thus, no limitations are intended or should be inferred with respect to the embodiments shown and described herein.

[0065] The use of backside contacts can improve the fabrication and performance of integrated circuits, especially those involving relatively small devices and high packing densities. Gate-all-around (GAA) transistors, such as nanosheet transistors and fin field-effect transistors (FinFETs), are among the devices being used in high-density, high-performance applications.

[0066] An exemplary sequence of steps that may be used to fabricate an integrated circuit including a backside contact is shown in Figure 1 and subsequent figures. The schematic top view in Figure 1 shows x, y-1, and y-2 cross-sectional views of a fin with a nanosheet stack 20 and a sacrificial gate 22 extending perpendicular to the fin. It will be understood that the techniques as described herein are applicable to architectures including FinFETs and architectures including nanosheet transistors.

[0067] The monolithic structure shown in Figures 1, 1A, 1B, and 1C includes a stack of nanosheets 20 including a semiconducting channel layer 21 formed on a substrate 34. The nanosheets can be formed, for example, on a semiconductor-on-insulator substrate. Referring to Figures 1A, 1B, and 1C, the substrate 34 includes a silicon layer 24, a silicon germanium overlayer 26 having a relatively high germanium content, and a buried oxide (BOX) layer 28 between the silicon layer and the silicon germanium overlayer 26.

[0068] In one or more exemplary embodiments, the semiconductor nanosheet (channel) layers 21 each have a thickness in the range of four to ten nanometers (4-10 nm). The number of semiconductor (channel) layers in the semiconductor layer stack can vary depending on the intended application and function of the nanosheet transistor being fabricated. The semiconductor channel layers 21 are essentially single-crystalline silicon layers and, in some embodiments, are spaced apart by ten to twenty nanometers (10-20 nm). The width of each semiconductor channel layer 21 in the upper fin-like portion of the exemplary monolithic structure, in some embodiments, is fifteen nanometers (15 nm) or greater (as viewed in the y-1 and y-2 cross sections). The channel layer dimensions and vertical spacing of the channel layers should be considered exemplary, not limiting.

[0069] The silicon layer 21 and the silicon germanium layer 26' are epitaxially grown alternately on the semiconductor substrate to obtain a layered stack having the desired number of silicon (channel) layers. The terms "epitaxially growing and / or depositing" and "epitaxially grown and / or deposited" refer to the growth of a semiconductor material on a deposition surface of the semiconductor material, where the grown semiconductor material has the same crystalline properties as the semiconductor material on the deposition surface. In an epitaxial deposition process, chemical reactants provided by source gases are controlled, and system parameters are set so that the depositing atoms reach the deposition surface of the semiconductor substrate with enough energy to move around on the surface and orient themselves to the crystalline structure of the atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same crystalline properties as the deposition surface on which it is formed.

[0070] The monolithic structure shown in Figures 1, 1A, 1B, and 1C is obtained by first growing alternating silicon and silicon germanium nanosheet layers on a substrate 34. The sacrificial silicon germanium layer 26', which is replaced by a metal gate and gate dielectric material later in the process, can have a thickness in the range of six to twenty nanometers (6-20 nm). The dimensional ranges of the channel layer and sacrificial silicon germanium layer should be considered exemplary, not limiting. The silicon germanium layer 26' has a composition Si to allow selective etching relative to silicon and the underlying silicon germanium overlayer 26. 1-x Ge x where x is between 0.2 and 0.3. In one exemplary embodiment, the sacrificial silicon germanium layer 26' may have the composition Si 1-x Ge x where x is about 0.3, while the upper substrate layer 26 has the composition Si 1-x Ge x where x is about 0.55. The thickness of the upper silicon germanium substrate layer 26 may or may not be the same as the thickness of the sacrificial silicon germanium layer 26' adjacent to the silicon channel layer 21. Using a patterned hard mask (e.g., silicon nitride), an initial reactive ion etch (RIE) is performed down to the BOX layer 28 to obtain an upper multilayer fin-like semiconductor structure with a dielectric cap (not shown) formed from the hard mask. The multilayer fin-like semiconductor structure (nanosheet stack 20) ​​extends vertically from the substrate 34. The remaining portion of the hard mask is removed.

[0071] A sacrificial gate layer is formed on the stack of nanosheet layers 20 and the BOX layer 28. The sacrificial gate layer may be composed of, for example, amorphous silicon (a-Si) or polycrystalline silicon (polysilicon). The sacrificial gate material used to form the sacrificial gate layer may be formed using, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), inductively coupled plasma chemical vapor deposition (ICP CVD), or any combination thereof. A hard mask (e.g., SiNx or a combination of SiNx and SiO2) is deposited and patterned on the top surface of the sacrificial gate layer. The sacrificial gate layer is then reactive ion etched down to the BOX layer 28. The resulting structure includes a sacrificial gate 22 extending perpendicular to the parallel nanosheet stack 20. A patterned gate hard mask 32 is adjacent to the top surface of the sacrificial gate. As shown in Figure 1B, a portion of the nanosheet stack is embedded within a sacrificial gate, which extends across both the nFET and pFET regions of the exemplary structure, as shown in Figure 1.

[0072] The top substrate layer 26 is selectively removed, thereby forming a space 36 between the BOX layer 28 and the nanosheet stack 20. As discussed above, the top substrate layer 26 has a higher germanium content than the sacrificial silicon germanium layer 26′ in the nanosheet stack 20 and can therefore be etched selectively with respect to such layers. A selective etching process, such as a dry HCl etch, can be used to remove the top substrate layer 26 selectively with respect to the silicon channel layer 21 and the sacrificial silicon germanium layer 26′. Figures 2A, 2B, and 2C show cross-sectional views of the resulting structure.

[0073] A dielectric layer is deposited over the resulting structure, filling the space 36 between the BOX layer 28 and the nanosheet stack 20. The dielectric gate spacer may be composed of, for example, SiN, SiBCN, SiOCN, and / or SiCO, or other suitable dielectric materials. Such materials can be deposited using atomic layer deposition (ALD). In an exemplary embodiment, a silicon nitride liner is deposited over the monolithic structure. The silicon nitride liner is selectively etched back to remove its unprotected horizontal portions, thereby forming vertical top sidewall gate spacers 38 on the sidewalls of the nanosheet stack 20 and the sacrificial gate 22. The spacer material below the nanosheet stack is protected and remains in the space 36 after the etchback, thereby forming a bottom dielectric isolation layer. Figures 3A, 3B, and 3C show cross-sectional views of the resulting structure, including the vertical gate spacer 38 and the bottom dielectric isolation layer (horizontal spacer 38A) below the nanosheet stack 20.

[0074] An organic planarization layer (OPL) 42 is deposited and then recessed to obtain structure 40 as shown in Figures 4A, 4B, and 4C. As shown in the x-cross section provided in Figure 4C, portions of hard mask 32 and vertical gate spacers 38 extend above the top surface of OPL 42 after recessing the OPL. The exposed portions of gate spacers 38 are then selectively removed down to the level of the top surface of the OPL.

[0075] Referring to structure 50 shown in the x-section of FIG. 5C, gate protection sidewall spacers 44 are formed on the sidewalls of the upper portion of hard mask 32. In some embodiments, oxide sidewall spacers are formed. Aluminum oxide, titanium oxide, and titanium nitride are additional alternative materials that may comprise gate protection sidewall spacers 44 in embodiments in which vertical gate spacers 38 are silicon nitride spacers. Gate protection sidewall spacers 44 are adjacent to the top surface of gate sidewall spacer 38 adjacent to sacrificial gate 22. As shown in the y-1 section of FIG. 5A, gate sidewall spacers 38 adjacent to nanosheet stack 20 remain embedded within OPL 42.

[0076] The OPL 42 is removed to expose the gate sidewall spacers 38 adjacent to the nanosheet stack 20. Ashing or other suitable processes can be used to remove the OPL. The unprotected portions of the gate sidewall spacers 38 are then removed, resulting in the structure 60 as shown schematically in FIGS. 6A, 6B, and 6C. Reactive ion etching can be used for such removal. The gate sidewall spacers 38 below the gate-protecting sidewall spacers 44 remain intact, while those adjacent to the nanosheet stack are removed. The spacers 38A that form the bottom dielectric isolation layer below the nanosheet stack 20 also remain intact.

[0077] 7A, 7B, and 7C, portions of the nanosheet stack 20 outside the area protected by the sacrificial gate 22 and hard mask 32 are reactive ion etched down to the horizontal spacers 38A. The resulting structure is subjected to a timed wet etching process to selectively recess the silicon germanium layers 26′ within the nanosheet stack 20. In some embodiments, hydrogen chloride gas is used to selectively remove the silicon germanium, leaving the silicon nanosheet (channel) layer 21 substantially intact. Alternatively, a wet etching process including ammonia and hydroperoxide can be used to etch SiGe selectively relative to other materials. Each exposed end of the silicon germanium layer 26′ can be recessed, for example, by three to seven nanometers (3-7 nm). The silicon germanium layer 26′ has a width smaller than the width of the silicon (channel) layer 21 after the timed etch. Thus, the stack of semiconductor nanosheet layers includes a recess between the ends of each pair of silicon (channel) layers 21.

[0078] A dielectric spacer material is deposited within the trenches resulting from reactive ion etching of the semiconductor layer stack. The dielectric spacer material is etched back to form inner spacers 46 within each recess of the nanosheet semiconductor layer stack. Selective wet etching can be used to remove the dielectric inner spacer material outside the recesses between the silicon layers. A structure 70 can be obtained, as shown schematically in Figures 7A, 7B, and 7C. The inner spacers 46 of the structure can be composed of, for example, a low-k dielectric material. In some embodiments, silicon oxynitride, SiBCN (Silicon Borocarbonitride), SiOCN (Silicon Oxycarbonitride), and / or SiOC (Silicon Oxycarbide) inner spacers can be formed. Relatively low-k silicon nitride-based materials, when used to form the inner spacers, can be selectively etched using, for example, phosphoric acid. Various techniques for forming inner spacers for nanosheet transistors have been discussed in the literature and continue to be developed. Therefore, the particular materials and processes discussed for forming the inner spacers should be considered exemplary rather than limiting.

[0079] An additional OPL 42′ is deposited on structure 70 and patterned, for example, using a lithographically patterned hard mask (not shown) formed thereon. As shown in FIGS. 8A and 8C , a placeholder trench 48 is formed through BOX layer 28 and partially extending into semiconductor substrate layer 24. Sidewalls adjacent to the placeholder trench are substantially vertical. Using the additional OPL 42′ as a mask, a reactive ion etch or a series of reactive ion etches is used to form placeholder trench 48. As shown in the x-cross section of FIG. 8C , the end of silicon nanosheet (channel) layer 21 on one side of nanosheet stack 20 is exposed upon formation of placeholder trench 48. The opposite side of the nanosheet stack of the resulting structure 80 is adjacent to the additional OPL 42′.

[0080] The OPL 42' is then removed and a placeholder material layer is deposited in the placeholder trench 48. The placeholder material layer is recessed to form a structure 90 as shown generally in Figures 9A, 9B, and 9C. The placeholder material layer comprises a sacrificial placeholder 52 that is later replaced by a backside contact, as described below. The sidewalls of the sacrificial placeholder are substantially vertical. Silicon germanium, aluminum oxide, and titanium oxide are among the materials that can comprise the sacrificial placeholder 52.

[0081] The source / drain regions 56-1 and 56-2 are epitaxially grown on the exposed edges of the silicon nanosheet channel layer 21. One of the source / drain regions 56-1 of each FET is grown on one of the sacrificial placeholders 52. The source / drain region 56-2 grown on the opposite side of each FET is grown on the BOX layer 28, as shown in FIGS. 10A and 10C. The width of the sacrificial placeholder 52 is wider than the width of the source / drain region 56-1 grown on it, as shown in the y-1 cross section (FIG. 10A). The epitaxial growth of the source / drain regions 56-1 and 56-2 is timed to control the height and width dimensions. Dopants can be incorporated in situ using appropriate precursors, as known in the art. By "in situ," we mean that the dopant that determines the conductivity type of the doped layer is introduced during the process step that forms the doped layer, e.g., during epitaxial deposition. As used herein, the term "conductivity type" refers to the addition of an impurity to an intrinsic semiconductor that creates a deficiency of valence electrons. For silicon-containing substrates, examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. As used herein, "n-type" refers to the addition of an impurity that provides free electrons to the intrinsic semiconductor. For silicon-containing substrates, examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus.Exemplary epitaxial growth processes suitable for use in forming silicon and / or silicon germanium epitaxy include rapid thermal chemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Referring to FIG. 1, the nFET region includes transistors with n-type source / drain regions, while the pFET region includes p-type source / drain regions. The source / drain regions of nanosheet devices are typically grown before the RMG (replacement metal gate) process.

[0082] An interlevel dielectric (ILD) layer 58 is deposited on the source / drain regions using a deposition technique including, but not necessarily limited to, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), radio-frequency CVD (RFCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam deposition (MBD), pulsed laser deposition (PLD), and / or liquid source mist chemical deposition (LSMCD), spin-on coating, sputtering, and / or plating. The ILD layer may include, but is not necessarily limited to, a low-k material (e.g., k less than about 4.0), such as porous silicates, carbon-doped oxides, silicon dioxide, silicon oxynitride, carbon-doped silicon oxide (SiCOH) and its porous variants, silsesquioxanes, siloxanes, or other dielectric materials, e.g., having a dielectric constant in the range of about 2 to about 4. A SiCOH dielectric film having a dielectric constant (k) of about 2.7 to 2.8, for example, may comprise one or more ILD layers. Such a dielectric film may be deposited using PECVD. The ILD layer may, in some embodiments, be comprised of an ultra low-k (ULK) dielectric material having a dielectric constant of 2.5 or less. In some embodiments, the ILD layer is comprised of multiple layers. The resulting structure is planarized using CMP or other suitable technique to remove excess ILD material and remove hard mask 32. After CMP, a structure 100 is obtained as shown schematically in Figures 10A, 10B, and 10C.

[0083] The sacrificial gate layer 22 is removed from the structure 100. The silicon germanium layer 26' is then selectively removed, leaving a stack of silicon (channel) layers 21 separated by spaces (not shown). In some embodiments, hydrogen chloride gas is used to selectively remove the silicon germanium, leaving the silicon nanosheets substantially intact. Alternatively, a wet etching process including ammonia and hydroperoxide can be used to etch SiGe selectively relative to other materials. A gate stack 62 is formed adjacent to the nanosheet (channel) layer 21. A gate dielectric layer forms part of the gate stack, replacing the sacrificial silicon germanium layer. The gate stack is adjacent to the silicon nanosheet channel layer 21. Non-limiting examples of materials suitable for the gate dielectric layer include oxides, nitrides, oxynitrides, silicates (e.g., metal silicates), aluminates, titanates, nitrides, or any combination thereof. Examples of high-k gate dielectric materials (dielectric constants greater than 7.0) include, but are not limited to, metal oxides such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. High-k materials may further include dopants such as lanthanum and aluminum. The gate dielectric layer may be formed by a suitable deposition process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), evaporation, physical vapor deposition (PVD), chemical solution deposition, or other similar processes. The thickness of the gate dielectric material may vary depending on the deposition process and the composition and number of high-k dielectric materials used. In one exemplary embodiment, a 2.5 nm thick high-k dielectric layer is used. In some embodiments, the gate dielectric layer comprises multiple dielectric layers.

[0084] A conductive gate material is deposited in the space previously filled by the silicon germanium nanosheet layer 26′. The deposited metal gate material forms the metal gate of the resulting nanosheet field effect transistor of the structure 110. In some embodiments, the conductive gate includes a work function metal (WFM) layer. The WFM serves the dual purpose of Vt setting and gate conductor. Non-limiting examples of suitable work function metals include p-type work function metal materials and n-type work function metal materials. P-type work function materials include compositions such as ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, titanium nitride, or any combination thereof. N-type metal materials include, for example, hafnium, zirconium, titanium, tantalum, aluminum, metal carbides (e.g., hafnium carbide, zirconium carbide, titanium carbide, and aluminum carbide), aluminides, or any combination thereof. The work function metal can be deposited by a suitable deposition process, for example, a conformal ALD process.

[0085] In one exemplary embodiment, an n-type WFM layer having a thickness of three nanometers (3 nm) may be formed on the gate dielectric layer. The thickness of the WFM layer may range, for example, from two to ten nanometers (2 to 10 nm), with thinner layers being used as device scaling decreases. The n-type WFM layer is intended for use in conjunction with n-type transistors. Portions of the n-type WFM layer, which may also be deposited in the pFET region, may be replaced accordingly later in the process. The n-type WFM layer and gate dielectric may fill the space between the silicon channel layer 21 and the region previously occupied by the sacrificial gate 22.

[0086] The n-type WFM layer in the nFET region may be protected by a patterned OPL (not shown). The exposed portions of the n-type WFM layer in the pFET region are removed, leaving open spaces between the silicon channel layer 21 in the pFET region. Thus, the gate metal is removed from the pFET region, while the protected nFET region remains intact. SC1 etching or other suitable etching processes can be used to selectively remove the gate metal while leaving the gate dielectric layer substantially intact. The duration of the etch is sufficient to remove all of the gate metal from the pFET region without affecting the gate metal in the nFET region. After removing the initially deposited n-type WFM layer from the pFET region, a new gate metal determined to be appropriate for the pFET transistor is deposited. In embodiments where the initially deposited metal is n-type, a p-type WFM layer is deposited. It will be understood that in some alternative embodiments, this process can be reversed, depositing the n-type metal after the p-type metal. Chemical mechanical planarization can be used to remove the metallization and complete front-end-of-line (FEOL) processing. Thus, a FEOL layer is provided that includes FETs and possibly other electronic devices (not shown) within ILD layer 58. Gate cut regions 67 (FIG. 11B) are also formed to separate the gates at the cell boundaries.

[0087] Referring again to FIGS. 11A, 11B, and 11C, the front contacts are formed in a middle-of-line (MOL) process. Silicon-based devices typically include multiple interconnect metallization layers above the device (front-end / FEOL) layer containing field-effect transistors (FETs) and / or other electronic structures. FEOL processing includes high-temperature steps to manipulate the conductivity of semiconductors. Middle-of-line (MOL) processing includes procedures typically used to fabricate metal contacts for logic circuit components such as field-effect transistors (FETs), resistors, diodes, and capacitors. MOL processing may include intermediate-temperature steps to form semiconductor-metal compounds (e.g., silicides, germanosilicides) for electrical contacts. Back-end (BEOL) processing involves creating metal interconnect lines that connect devices formed in FEOL processing to form electrical circuits and may include silicidation as discussed above with respect to MOL processing.

[0088] A first set of contacts 64-2 formed in the ILD layer 58 is electrically connected to the source / drain regions 56-2. Metal gate contacts 66 formed during the MOL process are electrically connected to the gate stack 62. The top (front) source / drain contacts 64-2 and gate contact 66 may be composed of conductive materials, including, but not limited to, a silicide layer such as Ti, Ni, NiPt, etc., a metal adhesion layer such as TiN, TaN, etc., and a conductive metal fill material such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), ruthenium (Ru), molybdenum (Mo), etc., or any other suitable conductive material, and combinations thereof. The metal silicide layer can be formed on the source / drain regions 64-2 by depositing a metal liner, such as a titanium liner, on the source / drain regions 64-2 before depositing the barrier layer and metal fill layer. Such titanium liners can be deposited using physical vapor deposition (PVD) and then annealed at temperatures between about 200 and 800° C. to form the metal silicide.

[0089] The FEOL processing described above provides a device layer 75 having a front surface and a back surface, which includes a FET consisting of a channel region (silicon nanosheet channel layer 21), source / drain regions 56-1, 56-2, and a gate stack 62, all of which are embedded within an ILD layer 58.

[0090] Metal interconnect lines that connect devices in the FEOL (device) layer 75, thereby forming electrical circuits, are formed in one or more BEOL interconnect layers 68 after MOL processing. BEOL interconnect layers are formed on the front side of the device layer 75. Metal lines, including the interconnect lines, are deposited in order (e.g., M1, M2, M3, etc.) on the FEOL layers, including dielectric layers. The interconnect lines within each metal line are electrically connected to the interconnect lines within other metal lines and to the devices in the FEOL (device) layer 75. BEOL processing typically includes low-temperature steps to form the metal lines and maintain temperature-sensitive FEOL and MOL structures. BEOL processing includes forming interconnect layers on the MOL layers. A chip may have multiple BEOL interconnect layers. Each interconnect layer, with its wiring scheme, is connected to another interconnect layer by vias. The lines and vias are in dielectric layers, one or more of which may be composed of low-k materials.

[0091] A carrier wafer 72 is bonded to the resulting structure and is adjacent to the BEOL layers 68. As shown in Figures 11A, 11B, and 11C, the monolithic structure 110 includes a FEOL (device) layer 75 containing nFET and pFET transistors, a MOL layer containing front contacts 64-2, 66, a BEOL layer 68 electrically connected to the devices in the device layer, and the carrier wafer 72.

[0092] The monolithic structure 110 is inverted and the silicon substrate layer 24 is removed therefrom. Ammonium hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) may be used for such removal due to their high selectivity to silicon germanium. (As noted above, the sacrificial placeholders 52 may be composed of silicon germanium.) A monolithic structure 120 may be obtained, as shown generally in Figures 12A, 12B, and 12C.

[0093] A dielectric capping layer 74 is deposited on the back surface of the structure 120 and planarized to the top surface of the sacrificial placeholder 52. In some embodiments, a silicon nitride capping layer is used. Thus, a structure 130 can be obtained as schematically shown in FIGS. 13A, 13B, and 13C. The sacrificial placeholder 52 is then selectively removed. A cavity 78 is formed above the source / drain region 56-1, thereby exposing its bottom, backside-oriented surface 56-1′. The width of the cavity 78 exceeds the width of the bottom surface 56-1′ of the adjacent source / drain region 56-1, respectively, as viewed in the y-1 cross section (FIG. 14A), thereby exposing portions of the ILD layer 58 on both sides of the source / drain region 56-1. FIGS. 14A, 14B, and 14C show an exemplary structure 140 that can be obtained after removing the sacrificial placeholder.

[0094] The cavity 78 extends into the ILD layer 58, exposing the sidewalls of the source / drain region 56-1. A dry etch (e.g., reactive ion etching) may be used to form the cavity extension 78'. The etch selectively removes portions of the ILD layer 58 without etching the capping layer 74. The etch can be timed so that the cavity extension 78' does not extend as deep into the ILD layer 58 as the source / drain region 56-1. The cavity 78 and cavity extension 78' form a recess that exposes the bottom (now top) and sidewalls of the source / drain region 56-1. A relatively large area of ​​the source / drain region 56-1 is exposed for subsequent processing. An exemplary structure 150 is obtained, as shown in Figures 15A, 15B, and 15C.

[0095] Backside contact metallization and metal overburden removal are performed, resulting in a structure 160 as shown schematically in FIGS. 16A, 16B, and 16C. The backside source / drain contacts 64-1 may or may not be composed of the same metal / metal silicide used to form the frontside source / drain contacts 64-2. The presence of the BEOL layer 68 at this stage of the process may prevent high-temperature thermal annealing. The relatively large contact area between the source / drain regions 56-1 and the backside source / drain contacts 64-1 helps mitigate contact resistance issues that may result from the lack of high-temperature thermal annealing during the backside metallization process. Each backside source / drain contact 64-1 has a width greater than the width CD of the bottom surface (the "bottom" surface becomes the top after wafer flip) of the corresponding source / drain region 56-1, as shown in the y-1 cross section of FIG. 16A. The backside source / drain contacts 64-1 extend into the ILD layer 58 deposited on the source / drain regions 56-1, 56-2 during the FEOL processing stage. Thus, a portion of the backside source / drain contact 64-1 is disposed between the ILD layer 58 and the sidewall of the source / drain region 56-1.

[0096] A backside power rail 82 and a backside power delivery network (BSPDN) 84 are formed on the capping layer 74. The backside power rail is electrically connected to one or more of the backside source / drain contacts 64-1. Thus, a monolithic structure 170 is obtained as shown schematically in Figures 17A, 17B, and 17C.

[0097] The monolithic structure 170 includes a device layer having a front surface and a back surface. The device layer includes an interlayer dielectric layer 58, a field-effect transistor, and optionally other electronic devices. The field-effect transistor includes a channel region that, in the exemplary embodiment, includes a stacked semiconductor nanosheet layer 21. First and second source / drain regions 56-1, 56-2 extend laterally from each channel region. A back-end layer 68 is disposed on the front surface of the device layer and electrically connected to the field-effect transistor. A back-end contact 64-1, having a width wider than the bottom surface of the first source / drain region 56-1, extends from the back surface of the device layer. The back-end contact is electrically connected to the first source / drain region 56-1 and contacts first and second sidewall surfaces of the first source / drain region 56-1. A front-end contact 64-2 connects the second source / drain region 56-2 to the BEOL layer 68. 17A, a first portion of the backside contact 64-1 extends between the interlayer dielectric layer 58 and a first sidewall surface of the first source / drain region 56-1, and a second portion of the backside contact extends between the interlayer dielectric layer 58 and a second sidewall surface of the first source / drain region 56-1. Thus, a relatively large contact area is formed between the backside contact 64-1 and the first source / drain region. The backside contact is electrically connected to a power supply rail (e.g., a VDD rail), which is electrically connected to the BSPDN 84.

[0098] As discussed above, the figures illustrate exemplary process steps / stages in the fabrication of exemplary structures. While the overall fabrication method and the structures formed thereby are entirely novel, certain individual process steps required to carry out the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tools. These techniques and tools will already be familiar to those skilled in the art in light of the teachings herein. Furthermore, one or more of the process steps and tools used in the fabrication of semiconductor devices are also described in several readily available publications, including, for example, "Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition" by James D. Plummer et al. (Prentice Hall, 2001), which are incorporated herein by reference. While several individual process steps are described herein, it is emphasized that these steps are merely exemplary, and that those skilled in the art may be familiar with several equally suitable alternatives that may be applicable.

[0099] It should be understood that the various layers and / or regions illustrated in the accompanying figures may not be drawn to scale. Furthermore, one or more semiconductor or other layers of the type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for ease of illustration. This does not imply that the semiconductor or other layers not explicitly shown are omitted in the actual integrated circuit device.

[0100] At least some of the techniques described above may be implemented in integrated circuits. In forming integrated circuits, identical dies are typically fabricated in a repeating pattern on the surface of a semiconductor wafer. Each die includes the devices described herein and may include other structures and / or circuits. Individual dies are cut or diced from the wafer and then packaged as integrated circuits. Those skilled in the art will know how to dic a wafer and package the dies to make integrated circuits.

[0101] Those skilled in the art will appreciate that the exemplary structures discussed above can be distributed in raw form (i.e., a single wafer having multiple unpackaged chips), as bare die, in packaged form, or can be incorporated as part of an intermediate or final product that would benefit from having, for example, FET devices and contacts formed in accordance with one or more of the exemplary embodiments.

[0102] Numerous techniques are used by those skilled in the art to remove material at various stages in the fabrication of semiconductor structures. These processes are collectively referred to herein as "etching." For example, etching includes techniques such as wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (RIE), all of which are known techniques for removing selected materials when forming semiconductor structures. Standard Clean 1 (SC1) contains a strong base, usually ammonium hydroxide, and hydrogen peroxide. SC2 contains a strong acid, such as hydrochloric acid and hydrogen peroxide. The techniques and applications of etching are well understood by those skilled in the art, and therefore, a detailed description of such processes will not be presented herein.

[0103] The illustrations of the embodiments described herein are intended to provide a general understanding of various embodiments and are not intended to serve as a complete description of all elements and features of apparatus and systems that may employ the circuits and techniques described herein. Many other embodiments will be apparent to those skilled in the art in view of the teachings herein; other embodiments may be utilized and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of the present invention. It should also be noted that in some alternative implementations, some of the steps of the exemplary method may occur in an order other than that shown in the figures. For example, two steps shown in succession may, in fact, be executed substantially concurrently, or certain steps may, in some cases, be executed in the reverse order, depending on the functionality involved. Also, the drawings are merely representational and not drawn to scale. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0104] Embodiments may be referred to herein, individually and / or collectively, by the term "embodiment" for convenience only, and this is not intended to limit the scope of the application to a single embodiment or inventive concept when multiple embodiments or inventive concepts are actually disclosed. Accordingly, although specific embodiments have been illustrated and described herein, it should be understood that arrangements which achieve the same purpose may be substituted for the specific embodiment shown. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those skilled in the art in view of the teachings herein.

[0105] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It will be further understood that the terms "comprise" and / or "comprising," when used herein, specify the presence of stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Terms such as "above," "below," and "vertical" are used to indicate the relative location of elements or structures to one another, rather than relative elevation. When a layer of a structure is described herein as being "on top of" another layer, it is understood that there may or may not be intermediate elements or layers between the two specified layers. When a layer is described as being "directly on top of" another layer, it indicates direct contact between the two layers.

[0106] When a means or step-plus-function element appears within the scope of the following claims, the corresponding structure, material, acts, and equivalents of that element are intended to include any structure, material, or acts for performing the function in combination with other specifically claimed elements. The description of various embodiments has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the disclosed forms. Numerous modifications and variations will be apparent to those skilled in the art without departing from the scope of the embodiments. The embodiments were chosen and described to best explain the principles and practical applications and to enable others skilled in the art to understand various embodiments with various modifications as suited to the particular uses contemplated.

[0107] The Abstract has been provided in accordance with 37 CFR Chapter 1.72(b). It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Additionally, in the foregoing Detailed Description, various features may be found grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments have more features than are expressly recited in each claim. Rather, as the appended claims reflect, claimed subject matter may lack all of the features of a single embodiment. Accordingly, the following claims are incorporated into the Detailed Description, with each claim standing on its own as separately claimed subject matter.

[0108] Given the teachings provided herein, those skilled in the art will be able to contemplate other implementations and applications of these techniques and the disclosed embodiments. Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the exemplary embodiments are not limited to those precise embodiments, and that various other changes and modifications can be made thereto by those skilled in the art without departing from the scope of the appended claims.

[0109] In a preferred embodiment of the invention described herein, there is provided a monolithic semiconductor structure comprising: a device layer including a front surface and a back surface, the device layer including an nFET region including an nFET transistor; a pFET region including a pFET transistor; and an interlayer dielectric layer, the nFET transistor and the pFET transistor being disposed within the interlayer dielectric layer; a back-end interconnect layer on the front surface of the device layer, the back-end interconnect layer being electrically connected to one or more of the nFET transistor and the pFET transistor; and one or more back surface contacts extending from the back surface of the device layer, each of the one or more back surface contacts being electrically connected to a first source / drain region of one of the nFET transistor and the pFET transistor, respectively, each of the one or more back surface contacts having a width wider than a bottom surface of the first source / drain region and contacting first and second sidewall surfaces of the first source / drain region. Preferably, a first portion of each backside contact extends between the interlayer dielectric layer and a first sidewall surface of the first source / drain region of one of the nFET transistors and the pFET transistor, respectively, and a second portion of each backside contact extends between the interlayer dielectric layer and a second sidewall surface of the first source / drain region of one of the nFET transistors and the pFET transistor. Preferably, the structure further includes front contacts electrically connecting the plurality of nFET transistors and pFET transistors to a back-end interconnect layer. Preferably, the structure further includes one or more power rails on the backside of the device layer and electrically connected to the one or more backside contacts. Preferably, each of the nFET transistors and the pFET transistors includes a channel region including a stack of nanosheet semiconductor layers. Preferably, the structure further includes an oxide layer on the backside of the device layer; and a dielectric capping layer on the oxide layer, wherein the one or more backside contacts extend through the oxide layer and the dielectric capping layer. Preferably, the structure further includes a plurality of front contacts extending through the interlevel dielectric layer and electrically connecting one or more of the nFET and pFET transistors to a back-end layer.Preferably, each of the nFET and pFET transistors includes a gate metal and further includes a gate contact electrically connecting the gate metal to a back-end layer.

Claims

1. a device layer comprising a front surface and a back surface, said device layer comprising: an interlevel dielectric layer; and field-effect transistor the field effect transistor including a channel region and first and second source / drain regions in the interlayer dielectric layer, the first and second source / drain regions extending laterally from the channel region; a back-end interconnect layer on the front side of the device layer; and a backside contact extending from the backside of the device layer, the backside contact including a width greater than a bottom surface of the first source / drain region, the backside contact electrically connected to the first source / drain region and contacting first and second sidewall surfaces of the first source / drain region; 1. A monolithic semiconductor structure comprising:

2. 2. The monolithic semiconductor structure of claim 1 , wherein a first portion of the backside contact extends between the interlayer dielectric layer and the first sidewall surface of the first source / drain region, and a second portion of the backside contact extends between the interlayer dielectric layer and the second sidewall surface of the first source / drain region.

3. 3. The monolithic semiconductor structure of claim 2, further comprising a front contact electrically connecting said second source / drain region and said back-end interconnect layer.

4. 4. The monolithic semiconductor structure of claim 3, further comprising a power rail on the backside of said device layer and electrically connected to said backside contact.

5. The monolithic semiconductor structure of claim 3 , wherein the channel region comprises a stack of nanosheet semiconductor layers.

6. an oxide layer on the backside of the device layer; and a dielectric capping layer on said oxide layer; further comprising the back contact extends through the oxide layer and the dielectric capping layer; 6. The monolithic semiconductor structure of claim 5.

7. 6. The monolithic semiconductor structure of claim 5, further comprising a front contact extending through said interlevel dielectric layer and electrically connecting a surface of said second source / drain region to said back-end interconnect layer.

8. 8. The monolithic semiconductor structure of claim 7, wherein said field effect transistor further comprises a gate metal, said gate metal further comprising a gate contact electrically connecting said gate metal to said back-end interconnect layer.

9. forming a sacrificial placeholder in a substrate; forming a device layer over the substrate, the device layer having a front surface and a back surface, the device layer including an interlayer dielectric layer, a semiconductor channel region, and first and second source / drain regions within the interlayer dielectric layer and extending laterally from the semiconductor channel region, the first source / drain region and portions of the interlayer dielectric layer adjacent the first source / drain region being formed directly over the sacrificial placeholder; forming a back-end interconnect layer on the front side of the device layer; removing the sacrificial placeholder, thereby exposing a bottom surface of the first source / drain region and the portion of the interlayer dielectric layer adjacent to the first source / drain region; forming a recess in the interlevel dielectric layer, thereby exposing a first sidewall and a second sidewall of the first source / drain region; and forming a backside contact on the bottom surface, the first sidewall, and the second sidewall of the first source / drain region and extending from the backside of the device layer; 1. A method for fabricating a semiconductor structure including a backside contact, comprising:

10. the substrate having a semiconductor substrate layer, and the method comprising: removing the semiconductor substrate layer; forming a backside dielectric layer on the backside of the device layer; further comprising 10. The method of claim 9, wherein removing the sacrificial placeholder forms a cavity extending through the backside dielectric layer, the cavity having a width greater than the bottom surface of the first source / drain region.

11. The method of claim 10 , further comprising bonding a carrier wafer to the back-end interconnect layer before removing the semiconductor substrate layer.

12. 10. The method of claim 9, further comprising forming a gate stack in the device layer, the gate stack adjacent the channel region.

13. The method of claim 9 , wherein the channel region comprises a stack of nanosheet semiconductor layers.

14. 10. The method of claim 9, further comprising forming a backside power rail electrically connected to the backside contact.

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