Device with reconfigurable short-term data retention - Patents.com

Abstract

The present invention is particularly directed to a device including a plurality of resistive memory elements, the plurality of resistive memory elements comprising a resistive material. The device is configured to apply programming pulses to a subset of the plurality of resistive memory elements to effect a temporary resistance change in the resistive material of the subset over a predetermined holding period, thereby programming the subset of the plurality of resistive elements from a first resistance state corresponding to a first binary state to a second resistance state corresponding to a second binary state. The device is configured such that the resistance of the subset of the plurality of resistive elements automatically reverts from the second resistance state to the first resistance state during the predetermined holding period due to inherent material properties of the resistive material, thereby automatically erasing the second binary state.

Description

[Background technology]

[0001] The present invention relates generally to the field of data security, and more particularly to devices with reconfigurable short-term data retention.

[0002] Data security / protection is the practice of protecting digital information from damage, unauthorized access, or theft. The latter two in particular are becoming increasingly relevant. For example, platforms such as social media offer users the ability to automatically delete their posted (uploaded) data from the cloud, as well as the option to specify a time period for scheduling the deletion. In other applications, such as cache memory and encryption, data destruction is also required to prevent the threat of hacking of important files such as passwords.

[0003] In modern systems, timer circuits and memory buffers are used for timed deletion of data. Modern computers use oscillator circuits to implement timers. These are usually large circuits. Summary of the Invention

[0004] According to one aspect, the invention is embodied in a device including a plurality of resistive memory elements, the plurality of resistive memory elements comprising a resistive material. The device is configured to apply a programming pulse to a subset of the plurality of resistive memory elements to effect a temporary resistance change in the resistive material of the subset over a predetermined hold period, thereby programming the subset of the plurality of resistive elements from a first resistance state corresponding to a first binary state to a second resistance state corresponding to a second binary state. The device is configured such that the resistance of the subset of the plurality of resistive elements automatically reverts from the second resistance state to the first resistance state during the predetermined hold period due to inherent material properties of the resistive material, thereby automatically erasing the second binary state.

[0005] According to another aspect, there is provided a design structure tangibly embodied in a machine-readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising a device according to the immediately preceding device aspect.

[0006] According to another aspect, a method for performing short-term data retention by a device including a plurality of resistive elements is provided. The plurality of resistive elements include a resistive material. The method includes applying a programming pulse to a subset of the plurality of resistive elements to perform a temporary resistance change in the resistive material of the subset for a predetermined retention period, thereby programming the subset of the plurality of resistive elements from a first resistance state corresponding to a first binary state to a second resistance state corresponding to a second binary state. The method further includes automatically reverting from the second resistance state to the first resistance state during the predetermined retention period due to an inherent material property of the resistive material, thereby automatically erasing the second binary state.

[0007] Embodiments of the invention will be described in more detail below, by way of illustrative and non-limiting examples, with reference to the accompanying drawings, in which: [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a simplified schematic block diagram of a device according to one embodiment of the present invention. [Figure 2] FIG. 2 is a diagram of a memory crossbar array, according to one embodiment of the present invention. [Figure 3] 3 is a schematic diagram of current / voltage characteristics of material components of a phase change memory cell, according to one embodiment of the present invention. [Figure 4A] FIG. 2 is a diagram of an exemplary resistive element according to one embodiment of the present invention. [Figure 4B] 4B is a diagram of an embodiment for utilizing crystallization dynamics in nanoscale devices, particularly of a phase change element as shown in FIG. 4A, according to one embodiment of the present invention. [Figure 5]4B is a diagram illustrating in more detail a retention curve of a resistive element, for example, the phase change element shown in FIG. 4A, according to an embodiment of the present invention. [Figure 6] FIG. 4 is a diagram of the state-dependent retention time of a resistive element, according to an embodiment of the present invention. [Figure 7] 1 is a diagram of an application of a device including a resistive element according to an embodiment of the invention in the area of ​​data security; [Figure 8] 1 is a diagram of an application of a device including a resistive element according to an embodiment of the invention in the area of ​​computational memory; [Figure 9] FIG. 2 is a diagram of a memory crossbar array, according to an embodiment of the present invention. [Figure 10] 1 is a diagram illustrating an exemplary retention curve for a phase change element including GeSb as the phase change material, in accordance with one embodiment of the present invention. [Figure 11A] 11A-11C are diagrams of device geometries of resistive elements that may be used in accordance with embodiments of the present invention, where FIG. 11A is a diagram of a bridge cell; [Figure 11B] 11A-11C are diagrams of device geometries of resistive elements that may be used in accordance with embodiments of the present invention, where FIG. 11B is a diagram of a mushroom cell. [Figure 11C] 11A-11C are diagrams of device geometries of resistive elements that may be used in accordance with embodiments of the present invention, where FIG. 11C is a diagram of a trench cell. [Figure 11D] 11A-11D are diagrams of device geometries of resistive elements that may be used in accordance with embodiments of the present invention, where FIG. 11D is a diagram of a confined cell. [Figure 12] 1 is a block diagram of an exemplary design flow according to one embodiment of the present invention. [Figure 13] 3 is a flowchart of method steps of a method for performing short-term data retention by a device including multiple resistive elements, according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Embodiments of the present invention recognize the need for devices with short-term and adjustable data retention capabilities. According to embodiments of the present invention, a resistive element may be defined as an element whose electrical resistance can be changed by applying an electrical programming signal to the resistive element. The resistive element may be particularly embodied as a resistive memory element. The electrical programming signal may be a current flowing through the resistive memory element or a voltage applied to the resistive memory element. The current and / or voltage may be applied to the resistive memory element in the form of, for example, a pulse. As a result, the electrical resistance of the resistive memory element depends on the history of currents previously flowing through the memory element and / or the history of electrical signals applied to the resistive memory element.

[0010] Resistive memory elements are based on physical phenomena occurring in materials that change their resistance under the action of an electric current or an electric field. The change is usually non-volatile and reversible. Several classes of resistive memory elements are known, ranging from metal oxides to chalcogenides. A typical resistive memory element is a metal / insulator / metal structure, in which the metal component acts as an electrode and the insulator is a resistive switching material such as a chalcogenide. These resistive memory elements exhibit good performance in terms of power consumption, integration density potential, retention, and endurance.

[0011] Phase change memory (PCM) is a rapidly emerging non-volatile memory technology for both data storage and computational memory applications, including neuromorphic computing. Traditionally, PCM devices have required long-term retention capabilities. However, embodiments of the present invention use selective phase change material systems and exploit their crystallization dynamics (amorphous to crystalline phase transition) to implement memory devices with tunable short-term data retention applications. According to embodiments, data retention time is a function of the starting amorphous volume of the phase change material and is therefore tunable by applying suitable write programming pulses; i.e., devices with larger amorphous volumes take longer to crystallize, and vice versa. Thus, embodiments of the present invention result in devices with reconfigurable short-term data retention.

[0012] According to embodiments, a self-destructing binary phase change memory may be provided, particularly for data protection applications. According to embodiments, a user may specify a retention time for program data, where the data may be spontaneously erased without requiring an erase programming operation.

[0013] Embodiments of the present invention may eliminate the need for external timer circuits and memory buffers, thus resulting in significant space and energy savings.

[0014] Embodiments of the present invention may provide a variety of data retention times that may scale from μs to hours or even days.

[0015] Embodiments of the present invention can be implemented using conventional phase change device architecture and circuitry hardware.

[0016] 1 is a simplified schematic block diagram of a device 100 according to one embodiment of the present invention. The device 100 includes a resistive memory 10 having a plurality of programmable resistance elements. Additionally, a signal generator 11 is provided. The signal generator 11 is configured to apply an electrical programming signal to the resistive elements of the resistive memory 10. The signal generator 11 includes circuitry for programming the resistive memory cells during a data write or programming operation. The signal generator 11 is configured to apply the programming signal to the resistive elements to program the conductance values ​​of the resistive elements.

[0017] Additionally, device 100 includes read circuitry 12 configured to read the resistance values ​​of the resistive elements during a data read operation. Device 100 is configured, for example, to apply read voltages to rows of the memory crossbar array. The device is further configured to read current values ​​of columns of the memory crossbar array.

[0018] The device 100 further includes control circuitry 13 configured to control the signal generator 11 and the readout circuitry 12 .

[0019] Memory 10 may generally be any type of resistive memory described above. In particular, it may be a phase change memory (PCM) or a resistive random access memory (RRAM). In the following, it is assumed that resistive memory 10 is embodied as a PCM. Accordingly, resistive memory 10 includes a plurality of PCM cells as resistive memory elements. The PCM cells of memory 10 may have s=2 programmable resistance states. The programmable resistance states correspond to various relative proportions of amorphous and crystalline phases within the cell's PCM material. These states may include a high-resistance, fully amorphous RESET state, a low-resistance, fully crystalline SET state, and an intermediate, partially amorphous RESET state corresponding to increasing sizes of amorphous phases within the multiple, otherwise crystalline PCM materials. Each amorphous volume of the amorphous cell state corresponds to a predetermined holding period of the corresponding RESET state.

[0020] 2 illustrates a memory crossbar array 200 according to one embodiment of the present invention. The memory crossbar array 200 includes three row lines 201, 202, and 203 and three column lines 204, 205, and 206. The three row lines 201, 202, and 203 are disposed above three column lines 204, 205, and 206, which are indicated by dotted lines. More specifically, the row lines 201, 202, and 203 extend in a first XY plane, and the three column lines extend in a second XY plane, with the first XY plane disposed above the second XY plane in the vertical Z direction.

[0021] The three row lines 201, 202, and 203 and the three column lines 204, 205, and 206 are connected to each other via a vertical junction 210. The junction 210 extends in the vertical Z direction between an upper intersection 211a of the row lines 201 to 203 and a lower intersection 211b of the column lines 204 to 206.

[0022] Each junction 210 comprises a series arrangement of a resistive memory element and a transistor, which are not shown in FIG.

[0023] More specifically, the crossbar array 200 comprises nine resistive memory elements embodied as PCM cells. Row lines 201 are connected to resistive memory elements R 11 , R 12 , and R 13 and row line 202 is connected to memory element R 21 , R 22 , and R 23 and row line 203 is connected to memory element R 31 , R 32 , and R 33 Equipped with.

[0024] To program the resistive element, the signal generator 11 applies a programming signal, in particular a current pulse, to the resistive element, thereby programming the conductance value.

[0025] To read out the respective conductance values, readout circuitry 12 may apply readout voltages to column lines 204, 205, and 206. Readout circuitry 12 then reads out the current values ​​of row lines 201, 202, and 203.

[0026] FIG. 3 is a schematic diagram 300 of the current / voltage (and therefore resistance) characteristics of material components of a memory cell, such as resistive element 400 of FIG. 4A below.

[0027] The solid lines show the variation of current with voltage for PCM materials, starting from the fully crystalline SET state (top curve) and similarly the fully amorphous RESET state (bottom curve). These two curves reflect the large (typically three orders of magnitude) variation in resistivity between the crystalline and amorphous phases. The amorphous phase exhibits nonlinear characteristics with a field-induced threshold switching phenomenon. At a particular threshold voltage V THAt , this phase switches to a very low "ON-state" resistance corresponding to that of crystalline PCM materials. The cell programming (write) voltage is chosen to be above this threshold voltage, as shown.

[0028] As can be seen in FIG. 3, the current in the read mode is a slightly non-linear function of the voltage.

[0029] 4A is a diagram of an exemplary resistive element 400, according to one embodiment of the present invention. Resistive element 400 is embodied as a phase change element and comprises a resistive material 403 disposed between a top electrode 401 and a bottom electrode 402. Resistive material 403 comprises a crystalline portion 403b and an amorphous portion 403a.

[0030] 4B illustrates one embodiment for utilizing crystallization dynamics in nanoscale devices, particularly the phase change element 400 shown in FIG. 4A. The phase change element exhibits a Joule heating-induced reversible phase transition between amorphous and crystalline states within the phase change material. The physical size of a phase, such as an amorphous phase within a crystalline matrix, can be controlled using programming parameters, particularly the programming current.

[0031] The X-axis represents the programming current in μA, and the Y-axis represents the resulting resistance of the phase-change element in Ω. According to the illustrated example, phase-change element 400 is configured to program the phase-change element into three different amorphous volumes 410, 411, and 412 and three different second resistance states corresponding to three second binary states having different retention times. The first resistance states and corresponding first binary states can be represented by the fully crystalline volumes of the phase-change element. The maximum amorphous volume 412 corresponds to the longest retention time, the medium amorphous volume 411 corresponds to the medium retention time, and the minimum amorphous volume 410 corresponds to the shortest retention time.

[0032] 5 shows in more detail a representation 500 of a retention curve for a resistive element, in accordance with an embodiment of the present invention, for example, for phase change element 400 shown in FIG. 4A. The x-axis represents the time in seconds after programming phase change element 400 to a predetermined amorphous volume. The y-axis represents the resistance of the phase change element in ohms.

[0033] By applying a programming pulse to phase change element 400, a temporary resistance change of the resistive material can be achieved for a predetermined retention period. More specifically, phase change element 400 can be programmed from a first resistance state corresponding to a first binary state to a second resistance state corresponding to a second binary state. The first resistance state can correspond, for example, to binary state "Bit 1" and can encompass a resistance range 521 below a reference or threshold 520, while the second resistance state can correspond, for example, to binary state "Bit 0" and can encompass a resistance range 522 above the reference or threshold 520.

[0034] FIG. 5 shows seven retention curves 510, 511, 512, 513, 514, 515, and 516, each having a different initial second resistance state corresponding to a different amorphous volume. As can be seen in FIG. 5, the resistance value of the second resistance state evolves over time. More specifically, it initially increases slightly over time due to relaxation. At the peak of each curve, crystallization begins, and shortly after the onset of crystallization, the resistance drops sharply. Shortly after the resistance state passes the reference value 520, the corresponding resistive device reverts from the second resistance state to the first resistance state. This automatic reversal is achieved by the inherent material properties of the resistive material, more specifically, the crystallization dynamics of the corresponding phase-change material. The automatic change of the resistance state from the second resistance state to the first resistance state automatically eliminates the second binary state. In other words, the device automatically reverts from "bit 0" back to "bit 1."

[0035] As can be seen by the different curves 510-516, devices programmed to "bit 0" will become "bit 1" after different retention periods depending on their starting resistance. Thus, devices according to embodiments of the present invention store "bit 0" in the RESET state and "bit 1" in the SET state. The RESET to SET operation is performed using a programming write electrical pulse. If this process occurs spontaneously through crystal growth, data can be controllably self-destructed. Such crystal growth is indeed dominant in phase-change materials and in nanoscale devices.

[0036] 6 is a diagram of the state-dependent retention period, or in other words, retention time, of resistive elements according to embodiments of the present invention. More specifically, the X-axis shows the amorphization length L of each phase-change element in nm, and the Y-axis shows the corresponding retention time of the second binary state / second resistive state in seconds. The amorphization length L indicates the maximum (radial) extension of the amorphous volume starting from the heating electrode. As can be derived from FIG. 6, the higher the amorphization length L, the longer the retention time.

[0037] FIG. 7 is a diagram of an application of a device including a resistive element according to an embodiment of the present invention in the field of data security. More specifically, FIG. 7 shows a display 700 for displaying a security image. The display 700 is programmed to self-destruct each security image. Every pixel of the image is associated with a phase-change memory element / device. A "0" bit is only temporarily stable and becomes a "1" due to crystallization of the phase-change material. According to this example, a "0" bit is associated with dark pixels representing the numbers A, B, C, and D. A "0" bit is implemented by programming the respective memory cell to a predetermined amorphous volume, illustrated by phase-change memory cell 710. A "1" bit is implemented by a crystalline phase-change memory cell 711.

[0038] FIG. 8 shows a graph 800 of an application of a device including a resistive element according to an embodiment of the present invention in the field of computational memory. More specifically, FIG. 8 illustrates a method for implementing a short-term plasticity synthetic synapse using a device according to an embodiment of the present invention. A PCM synapse with short-term memory properties may implement a biophysical mechanism. FIG. 8 illustrates an exemplary application of short-term synaptic fatigue in muscles. If a muscle is continuously active, depending on the intensity of the activity, the synapse may become less conductive and take longer to recover, thereby implementing muscle fatigue.

[0039] More specifically, the X-axis indicates the time of muscle activity in seconds, and the Y-axis indicates the corresponding conductivity G of the muscle in μS. As can be derived from Figure 6, the higher the amorphization length, the longer the retention time. As an example, curve 801 may be implemented with a phase change element programmed with a somewhat smaller amorphous volume, while curve 802 may be implemented with a phase change element programmed with a larger amorphous volume.

[0040] FIG. 9 is a diagram of a memory crossbar array 900 according to an embodiment of the present invention. The memory crossbar array 900 includes a plurality of resistive elements 901 arranged within the crossbar array. The crossbar array includes a plurality of row lines 902 (word lines “WL”), a plurality of column lines 903 (bit lines “BL”), and a plurality of junctions 904 arranged between the plurality of row lines 902 and the plurality of column lines 903. Each junction includes a programmable resistive element 901 and an access element (not shown), such as a transistor, for accessing the programmable resistive element. The crossbar array 900 may include three different device states. The first device state may be a bit “0” corresponding to a first (low) resistance state. This may also be referred to as a “SET” state. The second device state may be a bit “1” corresponding to a second (high) resistance state. The second device state may also be referred to as a “RESET1” state, or in other words, a first RESET state with a long retention period. The longer retention period corresponds to the larger amorphous volume illustrated by exemplary phase change element 920. The third device state may also be referred to as the “RESET2” state, or in other words, a second RESET state with a shorter retention period. The shorter retention period corresponds to the smaller amorphous volume illustrated by exemplary phase change element 921.

[0041] FIG. 10 shows a diagram 1000 illustrating exemplary retention curves 1001, 1002, 1003, 1004, 1005, and 1006 of a phase-change element including GeSb as the phase-change material. The retention curves 1001-1006 have different initial second resistance states corresponding to different amorphous onset volumes or amorphous onset lengths. The larger the amorphous onset volume / length, the longer the retention period. As can be seen in FIG. 10, the resistance value of the second resistance state evolves over time. Shortly after the resistance state passes the reference value 1020, the corresponding resistive device reverts from the second resistance state to the first resistance state. This automatic reversal is achieved by the inherent material properties of the resistive material, more specifically, the crystallization dynamics of GeSb phase-change material. The automatic change of the resistance state from the second resistance state to the first resistance state automatically eliminates the second binary state.

[0042] According to another embodiment, Sb, Ge x Sb y , Ga x Sb y , Sb x Te y , Ge x Sb y Te z , Ge x Te y , or Ag x In y Sb z Te n can be used as resistive materials, where x, y, z, and n represent atomic percentages. These materials exhibit advantageous crystallization dynamics that can be used for implementing short-term data retention applications. According to embodiments, the resistive materials can be doped with O, N, C, SiO2, or Sc. Using such doping, the crystallization dynamics and associated data retention properties, particularly data retention time, can be further tuned and / or adjusted.

[0043] Devices according to embodiments of the present invention may be configured to operate in an environment having an elevated temperature above room temperature. The elevated temperature may be within a temperature range between 25°C and 100°C. Operating the device and its resistive element at such elevated temperatures may promote short-term data retention characteristics of the resistive element. According to embodiments, the environmental temperature may be used to adjust the retention time of the second binary state of the resistive element. According to embodiments, the higher the environmental temperature, the shorter the retention time of the second binary state of the resistive element. This is due to the effect of the elevated temperature in promoting recrystallization of the amorphous volume.

[0044] According to embodiments, the predetermined hold period for the second resistance state may be in the range between 1 μs and 12 hours. According to further embodiments, the predetermined hold period may be one day or even several days.

[0045] According to embodiments, the resistive element may also be embodied as a conductive bridge resistive memory element, a metal oxide random access memory (RRAM) element, a magnetoresistive random access memory (MRAM) element, or a ferroelectric random access memory (FeRAM) element.

[0046] 11A-11D illustrate device geometries of resistive elements that may be used in accordance with embodiments of the present invention.

[0047] FIG. 11A shows a bridge cell including a substrate 1102, an electrode 1101, and a resistive material 1103 including an amorphous volume 1103a and a crystalline volume 1103b.

[0048] FIG. 11B shows a mushroom cell including a top electrode 1111, a resistive material 1112 including an amorphous volume 1112a and a crystalline volume 1112b, and a heater 1113.

[0049] FIG. 11C shows a trench cell including an electrode 1121 and a resistive material 1122 that includes an amorphous volume 1122a and a crystalline volume 1122b.

[0050] FIG. 11D shows a closed cell including a substrate 1131 and a resistive material 1132 that includes an amorphous volume 1132a and a crystalline volume 1132b.

[0051] FIG. 12 shows a block diagram of an exemplary design flow 1200 used, for example, in semiconductor IC logic design, simulation, testing, layout, and manufacturing. Design flow 1200 includes processes, machines, and / or mechanisms for processing design structures or devices to generate logically or otherwise functionally equivalent representations of the design structures and / or devices described above and shown, for example, in FIGS. 1-11D. The design structures processed and / or generated by design flow 1200 may be encoded on a machine-readable transmission or storage medium to include data and / or instructions that, when executed on a data processing system or otherwise processed, generate logically, structurally, mechanically, or otherwise functionally equivalent representations of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machines used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system. For example, the machine may include a lithography machine, a machine and / or equipment for generating a mask (e.g., an e-beam writer), a computer or equipment for simulating a design structure, any apparatus used in a manufacturing or testing process, or any machine for programming a functionally equivalent representation of a design structure into any medium (e.g., a machine for programming a programmable gate array).

[0052] Design flow 1200 may vary depending on the type of representation being designed. For example, a design flow 1200 for building an application specific integrated circuit (ASIC) may differ from a design flow 1200 for designing a standard component or for instantiating a design into a programmable array such as a programmable gate array (PGA) or field programmable gate array (FPGA).

[0053] FIG. 12 illustrates multiple such design structures, including input design structure 1220, which is preferably processed by design process 1210. Design structure 1220 may be a logic simulation design structure generated and processed by design process 1210 to generate a logically equivalent functional representation of a hardware device. Design structure 1220 may also or alternatively include data and / or program instructions that, when processed by design process 1210, generate a functional representation of the physical structure of the hardware device. Whether representing functional and / or structural design features, design structure 1220 may be generated using electronic computer-aided design (ECAD), as implemented by a core developer / designer. When encoded on a machine-readable data transmission, gate array, or storage medium, design structure 1220 may be accessed and processed by one or more hardware and / or software modules in design process 1210 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logical module, apparatus, device, or system, such as those shown in FIGS. 1-11D. As such, design structures 1220 may include files or other data structures containing human- and / or machine-readable source code, compiled structures, and computer-executable code structures that, when processed by a design or simulation data processing system, functionally simulate or otherwise represent a circuit or other level of hardware logic design. Such data structures may include hardware-description language (HDL) design entities or other data structures that conform to and / or are compatible with low-level HDL design languages ​​such as Verilog and VHDL, and / or high-level design languages ​​such as C or C++.

[0054] Design process 1210 preferably employs and incorporates hardware and / or software modules for synthesizing, translating, or otherwise processing design / simulation functional equivalents of the components, circuits, devices, or logic structures shown in FIGS. 1-11D to generate netlist 1280, which may include design structures such as design structure 1220. Netlist 1280 may include compiled or otherwise processed data structures, etc., representing lists of wires, discrete components, logic gates, control circuits, I / O devices, models, etc., that describe connections to other elements and circuits within an integrated circuit design. Netlist 1280 may be synthesized using an iterative process in which netlist 1280 is resynthesized one or more times depending on device design specifications and parameters. As with the other types of design structures described herein, netlist 1280 may be recorded on a machine-readable data storage medium or programmed into a programmable gate array. The medium may be a non-volatile storage medium such as a magnetic or optical disk drive, a programmable gate array, compact flash, or other flash memory. Additionally or alternatively, the medium may be a system or cache memory, buffer space, or electrically or optically conductive devices and materials in which data packets may be transmitted and intermediately stored over the Internet or other suitable means of networking.

[0055] Design process 1210 may include hardware and software modules for processing various input data structure types, including netlist 1280. Such data structure types may include sets of commonly used elements, circuits, and devices, such as those found in library elements 1230, including models, layouts, and symbolic representations for a given manufacturing technology (e.g., various technology nodes, 32 nm, 45 nm, 90 nm, etc.). Data structure types may further include design specifications 1240, characterization data 1250, verification data 1260, design rules 1270, and test data files 1285, which may include input test patterns, output test results, and other test information. Design process 1210 may also include standard mechanical design processes, such as stress analysis, thermal analysis, mechanical event simulation, and processing simulation for operations, such as casting, molding, and die press forming. Those skilled in the art of mechanical design will recognize the breadth of possible mechanical design tools and applications that may be used in design process 1210 without departing from the scope of the present invention. The design process 1210 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, and the like.

[0056] Design process 1210 employs and incorporates logical and physical design tools, such as HDL compilers and simulation model building tools, to process design structure 1220 together with some or all of the illustrated supporting data structures, along with any additional mechanical design or data (if applicable), to generate second design structure 1290. Design structure 1290 resides on a storage medium or programmable gate array in a data format used for the exchange of mechanical device and structure data (e.g., information stored in IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures). Like design structure 1220, design structure 1290 preferably resides on a transmission or data storage medium and includes one or more files, data structures, or other computer-encoded data or instructions that, when processed by an ECAD system, generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the present invention shown in FIGS. 1-11D. In one embodiment, design structure 1290 may include a compiled, executable HDL simulation model that functionally simulates the device shown in FIGS. 1-11D.

[0057] Design structure 1290 may employ a data format and / or symbolic data format used for the exchange of integrated circuit layout data (e.g., information stored in GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 1290 may include information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, metal layers, vias, shapes, data for routing through a manufacturing line, and any other data required by a manufacturer or other designer / developer to generate the devices or structures shown in FIGS. 1-11D described above. Design structure 1290 may then proceed to stage 1295, where, for example, design structure 1290 may proceed to tapeout, be released for manufacturing, be released to a mask house, be sent to another design house, be sent back to a customer, etc.

[0058] 13 shows a flowchart 1300 of method steps for performing short-term data retention with a device including multiple resistive elements. The method may be performed, for example, using a device according to an embodiment of the present invention, such as device 100 shown in FIG.

[0059] The method begins at step 1310 with one or more of the resistive elements having a first resistance state, in particular a low resistance state, corresponding to a first binary state.

[0060] In step 1320, the method includes encoding data by applying one or more programming pulses associated with selective second binary states to a subset of the plurality of resistive elements to effect a temporary resistance change in the resistive material of the subset for a predetermined retention period, which may involve an iterative write and verify procedure.

[0061] As a result of step 1320, a subset of the plurality of resistive elements is programmed to, and thus reaches, a second resistance state corresponding to a second binary state, in particular a high resistance state, i.e., a higher resistance state than that in step 1310, in step 1330.

[0062] In step 1340, the resistive element is automatically crystallized by the inherent crystallization dynamics of the resistive material, without the application of any additional pulses, such as erase pulses. In other words, step 1340 allows the binary state to flip due to the intrinsic crystallization properties. Crystallization can only be assisted by operating the device in an elevated temperature environment.

[0063] As a result of the automatic crystallization of step 1340, the device automatically reverted or reverted from the second resistance state to the first resistance state, thereby automatically erasing the second binary state.

[0064] In step 1350, new data may be encoded by applying programming pulses associated with selective second binary states.

[0065] The description of various embodiments of the present invention has been presented for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best explain the principles, practical applications, or technical improvements of the embodiments over art found in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

[0066] In general, modifications described with respect to one embodiment may be applied as appropriate to another embodiment.

Claims

1. 1. A device comprising a plurality of resistive elements, the plurality of resistive elements having a resistive material, the device being configured to apply a programming pulse to a subset of the plurality of resistive elements to effect a temporary resistance change in the resistive material of the subset for a predetermined holding period, thereby programming the subset of the plurality of resistive elements from a first resistance state corresponding to a first binary state to a second resistance state corresponding to a second binary state, the device being configured such that the resistance of the resistive material of the subset of the plurality of resistive elements automatically reverts from the second resistance state to the first resistance state during the predetermined holding period due to inherent material properties of the resistive material, thereby automatically erasing the second binary state.

2. the plurality of resistive elements are phase change elements, and the resistive material is a phase change material; programming the subset of the plurality of resistive elements from the first resistance state to the second resistance state includes performing a temporary amorphization of the phase change material, thereby creating an amorphous volume; the intrinsic material property is the crystallization dynamics of the phase change material; the device is configured such that the resistance of the subset of the plurality of resistive elements automatically reverts from the second resistance state to the first resistance state upon crystallization of the amorphous volume. The device of claim 1 .

3. the device is configured to adjust the predetermined retention period of the plurality of resistive elements by programming the subset of the plurality of resistive elements to a plurality of different amorphous volumes. The device of claim 2 .

4. The device of claim 1 , wherein the device is configured to program the subset of the plurality of resistive elements to a plurality of second binary states having different hold periods.

5. The resistive material is Sb, Ge ｘ Sb ｙ , Ga ｘ Sb ｙ , Sb ｘ Te ｙ , Ge ｘ Sb ｙ Te ｚ , Ge ｘ Te ｙ and Ag ｘ In ｙ Sb ｚ Te ｎ 10. The device of claim 1, wherein x, y, z, and n are selected from the group consisting of:

6. The resistive material is O, N, C, SiO ２ 6. The device of claim 5, wherein the device is doped with a material selected from the group consisting of: SiO.sub.2, SiO.sub.2, and Sc.

7. The device of claim 1 , wherein the device is configured to operate in an environment having an elevated temperature above room temperature.

8. 8. The device of claim 7, wherein the elevated temperature is within a temperature range between 25°C and 100°C.

9. The device of claim 1 , wherein the predetermined hold period is in a range between 1 μs and 12 hours.

10. 2. The device of claim 1, wherein the plurality of resistive elements are selected from the group consisting of phase change memory (PCM) elements, conductive bridge resistive memory elements, metal oxide random access memory (RRAM) elements, magnetoresistive random access memory (MRAM) elements, and ferroelectric random access memory (FeRAM) elements.

11. The device of claim 1 , wherein the device is embodied as a computational memory device.

12. The device of claim 1 , wherein the device is embodied as a short-term memory device.

13. The device of claim 1 , wherein the plurality of resistive element geometries are selected from the group consisting of bridge cells, mushroom cells, trench cells, and closed cells.

14. 2. The device of claim 1, wherein the plurality of resistive elements are arranged in a crossbar array, the crossbar array having a plurality of row lines, a plurality of column lines, and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines, each junction including a programmable resistive element and an access element for accessing the programmable resistive element.

15. The device of claim 1 , wherein the device comprises a signal generator configured to program the resistances of the plurality of resistive elements by an iterative programming and verify procedure.

16. 1. A design structure tangibly embodied in a machine-readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising a device having a plurality of resistive elements, the plurality of resistive elements comprising a resistive material, the device configured to apply a programming pulse to a subset of the plurality of resistive elements to effect a temporary resistance change in the resistive material of the subset for a predetermined holding period, thereby programming the subset of the plurality of resistive elements from a first resistance state corresponding to a first binary state to a second resistance state corresponding to a second binary state, the device configured such that the resistance of the resistive material of the subset of the plurality of resistive elements automatically reverts from the second resistance state to the first resistance state during the predetermined holding period due to inherent material properties of the resistive material, thereby automatically erasing the second binary state.

17. the plurality of resistive elements are phase change elements, and the resistive material is a phase change material; programming the subset of the plurality of resistive elements from the first resistance state to the second resistance state includes performing a temporary amorphization of the phase change material, thereby creating an amorphous volume; the intrinsic material property is the crystallization dynamics of the phase change material; the device is configured such that the resistance of the subset of the plurality of resistive elements automatically reverts from the second resistance state to the first resistance state upon crystallization of the amorphous volume.

17. The design structure of claim 16.

18. 1. A method for performing short-term data retention with a device comprising a plurality of resistive elements, the plurality of resistive elements having a resistive material, the method comprising: applying a programming pulse to a subset of the plurality of resistive elements to effect a temporary resistance change of the resistive material of the subset for a predetermined hold period, thereby programming the subset of the plurality of resistive elements from a first resistance state corresponding to a first binary state to a second resistance state corresponding to a second binary state; and automatically reverting from the second resistance state to the first resistance state during the predetermined hold period due to inherent material properties of the resistive material, thereby automatically erasing the second binary state. A method comprising:

19. the plurality of resistive elements are phase change elements, and the resistive material is a phase change material; programming the subset of the plurality of resistive elements from the first resistance state to the second resistance state includes performing a temporary amorphization of the phase change material, thereby creating an amorphous volume; the intrinsic material property is the crystallization dynamics of the phase change material; crystallizing the amorphous volume by performing an intrinsic crystallization of the amorphous volume, thereby automatically changing the resistance of the subset of the plurality of resistive elements from the second resistance state back to the first resistance state.

20. The method of claim 18, further comprising:

20. adjusting the predetermined hold periods of the plurality of resistive elements by programming the subset of the plurality of resistive elements to a plurality of different amorphous volumes.

20. The method of claim 19 further comprising:

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