Global Positioning Satellite System Receiver

Abstract

The positioning receiver, which is comprised of a positioning system (200), includes multiple radio frequency transmission paths configured to receive Global Navigation Satellite System (GNSS) signals from an antenna and transmit the GNSS signals in a frequency range for digitizing the GNSS signals. The positioning system includes several analog-to-digital converters (101); multiple signal processors (102) forming multiple signal transmission paths; a requantizer (103); a positioning channel (104); and a time control unit (105) transmitting a tick signal (S106). The positioning receiver further includes a CPU system (110) including a central processing unit (CPU) (107), a BUS (data bus) (108), and a memory (109), and receives a data creation completion flag signal (S111). The positioning system and the CPU system are connected by interface blocks (202) and (203). The present invention provides an increased processing speed for positioning data.

Description

[Technical Field]

[0001] The subject matter of this disclosure relates generally to positioning receivers, and more particularly to receivers for processing satellite positioning signals received from multiple satellites of various Global Navigation Satellite Systems (GNSS), such as GPS and GLONASS. [Background technology]

[0002] Global positioning satellite system receivers receive and process signals from multiple GNSS satellites to determine the receiver's position. Various techniques have been developed to process these signals, but these techniques require significant processing power and can be costly and time consuming. What is needed is a low-cost receiver that utilizes technology to quickly process multiple GNSS satellite signals. Summary of the Invention

[0003] The positioning receiver includes a plurality of RF transmission paths configured to receive GNSS signals from an antenna and transmit the GNSS signals to a frequency range for digitizing the GNSS signals. The positioning receiver further includes a positioning system and a CPU system. In one embodiment, the positioning system is configured to process the GNSS signals based on a clock CLKnav, and includes a plurality of analog-to-digital converters (ADCs) configured to digitize signals from the plurality of RF transmission paths, a plurality of signal processors configured to process the digitized signals, a plurality of requantizers configured to convert the digitized signals to low-bit data, a plurality of positioning system-to-CPU system (NS2CS) interface blocks configured to generate packages, a plurality of CPU system-to-positioning system (CS2NS) interface blocks configured to convert the packages to data, a MUX interconnection unit configured to distribute the data stream, a time control unit configured to generate a tick signal, and an asynchronous first-in-first-out (AFIFO) unit configured to send the low-bit data and the tick signal over the plurality of channels. In one embodiment, the CPU system is configured to process the package based on a clock CLKcpu, and includes a memory configured to store data and the package; a plurality of hardware accelerator units configured to process the package; a positioning direct memory access (DMA) configured to convert the package into data, the data being data for a plurality of channels configured to process data from one of the positioning DMAs or AFIFOs; and a CPU configured to control the positioning system and the CPU system, read results of the GNSS signal processing from the plurality of channels configured to process data from one of the positioning DMAs or AFIFOs, and process the results of the GNSS signal processing. [Brief explanation of the drawings]

[0004] [Figure 1]FIG. 1 shows a prior art Global Navigation Satellite System (GNSS) receiver.

[0005] [Figure 2A] FIG. 2A illustrates a GNSS receiver according to one embodiment.

[0006] [Figure 2B] FIG. 2B illustrates a GNSS receiver according to one embodiment.

[0007] [Figure 3] FIG. 3 illustrates a positioning system to CPU system (NS2CS) interface block connecting the positioning system and the CPU system, according to one embodiment.

[0008] [Figure 4] FIG. 4A illustrates a signal graph of interface block NS2CS of FIG. 3 operating in single package mode, according to one embodiment.

[0009] FIG. 4B illustrates a signal graph of interface block NS2CS of FIG. 3 operating in multi-package mode, according to one embodiment.

[0010] [Figure 5] FIG. 5 illustrates a CPU System to Positioning System (CS2NS) interface block connecting the CPU system and the positioning system, according to one embodiment.

[0011] [Figure 6] FIG. 6A illustrates components that transmit signals to the positioning DMA of FIGS. 2A, 2B, and 3, according to one embodiment.

[0012] FIG. 6B illustrates a data processing chain according to one embodiment.

[0013] [Figure 7] FIG. 7 shows a timing diagram of clock signals for decimation, according to one embodiment.

[0014] [Figure 8] FIG. 8 illustrates a positioning channel in communication with the positioning DMA, NS2CS, and CPU system of FIG. 2A, according to one embodiment.

[0015] [Figure 9A] FIG. 9A illustrates packaging processing steps according to one embodiment.

[0016] [Figure 9B] FIG. 9B shows a diagram of the positioning DMA of FIGS. 2A, 2B, 3, and 4A operating in a single package mode of operation, according to one embodiment.

[0017] [Figure 9C] FIG. 9C shows a diagram of the positioning DMA of FIGS. 2A, 2B, 3, and 4B operating in a multi-package mode of operation, according to one embodiment.

[0018] [Figure 10] FIG. 10 shows a high-level block diagram of a computer that performs the operations of each of the components described herein, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] FIG. 1 shows an overview of a prior art positioning receiver (e.g., a GNSS receiver) comprising a positioning system 100 including “A” analog-to-digital converters (ADCs), denoted as ADCs 101(1)...101(A). ADCs 101(1)...101(A) are collectively referred to as ADCs 101. The positioning system 100 further comprises multiple signal processors that form multiple signal transmission paths. One signal transmission path is comprised of “S” signal processors, represented by signal processors 102(1,1)...102(S,1). There are “P” signal transmission paths, represented by signal processors 102(1,1)...(1,P). Accordingly, the first transmission path is represented by signal processors 102(1,1)...102(S,1), and the last transmission path is represented by signal processors 102(1,P)...(S,P). The multiple signal processors, including signal processors 102(1,1)...102(1,P) and signal processors 102(S,1)...(S,P), are collectively referred to as signal processor 102. The positioning receiver further comprises "Q" requantizers, represented by requantizers 103(1)...103(Q). Requantizers 103(1)...103(Q) are collectively referred to as requantizer 103. The positioning receiver shown in FIG. 1 further comprises a positioning channel 104, a time control unit 105 that transmits a tick signal S106, and a CPU system 110, which comprises a CPU 107, a BUS 108, and a memory 109, and receives a data creation completion flag signal S111.

[0020] GNSS signals are received from the antenna and transmitted to one or more of multiple RF channels connected to the inputs of the ADCs 101. In one embodiment, these RF channels are configured to transmit the GNSS signals to a specific frequency range for digitization. In one embodiment, each of the ADCs 101 receives a signal from one of the multiple RF channels. In one embodiment, some or all of the ADCs 101 may receive a signal from a single RF channel. From the output of the ADCs 101, the digitized signal is input to a signal processor 102, which processes the signal.

[0021] The signal processor 102 may be one or more components, such as a filter, a noise suppressor, an equalizer, and / or a decimator.

[0022] The signals output from the signal processors 102(S,1)...102(S,P) are input to requantizers 103(1)...103(Q), which requantize the received data into low-bit data. The low-bit data output from the requantizers 103(1)...103(Q) is input to a positioning channel 104, which processes the low-bit data.

[0023] The positioning channel 104 transmits a data creation completion flag signal S111 to the CPU 107. The data creation completion flag signal S111 indicates that the positioning channel 104 has completed the creation of data.

[0024] The time control unit 105 generates a tick signal S106, which in one embodiment is a time scale. The period of the tick signal S106 is equal to the number of clock periods of CLKnav, which is set by the CPU 107 before operation (see FIG. 7). The tick signal S106 is input to the following: the signal processor 102, the requantizer 103, the positioning channel 104, and the CPU 107. The CPU clock is called CLKcpu (not shown) and is input to the CPU 107, the BUS 108, and the memory 109. The clocks CLKnav and CLKcpu are generally asynchronous, and the rate of CLKcpu is generally sufficiently fast compared to the rate of CLKnav.

[0025] The CPU 107, the memory 109, and all the components of the positioning system 100 are each connected to the BUS 108, which enables communication between the CPU 107, the memory 109, and all the components of the positioning system 100. When the tick signal S106 is generated, the CPU 107 receives data via the BUS 108 and controls the positioning system 100 based on the received data. The memory 109 is used to store data.

[0026] 2A shows an overview of a GNSS receiver, comprising a positioning system 200 and a CPU system 210. The GNSS receiver further comprises a MUX interconnection unit 201 and “N” positioning system to CPU system interface blocks (NS2CS), represented by interface blocks NS2CS 202(1)...202(N), which convert data received from the positioning system 200 before sending it to the CPU system 210. The positioning system 200 further comprises “C” CPU system to positioning system interface blocks (CS2NS), represented by interface blocks CS2NS 203(1)...203(C), which convert data received from the CPU system 210 before sending it to the positioning system 200. The positioning system 200 further comprises “H” hardware accelerators, represented by hardware accelerators 204(1)...204(H), and a positioning direct memory access (DMA) 205. The interface blocks NS2CS202(1)...202(N) are collectively referred to as the interface block NS2CS. The interface blocks CS2NS203(1)...203(C) are collectively referred to as the interface block CS2NS203. The hardware accelerators 204(1)...204(H) are collectively referred to as the hardware accelerator 204. Figure 2A shows an interrupt request signal (IRQ) S206 output from the positioning DMA 205 and input to the CPU 107.

[0027] GNSS signals are received from an antenna and transmitted to one or more RF transmission lines which connect to the inputs of ADCs 101. The digitized signals output from ADCs 101 are input to signal processor 102 which processes the signals. The output from signal processor 102 is input to requantizer 103 which requantizes the signals to lower bit data.

[0028] The outputs from the requantizer 103, the ADCs 101, and the signal processor 102 are input to a MUX interconnection unit 201. The MUX interconnection unit 201 inputs the outputs from the requantizer 103, the ADCs 101, and the signal processor 102 to interface blocks NS2CS 202(1)...202(N), where the signals can be further processed.

[0029] The signal output from the interface block CS2NS 203 is input to the MUX interconnection unit 201. The signal output from the interface block CS2NS 203 using the MUX interconnection unit 201 is input to one of the positioning system 200, the requantizer 103, and the signal processor 102, where the signal is processed.

[0030] The time control unit 105 generates a tick signal S106, which is used to control various components and is input to: the signal processor 102, the requantizer 103, the CPU 107, the interface block NS2CS202, and / or the interface block CS2NS203.

[0031] The CPU 107 uses the tick signal S106 to synchronize control between the signal processor 102, the requantizer 103, the interface block NS2CS 202, the interface block CS2NS 203, and / or the hardware accelerator 204, and the positioning DMA 205.

[0032] The CLKnav and CLKcpu clocks are generally asynchronous, and the CLKcpu frequency is sufficiently high compared to the CLKnav frequency. In one embodiment, the frequency of the CPU 107 is synchronous and sufficiently high compared to the CLKcpu frequency. In one embodiment, the positioning system 200 operates based on the clock CLKnav and includes: the ADC 101, the signal processor 102, the requantizer 103, the time control unit 105, the MUX interconnection unit 201, the interface block NS2CS 202, and the interface block CS2NS 203. In one embodiment, the CPU system 210 operates based on the clock CLKcpu and includes: the positioning DMA 205, the positioning channel 104, the CPU 107, the BUS 108, the memory 109, the interface block NS2CS 202, the interface block CS2NS 203, and the hardware accelerator 204.

[0033] In one embodiment, the frequency of CPU 107 is synchronous and very high compared to CLKcpu. In another embodiment, the operating frequencies of positioning channel 104 and positioning DMA 205 are synchronous and very high compared to CLKcpu.

[0034] In one embodiment, the following components are connected to the BUS 108: positioning DMA 205, CPU 107, memory 109, positioning system 200, interface block NS2CS 202, interface block CS2NS 203, hardware accelerator 204, and positioning channel 104.

[0035] The CPU 107 controls the following components via the BUS 108: the positioning DMA 205, the positioning system 200, the interface block NS2CS 202, the interface block CS2NS 203, the hardware accelerator 204, and the positioning channel 104.

[0036] In one embodiment, CPU 107 is configured to write data to memory 109 and hardware accelerator 204 via BUS 108. In one embodiment, memory 109 is used for data storage.

[0037] The following components can be sources of data: ADC 101, signal processor 102, requantizer 103, hardware accelerator 204, interface block NS2CS 202, interface block CS2NS 203, and CPU 107.

[0038] After processing, each of the multiple requantizers 103 produces the same number of samples within a predetermined period. The outputs from each requantizer 103 are aggregated into one stream and sent via a MUX interconnection unit 201 to the input of one interface block NS2CS 202 for further processing. In one embodiment, one interface block NS2CS 202 is allocated for further processing.

[0039] In one embodiment, the output from the requantizer 103 is input to an interface block NS2CS 202. In one embodiment, the interface block NS2CS 202 writes data from the positioning system 200 via BUS 108 to: memory 109, hardware accelerator 204, and / or CPU 107.

[0040] In one embodiment, the interface block CS2NS 203 transmits data from the memory 109 to the positioning system 200 via the BUS 108. When the transmission operation is completed, the interface block CS2NS 203 suspends the operation of the CPU 107.

[0041] One of the hardware accelerators 204 writes the results of the data processing via the BUS 108 to: the memory 109, a different one of the hardware accelerators 204, and / or the CPU 107.

[0042] The hardware accelerator 204 may be a coarse-grained reconfigurable architecture (CGRA) that can be incorporated into an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) that can be embedded in an ASIC, a spectrum analyzer, or other devices. When processing data, the hardware accelerator 204 generates an interrupt request signal (IRQ) and sends it to the CPU 107, and the signal S707 is sent to the positioning DMA 205.

[0043] The positioning DMA 205 reads data from the memory 109 via the BUS 108. The positioning DMA 205 transmits the data from the memory 109 to the positioning channel 104, where the data is processed. After completing the operation, the positioning DMA 205 outputs an IRQ signal S206 to the CPU 107.

[0044] The CPU 107 uses the tick signal S106 and IRQ signals (e.g., IRQ signal S206) from the positioning DMA 205, interface block NS2CS202, interface block CS2NS203, and hardware accelerator 204 to control the data stream between the positioning DMA 205, interface block NS2CS202, interface block CS2NS203, and hardware accelerator 204.

[0045] Figure 2B shows a GNSS receiver similar to the one shown in Figure 2A, except that Figure 2B includes an additional component: an asynchronous first-in, first-out buffer (AFIFO) 214. In one embodiment, the output from the requantizer 103 and tick signal S106 are connected to the input of AFIFO 214 via MUX interconnect unit 201. The CLKnav sample from the requantizer 103 and each clock pulse of the tick signal S106 are input to AFIFO 214.

[0046] Each sample is resynchronized to the clock CLKcpu before being output from the requantizer 103 to the positioning channel 104, where the sample is processed. The tick signal S106 is resynchronized to the clock CLKcpu before being input to the positioning channel 104, where it is used to process the samples from the requantizer 103.

[0047] Data is transmitted from the AFIFO 214 to the positioning channel 104 (i.e., to the internal logic of the positioning channel 104) based on the clock CLKcpu. The AFIFO 214 performs resynchronization of the data from the clock CLKnav to the clock CLKcpu.

[0048] When the positioning channel 104 works with data from the AFIFO 214 (sample and tick signal S106 from the requantizer 103), the positioning receiver is operating in an operating mode equivalent to a standard GNSS receiver and the positioning DMA 205 is not used.

[0049] Figure 3 shows an overview of the interface block NS2CS 202 of Figure 2 and the signal transmission from the positioning system 200 to the CPU system 210. The interface block NS2CS 202 comprises: an NS2CS control unit 300, a decimator NS2CS 301, a multiplexer 302, a data preparer and requantizer 303, an asymmetric and asynchronous first-in, first-out buffer (AAFIFO) 304, and a package manager 309. Figure 3 shows a composite signal, including an IRQ signal S305 from the NS2CS control unit 300 of the interface block NS2CS 202, an output S306 from the interface block NS2CS 202, a RUN signal S307, and a continuous data stream S308 from the MUX interconnection unit 201.

[0050] In one embodiment, before the CPU 107 starts, the NS2CS control unit 300 configures the following: decimator NS2CS 301 (if necessary), multiplexer 302, data preparer and requantizer 303, AAFIFO 304, and package manager 309. In one embodiment, the data preparer and requantizer 303 converts samples from a multi-level digitized signal to a two-level signal. In short, the BUS 108 accommodates many two-level samples. The interface block NS2CS 202 performs data processing and converts data from the MUX interconnect unit 201 into a format required for the positioning DMA 205, CPU 107, memory 109, or hardware accelerator 204. In one embodiment, the data stream output from the interface block NS2CS 202 is a package.

[0051] In one embodiment, a package is a number of samples assigned or set by the CPU 107. Each sample is data for one clock period. If necessary for controlling the hardware accelerator 204, service information or additional information from the NS2CS control unit 300 can be added to the package. In one embodiment, the interface block NS2CS 202 generates the package according to the tick signal S106. In one embodiment, the interface block NS2CS 202 generates the package and then stores the package in the memory 109.

[0052] In various embodiments, the package data can be processed in: the signal processor 102 using the interface block CS2NS 203, the requantizer 103 using the interface block CS2NS 203, the positioning channel 104 using the positioning DMA 205, the CPU 107, and / or the hardware accelerator 204.

[0053] In various embodiments, packages can be generated by the CPU 107, the interface block NS2CS 202, and / or the hardware accelerator 204. The continuous data stream S308 from the MUX interconnect unit 201 is input to a decimator NS2CS 301, which decimates the signal by a different decimation factor, if necessary, and inputs it to the data generator and requantizer 303. The data generator and requantizer 303 generates data and, if necessary, requantizes the data to lower-bit data. If decimation is not used, the continuous data stream S308 from the MUX interconnect unit 201 enters the input of the multiplexer 302 and then goes to the data generator and requantizer 303. The output data from the data generator and requantizer 303 passes through the AAFIFO 304 and inputs to the package manager 309, where the output data is converted into packages with a predetermined number of samples. The AAFIFO 304 resynchronizes the data from the clock CLKnav to the clock CLKcpu.

[0054] In one embodiment, during operation, interface block NS2CS202 stacks data at a predetermined address and generates an IRQ signal S305 for CPU 107. Data is written periodically as needed. In another embodiment, decimator NS2CS301 is eliminated to reduce the space required for interface block NS2CS202 within the ASIC.

[0055] The interface block NS2CS202 operates in two modes: single package mode and multi-package mode.

[0056] 4A shows a signal graph of interface block NS2CS202 operating in single package mode. One package is formed during one tick signal S106. When a package is formed, an IRQ signal S305 is generated and input to CPU 107. In this mode, CPU 107 is responsible for controlling the data stream using the tick signal S106 and IRQ signals from interface block NS2CS202, interface block CS2NS203, hardware accelerator 204, and positioning DMA 205. In one embodiment, positioning DMA 205 forms a multi-bit data signal S501 for positioning channel 104.

[0057] FIG. 4B shows a signal graph of the interface block NS2CS 202 operating in multi-package mode. The time control unit 105 generates a tick signal S106 and starts data processing accordingly. During one period of the tick signal S106, U packages are formed. When the first package is formed and written to memory 109, a signal S305 is generated. After each package is completed, a RUN signal S307 is generated. In one embodiment, packages 1...U have the same size. In another embodiment, packages 1...U have different sizes. The positioning DMA 205 reads the packages from memory 109 and forms a multi-bit data signal S501 for the positioning channel 104 based on the signal S307. Additional operations related to the packages are performed as needed; specifically, the interface block NS2CS 202 generates the S305 and S307 signals any time after writing a packet to memory 109.

[0058] Figure 5 shows an overview of the interface block CS2NS 203 and the signal transmission from the positioning system 200 to the CPU system 210. The interface block CS2NS 203 consists of: a CS2NS control unit 400, a CS2NS data generation unit 402, and a CS2NS asynchronous and asymmetric FIFO (CS2NS AAFIFO) unit 401. Figure 5 also shows the IRQ signal S303 output from the CS2NS control unit 400.

[0059] In one embodiment, the CPU 107 coordinates the following before operation: the CS2NS data creation unit 402, and the CS2NS AAFIFO unit 401. After operation begins, the interface block CS2NS 203 reads part of the package from the memory 109 before receiving the tick signal S106. The interface block CS2NS 203 starts issuing samples after receiving the tick signal S106. Based on a clock CLKnav (not shown, but used to synchronize package transmission), the entire package is sent to the MUX interconnection unit 201.

[0060] After starting the operation of the interface block CS2NS 203, data from the BUS 108 is input to the CS2NS data creation unit 402, where the data is processed. The data output from the CS2NS data creation unit 402 is input to the CS2NS AAFIFO unit 401. Before the tick signal S106 is generated, the data from the CS2NS AAFIFO unit 401 is input to the MUX interconnection unit 201 until the package transfer is completed.

[0061] In one embodiment, after an entire package is read from memory 109, the next package is read as needed to ensure a continuous stream of data is processed by CLKnav. Upon outputting the last package to CS2NS AAFIFO unit 401, interface block CS2NS 203 generates IRQ signal S303. CS2NS AAFIFO unit 401 resynchronizes the data from clock CLKcpu to clock CLKnav.

[0062] 6A shows signals received by the positioning DMA 205. The signals received by the positioning DMA 205 include "H" RUN signals, denoted as RUN signals S707(1)...S707(H), which are output from "H" hardware accelerators, denoted as hardware accelerators 204(1)...204(H). The signals received by the positioning DMA 205 also include "N" signals, denoted as signals S307(1)...S307(N), which are output from the interface block NS2CS. As described above, the signals received by the positioning DMA 205 are used in first-try automatic mode.

[0063] In one embodiment, signal S707 from hardware accelerator 204 is received by positioning DMA 205. Signal S707 is sent at the end of writing a package to memory 109. Signal S707 is used by positioning DMA 205 in a manner similar to signal S307, and is also used in first-try automatic mode.

[0064] In one embodiment, the positioning DMA 205 uses signals S307 and S707 to read packages from the memory 109 and generate signal S501 (see FIGS. 4A and 4B) from different data sources in the interface block NS2CS 202 and / or the hardware accelerator 204.

[0065] The interface block NS2CS 202, the interface block CS2NS 203, the hardware accelerator 204, and the positioning DMA 205 can be arranged in a data processing chain, during which data is transmitted from one module to another without the participation of the CPU 107.

[0066] In one embodiment shown in FIG. 6B, data is processed in a chain starting from the package at the output of interface block NS2CS 202(1) to the input to hardware accelerator 204(1), where the package is processed. The results of the package's processing by hardware accelerator 204(1) are input to hardware accelerator 204(2). The results of the package's processing by hardware accelerator 204(2) are written to memory 109. After processing the package, hardware accelerator 204(2) generates signal S707(2). Based on signal S707(2), positioning DMA 205 sends the data (signal S501) to positioning channel 104.

[0067] In the positioning system 200 (as shown in FIGS. 2, 3 and 5), the signal is decimated by the signal processor 102 (in this case a decimator).

[0068] FIG. 7 shows one of several possible variations of a clock that generates a clock signal, referred to as the decimation clock. Tick signal S106 has a specific tick period. Tick signal S106 is composed of multiples of ClkNav. Clock Divider 2 signal represents ClkNav divided by 2. Similarly, Clock Divider 3 signal represents ClkNav divided by 3, and Clock Divider 4 signal represents ClkNav divided by 4. In one embodiment, the signals are input to signal processor 102 (a decimator in this variation) to control the decimation. In one embodiment, tick signal S106 is used for all components (for all clock divisions) simultaneously (for all decimation factors).

[0069] When decimation is used, the number of samples at the input of the interface block NS2CS 202 is reduced, thereby reducing the size of the packages. In one embodiment, the interface block NS2CS converts the received digitized signal into packages of a set or specified size.

[0070] Figure 8 illustrates a positioning channel 104 in communication with the CS2NS CPU system of Figure 5, according to one embodiment. As shown in Figure 8, the positioning channel 104, according to one embodiment, includes: channel 500, "D" signals, denoted as signals S501(1)...S501(D), from positioning DMA 205, code rate NCO (CRNCO) 503, code rate signal S504, code phase signal S505, code generator 506, code signal S507, strobe generator 508, strobe signal S509, integration period counter 510, integration period (IP) signal S511, intermediate frequency NCO (IFNCO) 512, cosine signal S513, sine signal S514, correlator 515, commutator 516, and output signal S517 from the commutator.

[0071] In one embodiment, the positioning channel 104 is comprised of multiple channels 500. FIG. 8 illustrates one of the multiple channels, channel 500. In one embodiment, a package may contain data from one or more data sources. Data from different sources may be combined into a single package with the same number of samples within a given time period. The low-bit data received from the outputs of the different requantizers 103 (shown in FIGS. 2A, 2B, and 3) is multiplexed into a single multi-digit word and input to the associated interface block NS2CS 202 to generate a common package, which is then sent to memory 109 for storage. The positioning DMA 205 reads the packages from memory 109 and converts them (the data from the requantizers 103(1)...103(Q)) into "D" signals, denoted as signals S501(1)...S501(D). The signals from each requantizer 103(1)...103(Q) are transmitted as signals S501(1)...S501(D), respectively.

[0072] Positioning DMA 205 sends one package to positioning channel 104 while the next package is being generated. CPU 107 controls positioning DMA 205 via BUS 108. CPU 107 conditions positioning DMA 205 before operation to operate in one of several modes.

[0073] The positioning DMA 205 may operate in the following modes: CPU full control mode, and first-try automatic mode.

[0074] In one embodiment, in the CPU full control mode, the CPU 107 controls the positioning DMA 205 and the channel 500. In one embodiment, the CPU full control mode is used only when the interface block NS2CS 202 operates in the single package mode. The time control unit 105 generates a tick signal S106, which causes data processing to be performed. The interface block NS2CS 202 operates in the single package mode. When a package is formed, a signal S305 is generated. The CPU 107 writes a control command to the positioning channel 104 according to the signal S305, and then the positioning DMA 205 sends the package according to the command from the CPU 107. When the package is sent, the positioning DMA 205 generates a signal S206. The CPU 107 reads the data from the positioning channel 104 based on the signal S206. An advantage of this mode is that the CPU 107 itself can decide which block to send data to, allowing for a more flexible data processing chain.

[0075] In one embodiment, in first-try automatic mode, CPU 107 controls positioning DMA 205 and channel 500, where positioning DMA 205 itself sends packages via channel 500 using signals S307 and S707. In one embodiment, first-try automatic mode is used only when interface block NS2CS 202 operates in multi-package mode. Time control unit 105 generates tick signal S106, which causes data processing to be performed. After the first package is completely sent, signal S305 is generated. CPU 107 sends a control command to positioning channel 104 according to signal S305, and positioning DMA 205 sends the package based on the CPU command. At the end of each package, positioning DMA 205 runs according to RUN signal S307 and sends the package to positioning channel 104. After the last package, positioning DMA 205 generates signal S206 based on the current tick signal S106. CPU 107 reads data from positioning channel 104 based on signal S206. The advantage of this mode is that it requires less memory due to the smaller package, and also consumes less power since this mode requires less control from the CPU.

[0076] When a package is ready, positioning DMA 205 reads it from memory 109 and generates multi-bit data signal S501. When data signal S501(1) is sent through commutator 516, signal S501 is sent to the processing logic of channel 500 every clock. When data S501(D) is sent through commutator 516, signal S501 is sent to the processing logic of channel 500 every clock.

[0077] In CPU full control mode, the positioning DMA 205 generates an IRQ signal S206 at the end of the package, after the data has been sent to the channel 500, which corresponds to the duration of the tick signal S106.

[0078] In first-try automatic mode, the positioning DMA 205 generates an IRQ signal S206 once for several packages, which is when data transmission to the channel 500 is completed, and the IRQ signal S206 corresponds to the period of the tick signal S106.

[0079] Signals S501(1)...S501(D) are sent from positioning DMA 205 to the input of commutator 516. CPU 107 works in conjunction with commutator 516 to connect channel 500 to signal S501(i), where "i" is any number from 1 to D.

[0080] While the positioning DMA 205 is reading the package from memory 109, if there is not enough data to form signal S501 (i.e., if the positioning DMA 205 has not had time to read the data from memory), the channel 500 stops processing data during this period.

[0081] The positioning channel 104 consists of a set of multiple channels 500. The CPU 107 controls and acquires data from the channels 500 via the BUS 108. In the channels 500, each sample from the package is processed within one clock cycle of CLKcpu.

[0082] In one embodiment, the period of tick signal S106 is shorter than the period of integration period signal S511.

[0083] The current configuration of the channel 500 is a group of settings defined for a selected GNSS signal processing mode, e.g., the selected S501(i) and code generator 506 configurations are parameters.

[0084] In one embodiment, CPU 107 configures, controls, and acquires data from channel 500 when positioning DMA 205 is not sending data signal S501. Prior to operation, CPU 107 sets the current configuration of components and parameters for channel 500: code frequency and initial code phase in code rate NCO 503, code generator 506, strobe generator 508, duration of integration period signal S511 in integration period counter 510, intermediate frequency and initial code phase in intermediate frequency NCO 512, and commutator 516.

[0085] In one embodiment, channel 500 processes input signal S501(i) from start to finish of the package.

[0086] CRNCO 503 generates a code frequency signal S504, which is input to code generator 506 and integration period counter 510. Code generator 506 generates a coded signal S507 at the rate of signal S504. Coded signal S507 is input to strobe generator 508 and correlator 515. CRNCO 503 generates a code phase signal S505, which is input to strobe generator 508. Strobe generator 508 uses signals S507 and S505 to generate a strobe signal S509, which is input to correlator 515. IFNCO 512 generates a cosine signal (Cos) S513 and a sine signal S514 having an intermediate frequency. Signals S513 and S514 are input to correlator 515. From commutator 516, signal S517 is input to correlator 515. Integration period counter 510 generates integration period signal S511 based on code rate signal S504. Integration period signal S511 is input to correlator 515 and positioning DMA 205. In one embodiment, signal S517 is signal S501(i). Positioning DMA 205 determines signal S511 during tick signal S106.

[0087] In correlator 515, signal S517 is multiplied by cosine signal S513 and coded signal S507, and the multiplication result is accumulated over integration period signal S511. According to integration period signal S511, the accumulated value is stored in buffer register 1 (component I below), and when necessary, CPU 107 captures this value and the accumulated value is set to zero. (Equation 1) TIFF2025529028000002.tif16159

[0088] In the correlator 515, the signal S517 is multiplied by the sine signal S514 and the coded signal S507, and the multiplication result is accumulated over the integration period signal S511. According to the signal S511, the accumulated value is stored in the buffer register 2 (component Q below), and when necessary, the CPU 107 captures this value and the accumulated value is set to zero. (Equation 2) In the TIFF2025529028000003.tif16159 correlator 515, the signal S517 is multiplied by the cosine signal S513 and the strobe signal S509, and the multiplication result is accumulated over the integration period signal S511. According to the signal S511, the accumulated value is stored in the buffer register 3 (component dI below), and when necessary, the CPU 107 captures this value and the accumulated value is set to zero. (Equation 3) In the correlator 515, the signal S517 is multiplied by the sine signal S514 and the strobe signal S509, and the multiplication result is accumulated over the integration period signal S511. According to the signal S511, the accumulated value is stored in the buffer register 4 (component dQ below), and when necessary, the CPU 107 captures this value and the accumulated value is set to zero. (Equation 4) Based on signal S206, CPU 107 reads ready data from channel 500, including the values ​​(components I, Q, dI, dQ) in buffer registers 1 through 4, if signal S511 is defined by positioning DMA 205 and available. Note that other data such as the code phase CRNCO 503, the intermediate frequency phase in IFNCO 512, and the state of integration period counter 510 can also be read.

[0089] Before processing with signal S501(i), CPU 107 can control / change parameters of channel 500, including changing the code frequency in CRNCO 503, setting the code phase shift in CRNCO 503, changing the intermediate frequency in IFNCO 512, setting the intermediate frequency phase shift in IFNCO 512, etc.

[0090] The operation of strobe generator 508 is described in US Pat. No. 7,764,226 B1, the entire disclosure of which is incorporated herein by reference.

[0091] FIG. 9A illustrates the packaging process steps, which are described below.

[0092] Signals S305, S307, and S707 notify positioning DMA 205 that a new package is present in memory 109. CPU 107 uses a combination of signals S106, S206, S307, and S707 to control the GNSS signals processed on channel 500. Package processing by positioning DMA 205 includes the following steps: The table below describes the package processing steps. The "Designation" column in this table indicates that the last digit of the label in FIG. 9A is associated with a particular step (i.e., labels 9112, 9212, and 9312 each relate to a configuration step; labels 9113, 9213, and 9313 each relate to a control step, etc.). (table) TIFF2025529028000006.tif93159

[0093] In one embodiment, during the creation of a new package, all steps required for each current configuration of channels must be completed.

[0094] In the CPU full control mode, the configuration and control steps are controlled by the CPU 107. In the configuration and control steps, the CPU 107 controls the channel 500 before sending a package to the channel 500. The read step is controlled by the CPU 107. In the read step, the CPU 107 reads ready data from the channel 500 after processing the package in the channel 500. The positioning DMA 205 generates an IRQ signal S206 after processing the package (after the processing step).

[0095] In the first-try automatic mode, the configuration and control steps are controlled by CPU 107. In the configuration and control steps, CPU 107 controls channel 500 before the first package formed during the tick signal S106 is sent to channel 500. The read step is controlled by CPU 107. In the read step, CPU 107 reads ready data from channel 500 after channel 500 processes the last package generated during the tick signal S106. Positioning DMA 205 generates IRQ signal S206 after channel 500 processes the last package generated during the tick signal S106 (after the processing step).

[0096] In one embodiment, the following steps are performed in the following order: Configuration steps:

[0097] The configuration step can be used sequentially for multiple channels 500. If new GNSS signal processing needs to be performed, the channel 500 is set to the new configuration. The channel 500 can also stop GNSS signal processing if desired. Control steps:

[0098] Control steps can be used sequentially for multiple channels 500. Control commands are sent to channels 500 as needed. Processing Steps:

[0099] The processing steps are applied simultaneously (in parallel) for all channels 500. Each package (represented by signal S501) is sent simultaneously to all channels 500. Each channel 500 processes its own package received as signal S501(i). Read steps:

[0100] The read step is used sequentially as needed for multiple channels 500. When signal S511 is available in positioning DMA 205, ready data is obtained from channel 500.

[0101] In one embodiment, CPU 107 reads data from channel 500 without using positioning DMA 205, if necessary, and temporarily suspends operation of positioning DMA 205 after signal S206.

[0102] In one embodiment, channel 500 does not process a previously configured current configuration, CPU 107 does not set one or more new current configurations for channel 500, and positioning DMA 205 does not send a package to channel 500 (i.e., positioning DMA 205 skips all steps) and generates signal S206.

[0103] By using the CPU 107 for each step of configuration and control in the CPU Full Control mode and the First Try Automatic mode, synchronicity of control of all channels 500 is ensured.

[0104] In Figure 9A, steps with a shaded background are not activated (i.e., not used). In one embodiment, the time for package generation is equal to the period of the tick signal S106 (see Figure 7).

[0105] In one embodiment, channel 500(1) processes signal S500(i) in its current configuration, Configuration 1. In Configuration 1, data packages are processed in the same manner as a typical GNSS receiver (see FIG. 1) would operate channel 500 in pipeline mode.

[0106] In one embodiment, configuration of configuration 1 is performed in the following manner: in tick 1 9100, the current configuration is set, GNSS signals are processed, and data is read as needed; in tick 2 9200 and tick 3 9300, control steps are used, GNSS signal processing continues, and data is read as needed.

[0107] In one embodiment shown in FIG. 9A, the steps are performed in the following order:

[0108] When tick signal S106 number 1 (ie, tick 1 9100) occurs, the following steps are performed: set configuration 1 by configuration 9112; process 9114; and read 9115.

[0109] When tick signal S106 number 2 (ie, tick 2 9200) occurs, the following steps are performed: control 9213 for configuration 1; process 9214; and read 9215.

[0110] When tick signal S106 number 3 (ie, tick 3 9300) occurs, the following steps are executed: control for configuration 1 9313; processing 9314; CPU read 9315.

[0111] It should be noted that in one embodiment, in single GNSS signal processing mode, channel 500 always operates in a current configuration corresponding to configuration 1.

[0112] FIG. 9B shows a diagram of the operation of the positioning DMA 205 in full CPU control mode.

[0113] The package corresponds to the period of the tick signal S106. In the CPU full control mode, the CPU 107 uses the tick signals S106, S305, and S206 to control GNSS signal processing by using the positioning DMA 205, and controls the configuration, control, and read steps. The interface block NS2CS 202 starts forming a package based on the tick signal S106. The CPU 107 receives the signal S305 and executes the configuration and control steps. In the processing step, the positioning DMA 205 transmits the package to the positioning channel 104 at the command of the CPU 107. The positioning DMA 205 finishes transmitting the package and generates the signal S206. The CPU 107 receives the signal S206 and executes the read step. After that, all steps are repeated periodically.

[0114] FIG. 9C shows a diagram of the positioning DMA 205 in first-try automatic mode (four packages are formed per tick period).

[0115] During the period of the tick signal S106, four packages are formed (for example, in multi-package mode). In the first-try automatic mode, the processing of package 2 and package 3 does not require any control from the CPU 107. After processing package 4, the CPU 107 receives signal S206 and reads ready data from channel 500. The interface block NS2CS 202 starts forming packages with the tick signal S106. The CPU 107 receives signal S305 and performs configuration and control steps. In the processing step, the positioning DMA 205 transmits package 1 to the positioning channel 104 at the command of the CPU 107. In the processing step, the positioning DMA 205 transmits package 2, package 3, and package 4 to the positioning channel 104 with signal S307. The transmission by the positioning DMA 205 is completed with package 4, generating signal S206. The CPU 107 receives signal S206 and performs the read step. All steps are then repeated periodically.

[0116] The positioning system 200 processes the GNSS signals in a pipeline mode according to the clock CLKnav and generates packages using the modules of the interface block NS2CS 202, which increases the flexibility of the GNSS signal processing. The formation of the packages is associated with the tick signal S106. The packages are further processed in the CPU system 210 according to the clock CLKcpu.

[0117] The samples from all requantizers 103 are combined in one interface block NS2CS 202 to form a package, which is written to memory 109. The packages are input to the positioning channel 104 via positioning DMA 205, where they are processed based on the clock CLKcpu. The interface block NS2CS 202 generates the packages sequentially, which provides pipelined processing of the GNSS signals in the positioning channel 104. In one embodiment, the interface block NS2CS 202 generates the packages sequentially without data loss. The operation of the CPU 107 to control and read data from the positioning channel 104 is performed between package processing.

[0118] Packages may be processed in the positioning channel 104 in the following modes: CPU full control mode, and first try automatic mode.

[0119] In one embodiment, in CPU full control mode, the following operations occur: CPU 107 controls all processing, and the period is equal to the period of the tick signal S106.

[0120] In one embodiment, in first-try automatic mode, CPU 107 controls and reads data from positioning channel 104 between each package per tick signal S106 period. In this mode, the package size is reduced by a factor of 1, resulting in a smaller memory 109 footprint. Positioning DMA 205 transmits the first package, formed from each package per tick signal S106 period, to positioning channel 104 at the command of CPU 107. Next, a package is formed from each package per tick signal S106 period, and interface block NS2CS 202 automatically notifies positioning DMA 205 that a new package is ready and automatically enables transmission of part of the package to positioning channel 104. Positioning DMA 205 reads the package from memory 109 and transmits it to positioning channel 104.

[0121] In one embodiment, the operation of the interference suppressor (e.g., signal processor 102) requires the detection of interference in the positioning system 200. For this purpose, a spectrum analyzer (e.g., hardware accelerator 204) located in the CPU system is used. The packages formed by the interface block NS2CS 202 are processed in the spectrum analyzer. The CPU 107 analyzes the results and controls the interference suppressor.

[0122] In another embodiment, additional filters may be required in the positioning system after the ASIC has been fabricated. Such filters can be implemented using hardware accelerators 204 (e.g., embedded in the ASIC: using FPGAs or CGRAs). In this case, a chain exists that provides pipeline processing of the GNSS signals in the positioning channel 104. Samples from the output of the signal processor 102 are input to an interface block NS2CS202, which forms packages. The packages of the interface block NS2CS202 are synchronized with the tick signal S106 and processed in the hardware accelerator 204. The hardware accelerator 204 forms packages and writes them to the memory 109. The interface block CS2NS203 retrieves the packages from the memory 109 and returns the data to the signal processing chain in the positioning system 200. The data from the interface block CS2NS203 is synchronized with the tick signal S106, making it possible to take into account signal delays during signal processing in the positioning channel 104.

[0123] In one embodiment, the package is considered for processing by the CPU 107 to provide flexibility, and the package is recorded and stored in the memory 109 for further processing.

[0124] The interface block NS2CS 202 has a built-in decimator NS2CS 301, which reduces the number of samples in a package if necessary, thereby making it possible to reduce the processing time of the data in the CPU 107 or in the hardware accelerator 204.

[0125] In one embodiment, when the positioning channel 104 works with data from the AFIFO 214 (e.g., sample and tick signal S106 from the requantizer 103), the positioning DMA 205 is not used, resulting in a mode similar to the operation of a standard GNSS receiver, and all possibilities for additional processing of the GNSS signal remain.

[0126] According to one embodiment, a computer is used to implement the operations of the components and equations described herein and shown, for example, in FIGS. 2A, 2B, 3, 5, 6A, 6B, and 8. These components may include, for example, ADCs, signal processors, requantizers, etc. A high-level block diagram of the computer is shown in FIG. 10. The computer 1002 includes a processor 1004 that controls the overall operation of the computer 1002 by executing computer program instructions that define the overall operation of the computer. The computer program instructions may be stored in a storage device 1012 or other computer-readable medium (e.g., a magnetic disk, CD-ROM, etc.) and loaded from the memory 1010 when execution of the computer program instructions is desired. In this manner, the components and equations described herein may be defined by computer program instructions stored in the memory 1010 and / or the storage device 1012 and controlled by the processor 1004 executing the computer program instructions. For example, the computer program instructions may be implemented as computer-executable code programmed by one skilled in the art to perform algorithms defined by the components and equations described herein. In this manner, the processor 1004 executes the computer program instructions to perform algorithms defined by the components and equations described herein as components shown in Figures 2A, 2B, 3, 5, 6A, 6B, and 8, etc. The computer 1002 also has one or more network interfaces 1006 for communicating with other devices over a network. The computer 1002 also has input / output devices 1008 (e.g., a display, keyboard, mouse, speakers, buttons, etc.) that allow a user to interact with the computer 1002. Those skilled in the art will recognize that an actual computer implementation may include other components, and that Figure 10 is a high-level representation of some of these computer components for illustrative purposes.

[0127] The foregoing detailed description is to be understood in all respects as illustrative and illustrative, but not restrictive, and the scope of the inventive concepts disclosed herein is to be construed to the fullest extent permitted by applicable patent law. The embodiments shown and described herein are merely illustrative of the principles of the inventive concepts, and those skilled in the art will recognize that various modifications can be made without departing from the scope and spirit of the invention. Those skilled in the art will recognize that other combinations of the various features can be made without departing from the scope and spirit of the inventive concepts.

Claims

1. A positioning receiver, a plurality of RF transmission paths configured to receive GNSS signals from an antenna and transmit the GNSS signals in a frequency range for digitizing the GNSS signals; a positioning system configured to process the GNSS signals based on a clock CLKnav, wherein the positioning system a plurality of analog-to-digital converters (ADCs) configured to digitize signals from the plurality of RF transmission paths; a plurality of signal processors configured to process the digitized signals; a plurality of requantizers configured to convert the digitized signals into lower bit data; a plurality of interface blocks NS2CS configured to generate packages; a plurality of interface blocks CS2NS configured to convert said packages into data; a MUX interconnection unit configured to distribute the data from outputs of the plurality of ADCs, the signal processor, and the requantizer to inputs of an interface block NS2CS, and from outputs of interface block CS2NS to the plurality of signal processors and the plurality of requantizers; a time control unit configured to adjust the time scale to generate the tick signal; an asynchronous first-in, first-out (AFIFO) unit configured to send the low-bit data and the tick signal to multiple channels for processing; a CPU system configured to process the package based on a clock CLKcpu; a memory configured to store the data and the package; a plurality of hardware accelerators configured to process the packages; a positioning DMA configured to convert the package into data for multiple channels; a commutator configured to select data from the positioning DMA; A CPU configured to synchronize control between the signal processors, the requantizers, the interface block NS2CS, the interface block CS2NS, the hardware accelerators, and the positioning DMA based on the tick signal, and configured to control the positioning system and the CPU to read and process results of GNSS signal processing from the channels configured to process data from the positioning DMA or AFIFO unit; The operating frequencies of the positioning DMA and the multiple channels are synchronized and equal to or higher than the clock CLKcpu.

2. 2. A positioning receiver according to claim 1, characterized in that the interface block NS2CS converts the digitized signals into packages of a set size and resynchronizes the data from the clock CLKnav to the clock CLKcpu.

3. 2. The positioning receiver according to claim 1, wherein the interface block NS2CS writes the package to memory and generates a RUN signal sent to the positioning DMA and an interrupt request signal sent to the CPU.

4. 2. The positioning receiver according to claim 1, wherein the interface block NS2CS receives low-bit data from some of the requantizers and converts the low-bit data into a package of a specified size to be sent to a memory for the positioning DMA.

5. 2. A positioning receiver according to claim 1, characterized in that the interface block NS2CS is adapted to decimate the digitized signal and to requantize the decimated signal into lower bit data.

6. 2. A positioning receiver according to claim 1, characterized in that the interface block NS2CS is configured to form the packages according to the tick signal and to generate the packages sequentially without losing data.

7. 2. A positioning receiver according to claim 1, characterized in that the interface block NS2CS is adapted to generate one or more packages over the period of the tick signal.

8. 4. The positioning receiver according to claim 3, wherein the positioning DMA reads a package from the memory based on one of the RUN signals or a command received from the CPU.

9. 2. The positioning receiver according to claim 1, wherein the positioning DMA determines whether data is ready in multiple channels according to signals within an integration period, and the CPU reads signals from the multiple channels after data processing.

10. 9. The positioning receiver of claim 8, wherein after processing the last package during the current period of the tick signal, the positioning DMA generates an interrupt request signal that is sent to the CPU.

11. 9. The positioning receiver of claim 8, wherein said CPU reads readiness data from said plurality of channels between processing of each package and sends current channel configuration and control to said plurality of channels.

12. 2. The positioning receiver of claim 1, wherein, in response to a command from the CPU, one of the plurality of hardware accelerators reads the package from memory or receives the package from an interface block NS2CS, processes the package, and then generates an interrupt request signal that is sent to the CPU.

13. 13. The positioning receiver of claim 12, wherein the one of the plurality of hardware accelerators receives and processes a package, converts the processed result into a package that is written to the memory or a different one of the plurality of hardware accelerators, and then generates an interrupt request signal that is sent to the CPU.

14. 2. A positioning receiver according to claim 1, characterized in that the interface block CS2NS reads a package from the memory, transmits the data to one of the plurality of signal processors or one of the plurality of requantizers via the MUX interconnection unit, and resynchronizes the data from clock CLKcpu to clock CLKnav.

15. 15. The positioning receiver according to claim 14, wherein the interface block CS2NS starts transmitting the data based on a tick signal, and generates an interrupt request signal to be sent to the CPU upon receiving a data end.

16. 2. The positioning receiver according to claim 1, wherein said CPU reads and processes a package from memory, converts the processed result into a package, and writes said package into said memory.

17. 4. The positioning receiver of claim 3, wherein the CPU processes an interrupt request signal from one of the interface block NS2CS, the interface block CS2NS, the hardware accelerator, and the positioning DMA.

18. 2. The positioning receiver of claim 1, wherein the channel processes low-bit data from the AFIFO unit using the tick signal from the output of the AFIFO unit.

19. 2. The positioning receiver according to claim 1, characterized in that the signal processing chain can be assembled using any combination of components consisting of a CPU, a signal processor, an interface block NS2CS, an interface block CS2NS, a requantizer, a hardware accelerator, an AFIFO unit, a positioning DMA, and a positioning channel.

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