Reloadable Channel Implementations

Abstract

The global positioning satellite system receiver includes a plurality of radio frequency transmission paths, a positioning system (200), a plurality of analog-to-digital converters (101), a plurality of signal processors (102), a plurality of requantizers (103), an interface block (202) from the positioning system to a central processing unit (CPU) system, a MUX interconnection unit (201), a time control unit (105), a CPU system (210) that operates based on a tick signal, and the CPU system operates at a speed based on a CPU clock (CLKcpu), and further includes a memory (109), a multi-channel data manager (205), a plurality of channels (104), a direct memory access channel reload unit (207), and a CPU (107). The present invention aims to speed up positioning data processing.

Description

[Technical Field]

[0001] The subject matter of this disclosure relates generally to receivers, and more particularly to receivers for processing satellite positioning signals using reloadable channel implementations. [Background technology]

[0002] A Global Navigation Satellite System (GNSS) receiver can obtain a positioning solution (i.e., positioning information) only if it has reliable signal reception from the GNSS satellites with which it communicates. Reliable signal reception is generally available only under certain operating conditions, i.e., in open-sky environments where there are no obstructions to the radio signals propagating from the selected positioning satellites to the receiver's antenna. Antenna obstructions caused by natural or man-made obstructions (e.g., tall trees with dense foliage, vertical walls of buildings, bridges, urban canyons, structures on moving vehicles equipped with GNSS antennas, etc.) can degrade the quality of signal reception. Their presence can severely impact the accuracy of the positioning solution, including completely losing the ability to accurately provide GNSS-based positioning. GNSS receivers are also required to have sufficient processing power to perform the required operations to determine positioning information in a timely manner.

[0003] GNSS receivers typically process GNSS satellite signals to generate position data. These signals are often processed over different channels, and the configuration of these channels often changes during processing. What is needed is a receiver that can process GNSS satellite signals quickly and efficiently using low-cost components. Summary of the Invention

[0004] The positioning receiver includes multiple RF transmission paths configured to receive Global Navigation Satellite System (GNSS) signals and transmit GNSS signals. The positioning receiver further includes a positioning system configured to process the GNSS signals based on a clock CLKnav. The positioning system includes multiple analog-to-digital converters (ADCs), each configured to receive the GNSS signals from one of the multiple RF transmission paths and generate a digitized signal; multiple signal processors configured to process the digitized signals; multiple requantizers configured to convert the processed digitized signals to low-bit data; multiple positioning system-to-CPU system (NS2CS) interface blocks configured to generate packages based on the low-bit data; a MUX interconnection unit configured to distribute the data streams; and a time control unit configured to generate a tick signal. The positioning receiver also includes a CPU system operating based on the tick signal and operating a clock CLKcpu. The CPU system includes a memory configured to store data and packages; a multi-channel data manager configured to convert the packages into data; a plurality of channels configured to receive and process data from the multi-channel data manager; and a DMA channel reload unit configured to control the current state of each of the plurality of channels, wherein the multi-channel data manager is further configured to control the DMA channel reload unit. The positioning receiver further includes a CPU configured to control the positioning system and the CPU system and configured to process data received from the positioning system and the CPU system. [Brief explanation of the drawings]

[0005] In the drawings, like numbers describe like components in different views. Like numbers but with different suffixes represent similar components and / or signals but in different cases.

[0006] [Figure 1]FIG. 1 shows a prior art Global Navigation Satellite System (GNSS) receiver.

[0007] [Figure 2] FIG. 2 illustrates a GNSS receiver according to one embodiment.

[0008] [Figure 3] FIG. 3 illustrates a positioning system communicating with a CPU system via an NS2CS interface block, according to one embodiment.

[0009] [Figure 4] FIG. 4A illustrates a signal graph of the NS2CS interface block operating in single package mode, according to one embodiment.

[0010] FIG. 4B illustrates a signal graph of the NS2CS interface block operating in multi-package mode, according to one embodiment.

[0011] [Figure 5] FIG. 5 illustrates signals received by the multi-channel data manager according to one embodiment.

[0012] [Figure 6] FIG. 6 illustrates a positioning channel in communication with components of the NS2CS CPU system of FIG. 3, according to one embodiment.

[0013] [Figure 7A1] [Figure 7A2] FIG. 7A illustrates packaging processing steps according to one embodiment.

[0014] [Figure 7B] FIG. 7B illustrates a diagram of the multi-channel data manager of FIGS. 2, 3, 5, and 6 operating in a CPU-full control mode of operation, according to one embodiment.

[0015] [Figure 7C]FIG. 7C illustrates a diagram of the multi-channel data manager of FIGS. 2, 3, 5, and 6 operating in a first-try automatic mode of operation, according to one embodiment.

[0016] [Figure 7D] FIG. 7D illustrates a diagram of the multi-channel data manager of FIGS. 2, 3, 5, and 6 operating in the NS2CS interface block in a single package mode of operation and in an automatic control mode of operation, according to one embodiment.

[0017] [Figure 7E] FIG. 7E illustrates a diagram of the multi-channel data manager of FIGS. 2, 3, 5, and 6 operating in the NS2CS interface block in a multi-package mode of operation and in an automatic control mode of operation, according to one embodiment.

[0018] [Figure 8] FIG. 8 shows a high-level block diagram of a computer that performs the operations of each of the components described herein, according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0019] FIG. 1 shows an overview of the components of a prior art positioning receiver 1 (e.g., a GNSS receiver) comprising a positioning system 100 including “A” analog-to-digital converters (ADCs), denoted ADCs 101(1)...101(A). ADCs 101(1)...101(A) are collectively referred to as ADCs 101. The positioning system 100 further comprises multiple signal processors that form multiple signal transmission paths. One signal transmission path is comprised of “S” signal processors, represented by signal processors 102(1,1)...102(S,1). There are “P” signal transmission paths, represented by signal processors 102(1,P)...(1,P). Accordingly, the first transmission path is represented by signal processors 102(1,1)...102(S,1), and the last transmission path is represented by signal processors 102(1,P)...(S,P). The multiple signal processors, including signal processors 102(1,1)...102(1,P) and signal processors 102(S,1)...(S,P), are collectively referred to as signal processor 102. Positioning receiver 1 further comprises "Q" requantizers, represented by requantizers 103(1)...103(Q). Requantizers 103(1)...103(Q) are collectively referred to as requantizer 103. Positioning receiver 1 shown in FIG. 1 further comprises a positioning channel 104, a time control unit 105 that transmits a tick signal S106, and a CPU system 110, which comprises a CPU 107, a BUS 108, and a memory 109, and receives a data creation completion flag signal S111.

[0020] GNSS signals received by one or more antennas (not shown) are transmitted to one or more of a plurality of RF channels connected to the inputs of the ADCs 101. In one embodiment, these RF channels are configured to transmit the GNSS signals in a particular frequency range for digitization. In one embodiment, each of the ADCs 101 receives signals from one of the plurality of RF channels. In one embodiment, some or all of the ADCs 101 may receive signals from a single RF channel. From the output of the ADCs 101, the digitized signals are input to a signal processor 102, which processes the signals.

[0021] The signal processor 102 may be one or more components, such as a filter, a noise suppressor, an equalizer, and / or a decimator.

[0022] The signals output from the signal processors 102(S,1)...102(S,P) are input to requantizers 103(1)...103(Q), which requantize the received data into low-bit data. The low-bit data output from the requantizers 103(1)...103(Q) is input to a positioning channel 104, which processes the low-bit data.

[0023] The positioning channel 104 transmits a data creation completion flag signal S111 to the CPU 107. The data creation completion flag signal S111 indicates that the positioning channel 104 has completed the creation of data.

[0024] The time control unit 105 generates a tick signal S106, which in one embodiment is a time scale. The period of the tick signal S106 is equal to the number of clock periods of CLKnav. In one embodiment, the tick signal S106 is set by the CPU 107 before the positioning system 100 operates. The tick signal S106 is input to the following: the signal processor 102, the requantizer 103, the positioning channel 104, and the CPU 107. The CPU clock is input to the CPU 107, the BUS 108, and the memory 109. The positioning system operates at a rate based on the clock CLKnav. The clocks CLKnav and CLKcpu are generally asynchronous, and the rate of CLKcpu is generally sufficiently fast compared to the rate of CLKnav.

[0025] The CPU 107, the memory 109, and all the components of the positioning system 100 are each connected to the BUS 108, which enables communication between the CPU 107, the memory 109, and all the components of the positioning system 100. When the tick signal S106 is generated, the CPU 107 receives data via the BUS 108 and controls the positioning system 100 based on the received data. The memory 109 is used to store data.

[0026] 2 shows an overview of the GNSS receiver 2, which consists of a positioning system 200 and a CPU system 210. The positioning system 200 further comprises "N" positioning system to CPU system interface blocks (NS2CS), represented as NS2CS interface blocks 202(1)...202(N), which convert data received from the positioning system 200 before sending it to the CPU system 210. The positioning system 200 comprises multiple ADCs 101, multiple signal processors 102, multiple requantizers 103, a time control unit 105, a MUX interconnect unit 201, and multiple NS2CS interface blocks 202. The CPU system 210 comprises a BUS 108, a CPU 107, a memory 109, a multi-channel data manager 205, a positioning channel 104, and a DMA channel reload unit 207. The NS2CS interface blocks 202(1)...202(N) are collectively referred to as the NS2CS interface block 202. Figure 2 shows an interrupt request signal (IRQ) S206 that is output from the multi-channel data manager 205 and input to the CPU 107.

[0027] GNSS signals are received from an antenna and transmitted to one or more RF transmission lines which connect to the inputs of ADCs 101. The digitized signals output from ADCs 101 are input to signal processor 102 which processes the signals. The output from signal processor 102 is input to requantizer 103 which requantizes the signals to lower bit data.

[0028] The outputs from the requantizer 103, ADC 101, and signal processor 102 are input to a MUX interconnection unit 201. The MUX interconnection unit 201 inputs the outputs from the requantizer 103, ADCs 101, and signal processor 102 to NS2CS interface blocks 202(1)...202(N), where the signals can be further processed. The time control unit 105 generates a tick signal S106, which is used to control various components and is further input to: the signal processor 102, the requantizer 103, the CPU 107, and the NS2CS interface block 202.

[0029] The CPU 107 uses the tick signal S106 to synchronize control between the signal processor 102, the requantizer 103, and the NS2CS interface block 202.

[0030] The positioning system 200 operates at a rate based on the clock CLKnav. The CPU system 210 operates at a rate based on the clock CLKcpu. The clocks CLKnav and CLKcpu are generally asynchronous, and the CLKcpu frequency is sufficiently high compared to the CLKnav frequency. In one embodiment, the frequency of the CPU 107 is synchronous and sufficiently high compared to the CLKcpu frequency.

[0031] In another embodiment, the operating frequencies of the positioning channel 104, the multi-channel data manager 205, and the DMA channel reload unit 207 are synchronous and significantly higher than the CLKcpu.

[0032] In one embodiment, the following components are connected to the BUS 108: a multi-channel data manager 205, a CPU 107, a memory 109, a positioning system 200, an NS2CS interface block 202, a DMA channel reload unit 207, and a positioning channel 104.

[0033] The CPU 107 controls the following components via the BUS 108: the multi-channel data manager 205, the positioning system 200, the NS2CS interface block 202, the DMA channel reload unit 207, and the positioning channel 104.

[0034] In one embodiment, CPU 107 is configured to write data to memory 109 via BUS 108. In one embodiment, memory 109 is used for data storage.

[0035] The following components can be sources of data: ADC 101, signal processor 102, requantizer 103, NS2CS interface block 202, and CPU 107.

[0036] In one embodiment, after processing, each of the multiple requantizers 103 produces the same number of samples within a predetermined period. The outputs from each requantizer 103 are aggregated into one stream and sent via a MUX interconnection unit 201 to the input of one NS2CS interface block 202 for further processing. In one embodiment, one NS2CS interface block 202 is allocated for further processing.

[0037] In one embodiment, the output from the requantizer 103 is input to the NS2CS interface block 202 via a MUX interconnect unit 201. In one embodiment, the NS2CS interface block 202 writes data from the positioning system 200 to: memory 109, and / or CPU 107 via BUS 108.

[0038] The multi-channel data manager 205 reads the data from the memory 109 via the BUS 108. The multi-channel data manager 205 transmits the data from the memory 109 to the positioning channel 104, where the data is processed. After completing the operation, the multi-channel data manager 205 outputs an IRQ signal S206 to the CPU 107.

[0039] The CPU 107 uses the tick signal S106 and several IRQ signals (e.g., IRQ signal S206) from the multi-channel data manager 205, as well as data from the NS2CS interface block 202, to control the data stream between the multi-channel data manager 205 and the NS2CS interface block 202.

[0040] The DMA channel reload unit 207 is used to save / load the current state of the positioning channel 104 during data processing. The DMA channel reload unit 207 saves the current state of the positioning channel 104 in memory 109. The DMA channel reload unit 207 retrieves data from memory 109 and loads the current state into the positioning channel 104. The DMA channel reload unit 207 exchanges information with the multi-channel data manager 205 during operation.

[0041] In one embodiment, the GNSS receiver has allocated memory (not shown) that is accessed only by the NS2CS interface blocks 202 and the multi-channel data manager 205. Packages from the NS2CS interface blocks 202 are written to the allocated memory. The multi-channel data manager 205 reads packages from the allocated memory. Figure 3 shows a positioning system 200 communicating with a CPU system 210 via an NS2CS interface block 202, according to one embodiment.

[0042] In one embodiment, the NS2CS interface block 202 comprises an NS2CS control unit 300, which receives a tick signal S106 from the time control unit 105. The NS2CS control unit 300 communicates with a decimator NS2CS 301. The decimator NS2CS 301 and the MUX interconnection unit 201 send signals to a multiplexer 302, which communicates with the NS2CS control unit 300. The MUX interconnection unit 201 sends a continuous data stream S308 to the multiplexer 302 and the decimator NS2CS 301. The signal output from the multiplexer 302 is sent to a data preparer and requantizer 303, which communicates with the NS2CS control unit 300. The data preparer and requantizer 303 sends signals to an asymmetric and asynchronous first-in, first-out buffer (also known as a FIFO) 304, which communicates with the NS2CS control unit 300. The FIFO 304 sends a signal to a package manager 309, which communicates with the NS2CS control unit 300. The package manager 309 communicates with the BUS 108 via signal S306. The BUS 108 communicates with the CPU 107 and the multi-channel data manager 205. The multi-channel data manager 205 also receives a RUN signal S307 and an IRQ signal S305 from the NS2CS control unit 300. The CPU 107 similarly receives the IRQ signal S305 from the NS2CS control unit 300.

[0043] The continuous data stream signal S308 from the MUX interconnection unit 201 is input to a decimator NS2CS301 as needed, which decimates the signal to different decimation factors. The signal output from the decimator NS2CS301 is input to a data generator / requantizer 303.

[0044] The data generator and requantizer 303 generates data and, if necessary, requantizes the data to lower bit data.

[0045] If decimation is not used, the continuous data stream signal S 308 from the MUX interconnection unit 201 is input to a multiplexer 302 and then sent to a data generator and requantizer 303 .

[0046] The data output from the data generator / requantizer 303 is input to a FIFO 304. The output from the FIFO 304 is then input to a package manager 309, where the data is converted into packages of a predetermined number of samples.

[0047] In one embodiment, the NS2CS control unit 300 before operation consists of: a decimator NS2CS 301 (if required), a multiplexer 302, a data preparer and requantizer 303, a FIFO 304, and a package manager 309.

[0048] In one embodiment, the NS2CS interface block 202 performs data pre-processing. The NS2CS interface block 202 converts data from the MUX interconnect unit 201 into the format required for the multi-channel data manager 205, the CPU 107, and the memory 109 (shown in FIG. 2). In one embodiment, the data stream output from the NS2CS interface block 202 is a package.

[0049] In one embodiment, a package is a number of samples allocated / configured by CPU 107. Each sample is data for one clock period CLKnav. NS2CS interface block 202 starts generating a package according to tick signal S106. In one embodiment, NS2CS interface block 202 generates a package and places it in memory 109 (shown in FIG. 2).

[0050] In one embodiment, the data in the package can be processed by: the positioning channel 104 (shown in FIG. 2) using a multi-channel data manager 205; the CPU 107;

[0051] In one embodiment, the package can be generated by: the CPU 107, the NS2CS interface block 202.

[0052] In one embodiment, the FIFO 304 resynchronizes data from the clock CLKnav to the clock CLKcpu.

[0053] In one embodiment, the NS2CS interface block 202 stacks data at a predetermined address during operation and generates an interrupt request signal S305 for the CPU 107. Data is written periodically as needed. In another embodiment, the decimator NS2CS 301 is eliminated to reduce the space required for the NS2CS interface block 202 in the ASIC.

[0054] The NS2CS interface block 202 operates in two modes: single package mode and multi-package mode.

[0055] FIG. 4A shows a signal graph of the NS2CS interface block 202 operating in single package mode. One package is formed during one tick signal S106. Once the package is formed, an IRQ signal S305 is generated and input to the CPU 107 and the multi-channel data manager 205. In this mode, the CPU 107 uses the tick signal S106 and the IRQ signal S305 from the NS2CS interface block 202 to control the data stream. In one embodiment, the multi-channel data manager 205 uses the IRQ signal S305 from the NS2CS interface block 202 to control the data stream. In one embodiment, the multi-channel data manager 205 generates a multi-bit data signal S501 and an enable signal S502 for the positioning channel 104.

[0056] FIG. 4B shows a signal graph of the NS2CS interface block 202 operating in multi-package mode. The time control unit 105 generates a tick signal S106 and initiates data processing accordingly. During one period of the tick signal S106, U packages are formed. When the first package is formed and written to memory 109, a signal S305 is generated. After each package is completed, a RUN signal S307 is generated. In one embodiment, packages 1...U have the same size. In another embodiment, packages 1...U have different sizes. The multi-channel data manager 205 reads the packages from memory 109 and generates multi-bit data signals S501 and S502 for the positioning channel 104 based on the signal S307 and the IRQ signal S305. Additional operations related to the packages are performed as needed; specifically, the NS2CS interface block 202 generates the S305 and S307 signals any time after writing the packages to memory 109.

[0057] 5 shows signals received by multi-channel data manager 205. The signals received by multi-channel data manager 205 include "N" signals output from NS2CS interface blocks 202(1)...202(N), indicated as signals S307(1)...S307(N). As previously mentioned, the signals received by multi-channel data manager 205 are used in first-try automatic mode.

[0058] The multi-channel data manager 205 uses signal S307 to read the package from memory 109 and generate signals S501 (see FIGS. 4A and 4B) and S502 from multiple NS2CS interface blocks 202 simultaneously.

[0059]

[0060] When decimation is used, the number of samples at the input of the NS2CS interface block 202 is reduced, thereby reducing the size of the packages. In one embodiment, the NS2CS interface block converts the received digitized signal into packages of a set or specified size.

[0061] Figure 6 illustrates a positioning channel in communication with components of the NS2CS CPU system 210 of Figure 3, according to one embodiment. As shown in Figure 6, the positioning channel 104 includes at least one channel 500. Channel 500 receives "D" signals, designated signals S501(1)...S501(D) and enable signals S502(1)...S502(D), from the multi-channel data manager 205, and further comprises a code rate NCO (CRNCO) 503, a code generator 506, a strobe generator 508, an integration period counter 510, an intermediate frequency NCO (IFNCO) 512, a correlator 515, and a commutator 516. The signals transmitted and / or received include a code rate signal S504, a code phase signal S505, a coding signal S507, a strobe signal S509, an integration period (IP) signal S511, a cosine signal S513, a sine signal S514, and an output signal S517 from a commutator 516.

[0062] In one embodiment, the positioning channel 104 is comprised of multiple channels 500. FIG. 6 illustrates one of the multiple channels, channel 500. In one embodiment, a package may contain data from one or more data sources. Data from different sources may be combined into a single package with the same number of samples within a given time period. Low-bit data received from the outputs of different requantizers 103 (shown in FIG. 2) is multiplexed into a single multi-digit word and input to the assigned NS2CS interface block 202 to generate a common package, which is then sent to and stored in memory 109. The multi-channel data manager 205 reads the package from memory 109 and converts the data from the requantizers 103(1)...103(Q) (shown in FIG. 2) into "D" signals, denoted signals S501(1)...S501(D), to form enable signals S502(1)...S502(D). Data from each requantizer 103(1)...103(Q) is transmitted as signals S501(1)...S501(D) and enable signals S502(1)...S502(D), respectively. Signals S501(1...D) and S502(1...D) are transmitted from multi-channel data manager 205 to the inputs of commutator 516. Signals S501(1) and S502(1) are used simultaneously. Signals S501(D) and S502(D) are used simultaneously. CPU 107 connects channel 500 to signals S501(i) and S502(i) via commutator 516, where is any number from 1...D. If signal S502(i) is valid, processing of data S501(i) in channel 500 is permitted, and the internal clock CLKcpu within channel 500 is enabled. When signal S502(i) is invalid and processing of S501(i) in channel 500 stops, the internal clock CLKcpu is disabled within channel 500.

[0063] In one embodiment, multi-channel data manager 205 sends one package to positioning channel 104 while the next package is being generated. In one embodiment, multi-channel data manager 205 sends multiple packages formed simultaneously to positioning channel 104 while the next package is being generated in parallel. CPU 107 controls multi-channel data manager 205 and DMA channel reload unit 207 via BUS 108. Multi-channel data manager 205 also controls DMA channel reload unit 207. CPU 107 adjusts multi-channel data manager 205 prior to operation to operate in one of several modes.

[0064] The multi-channel data manager 205 may operate in the following modes: CPU full control mode, first try automatic mode, and automatic control mode.

[0065] In one embodiment, in the CPU full control mode, the CPU 107 controls the multi-channel data manager 205, the DMA channel reload unit 207, and the channel 500. In one embodiment, the CPU full control mode is used only when the NS2CS interface block 202 operates in single package mode. The time control unit 105 generates a tick signal S106, which sets the rate at which data is processed. When a package is formed, a signal S305 is generated. The CPU 107 writes a control command to the positioning channel 104 according to the signal S305, after which the multi-channel data manager 205 sends the package according to the command from the CPU 107. When the package is sent, the multi-channel data manager 205 generates a signal S206. The CPU 107 reads the data from the positioning channel 104 based on the signal S206. An advantage of this mode is that the CPU 107 itself can decide which block to send data to, allowing for a more flexible data processing chain.

[0066] In one embodiment, in first-try automatic mode, the CPU 107 controls the multi-channel data manager 205 and the channel 500 to send packages via the channel 500 using signals S305 and S307 (see FIGS. 5 and 6). In one embodiment, the first-try automatic mode is used only when the NS2CS interface block 202 operates in multi-package mode. The time control unit 105 generates a tick signal S106, which sets the rate at which data is processed. After the first package is completely sent, the signal S305 is generated. The CPU 107 sends a control command to the positioning channel 104 according to the signal S305, and the multi-channel data manager 205 sends the package based on the CPU command. At the end of each package except the first package, the multi-channel data manager 205 executes according to the RUN signal S307, and the package is sent to the positioning channel 104. After the last package, the multi-channel data manager 205 generates a signal S206 based on the current tick signal S106. CPU 107 reads data from positioning channel 104 based on signal S206. The advantage of this mode is that it requires less memory due to a smaller package. Additionally, this mode requires less control from the CPU, resulting in less power consumption.

[0067] In one embodiment, in automatic control mode, multi-channel data manager 205 controls channel 500 and DMA channel reload unit 207. CPU 107 communicates data with multi-channel data manager 205 via memory 109. In this mode, multi-channel data manager 205 uses signals S206, S305, and S307.

[0068] In one embodiment, in the automatic control mode, the NS2CS interface block 202 operates in single-package mode. The time control unit 105 generates a tick signal S106, which sets the rate at which data is processed. The CPU 107 writes control commands to the memory 109 as needed. When a package is formed, a signal S305 is generated. The multi-channel data manager 205 reads the control command from the memory 109 and writes the control command to the positioning channel 104 in accordance with the signal S305, and then sends the package. When the package is sent, the multi-channel data manager 205 reads the ready data from the channel 500, writes it to the memory 109, and then generates a signal S206. The CPU 107 reads the ready data from the memory 109 based on the signal S206. In one embodiment, the multi-channel data manager 205 automatically controls the DMA channel reload unit 207 to reuse the channel 500. Advantages of this mode include minimal CPU usage and reuse of the channel 500.

[0069] In one embodiment, in the automatic control mode, the NS2CS interface block 202 operates in multi-package mode. The time control unit 105 generates a tick signal S106, which sets the rate at which data is processed. After the first package is completely sent, a signal S305 is generated. The multi-channel data manager 205 reads control commands from the memory 109, writes the control commands to the positioning channel 104, and then sends the package. At the end of each package except the first package, the multi-channel data manager 205 executes according to the RUN signal S307, and sends the package to the positioning channel 104. After the last package, based on the current tick signal S106, the multi-channel data manager 205 reads ready data from the channel 500, writes it to the memory 109, and then generates a signal S206. The CPU 107 reads the ready data from the memory 109 based on the signal S206. In one embodiment, the multi-channel data manager 205 automatically controls the DMA channel reload unit 207 to reuse the channel 500. The advantages of this mode are minimal CPU usage, reuse of channel 500, and smaller packaging, which requires less memory.

[0070] In CPU full control mode, multi-channel data manager 205 generates IRQ signal S206 at the end of the package, after the data has been sent to channel 500, which corresponds to the duration of tick signal S106.

[0071] In first-try automatic mode, the multi-channel data manager 205 generates an IRQ signal S206 once for some packages, which is when data transmission to the channel 500 is completed, and the IRQ signal S206 corresponds to the duration of the tick signal S106.

[0072] Signals S501(1)...S501(D) and signals S502(1)...S502(D) are sent from multi-channel data manager 205 to inputs of commutator 516. CPU 107 interfaces with commutator 516 to connect channel 500 to signals S501(i) and S502(i), where "i" is any number from 1 to D.

[0073] If signal S502(i) is not valid at the time multi-channel data manager 205 is reading a package from memory 109, it indicates that the package has ended or that multi-channel data manager 205 has not had time to read the next data from memory 109, and channel 500 stops processing data during this period.

[0074] The positioning channel 104 is made up of a set of multiple channels 500. The CPU 107 controls the channels 500 via the BUS 108. In the channels 500, each sample from the package is processed within one clock cycle of the CLKcpu.

[0075] In one embodiment, the period of tick signal S106 is shorter than the period of integration period signal S511.

[0076] The current configuration of channel 500 is a group of settings or parameters defined for a selected GNSS signal processing mode, such as signal S501(i) (referred to as selected enabling signal S502(i)) and the configuration of code generator 506.

[0077] In one embodiment, CPU 107 configures, controls, and acquires data from channels 500 when multi-channel data manager 205 is not sending data signal S501. Before operation, CPU 107 configures the following components and parameters of channel 500: code frequency and initial code phase in code rate NCO 503, code generator 506, strobe generator 508, duration of integration period signal S511 in integration period counter 510, intermediate frequency and initial code phase in intermediate frequency NCO 512, and commutator 516. In one embodiment, multi-channel data manager 205 determines whether data is ready in multiple channels based on integration period signal S511, and CPU 107 reads it after processing the data.

[0078] In one embodiment, channel 500 processes input signal S501(i) from start to finish of the package.

[0079] CRNCO 503 generates a code frequency signal S504, which is input to code generator 506 and integration period counter 510. Code generator 506 generates a coded signal S507 at the code rate of signal S504. Coded signal S507 is input to strobe generator 508 and correlator 515. CRNCO 503 generates a code phase signal S505, which is input to strobe generator 508. Strobe generator 508 uses signals S507 and S505 to generate a strobe signal S509, which is input to correlator 515. IFNCO 512 generates a cosine signal (Cos) S513 and a sine signal (Sin) S514 having an intermediate frequency. Signals S513 and S514 are input to correlator 515. From commutator 516, signal S517 is input to correlator 515. Integration period counter 510 generates integration period signal S511 based on coding rate signal S504. Integration period signal S511 is input to correlator 515 and multi-channel data manager 205. In one embodiment, signal S517 is signal S501(i).

[0080] In correlator 515, signal S517 is multiplied by cosine signal S513 and coded signal S507, and the multiplication result is accumulated over integration period signal S511. According to integration period signal S511, the accumulated value is stored in buffer register 1 (component I below), and when necessary, CPU 107 captures this value and the accumulated value is set to zero. (Equation 1) TIFF2025529029000002.tif16159

[0081] In the correlator 515, the signal S517 is multiplied by the sine signal S514 and the coded signal S507, and the multiplication result is accumulated over the integration period signal S511. According to the signal S511, the accumulated value is stored in the buffer register 2 (component Q below), and when necessary, the CPU 107 captures this value and the accumulated value is set to zero. (Equation 2) TIFF2025529029000003.tif16159

[0082] In correlator 515, signal S517 is multiplied by cosine signal S513 and strobe signal S509, and the multiplication result is accumulated over integration period signal S511. According to signal S511, the accumulated value is stored in buffer register 3 (component dI below), and when necessary, CPU 107 captures this value and the accumulated value is set to zero. (Equation 3) In the TIFF2025529029000004.tif16159 correlator 515, the signal S517 is multiplied by the sine signal S514 and the strobe signal S509, and the multiplication result is accumulated over the integration period signal S511. According to the signal S511, the accumulated value is stored in the buffer register 4 (component dQ below), and when necessary, the CPU 107 captures this value and the accumulated value is set to zero. (Equation 4) In one embodiment, in full CPU control mode or first-try automatic mode, CPU 107, based on signal S206, reads ready data from channel 500, including the values ​​(components I, Q, dI, dQ) in buffer registers 1 through 4, if signal 511 in multi-channel data manager 205 is available. Note that other data such as the code phase CRNCO 503, the intermediate frequency phase in IFNCO 512, and the state of integration period counter 510 can also be read.

[0083] In one embodiment, in automatic control mode, CPU 107, based on signal S206, reads ready data from memory 109, including the values ​​of buffer registers 1 through 4 (components I, Q, dI, dQ) if signal 511 in multi-channel data manager 205 is available. Multi-channel data manager 205 may be configured to read and write additional data from channel 500 to memory 109, such as code phase CRNCO 503, intermediate frequency phase in IFNCO 512, and the state of integration period counter 510. CPU 107 reads the additional data from memory 109.

[0084] In one embodiment, before processing by signal S501(i), CPU 107 can control / change parameters of channel 500, including changing the code frequency in CRNCO 503, setting the code phase shift in CRNCO 503, changing the intermediate frequency in IFNCO 512, setting the intermediate frequency phase shift in IFNCO 512, etc.

[0085] The operation of strobe generator 508 is described in US Pat. No. 7,764,226 B1, the entire disclosure of which is incorporated herein by reference.

[0086] In one embodiment, the multi-channel data manager 205 controls the DMA channel reload unit 207. The DMA channel reload unit 207 connects to several channels 500, the BUS 108, and the multi-channel data manager 205. The DMA channel reload unit 207 acts as a server for each channel 500.

[0087] In one embodiment, the DMA channel reload unit 207 is in communication with the components of each channel 500, including a code rate NCO (CRNCO) 503, a code generator 506, a strobe generator 508, an integration period counter 510, an intermediate frequency NCO (IFNCO) 512, a correlator 515, and a commutator 516.

[0088] Each channel 500 has a current state when processing a signal, including the current configuration and current state of the operating logic of each channel 500, for example, the current CRNCO 503 phase and IFNCO 512 phase.

[0089] FIG. 7A illustrates the package processing steps, which are described below.

[0090] Signals S305 and S307 notify multi-channel data manager 205 that a new package is present in memory 109. CPU 107 uses a combination of signals S106, S206, S307, and S305 to control the GNSS signals processed on channel 500. Package processing by multi-channel data manager 205 and DMA channel reload unit 207 includes the following steps: The table below describes the package processing steps. The "Designation" column in this table indicates that the last digit of the label in FIG. 7A is associated with a particular step (i.e., labels 9111, 9211, and 9311 each relate to a configuration step; labels 9112, 9212, and 9312 each relate to a load step; labels 9113, 9213, and 9313 each relate to a control step, etc.). (table) TIFF2025529029000006.tif153159

[0091] In one embodiment, during the creation of a new package, all steps required for each current configuration of channels must be completed.

[0092] In the CPU full control mode, the configuration and control steps are controlled by the CPU 107. In the configuration and control steps, the CPU 107 controls the channel 500 before sending a package to the channel 500. The read step is controlled by the CPU 107. In the read step, the CPU 107 reads ready data from the channel 500 after processing the package in the channel 500. The multi-channel data manager 205 generates an IRQ signal S206 after processing the package (after the processing step).

[0093] In first-try automatic mode, the configuration and control steps are controlled by CPU 107. In the configuration and control steps, CPU 107 controls channel 500 before the first package formed during tick signal S106 is sent to channel 500. The read step is controlled by CPU 107. In the read step, CPU 107 reads ready data from channel 500 after channel 500 processes the last package generated during tick signal S106. Multi-channel data manager 205 generates IRQ signal S206 after channel 500 processes the last package generated during tick signal S106 (after the processing step).

[0094] The load and save steps are used only in automatic control mode and allow processing of GNSS signals in several configurations using channel 500. Multi-channel data manager 205 generates an interrupt request signal S206 after the read step to notify CPU 107 that data has been sent to memory 109. Multi-channel data manager 205 receives signals S305, S307 to notify that a new package is present in memory 109. Multi-channel data manager 205 then sends the package to channel 500. CPU 107 uses signals S106, S206, and S305 to prepare data for the configuration and control steps and to read the data after the read step.

[0095] In one embodiment, in the automatic control mode, when the NS2CS interface block 202 operates in the single package mode, the configuration and control steps are controlled by the multi-channel data manager 205. The load and save steps are controlled by the DMA channel reload unit 207. The CPU 107 writes control commands for the configuration and control steps to the memory 109. Before sending the package to the channel 500, the configuration, load, and control steps are performed. In the configuration step, the multi-channel data manager 205 reads control commands from the memory 109 and writes the commands to the channel 500. In the load step, the DMA channel reload unit 207 reads data from the memory 109 and writes the data to the channel 500. In the control step, the multi-channel data manager 205 reads control commands from the memory 109 and writes the commands to the channel 500. Thereafter, the processing steps are performed under the control of the multi-channel data manager 205. After sending the package to the channel 500, the save and read steps are performed. In the storing step, the DMA channel reload unit 207 reads data from the channel 500 and writes it to the memory 109. The reading step is controlled by the multi-channel data manager 205. After processing the package in the channel 500, in the reading step the multi-channel data manager 205 reads the ready data from the channel 500, writes it to the memory 109, and generates an IRQ signal S206. Based on the IRQ signal S206, the CPU 107 reads the ready data from the memory 109.

[0096] In one embodiment, in the automatic control mode, when the NS2CS interface block 202 operates in the multi-package mode, the configuration step and the control step are controlled by the multi-channel data manager 205. The load step and the save step are controlled by the DMA channel reload unit 207. The CPU 107 writes control commands for the configuration step and the control step to the memory 109. The configuration, load, and control steps are executed before sending the first package generated during the tick signal S106 to the channel 500. In the configuration step, the multi-channel data manager 205 reads the control command from the memory 109 and writes the command to the channel 500. In the load step, the DMA channel reload unit 207 reads data from the memory 109 and writes it to the channel 500. In the control step, the multi-channel data manager 205 reads the control command from the memory 109 and writes the command to the channel 500. The multi-channel data manager 205 uses signal S305 to perform processing steps and send the first package generated during the tick signal S106. The multi-channel data manager 205 uses signal S206 to perform processing steps and send each package except the first. During the tick signal S106, after processing the last package in the channel 500, a store step and a read step are performed. In the store step, the DMA channel reload unit 207 reads data from the channel 500 and writes it to memory 109. The read step is controlled by the multi-channel data manager 205. After processing the last package generated during the tick signal S106 in the channel 500, the multi-channel data manager 205 reads ready data from the channel 500, writes it to memory 109, and generates an IRQ signal S206. Based on the IRQ signal S206, the CPU 107 reads the ready data from memory 109. In one embodiment, the following steps are performed in the following order: Configuration steps:

[0097] The configuration step (e.g., shown as step 9**1 in FIG. 7A) can be used sequentially for multiple channels 500. If processing of a new GNSS signal needs to be performed, the channel 500 is set to the new configuration. The channel 500 can also stop GNSS signal processing if necessary. Load Step:

[0098] For channel 500, if a load step (e.g., shown as step 9**2 in FIG. 7A) is used in the processing, the load step is executed sequentially, the current state of channel 500 is read from memory 109 and written to channel 500, and for continuous processing, channel 500 is saved in memory 109 using each configuration of the previous GNSS signal. Control steps:

[0099] The control steps (shown for example in FIG. 7A as step 9**3) can be used sequentially for multiple channels 500. Control commands are sent to the channels 500 as needed. Processing Steps:

[0100] For all channels 500, the processing steps (e.g., shown as step 9**4 in FIG. 7A) are applied simultaneously (in parallel). Each package (represented by signal S501) is sent simultaneously to all channels 500. Each channel 500 processes its own package received as signal S501(i).

[0101] Save step:

[0102] The save steps (e.g., shown as step 9**5 in FIG. 7A) are performed sequentially, where the save step is performed after processing. The current state of the channel 500 is written to the memory 109, and the current state that the channel 500 continuously writes to the memory 109 is the processed GNSS signal, and the data thus written to the memory 109 is used for the next load step. Read steps:

[0103] The read step is used sequentially as needed (e.g., as shown in FIG. 7A as step 9**6) for multiple channels 500. When signal S511 is available in multi-channel data manager 205, ready data is obtained from channel 500.

[0104] In one embodiment, CPU 107 reads data from channel 500 without using multi-channel data manager 205, if necessary, and temporarily suspends operation of multi-channel data manager 205 after signal S206.

[0105] In one embodiment, the channel 500 does not process a previously configured configuration, the CPU 107 does not set one or more new configurations for the channel 500, and the multi-channel data manager 205 does not send a package to the channel 500 (i.e., the multi-channel data manager 205 skips all steps) and generates a signal S206.

[0106] In one embodiment, in automatic control mode, signal S206 is formed only after the read step of the package that is processed at the end of the current period of tick signal S106.

[0107] The load and store steps are used when processing several configurations by one of the channels 500. By using the load and store steps, when processing several configurations in one of the channels 500, it is possible to implement a pipeline mode for all configurations of the channel 500. To process each configuration, a package needs to be sent to the channel 500.

[0108] When a load and store step is required, multi-channel data manager 205 gives control to DMA channel reload unit 207. DMA channel reload unit 207 performs the load / store step and reports it to multi-channel data manager 205.

[0109] In one embodiment, the multi-channel data manager 205 and the DMA channel reload unit 207 may be combined into one module with a single output sent to the BUS 108 .

[0110] By using the CPU 107 for each step of configuration and control in the CPU Full Control mode and the First Try Automatic mode, synchronicity of control of all channels 500 is ensured.

[0111] In one embodiment, in automatic control mode, while processing a package for the current period of the tick signal S106, the CPU 107 writes the configuration and control for the channel 500 to memory 109. When the multi-channel data manager 205 processes a package for the next period of the tick signal S106, it reads the configuration from memory 109 and sends it to the channel 500. This control ensures synchronous control of the channel 500.

[0112] In the automatic control mode, if it is necessary to stop the operation of the multi-channel data manager 205 before or after a configuration step and / or a control step, the CPU 107 sends a command to the multi-channel data manager 205. The multi-channel data manager 205 stops operation and generates an interrupt request signal S206. The multi-channel data manager 205 continues processing based on the command from the CPU 107. The stop of the multi-channel data manager 205 set by the CPU 107 may be single or periodic.

[0113] In Figure 7A, steps with a shaded background are not activated (i.e., not used). In one embodiment, the time for package generation is equal to the period of the tick signal S106.

[0114] In one embodiment, channel 500(1) processes signal S501(i) in the configuration of Configuration 1. In the configuration of Configuration 1, the data packages are processed in the same way as a typical GNSS receiver (see FIG. 1) operates channel 500 in pipeline mode.

[0115] In Configuration 1, the load and save steps are not used. Configuration 1 is performed in the following manner: in tick 1, the configuration is set and GNSS signals are processed. Ready data is read as needed; in ticks 2 and 3, GNSS signal processing continues, and control commands are used to read and / or write ready data as needed.

[0116] In one embodiment, channel 500(2) processes signal S501(i+1) in configuration 2 and configuration 3.

[0117] Configuration 2 is executed in the following manner: In tick 1, the configuration is set, GNSS signals are processed, the current state of configuration 2 channel 500(2) is saved, and ready data is read as needed. In ticks 2 and 3, GNSS signal processing continues, the current state of configuration 2 channel 500(2) is loaded / saved, ready data is read as needed, and control commands are written.

[0118] Configuration 3 is executed in the following manner: Tick 1 is unused. In tick 2, the configuration is set, GNSS signals are processed, the current state of configuration 3 channel 500(2) is saved, and ready data is read as needed. In tick 3, GNSS signal processing continues, the current state of configuration 3 channel 500(2) is loaded / saved, ready data is read as needed, and control commands are written.

[0119] In another embodiment, channel 500(3) processes signal S501(i+2) in configuration 4 and configuration 5.

[0120] Configurations 4 and 5 are executed in the following manner: In tick 1, the configuration is set, the GNSS signals are processed, the current state of configuration 4 / configuration 5 channel 500(3) is saved, and ready data is read as needed. In ticks 2 and 3, GNSS signal processing continues, the current state of configuration 4 / configuration 5 channel 500(3) is loaded / saved, and ready data is read as needed, and control commands are written.

[0121] During the formation of a new package after tick signal S106 9200, the following packages are processed simultaneously: channel 500(1) in configuration 1 processes signal S501(i), channel 500(2) in configuration 2 processes signal S501(i+1), and channel 500(3) in configuration 4 processes signal S501(i+2). The packages are then processed again as follows: channel 500(2) in configuration 3 processes signal S501(i+1), and channel 500(3) in configuration 5 processes signal S501(i+2).

[0122] As shown in Figure 7A, the steps are performed in the following order:

[0123] When tick signal S106 number 1, i.e., tick 1 9100, occurs, the following steps are executed: setting configuration 1 by configuration step 9111; setting configuration 2 by configuration step 9121; setting configuration 4 by configuration step 9141; processing steps 9114, 9124, and 9144; saving steps 9125 and 9145; reading steps 9116, 9126, and 9146; setting configuration 5 by configuration step 9151; processing step 9154; saving step 9155; reading step 9156.

[0124] When tick signal S106 number 2, i.e., tick 2 9200, occurs, the following steps are executed: load steps 9222 and 9242; control step 9213 for configuration 1; control step 9223 for configuration 2; control step 9243 for configuration 4; processing steps 9214, 9224, and 9244; save steps 9225 and 9245; read steps 9216, 9226, and 9246; setting of configuration 3 by configuration step 9231; load step 9252; control step 9253 for configuration 5; processing steps 9234 and 9254; save steps 9235 and 9255; read step 9236; read step 9256.

[0125] When tick signal S106 number 3, i.e., tick 3 9300, occurs, the following steps are executed: load steps 9322 and 9342; control step 9313 for configuration 1; control step 9323 for configuration 2; control step 9343 for configuration 4; processing steps 9314, 9324, and 9344; save steps 9325 and 9345; read step 9316; read step 9326; read step 9346; load steps 9332 and 9352; control step 9333 for configuration 3; control step 9353 for configuration 5; processing steps 9334 and 9354; save steps 9335 and 9355; read steps 9336 and 9356. It should be noted here that: processing steps 9114, 9124, and 9144 are performed simultaneously; processing steps 9214, 9224, and 9244 are performed simultaneously; processing steps 9234 and 9254 are performed simultaneously; processing steps 9314, 9324, and 9344 are performed simultaneously; and processing steps 9334 and 9354 are performed simultaneously.

[0126] During the tick signal S106 (ie, when a new package is formed), the package must be sent twice to channel 500(2,3) in order to process the configuration "Configuration 2...5."

[0127] In one embodiment, in single GNSS signal processing mode, channel 500 operates in a configuration corresponding to configuration 1.

[0128] In one embodiment, in a multi-configuration mode of GNSS signal processing, channel 500 is used for several configurations, corresponding to configurations 2...5, which can be added or removed from the processing, with operation occurring only for the required configuration.

[0129] In one embodiment, the multi-channel data manager 205 can be used to process multiple channels 500 simultaneously in a single GNSS signal processing mode and in a multi-configuration mode of GNSS signal processing.

[0130] FIG. 7B shows a diagram of the operation of the multi-channel data manager 205 in full CPU control mode according to one embodiment.

[0131] The package corresponds to the period of the tick signal S106. In the CPU full control mode, the CPU 107 uses the tick signal S106, the signal S305, and the signal S206 to fully control the GNSS signal processing by using the multi-channel data manager 205, and controls each step of configuration, control, and readout.

[0132] In one embodiment, in single GNSS signal processing mode, channel 500 uses only one configuration. NS2CS interface block 202 starts operation and forms a package based on tick signal S106. CPU 107 receives signal S305 and performs configuration and control steps. In the processing step, multi-channel data manager 205 transmits the package to positioning channel 104 at the command of CPU 107. Multi-channel data manager 205 finishes transmitting the package and generates signal S206. CPU 107 receives signal S206 and performs a read step. All steps are then repeated periodically.

[0133] FIG. 7C shows a diagram of the operation of the multi-channel data manager 205 in first-try automatic mode (four packages are formed per tick period), according to one embodiment.

[0134] Over the period of tick signal S106, four packages are formed (i.e., multi-package mode). In first-try automatic mode, the processing of package 2 and package 3 does not require any control from CPU 107. After processing package 4, CPU 107 receives signal S206 and reads ready data from channel 500.

[0135] In one embodiment, in single GNSS signal processing mode, channel 500 uses only one configuration. NS2CS interface block 202 initiates package formation via tick signal S106. CPU 107 receives signal S305 and executes configuration and control steps. In the processing step, multi-channel data manager 205 transmits package 1 to positioning channel 104 via command from CPU 107. In the processing step, multi-channel data manager 205 transmits package 2, package 3, and package 4 to positioning channel 104 via signal S307. Transmission by multi-channel data manager 205 is completed with package 4, and multi-channel data manager 205 generates signal S206. CPU 107 receives signal S206 and executes a read step. All steps are then repeated periodically.

[0136] FIG. 7D illustrates a diagram of the operation of multi-channel data manager 205 and DMA channel reload unit 207 in automatic control mode and NS2CS interface block 202 in single package mode, according to one embodiment.

[0137] The package corresponds to the period of the tick signal S106 (single package mode). During the formation of a new package, the current package is sent twice to channel 500, and one channel 500 is used to process GNSS signals in two configurations. The NS2CS interface block 202 starts the package formation based on the tick signal S106. The CPU 107 writes control commands for channel 500 to memory 109. The following steps are repeated twice for the two configurations. The multi-channel data manager 205 receives signal S305, performs the configuration, load, and control steps, and reads data from memory 109. In the processing step, the multi-channel data manager 205 transmits the package to the positioning channel 104. The multi-channel data manager 205 finishes transmitting the package, performs the storage step (reading the current state from channel 500 and writing it to memory 109), performs the read step (reading the ready data from channel 500 and writing it to memory 109), and generates signal S206. The CPU 107 receives the signal S206 and reads the ready data from the memory 109. Then the multi-channel data manager 205 waits for the signal S305. Then all steps are repeated periodically.

[0138] FIG. 7E illustrates the operation of multi-channel data manager 205 and DMA channel reload unit 207 in automatic control mode, and a diagram of NS2CS interface block 202 in multi-package mode (three packages formed per tick), according to one embodiment.

[0139] During the period of the tick signal S106, three packages are formed (multi-package mode). During the formation of a new package, the current package is sent to channel 500 five times, and five configurations of GNSS signals are processed in one channel 500. The NS2CS interface block 202 starts forming the package based on the tick signal S106. The CPU 107 writes control commands for channel 500 to memory 109. The multi-channel data manager 205 receives signal S305 and starts processing package 1. The following steps are repeated five times for five configurations. The multi-channel data manager 205 performs the configuration, load, and control steps and reads data from memory 109. In the processing step, the multi-channel data manager 205 transmits the package to the positioning channel 104. The multi-channel data manager 205 finishes transmitting the package and performs the storage step (reading the current state from channel 500 and writing it to memory 109). The multi-channel data manager 205 receives signal S307 and begins processing package 2. The following steps are repeated five times in five configurations. In the load step, the multi-channel data manager 205 reads the current state from memory 109 and writes it to channel 500. In the process step, the multi-channel data manager 205 transmits the package to the positioning channel 104. The multi-channel data manager 205 finishes transmitting the package and executes the save step (reading the current state from channel 500 and writing it to memory 109). The multi-channel data manager 205 receives signal S307 and begins processing package 3. The following steps are repeated five times in five configurations. In the load step, the multi-channel data manager 205 reads the current state from memory 109 and writes it to channel 500. In the process step, the multi-channel data manager 205 transmits the package to the positioning channel 104. The multi-channel data manager 205 finishes sending the package and performs a save step (reading the current state from the channel 500 and writing it to memory 109).The multi-channel data manager 205 then executes a read step, reading the ready data from the channel 500 and writing it to the memory 109, generating a signal S206. The CPU 107 receives the signal S206 and reads the ready data from the memory 109. The multi-channel data manager 205 then waits for a signal S305. All steps are then repeated periodically. In one embodiment, the GNSS receiver architecture includes a positioning system 200 that processes GNSS signals in a pipeline mode based on a clock CLKnav and generates packages using the NS2CS interface block 202 to provide additional flexibility in processing the GNSS signals. In one embodiment, the formation of the packages is associated with a tick signal S106, and the packages are further processed in the CPU system 210 based on a clock CLKcpu.

[0140] In one embodiment, data from multiple requantizers 103 are combined into a package with the same number of samples over a period of time in one NS2CS interface block 202, forming a package that is placed in memory 109. This package is input to the positioning channel 104 via the multi-channel data manager 205, where it is processed based on the clock CLKcpu. The NS2CS interface block 202 then generates sequential packages that enable pipelined processing of the GNSS signals in the positioning channel 104. Control and data readout of the positioning channel 104 are performed between package processing.

[0141] In one embodiment, when a decimator (e.g., signal processor 102, decimator NS2CS 301) is used, the packages are formed by separate NS2CS interface blocks 202. Each NS2CS interface block 202 forms its own package and writes it to memory 109. After the packages are formed, multi-channel data manager 205 retrieves each package from memory 109 and sends them simultaneously to positioning channel 104.

[0142] In one embodiment, a key feature is the addition of DMA channel reload unit 207. DMA channel reload unit 207 enables processing of GNSS signals in several current configurations with the assistance of channel 500 during the creation of a new package. In one embodiment, DMA channel reload unit 207 provides pipeline processing of several current configurations by channel 500.

[0143] Packages may be processed in the positioning channel 104 in different modes: a CPU full control mode, in which the CPU 107 controls all GNSS signal processing; a first-try automatic mode, in which the CPU 107 controls the multi-channel data manager 205 and the channel 500. The multi-channel data manager 205 sends packages for the channel 500 upon command from the CPU 107 using signal S307. Additionally, an automatic control mode, in which the CPU 107 controls the channel 500 via the memory 109. The multi-channel data manager 205 reads control data from the memory 109 and generates the packages itself. In this mode, the DMA channel reload unit 207 is used to process the packages in some current configuration. The CPU 107 controls the multi-channel data manager 205 before and during operation as needed.

[0144] The use of the DMA channel reload unit 207 allows for a reduction in the number of channels 500 while ensuring the same quality of GNSS signal processing, or conversely, the functional advantage of channel reuse in some configurations can be obtained without changing the number of channels.

[0145] In a standard GNSS receiver, a channel 500 processes GNSS signals in one configuration. In the present disclosure, the channel 500 processes GNSS signals in several configurations, which equates to an increase in the number of channels 500. Using a greater number of configurations improves the operational quality of the GNSS receiver.

[0146] According to one embodiment, a computer is used to perform the operations and equations of the components described herein and shown, for example, in FIGS. 2, 3, 5, and 6. These components may include, for example, ADCs, signal processors, requantizers, etc. A high-level block diagram of the computer is shown in FIG. 8. The computer 1002 includes a processor 1004 that controls the overall operation of the computer 1002 by executing computer program instructions that define the overall operation of the computer. The computer program instructions may be stored in a storage device 1012 or other computer-readable medium (e.g., a magnetic disk, CD-ROM, etc.) and loaded from the memory 1010 when execution of the computer program instructions is desired. In this manner, the method steps described herein may be defined by computer program instructions stored in the memory 1010 and / or the storage device 1012 and controlled by the processor 1004 executing the computer program instructions. For example, the computer program instructions may be implemented as computer-executable code programmed by one skilled in the art to perform an algorithm defined by one of the various methods described herein. In this manner, processor 1004 executes the computer program instructions to perform the algorithms defined by the method steps. Computer 1002 also includes one or more network interfaces 1006 for communicating with other devices over a network. Computer 1002 also includes input / output devices 1008 (e.g., a display, keyboard, mouse, speakers, buttons, etc.) that allow a user to interact with computer 1002. Those skilled in the art will recognize that an actual computer implementation may include other components, and that Figure 8 is a high-level representation of some of these computer components for illustrative purposes.

[0147] The foregoing detailed description is to be understood in all respects as being illustrative and illustrative, but not restrictive, and the scope of the inventive concepts disclosed herein is to be construed to the fullest extent permitted by applicable patent law. The embodiments shown and described herein are merely illustrative of the principles of the inventive concepts, and those skilled in the art will recognize that various modifications can be made without departing from the scope and spirit of the invention. Those skilled in the art will recognize that other combinations of the various features can be made without departing from the scope and spirit of the inventive concepts.

Claims

1. A positioning receiver, a plurality of RF transmission paths configured to receive and transmit Global Navigation Satellite System (GNSS) signals from the antenna; a positioning system configured to process the GNSS signals operating on a clock CLKnav; a plurality of analog-to-digital converters (ADCs), each configured to receive a GNSS signal from one of the plurality of RF transmission paths and generate a digitized signal; a plurality of signal processors configured to process the digitized signals; a plurality of requantizers configured to convert the processed digitized signals into lower bit data; a multiple navigation system to CPU system (NS2CS) interface block configured to generate a package based on the low-bit data; a MUX interconnection unit configured to distribute the data stream; a time control unit configured to generate a tick signal that is a time scale; Equipped with A CPU system that operates based on the tick signal, the CPU system operates a CLKcpu, and further a memory configured to store the data and the package; a multi-channel data manager configured to convert the package into data; a plurality of channels configured to receive and process data from the multi-channel data manager; a channel generated integration period signal indicating that the data is ready; a DMA channel reload unit configured to control a current state of each of the plurality of channels operating in various configurations, the multi-channel data manager further configured to control the DMA channel reload unit; a CPU configured to control the positioning system and the CPU system and configured to process data received from the positioning system and the CPU system, wherein the CPU uses the tick signal and uses interrupt request signals to synchronize control between the signal processor, the requantizer, the NS2CS interface block, the multi-channel data manager, and the plurality of channels.

2. 2. The positioning receiver of claim 1, wherein the NS2CS interface block generates an interrupt request signal to the CPU and the multi-channel data manager after writing the last package to the memory for the period of the tick signal.

3. 2. The positioning receiver according to claim 1, wherein the NS2CS interface block writes the package to memory and generates a RUN signal.

4. 2. A positioning receiver according to claim 1, characterized in that the NS2CS interface block receives low-bit data from several requantizers with the same number of samples per period and converts the low-bit data into packages of a set size.

5. 2. The positioning receiver of claim 1, wherein the NS2CS interface block starts sending data based on a tick signal, generating one package over the duration of the tick signal, or generating several packages over the duration of the tick signal.

6. 2. The positioning receiver of claim 1, wherein the multi-channel data manager reads all packages formed over a period of time from the memory, converts the packages into data, and sends the data simultaneously to the multiple channels.

7. 2. The positioning receiver of claim 1, wherein after processing the last package in the current tick signal period, the multi-channel data manager generates an interrupt request signal for the CPU, and the CPU processes the interrupt request signal from the multi-channel data manager.

8. 2. The positioning receiver of claim 1, wherein the multi-channel data manager reads packages from the memory based on various combinations of the RUN signal, an interrupt request signal from the NS2CS interface block, and a command from the CPU.

9. 2. The positioning receiver of claim 1, wherein said multi-channel data manager converts packages into data and sends it to said multiple channels at various times during the formation of subsequent packages.

10. 2. The positioning receiver of claim 1, wherein the DMA channel reload unit reads the current states of the plurality of channels from the memory and loads the current states into the channels before processing the data.

11. 2. The positioning receiver according to claim 1, wherein said DMA channel reload unit reads out said current states of said plurality of channels and stores them in said memory after data processing.

12. 2. The positioning receiver of claim 1, wherein one of the plurality of channels uses a commutator to process the data selected from the multi-channel data manager if a selected enabling signal for one of the plurality of channels is available.

13. 2. The positioning receiver according to claim 1, wherein said CPU reads and processes ready data after processing data in a plurality of said channels.

14. 2. The positioning receiver according to claim 1, wherein said CPU sends control signals to said plurality of channels between data processing operations to set a channel configuration for said plurality of channels.

15. 2. The positioning receiver according to claim 1, wherein said CPU sends control signals to said plurality of channels via a memory to set a channel configuration for said plurality of channels.

16. 16. The positioning receiver of claim 15, wherein the multi-channel data manager reads the control signals, the plurality of channels, and the channel configurations for the plurality of channels from the memory and writes them to the channels before processing the data.

17. 16. The positioning receiver of claim 15, wherein after data processing, the multi-channel data manager reads ready data from the channels, writes it to memory, and generates an interrupt request signal for a CPU, which processes the interrupt request signal from the multi-channel data manager.

18. 2. The positioning receiver of claim 1, wherein, based on a command from the CPU, the multi-channel data manager stops operation between data processing, generates an interrupt request signal for the CPU, and resumes data processing, and the CPU processes the interrupt request signal from the multi-channel data manager.

19. 2. A positioning receiver according to claim 1, characterized in that one channel processing package uses several configurations.

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