Nitride Thermal Atomic Layer Etching

Abstract

A nitride atomic layer etch is provided that includes generating phosphoric acid in situ on the surface of a silicon nitride layer by reacting a phosphorus-containing reactant with one or more oxidizing agents, where the phosphoric acid selectively etches the silicon nitride layer over silicon oxide and / or silicon.

Description

Incorporation by Reference

[0001] A PCT application is being filed concurrently herewith as part of this application, and each application identified in that concurrently filed PCT application to which this application claims benefit or priority is incorporated herein by reference in its entirety for all purposes. [Background technology]

[0002] Semiconductor fabrication processes often involve selectively etching one or more materials within a semiconductor substrate. As device sizes shrink and technology advances, it becomes increasingly difficult to selectively etch controlled amounts of material from the substrate without compromising the structural integrity of the device.

[0003] The background discussion provided herein is intended to provide a general overview of the contents of the present disclosure. Work by the currently named inventors within the scope of what is described in this background section, as well as aspects of the description that may not otherwise be considered prior art at the time of filing, are not admitted, expressly or impliedly, as prior art against the present disclosure. Summary of the Invention

[0004] Atomic layer etching of a silicon nitride layer is provided. The method may include reacting a phosphorus-containing reactant, an oxidizer, and / or water vapor to generate phosphoric acid in situ at the surface of the silicon nitride layer to act as a dry etching chemical. The phosphoric acid can selectively etch the silicon nitride layer over other adjacent materials, such as silicon or silicon oxide. The substrate temperature may be adjusted to above 100°C to increase the etch rate of the silicon nitride layer.

[0005] One aspect of the present disclosure relates to a method for treating a silicon nitride layer, which may include (a) forming phosphoric acid on a surface of the silicon nitride layer, and (b) treating a portion of the surface of the silicon nitride layer using the phosphoric acid.

[0006] In some embodiments, the method may further include, prior to (a), (c) providing water vapor to form one or more monolayers of water molecules on the surface of the silicon nitride layer.

[0007] In some embodiments, the temperature at the surface of the silicon nitride layer may range from about 0° C. to about 100° C., and the pressure at the surface of the silicon nitride layer ranges from about 1 Torr to about 100 Torr.

[0008] In some embodiments, the temperature may be about 20° C. and the pressure may be about 10 Torr.

[0009] In some embodiments, generating phosphoric acid may include providing a first reactant, providing a second reactant, and reacting the first reactant with the second reactant to form phosphoric acid. The first reactant may include phosphorus. The first reactant may be selected from the group consisting of phosphine, diphosphoric acid trioxide (PO), phosphorus trichloride, phosphorus oxychloride, methoxyphosphine, alkyl phosphine halide, trimethylphosphine, triethylphosphine, tripropylphosphine, and / or mixtures thereof. The second reactant may be selected from the group consisting of oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO), nitrous oxide (NO), nitric oxide (NO), nitrogen dioxide (NO), and / or mixtures thereof.

[0010] In some embodiments, the method may further include providing water vapor and adjusting the temperature to about 100° C. or higher before providing the water vapor or during the provision of the water vapor.

[0011] In some embodiments, treating the surface of the silicon nitride layer may include etching a portion of the surface of the silicon nitride layer to generate etching by-products.

[0012] In some embodiments, the method may further include removing etch by-products from the surface of the silicon nitride layer by (i) heating to about 360° C. or higher, (ii) heating to about 100° C. to about 120° C. by reaction with hydrogen fluoride, or (iii) reacting with hydrogen fluoride. The etch by-products may include phosphorus or silicon.

[0013] In some embodiments, generating phosphoric acid may include co-flowing a first reactant containing phosphorus with a second reactant. The first reactant may be selected from the group consisting of phosphine, diphosphoric acid trioxide (PO), phosphorus trichloride, phosphorus oxychloride, methoxyphosphine, alkyl phosphine halide, trimethylphosphine, triethylphosphine, tripropylphosphine, and / or mixtures thereof. The second reactant may be selected from the group consisting of oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO), nitrous oxide (NO), nitric oxide (NO), nitrogen dioxide (NO), and / or mixtures thereof.

[0014] Another aspect of the present disclosure relates to a method for etching a silicon nitride layer in a reaction chamber. The method may include providing a semiconductor substrate including a silicon nitride layer in a reaction chamber. The method may further include providing a first water vapor to form one or more monolayers of water molecules on a surface of the silicon nitride layer, and providing phosphine to the surface of the silicon nitride layer. The method may also include providing an oxidizing agent to the phosphine to in-situ generate phosphoric acid on the silicon nitride layer.

[0015] In some embodiments, the temperature at the surface of the silicon nitride layer may range from about 0° C. to about 100° C., and the pressure at the surface of the silicon nitride layer may range from about 1 Torr to about 100 Torr.

[0016] In some embodiments, the temperature may be about 20° C. and the pressure may be about 10 Torr.

[0017] In some embodiments, the oxidizing agent may be selected from the group consisting of oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO), nitrous oxide (NO), nitric oxide (NO), nitrogen dioxide (NO), and / or mixtures thereof.

[0018] In some embodiments, the method may further include supplying a second water vapor into the reaction chamber and adjusting the temperature to about 100° C. or higher before or during supply of the water vapor.

[0019] In some embodiments, the method may further include generating etching by-products comprising silicon or phosphorus and removing the etching by-products from the surface of the silicon nitride layer by (i) heating to about 360° C. or higher, (ii) heating to about 100° C. to about 120° C. by reacting with hydrogen fluoride, or (iii) reacting with hydrogen fluoride. The etching by-products include orthosilicic acid or phosphorus pentoxide.

[0020] Another aspect of the present disclosure relates to an apparatus for processing a substrate. The apparatus may include a process chamber for processing the substrate, a pedestal including one or more heating elements for heating the substrate, a gas distribution unit for delivering one or more gaseous reactants to the substrate, and a controller. The controller is configured to control the gas distribution unit to control the flow rate and duration of the one or more gaseous reactants and / or vapors and to control operation of the heating element to control the temperature of the substrate.

[0021] In some embodiments, one or more heating elements may be located on the backside of the substrate.

[0022] In some embodiments, the one or more heating elements may include one or more light emitting diode (LED) units.

[0023] In some embodiments, the one or more heating elements may be configured to increase the substrate temperature by up to about 20° C. / second.

[0024] In some embodiments, the pedestal may be spaced a predetermined distance from the substrate.

[0025] In some embodiments, the pedestal may be in direct contact with the substrate.

[0026] In some embodiments, the one or more gaseous reactants may include water vapor; a first reactant selected from the group consisting of phosphine, diphosphoric acid trioxide (PO), phosphorus trichloride, phosphorus oxychloride, methoxyphosphine, alkyl phosphine halide, trimethylphosphine, triethylphosphine, tripropylphosphine, and / or mixtures thereof; a second reactant selected from the group consisting of oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO), nitrous oxide (NO), nitric oxide (NO), nitrogen dioxide (NO), and / or mixtures thereof; or hydrogen fluoride.

[0027] In some embodiments, the substrate may include a silicon nitride layer.

[0028] These and other aspects are further described below with reference to the drawings. [Brief explanation of the drawings]

[0029] [Figure 1] FIG. 1 is a process flow diagram illustrating thermal atomic layer etching according to some embodiments.

[0030] [Figure 2A] FIG. 2A is a schematic diagram of a reaction chamber for thermal atomic layer etching according to some embodiments.

[0031] [Figure 2B] FIG. 2B is a schematic design diagram illustrating the placement of light sources according to some embodiments.

[0032] [Figure 2C] FIG. 2C is another schematic design diagram illustrating the placement of light sources according to some embodiments.

[0033] [Figure 2D] FIG. 2D is a schematic diagram showing a cross-sectional depiction of a pedestal according to some embodiments.

[0034] [Figure 2E] FIG. 2E is another schematic diagram showing a cross-sectional depiction of a pedestal according to some embodiments.

[0035] [Figure 2F] FIG. 2F is another schematic diagram showing a cross-sectional depiction of a substrate support according to some embodiments.

[0036] [Figure 3A] FIG. 3A is a schematic diagram illustrating a cross-sectional representation of a feature before atomic layer etching in accordance with some embodiments.

[0037] [Figure 3B] FIG. 3B is a schematic diagram illustrating a cross-sectional view of a feature after atomic layer etching in accordance with some embodiments.

[0038] [Figure 4] FIG. 4 is a process flow diagram illustrating thermal atomic layer etching of the features shown in FIGS. 3A-3B. DETAILED DESCRIPTION OF THE INVENTION

[0039] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the presented embodiments. Embodiments of the present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail in order to not unnecessarily obscure the embodiments of the present disclosure. While the embodiments of the present disclosure will be described in conjunction with specific embodiments, it will be understood that they are not intended to limit the embodiments of the present disclosure.

[0040] In this disclosure, the terms “semiconductor wafer,” “wafer,” “substrate,” “semiconductor substrate,” “silicon substrate,” “features on a substrate,” and “features formed on a substrate” are used interchangeably. Those skilled in the art will understand that the term “features on a substrate” can refer to one or more partially fabricated integrated circuits formed on a silicon wafer during any of the many stages of integrated circuit fabrication. Wafers or substrates used in the semiconductor device industry typically have diameters of 200 mm, 300 mm, or 450 mm. The above detailed description assumes that the present disclosure is practiced on a wafer; however, the present disclosure is not so limited. Workpieces may be of various shapes, sizes, and materials. In addition to semiconductor wafers, other workpieces that may utilize the present disclosure include various articles such as printed circuit boards.

[0041] In this disclosure, the terms "depositing" and "forming" are used interchangeably. Also, the terms "layer" and "film" are used interchangeably. Those skilled in the art will understand that "forming" a layer at any of the many stages of integrated circuit fabrication can refer to "depositing" a thin layer by one of a variety of thin film formation methods, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), hot-wire chemical vapor deposition (hot-wire CVD), atomic layer deposition (ALD), or plasma-enhanced atomic layer deposition (PEALD), due to the shrinking size of features in semiconductor devices.

[0042] Introduction and Background

[0043] A method for processing a feature including a silicon nitride layer is provided. The method includes selectively etching the silicon nitride layer in one or more features on a substrate at the nanometer scale. The method includes in-situ generating phosphoric acid on a surface of the silicon nitride layer, followed by selectively removing at least a portion of the silicon nitride layer. The silicon nitride layer may be formed in a variety of deposition processes, such as CVD, PECVD, ALD, or PEALD.

[0044] The semiconductor device may include 3D-NAND, 2D-NAND, DRAM (random access memory), or logic devices. The semiconductor device may include one or more partially fabricated integrated circuits and may include a stack of oxide, nitride, or carbide layers associated with one or more metal elements, or a stack of one or more metal layers, patterned or unpatterned. The patterned substrate may have "features" such as pillars, poles, trenches, vias, or contact holes, which may be characterized by one or more narrow openings and / or recessed openings, constrictions within the feature, or high aspect ratios (HARs). As device density on a substrate increases and individual feature sizes decrease, precise control of the etching process may become important.

[0045] For example, fabrication of high density semiconductor devices requires etching processes that can reliably remove very small amounts of material from features to meet design rules. Etching processes may be designed to provide selectivity over other materials that should not be etched. Additionally, etching processes may be designed to remove material without directionality. This may be particularly critical for small, high aspect ratio features where directional etching may be desirable. Minimizing or preventing feature collapse during etching may also be important for high density semiconductor devices with small, high aspect ratio (HAR) features.

[0046] Etching processes may include wet etching and dry etching. Wet etching is a liquid-based process that can remove portions of features using liquid etching chemistries at appropriate temperatures. For example, wet etching may be performed at temperatures ranging from ambient temperature to 200-300°C, depending on the material being removed. Wet etching may be isotropic. Dry etching may use gaseous etching chemistries, such as oxygen plasma. Dry etching may be more suitable for anisotropic etching.

[0047] One aspect of this embodiment relates to a method for removing at least a portion of a silicon nitride layer on a substrate using phosphoric acid generated in situ by a reaction between water vapor, phosphine, and / or one or more oxidizing agents. Water vapor may be supplied to form one or more monolayers of water molecules adsorbed on the silicon nitride layer. Alternatively, water vapor may be supplied from the atmosphere in the reaction chamber. Phosphine reacts with water to form phosphoric acid in situ. Phosphoric acid may also be generated in situ by hydrating phosphorus oxide (PO), which is generated by reacting phosphine with one or more oxidizing agents. The one or more oxidizing agents may be oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO), nitrous oxide (NO), nitric oxide (NO), nitrogen dioxide (NO), and / or mixtures thereof. Water vapor may then be supplied, and the substrate temperature may be increased to above 100°C to increase the reactivity of the phosphoric acid and the etch rate of the silicon nitride layer.

[0048] Another aspect of the present embodiment relates to a method for selectively etching a portion of a silicon nitride layer on a substrate using phosphoric acid generated in situ by reacting phosphine with one or more oxidizing agents. The one or more oxidizing agents may be oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO), nitrous oxide (NO), nitric oxide (NO), nitrogen dioxide (NO), and / or mixtures thereof. The phosphoric acid may be uniformly formed on the surface of the silicon nitride layer. Adding water vapor to the phosphoric acid may increase the reactivity of the phosphoric acid and the etch rate of the silicon nitride layer. Adjusting the substrate temperature to above 100°C may further increase the etch rate of the silicon nitride layer. The phosphoric acid can selectively etch the silicon nitride layer over adjacent materials such as silicon or silicon oxide.

[0049] Yet another aspect of the present embodiment relates to a method for removing one or more etching byproducts generated during etching of a silicon nitride layer. The etching byproducts may contain silicon and / or phosphorus and may remain on the surface of the silicon nitride layer. Silicon-containing etching byproducts can be removed by reacting them with hydrogen fluoride (HF) at between about 100°C and about 120°C to produce volatile etching byproducts, such as silicon tetrafluoride. Phosphorus-containing etching byproducts can be removed by reacting them with hydrogen fluoride above 100°C or by thermal sublimation above about 360°C, or above about 375°C, or above about 400°C.

[0050] Yet another aspect of the present embodiments relates to a method of etching a silicon nitride layer and then depositing one or more silicon-containing layers on a substrate without breaking vacuum in a reaction chamber or exposing the substrate to an atmospheric atmosphere. The one or more silicon-containing layers may be deposited by CVD, PECVD, ALD, or PEALD.

[0051] The present disclosure also provides semiconductor processing apparatuses for etching semiconductor substrates using thermal energy, for example, rather than or in addition to plasma energy. In various embodiments, the apparatuses described herein are designed or configured to rapidly heat and cool the substrate and to precisely and uniformly control the temperature of the substrate. In some embodiments, the substrate is rapidly heated and its temperature is precisely controlled using a portion of visible light emitted from light-emitting diodes (LEDs) positioned in a pedestal below the substrate. The visible light may have a wavelength ranging from 400 nm to 800 nm. The pedestal may include various features that allow for substrate temperature control, such as a transmissive window that may have a lens to advantageously direct or focus the emitted light, a reflective material to advantageously direct or focus the emitted light, and temperature control elements that assist in temperature control of the LEDs, pedestal, and chamber.

[0052] The apparatus may also thermally isolate, or "float," the substrate within the processing chamber, heating only minimal thermal mass, ideally the substrate itself, allowing for faster heating and cooling. The substrate may be rapidly cooled using cooling gas and / or radiative heat transfer to a heat sink, such as a top plate (or other gas distribution element) above the substrate. In some cases, the apparatus may also include temperature control elements within the processing chamber walls, pedestal, and top plate (or other gas distribution element) to allow for further temperature control of the substrate and processing conditions within the chamber, such as preventing undesired condensation of processing gases and vapors.

[0053] The apparatus may also be configured to implement various control loops (e.g., include a controller configured to execute instructions that cause the apparatus to implement these loops) for accurately controlling the substrate and chamber temperatures. This may include the use of various sensors to determine the substrate and chamber temperatures as part of open-loop and feedback control loops. These sensors may include temperature sensors in the substrate support that contact and measure the substrate temperature, non-contact sensors such as photodetectors that measure the light output of LEDs, and pyrometers configured to measure the temperature of various types of substrates. As described in more detail below, some pyrometers determine the temperature of an object by emitting infrared or other optical signals at the object and measuring the signal reflected or emitted by the object. However, the temperatures of many silicon substrates cannot be measured by some pyrometers because silicon can be optically transparent at various temperatures and due to various processes, such as doped or lightly doped silicon. For example, lightly doped silicon substrates at temperatures below 200°C are transparent to infrared signals. The pyrometers provided herein can measure multiple types of silicon substrates at various temperatures.

[0054] Thermal atomic layer etching

[0055] FIG. 1 is a process flow diagram illustrating a method for performing thermal atomic layer etching on a substrate according to some embodiments. The substrate may include one or more features. The one or more features may include a stack of materials having different chemical compositions. The stack may include alternating layers of materials having different compositions. The one or more features may include a material that is etched and a material that is not etched. In some embodiments, the material that is removed may be silicon nitride. In some embodiments, the material that is not removed may be silicon oxide or silicon. Example applications for thermal atomic layer etching according to some embodiments include features in 2D-NAND, 3D-NAND, DRAM, and logic devices. While FIG. 1 illustrates a method for generating phosphoric acid from phosphine, the method of FIG. 1 is not limiting. It should be understood that any of the phosphorus-containing reactants described herein may be substituted for phosphine and used to generate phosphoric acid.

[0056] The method begins in operation 102 by providing a substrate. The substrate may be provided into a reaction chamber using a transfer tool. Once provided into the reaction chamber, the substrate may be supported on a pedestal. After providing the substrate, an optional cleaning step may be performed. The optional cleaning may remove any oxide layer or undesired material formed on the surface of features on the substrate. In some embodiments, Si oxides undesirably formed on the features or substrate may be reduced by treatment with a chlorine (Cl)-based plasma, a hydrogen fluoride (HF) vapor clean, an ammonium fluoride (NHF) clean, or other reducing agent. One or more features, including one or more layers described herein, may be formed on the substrate before operation 102 by any suitable process, including, but not limited to, CVD, PECVD, ALD, or PEALD. In some embodiments, one or more layers may be adsorbed onto a silicon nitride layer.

[0057] In optional operation 104, the process recipe provides water vapor into the chamber. In some embodiments, a controller and switching system may control the flow rate and duration of the water vapor into the chamber. In some embodiments, the flow rate and duration of the water vapor may be configured to prevent the water vapor from condensing on the surface of the silicon nitride layer. For example, about one to about ten monolayers of water molecules may be adsorbed on the surface of the feature. One or more monolayers of water molecules may be configured to uniformly cover the surface of the feature or the surface of the silicon nitride layer on the substrate.

[0058] Temperature and pressure can affect the amount of absorbed water molecules. For example, the amount of water absorbed into a surface may be inversely proportional to temperature and proportional to pressure. During optional operation 104, the substrate temperature may be between about 0°C and 100°C, or between about 10°C and 50°C, or between about 10°C and 30°C, or about 20°C. In some embodiments, the chamber temperature may be substantially the same as the substrate temperature. In some embodiments, the chamber temperature, the temperature of the substrate, the silicon nitride layer, and / or the water vapor may be configured to be substantially the same as one another. The chamber pressure during operation 104 may be adjusted to between about 1 Torr and 100 Torr, or between about 5 Torr and 50 Torr, or about 10 Torr.

[0059] In operation 106, a phosphorus-containing reactant may be provided. In one example, the phosphorus-containing reactant may be a gaseous reactant. One example may include gaseous phosphine. However, it should be understood that the process flow of FIG. 1 is not limited to phosphine. However, according to some embodiments, other phosphorus-containing reactants may be substituted for phosphine to generate phosphoric acid in situ on the silicon nitride surface. For example, phosphine, diphosphoric acid trioxide (PO), phosphorus trichloride, phosphorus oxychloride, methoxyphosphine, alkyl phosphine halide, trimethylphosphine, triethylphosphine, tripropylphosphine, and / or mixtures thereof may be used as the phosphorus-containing reactant.

[0060] When water vapor is provided to the silicon nitride surface in operation 104, phosphine can react with water to form phosphoric acid (H3PO4) in situ. The reaction of phosphine with water can increase the solubility of phosphine in water, making it easier to form phosphoric acid. By providing water vapor, even if there are no absorbed water molecules on the feature surface, phosphine can still react with water molecules (humidity) in the reaction chamber to form phosphoric acid.

[0061] The amount of phosphoric acid produced from the reaction with water may depend, for example, on the relative amount of water in the chamber atmosphere to the amount of phosphine. In some embodiments, some of the phosphine may be consumed to react with water in the chamber atmosphere to produce phosphoric acid, while some of the phosphine may still remain unreacted on the surface of the feature. For example, depending on the amount of phosphine, excess phosphine may not react with water and may remain unreacted on the surface of the silicon nitride layer. Thus, a mixture of phosphine and phosphoric acid may be present on the surface of the silicon nitride layer. In some embodiments, the substrate temperature and chamber pressure during operation 106 may be substantially the same as in operation 104. For example, the substrate temperature in operation 106 may be between about 0° C. and 100° C., or between about 0° C. and 50° C., or between about 10° C. and 30° C., or about 20° C. The chamber pressure in operation 106 may be adjusted to between about 1 Torr and 100 Torr, or between about 5 Torr and 50 Torr, or about 10 Torr.

[0062] In operation 108, one or more oxidizing agents may be supplied into the reaction chamber. The oxidizing agents may react with phosphine at the surface of the silicon nitride layer where unreacted phosphine remains. The phosphine may be oxidized by the one or more oxidizing agents to form phosphorus oxide (PO). The PO may be hydrated by water that may be present at or near the silicon nitride surface to produce phosphoric acid in situ. Examples of oxidizing agents include oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO), nitrous oxide (NO), nitric oxide (NO), nitrogen dioxide (NO), and / or mixtures thereof.

[0063] While operations 106 and 108 can be performed sequentially as described, it should be understood that operations 106 and 108 may be performed simultaneously or substantially simultaneously. In an example, phosphine and ozone (or oxygen or other oxidizing agent) may be co-flowed into the chamber through a fluid inlet. The phosphine may react with water (from the reaction chamber atmosphere or water vapor supplied to the substrate surface in optional operation 104) to produce phosphoric acid in situ. Simultaneously or substantially simultaneously, unreacted phosphine may be oxidized and hydrated by the oxidizing agent to form phosphoric acid. The substrate temperature and chamber pressure during operation 108 may be maintained substantially the same as the substrate temperature and chamber pressure in operations 104 and / or 106.

[0064] In operation 110, water vapor may be supplied into the reaction chamber. In some embodiments, the flow rate and duration of the water vapor may be configured to prevent condensation of the water vapor on the features. Providing additional water vapor in operation 110 may increase the concentration and / or reactivity of the phosphoric acid. Thus, the etch rate of the silicon nitride layer in operation 110 may be greater than the etch rate in operations 106 and / or 108. The substrate temperature and chamber pressure during operation 110 may be maintained substantially the same as the substrate temperature and chamber pressure in operations 104-108.

[0065] In operation 112, the substrate temperature may be increased to greater than 100° C., or between about 100° C. and about 180° C., or between about 120° C. and about 180° C. In some embodiments, the substrate temperature may be configured to be increased before the start of operation 112. Increasing the substrate temperature in operation 112 may increase the etch rate of the silicon nitride. A faster ramp rate in operation 112 may result in a more uniform nitride etch. For example, the substrate temperature may be configured to increase at a ramp rate of about 20° C. / sec. Thus, operation 112 may include substantially etching the silicon nitride layer. The etch rate of the silicon nitride layer in operation 112 may be significantly greater than the etch rate in other operations. For example, most or substantially all of the etching process may be performed in operation 112. One or more etch byproducts may be generated during the nitride etch in operation 112. The one or more etch byproducts may include silicon or phosphorus, which may be non-volatile. The pressure in operation 112 may be configured to range from about 1 Torr to about 100 Torr.

[0066] Nitride etching according to some embodiments may be a dry etching process performed by supplying gaseous and / or vapor reactants to the surface of a silicon nitride layer in a feature. The silicon nitride layer is etched by exposing the silicon nitride layer to in-situ generated phosphoric acid. The phosphoric acid may be generated in-situ through a combination of different reaction routes. For example, water vapor in operation 104 can increase the solubility of phosphine (or other phosphorus-containing reactant) provided in operation 106, generating phosphoric acid in-situ. Phosphoric acid may be generated by hydrating phosphorus oxide (PO), which is formed by reacting phosphine (or other phosphorus-containing reactant) with one or more oxidizing agents. In either route, the generated phosphoric acid may include gaseous etching chemicals. Thus, phosphoric acid according to some embodiments may uniformly cover and adsorb to the surface of a feature without providing excessive etching chemicals in localized areas on the substrate. This is particularly advantageous for semiconductor devices that contain denser and smaller sized features, where non-uniform and excessive etching chemistries can result in non-uniform etch rates, compromise the structural stability of the features, and increase the probability of device failure.

[0067] In operation 114, one or more etch by-products may be removed by a thermal process or a combination of chemical and thermal processes. In one example, orthosilicic acid (Si(OH)4) may be present on the surface of silicon nitride as an etch by-product. Si(OH)4 may be non-volatile. The Si(OH)4 on the substrate may be heated to above about 100°C, or above 120°C, or between about 100°C and about 120°C, or above 130°C, or above 140°C, or above 150°C when reacting with hydrogen fluoride (HF) vapor. Because HF does not react with silicon oxide at elevated temperatures in the absence of moisture, this combination of chemical and thermal processes can produce volatile silicon tetrafluoride (SiF4) without substantially reacting with other adjacent materials, such as silicon or silicon oxide (SiO2).

[0068] In another example, excess phosphoric acid may remain on the surface of the silicon nitride layer without being completely consumed in operations 106-112. The substrate may be heated to above 100°C to remove any water molecules from the phosphoric acid, leaving P2O5 on the substrate surface. HF vapor may be supplied to the P2O5 to form a volatile phosphorus-containing by-product, such as phosphorus pentafluoride (PF5). Alternatively, the P2O5 may be removed by sublimation without the aid of HF or other reducing agents. P2O5 may have a boiling point of approximately 350-360°C. Further heating the substrate with the remaining P2O5 to above approximately 360°C, or above approximately 375°C, or above approximately 400°C may sublimate the P2O5 from the feature and remove it from the feature. The duration of the sublimation may range from approximately 5 seconds to approximately 600 seconds.

[0069] After operation 114 is completed, the device design may determine whether to further etch the feature or substrate containing the silicon nitride layer. If further etching of the silicon nitride layer may be required, operations 104-114 (or operations 106-114) may be repeated until the desired etching is achieved. For example, the number of cycles of etching the nitride atomic layers may depend on the dimensions of the feature, such as the depth of the silicon nitride layer within the stack.

[0070] After operation 114, subsequent processes may optionally be performed. For example, as described herein, one or more silicon-containing layers may be deposited after etching byproducts are removed from the silicon nitride surface. The one or more silicon-containing layers may be formed in a suitable deposition process, such as CVD, PECVD, ALD, PEALD, or any other deposition technique. In another example, another substrate may be transferred to the reaction chamber for etching the silicon nitride layer. It should be noted that the reaction chamber may be configured to deposit one or more layers of oxide, nitride, carbide, oxynitride, oxycarbide, or oxycarbide associated with one or more metal elements, or one or more metal layers, or may be configured to selectively etch at least a portion of a layer deposited prior to the selective etching, without breaking vacuum or exposing the substrate to ambient atmosphere.

[0071] Device

[0072] 2A shows a cross-sectional side view of an exemplary apparatus 200 according to some embodiments, which, as described in detail below, is capable of rapidly and precisely controlling the temperature of a substrate, including performing thermal etching operations, such as the Prevos® selective etching tool manufactured by Lam Research Corporation of Fremont, California.

[0073] The apparatus 200 includes a processing chamber 202, a pedestal 204 having a plurality of substrate supports 208 configured to support a substrate 218, and a gas distribution unit 210. The processing chamber 202 includes a sidewall 212A, a top surface 212B, and a bottom surface 212C that at least partially define a chamber interior 214, which may be considered a plenum volume. As discussed herein, in some embodiments, it may be desirable to actively control the temperature of the processing chamber walls 212A, top surface 212B, and bottom surface 212C to prevent undesired condensation on those surfaces. In some emerging semiconductor processing operations, vapors, such as water vapor and / or alcohol vapor, are flowed over and adsorb onto the substrate, but may also undesirably adsorb onto the interior surfaces of the chamber. This can result in undesired deposition and etching on the interior chamber surfaces, damage to the chamber surfaces, and flaking of particles onto the substrate, which can cause defects in the substrate. To reduce and prevent unwanted condensation on the interior surfaces of the chamber, the temperatures of the chamber walls, top, and bottom may be maintained at temperatures that do not result in condensation of chemicals used in processing operations.

[0074] This active temperature control of the chamber surfaces can be achieved by using heaters to heat the chamber walls 212A, top surface 212B, and bottom surface 212C. As shown in FIG. 2A , chamber heater 216A is positioned on chamber wall 212A and configured to heat chamber wall 212A, chamber heater 216B is positioned on top surface 212B and configured to heat top surface 212B, and chamber heater 216C is positioned on bottom surface 212C and configured to heat bottom surface 212C. Chamber heaters 216A-216C may be resistive heaters configured to generate heat when an electric current flows through a resistive element. Chamber heaters 216A-216C may also be fluid conduits through which a heat transfer fluid, such as a heating fluid that may include heated water, can flow. In some cases, chamber heaters 216A-216C may be a combination of both a heating fluid and a resistive heater. The chamber heaters 216A-216C may be configured to generate heat to bring the interior surfaces of the chamber walls 212A, top surface 212B, and bottom surface 212C to a desired temperature, which may range from about 40°C to about 400°C, about 40°C to about 250°C, or about 40°C to about 150°C, such as about 80°C to about 130°C, about 90°C, or about 120°C. It has been found that under some conditions, water vapor and alcohol vapor do not condense on surfaces maintained at about 90°C or above. Although not shown in FIG. 2A , the chamber heaters 216A-216C may include one or more temperature sensors operably coupled to the chamber heaters 216A-216C to monitor the chamber temperature.

[0075] The chamber walls 212A, top surface 212B, and bottom surface 212C may also be constructed of various materials that can withstand the chemicals used in processing techniques. These chamber materials may include, for example, aluminum, anodized aluminum, aluminum with a polymer such as plastic, a metal or metal alloy with a yttria coating, a metal or metal alloy with a zirconia coating, and a metal or metal alloy with an aluminum oxide coating. In some cases, the coating materials may be mixed or may be layers of different material combinations, such as alternating layers of aluminum oxide and yttria or aluminum oxide and zirconia. These materials are configured to withstand the chemicals used in processing techniques, such as anhydrous HF, water vapor, methanol, isopropyl alcohol, chlorine, fluorine gas, nitrogen gas, hydrogen gas, helium gas, and / or mixtures thereof.

[0076] Additionally, the apparatus 200 may be configured to perform processing operations at vacuum or near-vacuum conditions, such as pressures of about 0.1 Torr to about 100 Torr, about 20 Torr to about 200 Torr, about 0.1 Torr to about 10 Torr, or about 10 Torr. The apparatus 200 may also include a vacuum pump 284 configured to provide a low pressure to the chamber interior 214, such as a vacuum having a pressure of about 0.1 Torr to about 100 Torr, including about 0.1 Torr to about 10 Torr, about 20 Torr to about 200 Torr, about 0.1 Torr to about 10 Torr, or about 10 Torr.

[0077] Various features of the pedestal 204 will now be described. The pedestal 204 includes a heater 222 (enclosed in FIG. 2A by a dashed rectangle) having a plurality of LEDs 224 configured to emit visible light having wavelengths between 400 nm and 800 nm, including 450 nm. The heater LEDs emit this visible light toward the backside of the substrate to heat it. Because silicon absorbs visible light having wavelengths between approximately 400 nm and 800 nm, visible light having wavelengths between approximately 400 nm and 800 nm can quickly and efficiently heat a silicon substrate from ambient temperatures, e.g., about 20° C., to temperatures as high as approximately 600° C. In contrast, radiative heating, including infrared radiative heating, may not efficiently heat silicon at temperatures up to approximately 400° C. because silicon tends to be transparent to infrared light below approximately 400° C. Furthermore, as in many conventional semiconductor processes, radiative heaters that directly heat the top surface of the substrate can damage or otherwise adversely affect films on the top surface. Many "hot plate" heaters that rely on solid-state heat transfer between the substrate and a heated platen, such as a pedestal with a heating coil, have relatively slow heating and cooling rates, resulting in uneven heating that can occur due to substrate warping and uneven contact with the heated platen. For example, it may take several minutes to heat some pedestals to a desired temperature, and then to heat them from a first temperature to a second, higher temperature, as well as to cool the pedestal to a lower temperature.

[0078] The heater's multiple LEDs can be arranged, electrically connected, and electrically controlled in a variety of ways. Each LED may be configured to emit blue and / or white visible light. In certain embodiments, white light (generated using a wavelength range in the visible portion of the EM spectrum) is used. In some semiconductor processing operations, white light can reduce or prevent unwanted thin-film interference. For example, some substrates have backside films that reflect different light wavelengths in varying amounts, which can result in uneven and inefficient heating. Using white light can reduce this variability in unwanted reflection by averaging out the thin-film interference across the broad visible spectrum that white light introduces. In some cases, depending on the substrate backside material, it may be advantageous to use non-white visible light, such as blue light having a wavelength of 450 nm, to provide a single or narrow band of wavelengths that can result in more efficient, intense, and directed heating for some substrates that may absorb narrow bands of wavelengths better than white light.

[0079] Various types of LEDs may be employed. Examples include chip-on-board (COB) LEDs or surface-mount diode (SMD) LEDs. In the case of SMD LEDs, the LED chip may be fused to a printed circuit board (PCB), which may have multiple electrical contacts that allow control of each diode on the chip. For example, a single SMD chip may have three diodes (e.g., red, blue, or green) that can be individually controlled and produce various colors. SMD LED chip sizes may range from 2.8 x 2.5 mm, 3.0 x 3.0 mm, 3.5 x 2.8 mm, 5.0 x 5.0 mm, and 5.6 x 3.0 mm. In the case of COB LEDs, each chip may have more than three diodes, such as nine, twelve, dozens, hundreds, or more, printed on the same PCB. COB LED chips typically have one circuit and two contacts, regardless of the number of diodes, resulting in a simple design and efficient monochromatic applications. The ability and performance of the LEDs to heat the substrate can be measured by the wattage of heat emitted by each LED, and these wattages of heat can be directly contributed to heating the substrate.

[0080] FIG. 2B shows a top view of a substrate heater with multiple LEDs. The substrate heater 222 includes a printed circuit board 226 and multiple LEDs 224, some of which are labeled, with approximately 1,300 LEDs in this illustration. External connections 228 are connected by traces to provide power to the multiple LEDs 224. As shown in FIG. 2B, the LEDs may be arranged along multiple arcs radially offset at different radii from a center 230 of the substrate heater 222, and within each arc, the LEDs may be equally spaced from one another. For example, one arc 232 is surrounded by a partially shaded, dotted-line shape, includes 16 LEDs 224, and is a portion of a circle having a radius R extending around the center 230. The 16 LEDs 224 may be considered to be equally spaced from one another along this arc 232.

[0081] Also, in some embodiments, the LEDs may be arranged along a circle around the center of the substrate heater. In some cases, some LEDs may be arranged along a circle, while other LEDs may be arranged along an arc. FIG. 2C shows a top view of another example substrate heater with multiple LEDs. The substrate heater 222 in FIG. 2C includes a printed circuit board 226 and multiple LEDs 224, some of which are labeled. Here, the LEDs 224 may be arranged along multiple circles radially offset at different radii from the center 230 of the substrate heater 222, and within each circle, the LEDs may be equally spaced from one another. For example, one circle 234 is surrounded by a partially shaded ring, includes 78 LEDs 224, and has a radius R extending around the center 230. The 78 LEDs 224 may be considered to be equally spaced from one another along this circle 234. The area of ​​the substrate heater 222 in FIG. 2B that includes external connections may result in unheated cold spots on the substrate, and the arrangement of LEDs in FIG. 2C may provide a more uniform light and heat distribution pattern across the backside of the substrate compared to the arrangement in FIG. 2B, particularly because the substrate and heater remain stationary relative to each other during processing and the substrate and substrate heater do not rotate.

[0082] In some embodiments, the plurality of LEDs may include at least about 1,000 LEDs, including, for example, more than about 1,200, 1,500, 2,000, 3,000, 4,000, 5,000, or 6,000. Each LED may optionally be configured to use about 4 watts or less at 100% power, including about 3 watts at 100% power and about 1 watt at 100% power. The LEDs may be arranged and electrically connected into individually controllable zones to allow for temperature adjustment and fine-tuning across the substrate. In some cases, the LEDs may be grouped into at least 20 zones, e.g., independently controllable zones, including, for example, at least about 25, 50, 75, 80, 85, 90, 95, or 100 zones. These zones may allow for temperature adjustment in the radial and azimuthal (i.e., angular) directions. These zones can be arranged in a defined pattern, such as a rectangular grid, a hexagonal grid, or other suitable pattern to generate a desired temperature profile. The zones can also have various shapes, such as squares, trapezoids, rectangles, triangles, orb rounds, ellipses, circles, annular (e.g., rings), partial annular (e.g., annular sectors), arcs, segments, and sectors centered around the heater and having a radius equal to or less than the full radius of the PCB of the substrate heater. For example, in FIG. 2B, the LEDs may have 88 zones and be configured with at least 20, such as 20 or 21, concentric rings. These zones allow for temperature adjustment at multiple locations across the substrate, creating desired temperature profiles, such as more uniform temperature distribution and higher temperatures around the edge of the substrate than the center of the substrate. Independent control of these zones can also include the ability to control the power output of each zone. For example, each zone may have at least 15, 20, or 25 adjustable power outputs. In some cases, each zone may have one LED, which may allow each LED to be individually controlled and tuned, resulting in a more uniform heating profile on the substrate. Thus, in some embodiments, each LED of multiple LEDs in a substrate heater may be individually controllable.

[0083] In certain embodiments, the substrate heater 222 is configured to heat the substrate to multiple temperatures and maintain each such temperature for various durations. The substrate heater may be configured to heat the substrate to between about 50° C. and about 600° C., including any temperature or range between about 50° C. and about 600° C. Furthermore, in some embodiments, the substrate heater 222 is configured to heat the substrate to any temperature within, for example, less than about 60 seconds, less than about 45 seconds, less than about 30 seconds, or less than about 15 seconds. In certain embodiments, the substrate heater 222 is configured to heat the substrate at one or more heating rates, for example, between at least about 0.1° C. / second and at least about 20° C. / second.

[0084] The substrate heater may increase the temperature of the substrate by causing the LEDs to emit visible light at one or more power levels, including at least about 80%, at least about 90%, at least about 95%, or at least about 100% power. In some embodiments, the substrate heater is configured to emit light between about 10 W and 4000 W, including at least about 10 W, at least about 30 W, at least about 0.3 kilowatts (kW), at least about 0.5 kW, at least about 2 kW, at least about 3 kW, or at least about 4 kW. The apparatus is configured to provide between about 0.1 kW and 9 kW of power to the pedestal, and a power supply (not shown) is connected to the substrate heater through the pedestal. During the temperature ramp, the substrate heater may operate at a high power or at a lower power level (e.g., between about 5 W and about 0.5 kW) to maintain the temperature of the heated substrate.

[0085] The pedestal may include a reflective material on its inner surface that, during operation, reflects and directs light emitted by the LEDs toward the backside of the substrate supported by the pedestal. In some such embodiments, the substrate heater may include such a reflective material positioned on the top surface 240, as shown in FIG. 2A , of the PCB 226 on which the plurality of LEDs 224 are positioned. The reflective material may be composed of aluminum, such as polished aluminum, stainless steel, aluminum alloys, nickel alloys, and other protective layers that may prevent oxidation of the metal and / or increase reflectivity at certain wavelengths, such as greater than 99% reflectivity for certain wavelengths, and other durable reflective coatings. Additionally or alternatively, the pedestal 204 may have a bowl 246 in which the substrate heater 222 is at least partially positioned. The bowl 246 may have an exposed inner surface 248 of the pedestal sidewall 249 on which the reflective material may be positioned. This reflective material increases the heating efficiency of the substrate heater and reduces unwanted heating of the PCB 226 and pedestal 204 by advantageously redirecting light that would otherwise be absorbed by the PCB 226 and pedestal 204 back onto the substrate.

[0086] In some embodiments, the substrate heater may also include a pedestal cooler thermally connected to the LEDs, such that heat generated by the LEDs can be transferred from the LEDs to the pedestal cooler. This thermal connection is such that heat can be transferred from the LEDs to the pedestal cooler along one or more heat flow paths between these components. In some cases, the pedestal cooler is in direct contact with one or more elements of the substrate heater, while in other cases, another conductive element, such as a heat transfer plate (e.g., constructed of metal), is interposed between the substrate heater and the pedestal cooler. Referring again to FIG. 2A , the substrate heater includes a pedestal cooler 236 in direct contact with the bottom surface of the PCB 226. Heat is configured to flow from the LEDs to the PCB 226 and to the pedestal cooler 236. The pedestal cooler 236 also includes a plurality of fluid conduits 238 configured to carry a heat transfer fluid, such as water, to receive heat and thereby cool the LEDs in the substrate heater 222. The fluid conduit 238 may be connected to a reservoir and pump, not shown, located outside the chamber. In some cases, the pedestal cooler may be configured to flow water that is cooled, such as to between about 5°C and 20°C.

[0087] As provided herein, it may be advantageous to actively heat the exterior surface of the processing chamber 202. In some cases, it may likewise be advantageous to heat the exterior surface of the pedestal 204 to prevent undesired condensation and deposition thereon. As shown in FIG. 2A , the pedestal 204 may further include a pedestal heater 244 configured to heat the exterior surface of the pedestal 204, including the side surface 242A and bottom surface 242B of the pedestal 204. The pedestal heater 244 may include one or more heating elements, such as one or more resistive heating elements, and a fluid conduit configured to carry a heated fluid. In some cases, both the pedestal cooler and the pedestal heater may have fluid conduits fluidly connected to each other, allowing the same heat transfer fluid to flow through both the pedestal cooler and the pedestal heater. In these embodiments, the fluid may be heated to between 50°C and 130°C, including between approximately 90°C and 120°C.

[0088] The pedestal may also include a window to protect the substrate heater, including the plurality of LEDs, from damage caused by exposure to the processing chemicals and pressures used during processing operations. As shown in FIG. 2A , the window 250 may be positioned above the substrate heater 222, and the window 250 may be sealed to the sidewall 249 of the pedestal 204, creating a plenum volume within the pedestal that is fluidly isolated from the chamber interior. This plenum volume may also be considered the interior of the bowl 246. The window may be composed of one or more materials that are optically transparent to visible light emitted by the LEDs, including light having wavelengths in the range of 400 nm to 800 nm. In some embodiments, this material may be quartz, sapphire, quartz with a sapphire coating, or calcium fluoride (CaF). The window may also be free of any holes or openings therein. In some embodiments, the heater may have a thickness of about 15 to about 30 mm, including about 20 mm to about 25 mm.

[0089] 2D illustrates the pedestal of FIG. 2A with additional features according to various embodiments. As identified in FIG. 2D , window 250 includes a top surface 252 facing substrate 218 supported by pedestal 204 and a bottom surface 254 facing substrate heater 222. In some embodiments, top surface 252 and bottom surface 254 may be flat, planar (or substantially flat, e.g., within ±10% or 5% planar). In some other examples, top surface 252, bottom surface 254, or both top surface 252 and bottom surface 254 may be non-planar. The non-planarity of these surfaces may be configured to refract and / or direct light emitted by LEDs 224 of substrate heater 222 to heat the substrate more efficiently and / or effectively. Additionally, the non-planarity may be along some or all of the surface. For example, the entire bottom surface may have a convex or concave curvature, while in another example, an outer annular region of the bottom surface may have a convex or concave curvature while the remainder of the surface is planar. In a further example, the surfaces may have multiple non-planar sections, but may have various non-planar sections, such as a conical section in the center of the surface, which is adjacent to a planar annular section that is adjacent to a frustum surface at the same or a different angle as the conical section. In some embodiments, window 250 may have features that function as an array of lenses oriented to focus light emitted by one or more LEDs, such as each LED.

[0090] When the window 250 is positioned above the substrate heater 222, it can be heated by the substrate heater 222 and affect the thermal environment surrounding the substrate. Depending on the material or materials used for the window 250, such as quartz, the window may retain heat and gradually retain more heat over the course of processing one or more substrates. This heat can be transferred radially to the substrate, thus directly heating it. In some cases, the window can generate a temperature rise between 50°C and 80°C higher than the heater temperature. This heat can also create a temperature gradient across or vertically through the window. In some cases, the top surface 252 can be 30°C hotter than the bottom surface 254. Therefore, it can be advantageous to adjust and configure the chamber to account for and reduce the thermal effects of the window. This may include sensing the temperature of the substrate and adjusting the substrate heater to account for the heat retained by the window.

[0091] This may also include various configurations of the pedestal, such as actively cooling the window. In some embodiments, as shown in FIGS. 2A and 2D , the window 250 may be offset from the substrate heater 222 by a first distance 256. In some embodiments, this first distance may be between about 2 mm and 50 mm, including between about 5 mm and 40 mm. A cooling fluid, such as an inert gas, may be flowed between the window 250 and the substrate heater 222 to cool both the window 250 and the substrate heater 222. The pedestal may have one or more inlets and one or more outlets for flowing this gas into the plenum volume, i.e., bowl 246, of the pedestal 204. The one or more inlets may be fluidly connected to an inert gas source outside the processing chamber 202, and the one or more inlets may include fluid conduits that may run at least partially through the interior of the pedestal 204. The one or more outlets may be fluidly connected to an exhaust or other environment outside the processing chamber 202, and the one or more outlets may be fluid conduits that run through the pedestal. 2E, which shows the pedestal of FIG. 2D with additional features according to various embodiments, one or more inlets 251 are positioned in the sidewall 249 and extend through the inner surface 248, and the one or more inlets are fluidly connected to a gas source 272 (e.g., an inert gas source) through a portion of a fluid conduit 255 that runs through the pedestal 204. A single outlet 253 is positioned near a central region of the substrate heater 222, i.e., not exactly at the center. In some embodiments, the one or more gas inlets and one or more outlets may be switched, with one or more outlets extending through the sidewall 249 (i.e., the one or more outlets are item 251 in FIG. 2E) and one or more inlets in the central region of the substrate heater 222 (i.e., the one or more inlets are item 253 in FIG. 2E). In some embodiments, there may be multiple outlets, and in some embodiments, there may be only a single gas inlet. In some embodiments, one or more gas inlets extend through the inner surface 248 of the pedestal sidewall 249 below the LED heater 222, and one or more gas outlets extend through another portion of the pedestal sidewall 249, such as a mounting bracket between the LED heater 222 and the pedestal sidewall 249.

[0092] In some embodiments, the window may be placed in direct thermal contact with the substrate heater, and a pedestal cooler may be configured to cool both the PCB and the window. In some embodiments, as also shown in FIGS. 2A and 2D , the window 250 may be thermally connected to a sidewall 249 of the pedestal 204 to transfer a portion of the heat retained in the window 250 to the pedestal 204. This transferred heat may be further transferred out of the pedestal 204 using, for example, a pedestal heater 244, which may flow a fluid heated to, for example, between about 20° C. and 100° C. into the pedestal 204. This heated fluid may be at a lower temperature than the temperature of the pedestal 204 at the thermal connection with the window 250. In some embodiments, the window 250 may have one or more fluid conduits configured to flow a transparent cooling fluid through the window 250. The fluid may be delivered from a fluid source or reservoir outside the chamber through the pedestal and to the window.

[0093] As shown in Figures 2A and 2D, the substrate support 208 of the pedestal 204 is configured to support the substrate 218 above and offset from the window 250 and the substrate heater 222. In certain embodiments, the substrate is thermally suspended, or thermally isolated, within the chamber, allowing for rapid and accurate control of the substrate temperature. It is desirable to position the substrate so that minimal thermal mass is heated and cooled. This thermal suspension is configured to position the substrate so that it has minimal thermal contact (including direct and radiative) with other objects within the chamber.

[0094] Thus, in some embodiments, the pedestal 204 is configured to support the substrate 218 by thermally floating or thermally isolating the substrate within the chamber interior 214. The multiple substrate supports 208 of the pedestal 204 are configured to support the substrate 218 in a manner that reduces the thermal mass of the substrate 218 to as little as possible of the thermal mass of the substrate 218 alone. Each substrate support 208 may have a substrate support surface 220 that minimizes contact with the substrate 218. The number of substrate supports 208 may range from at least three to, for example, at least six or more. Additionally, the surface area of ​​the support surface 220 may be the minimum area required to adequately support the substrate during processing operations (e.g., to support the weight of the substrate and prevent inelastic deformation of the substrate).

[0095] The substrate support is also configured to prevent the substrate from contacting other elements of the pedestal, including the surface of the pedestal and features below the substrate. As can be seen in FIGS. 2A and 2D , the substrate support 208 holds the substrate 218 above and offsets it from the next adjacent surface of the pedestal 204 below the substrate 218, which is at the top surface 252 of the window 250 (identified in FIG. 2D ). As can be seen from these figures, a volume or gap exists below the substrate, excluding contact with the substrate support. As shown in FIG. 2D , the substrate 218 is offset from the top surface 252 of the window 250 by a distance 258. This distance 258 can affect the thermal effect the window 250 has on the substrate 218. The greater the distance 258, the less the effect. It has been found that distance 258 of 2 mm or less results in significant thermal coupling between the window and the substrate. Therefore, it is desirable for the distance 258 to be greater than 2 mm, such as, for example, at least about 5 mm, about 10 mm, about 15 mm, about 20 mm, about 30 mm, about 50 mm, or about 100 mm.

[0096] Additionally, the substrate 218 is offset from the substrate heater 222 by a distance 260 (measured from the top surface of the substrate heater 222, which may in some cases be the top surface of the LEDs 224). This distance 260 affects many aspects of the heating of the substrate 218. In some embodiments, a distance 260 of between about 10 mm and about 90 mm, between about 5 mm and about 100 mm, including, for example, between about 10 mm and about 30 mm, provides a substantially uniform heating pattern and acceptable heating efficiency.

[0097] As previously described, the substrate supports 208 are configured to support the substrate 218 above the window. In some embodiments, these substrate supports are stationary and have a fixed position. That is, the substrate supports are not lift pins or support rings. In some embodiments, at least a portion of each substrate support 208, including the support surface 220, may be constructed from a material that is at least transparent to the light emitted by the LEDs 224. This material may be quartz or sapphire in some cases. The transparency of these substrate supports 208 allows visible light emitted by the LEDs 224 in the substrate heater 222 to pass through the substrate supports 208 and reach the substrate 218, thereby allowing the substrate supports 208 to unobstruct the light and heat the substrate 218 within the region where the substrate 218 is supported. This allows for more uniform heating of the substrate 218 than substrate supports constructed from a material that is opaque to visible light. In some other embodiments, the substrate supports 208 may be constructed from a non-transparent material, such as zirconium dioxide (ZrO).

[0098] In some embodiments, the pedestal may be configured to directly support a substrate (not shown). The pedestal may include lift pins or other movable support members configured to position the substrate within a deposition zone in the substrate's environment. The substrate may move vertically within the chamber. In some embodiments, the pedestal includes an electrostatic chuck. The electrostatic chuck may be on top of the pedestal and may include one or more electrostatic clamping electrodes embedded in the body of the electrostatic chuck. The substrate may be supported on an upper surface of the electrostatic chuck. In some embodiments, the one or more electrostatic clamping electrodes may be coplanar or substantially coplanar. The electrostatic clamping electrodes may be powered by a DC power supply or a DC chucking voltage (e.g., between about 200 V and about 2000 V), which may hold the substrate on the electrostatic chuck by electrostatic attraction. Power to the electrostatic clamping electrodes may be supplied via a first electrical line connected to the electrostatic clamping electrodes. The electrostatic chuck may further include one or more heating elements embedded in the body of the electrostatic chuck. The one or more heating elements may include resistive heaters. In some embodiments, one or more heating elements are positioned below the one or more electrostatic clamping electrodes. The one or more heating elements may be configured to heat the substrate to a temperature greater than about 200°C, greater than about 450°C, greater than about 500°C, greater than about 550°C, greater than about 600°C, or greater than about 650°C. The one or more heating elements provide selective temperature control for the substrate. Power to the one or more heating elements may be supplied via a second electrical line connecting the one or more heating elements to a power source.

[0099] 2D , the substrate supports 208 may be positioned closer to the central axis 262 of the window 250 than to the outer diameter 264 of the window 250. In some cases, portions of these substrate supports may extend across and above the window 250.

[0100] In some embodiments, the substrate supports may each include a temperature sensor configured to detect the temperature of a substrate positioned on the support surface of the substrate support. FIG. 2F illustrates the substrate support of FIGS. 2A and 2D according to an embodiment of the present disclosure. Here, the support surface 220 of the substrate support 208 is identified along with a temperature sensor 266. In some embodiments, the temperature sensor 266 extends through the support surface 220 such that the temperature sensor 266 is in direct contact with a substrate held by the support surface 220. In some other embodiments, the temperature sensor 266 is positioned within the substrate support 208 below the support surface 220. In some embodiments, the temperature sensor 266 is a thermocouple. In some other embodiments, the temperature sensor 266 may be a thermistor, a resistance temperature detector (RTD), or a semiconductor sensor. Electrical wiring 268 for the temperature sensor 266 may be routed through the substrate support 208 and may also be routed through the pedestal 204.

[0101] 2A , in some embodiments, the pedestal is also configured to move vertically. This may include moving the pedestal such that the gap 286 between the faceplate 276 of the gas distribution unit 210 and the substrate 218 can be within a range of approximately 2 mm to 70 mm. Because of the small volume created between the gas distribution unit 210 and the substrate 218, moving the pedestal vertically may enable active cooling of the substrate as well as faster cycle times for processing operations, including venting and purging. This movement may also create a small process volume between the substrate and the gas distribution unit, resulting in smaller purge and process volumes, which in turn may reduce purge and gas transfer times and increase throughput.

[0102] The gas distribution unit 210 is configured to flow a process gas, which may include liquids and / or gases, such as reactants, modifier molecules, transformation molecules, or removal molecules, over a substrate 218 in the chamber interior 214. In some embodiments, the process gas may include phosphine. In some embodiments, the process gas may include hydrogen fluoride (HF), oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO), nitrous oxide (NO), nitric oxide (NO), nitrogen dioxide (NO), or combinations thereof. As can be seen in FIG. 2A , the gas distribution unit 210 includes one or more fluid inlets 270 fluidly connected to one or more gas sources 272 and / or one or more vapor sources 274. The gas distribution unit 110 and other units or components that may be in fluid contact with the process gas may be designed and fabricated to be chemically resistant or chemically inert to the process gas. In some embodiments, the gas lines and mixing chamber may be heated to prevent undesired condensation of vapors and gases flowing therethrough. The lines may be heated to at least about 40°C, at least about 80°C, at least about 90°C, at least about 100°C, at least about 120°C, at least about 130°C, or at least about 150°C. The one or more vapor sources may include one or more sources of gas and / or liquid to be vaporized. In some embodiments, the one or more sources of gas and / or liquid include water vapor, alcohol (including, but not limited to, methyl alcohol, ethyl alcohol, isopropyl alcohol, butyl alcohol), diphosphate trioxide (PO), phosphorus trichloride, phosphorus oxychloride, methoxyphosphine, alkyl phosphine halide, trimethylphosphine, triethylphosphine, tripropylphosphine, and / or mixtures thereof. In some embodiments, the one or more sources of gas and / or liquid may be provided by a vaporizer as a fine spray without heating the one or more sources of gas and / or liquid to an elevated temperature.In some embodiments, one or more sources of gas and / or liquid may be further diluted with one or more appropriate solvents or liquids designed for atomization. Vaporization may be via a direct injection vaporizer, a flow-over vaporizer, or both. In some embodiments, one or more vapor sources and one or more process gases may be configured to operate sequentially or simultaneously. For example, one vapor source, such as water vapor, and one process gas, such as phosphine, may be supplied sequentially or simultaneously to the interior of the reaction chamber. The gas distribution unit 210 also includes a faceplate 276 including a plurality of through-holes 278 that fluidly connect the gas distribution unit 210 to the chamber interior 214. These through-holes 278 extend through a front surface 277 of the faceplate 276, which is fluidly connected to one or more fluid inlets 270 and is configured to face the substrate 218. In some embodiments, the gas distribution unit 210 may be considered a top plate, and in some other embodiments, it may be considered a showerhead.

[0103] The through-holes 278 may be configured in various ways to deliver a uniform flow of gas to the substrate. In some embodiments, the through-holes may all have the same outer diameter, such as between about 0.03 inches and 0.05 inches, including about 0.04 inches (1.016 mm). The faceplate through-holes may also be distributed across the faceplate to create a uniform flow from the faceplate.

[0104] 2A , the gas distribution unit 210 may also include a unit heater 280 thermally connected to the faceplate 276, thereby allowing heat to be transferred between the faceplate 276 and the unit heater 280. The unit heater 280 may include a fluid conduit through which a heat transfer fluid may flow. As above, the heat transfer fluid may be heated, for example, to a temperature range of approximately 20° C. to 120° C. In some cases, the unit heater 280 may be used to heat the gas distribution unit 210 to prevent undesired condensation of vapors and gases; in such cases, this temperature may be at least approximately 90° C. or 120° C.

[0105] In some embodiments, the gas distribution unit 210 may include a second unit heater 282 configured to heat the faceplate 276. This second unit heater 282 may include one or more resistive heating elements, fluid conduits for flowing a heated fluid, or both. The use of two unit heaters 280 and 282 in the gas distribution unit 210 may enable various heat transfers within the gas distribution unit 210. This may include using the first unit heater 280 and / or the second unit heater 282 to heat the faceplate 276 to provide a temperature control chamber, as described above, to reduce or prevent undesired condensation on the elements of the gas distribution unit 210.

[0106] The apparatus 200 may also be configured to cool the substrate. This may include flowing a cooling gas over the substrate, moving the substrate closer to the faceplate to allow heat transfer between the substrate and the faceplate, or both. Actively cooling the substrate allows for more precise temperature control and faster transitions between temperatures, reducing processing time and increasing throughput. In some embodiments, the substrate 218 may be cooled by using a first unit heater 280 that flows a heat transfer fluid through fluid conduits to transfer heat from the substrate 218 away from the faceplate 276. Thus, the substrate 218 may be cooled by positioning the substrate 218 in close proximity to the faceplate 276, such as with a gap 286 of 5 mm or less, or 2 mm or less, such that heat from the substrate 218 is transferred radially to the faceplate 276 and transferred away from the faceplate 276 by the heat transfer fluid in the first unit heater 280. Thus, the faceplate 276 may be considered a heat sink for the substrate 218 to cool the substrate 218 .

[0107] In some embodiments, the apparatus 200 may further include a cooling fluid source 273, which may contain a cooling fluid (gas or liquid), and a cooler (not shown) configured to cool the cooling fluid to a desired temperature, such as, for example, about 90° C. or less, about 70° C. or less, about 50° C. or less, about 20° C. or less, about 10° C. or less, about 0° C. or less, about −50° C. or less, about −100° C. or less, about 150° C. or less, about 190° C. or less, about 200° C. or less, or about 250° C. or less. The apparatus 200 includes piping that delivers the cooling fluid to the one or more fluid inlets 270 and a gas distribution unit 210 configured to flow the cooling fluid to the substrate. In some embodiments, the fluid may be in a liquid state when the fluid is flowed into the processing chamber 202 and may change to a vapor state when the fluid reaches the chamber interior 214, for example, if the chamber interior 214 is at a low pressure, such as between about 0.1 Torr and 10 Torr, or between about 0.1 Torr and 100 Torr, or between about 20 Torr and 200 Torr, as described above. The cooling fluid may be an inert element, such as nitrogen, argon, or helium. In some cases, the cooling fluid may include or have only non-inert elements and / or mixtures, such as hydrogen gas. In certain embodiments, the apparatus may be configured to cool the substrate at one or more cooling rates, such as at least about 5° C. / s, at least about 10° C. / s, at least about 15° C. / s, at least about 20° C. / s, at least about 30° C. / s, or at least about 40° C. / s.

[0108] In some embodiments, the apparatus 200 may actively cool the substrate by both moving the substrate closer to the faceplate and by flowing a cooling gas over the substrate. In some cases, active cooling may be more effective by flowing a cooling gas while the substrate is in close proximity to the faceplate. The effectiveness of the cooling gas may also depend on the type of gas used.

[0109] In some embodiments, the apparatus 200 may include a mixing plenum for mixing and / or conditioning the process gases before they reach the fluid inlet 270. One or more mixing plenum inlet valves may control the introduction of the process gases into the mixing plenum. In some other embodiments, the gas distribution unit 210 may include one or more mixing plenums within the gas distribution unit 210. The gas distribution unit 210 may also include one or more annular channels fluidly connected to the through-holes 278 that can evenly distribute the fluids received therein to the through-holes 278, providing uniform flow to the substrate.

[0110] The apparatus 200 may also include one or more additional non-contact sensors for detecting the temperature of the substrate. Such sensors may include, for example, an improved pyrometer. While conventional pyrometers are unable to detect specific substrates within a specific temperature range, the pyrometers described herein address these issues. For example, the pyrometer may be configured to detect multiple radiation ranges to detect multiple types of substrates, e.g., doped, lightly doped, or undoped, at various temperature ranges. This includes configurations for detecting radiation ranges from about 0.95 microns to about 1.1 microns, about 1 micron, about 1 to about 4 microns, and / or about 8 to 15 microns. The pyrometer may also be configured to detect the substrate temperature at shorter wavelengths to distinguish its signal from chamber thermal noise.

[0111] The pyrometer may include an emitter configured to emit an infrared signal and a detector configured to receive the radiation. Referring to FIG. 2A , the apparatus includes a pyrometer 288 having an emitter therein and a detector 290. The pyrometer may be configured to emit a signal toward either the top or bottom side of the substrate and receive the signal on the other side of the substrate. For example, the emitter may emit a signal toward the top surface of the substrate, and the detector may be below the substrate and receive the signal emitted through the substrate from below the substrate. Thus, the apparatus may have at least a first port 292A, such as port 292A through the center of the gas distribution unit 210, at the top of the processing chamber 202, and a second port 292B through the pedestal 204 and the substrate heater 222. The emitter in pyrometer 288 may be connected to one of ports 292A or 292B via a fiber optic connection, such as first port 292A, as shown in FIG. 2A, and the detector is optically connected to the other port, such as second port 292B in FIG. 2A. First port 292A may include a port window 294 that seals first port 292A from chemicals in chamber interior 214. In FIG. 2A, second port 292B can be seen extending through pedestal 204 and substrate heater such that emitter radiation can pass through the substrate, through window 250, into second port 292B, and reach detector 290, which may be positioned at the second port or optically connected to the second port through another fiber optic connection (not shown). In some other embodiments, the emitter and detector are reversed, with the emitter emitting through second port 292B and the detector detecting through first port 292A.

[0112] The apparatus 200 may also include one or more optical sensors 298 that detect one or more metrics of the visible light emitted by the LEDs. In some embodiments, these optical sensors may be one or more photodetectors configured to detect the light and / or light intensity of the light emitted by the LEDs of the substrate heater. In FIG. 2A , a single optical sensor 298 is shown connected to the chamber interior 214 via a fiber optic connection so that it can detect light emitted by the substrate heater 222. The optical sensor 298, and additional optical sensors, may be positioned at various locations within the processing chamber 202, for example, on the top and sides of the processing chamber 202, to detect light emitted at various locations within the processing chamber 202. As described below, this may enable measurement and adjustment of the substrate heater, such as adjustment of one or more independently controllable zones of LEDs. In some embodiments, there may be multiple optical sensors 298 arranged along a circle or multiple concentric circles to measure various areas of the LEDs throughout the processing chamber 202. In some embodiments, the optical sensor may be positioned within the chamber interior 214.

[0113] In some embodiments, the apparatus described herein may include a controller configured to control various aspects of the apparatus to implement the techniques described herein. For example, referring again to FIG. 2A , the apparatus 200 includes a controller 231 (which may include one or more physical or logical controllers) communicatively coupled to and controlling some or all of the operation of the processing chamber. The system controller 231 may include one or more memory devices 233 and one or more processors 235. In some embodiments, the apparatus includes a switching system operably coupled to the system controller 231 for controlling, for example, the flow rate and duration, the substrate heating unit, the substrate cooling unit, the loading and unloading of the substrate in the chamber, the thermal suspension of the substrate, and the process gas units when embodiments of the present disclosure are implemented. For example, the switching system may control the flow rate and duration of water vapor in the chamber so that one or more monolayers of water are controllably adsorbed on the substrate or silicon nitride surface. In some embodiments, the apparatus may have a switching time of up to about 500 milliseconds (ms), or up to about 750 ms. The switching time may depend on the flow synthesis, the selected recipe, the reactor configuration, and other factors.

[0114] In some embodiments, the switching system of the apparatus may be coupled to one or more contact or non-contact sensors that monitor the substrate temperature, one or more temperature sensors operably coupled to the chamber heater that monitor the chamber temperature, or a gas distribution unit that monitors and controls the flow rate and duration of one or more gaseous reactants and vapors.

[0115] In some embodiments, the controller is part of a system, which may be part of the examples described above. Such systems may include semiconductor processing equipment, including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as a wafer pedestal, gas flow system, etc.). These systems may be integrated with electronics for controlling the operation of the system before, during, and after processing of a semiconductor wafer or substrate. The electronics, sometimes referred to as a "controller," may control various components or subparts of one or more systems. The controller may be programmed to control any of the processes disclosed herein, depending on the processing requirements and / or type of system. Such processes may include delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid supply settings, position and motion settings, wafer transfer into and out of the tool, and wafer transfer into and out of other transport tools and / or load locks connected or interfaced to the particular system.

[0116] Broadly, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions communicated to the controller in the form of various individual settings (or program files) that define operational parameters for performing a particular process on or for a semiconductor wafer or for a system. The operational parameters, in some embodiments, may be part of a recipe defined by a process engineer to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0117] The controller, in some embodiments, may be part of or coupled to a computer that is integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the “cloud” or all or part of a fab host computer system, potentially enabling remote access of wafer processing. The computer may enable remote access to the system to monitor the current progress of a fabrication operation, examine the history of past fabrication operations, examine trends or performance criteria from multiple fabrication operations, modify parameters of a current process, configure processing steps following a current process, or initiate a new process. In some embodiments, a remote computer (e.g., a server) may provide process recipes to the system over a network, which may include a local network or the Internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some embodiments, the controller receives instructions in the form of data, which specifies parameters for each of the processing steps performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tool the controller is configured to interface with or control. Thus, as noted above, the controller may be distributed, such as by including one or more individual controllers networked together and cooperating toward a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes would include one or more integrated circuits on the chamber that are located remotely (e.g., at the platform level or as part of a remote computer) and communicate with one or more integrated circuits that are coupled to control the process on the chamber.

[0118] Exemplary systems may include, but are not limited to, plasma etch chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etch chambers or modules, PVD chambers or modules, CVD chambers or modules, ALD chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, tracker chambers or modules, and any other semiconductor processing systems associated with or usable for the fabrication and / or manufacturing of semiconductor wafers. In some embodiments, exemplary systems may include a combination of ALD chambers or modules and ALE chambers or modules such that one or more depositions are performed on a substrate, followed by one or more etches, without breaking vacuum in the chamber or exposing the substrate to ambient atmosphere.

[0119] As described above, depending on the process step or steps being performed by the tool, the controller may communicate with one or more of the other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used in material transport to and from tool locations and / or load ports of wafers within a semiconductor fabrication factory.

[0120] In some embodiments, the apparatus may be further configured to generate plasma and use plasma for some processes in various embodiments, which may include having a plasma source configured to generate plasma within the chamber, such as capacitively coupled plasma (CCP), inductively coupled plasma (ICP), top remote plasma, and bottom remote plasma.

[0121] The apparatus described herein may be used for a variety of etching techniques, including, but not limited to, continuous etching methods such as atomic layer etching and cyclic methods.

[0122] application

[0123] There are various applications in which etching processes according to embodiments herein can be used. One application is the selective etching of nitride layers within a 3D memory stack. In the fabrication of 3D NAND or other devices, alternating silicon oxide and silicon nitride layers may be deposited to form an oxide / nitride stack. The silicon oxide and silicon nitride layers may be deposited by any suitable process, for example, ALD, PEALD, CVD, or PECVD. The silicon oxide / silicon nitride layer stack may be etched to form a high aspect ratio (HAR) structure with trenches formed between adjacent HAR structures. FIG. 3A is a schematic diagram illustrating a cross-sectional view of a feature before atomic layer etching according to some embodiments. The feature on the substrate may be a HAR structure 300 including alternating silicon oxide layers 310 and silicon nitride layers 320 stacked on a substrate (i.e., a silicon substrate) 330 with trenches 340 formed between adjacent HAR structures 300. In some embodiments, the HAR structure may be about 7 μm to about 10 μm high. The thickness of each silicon nitride layer may be between about 5 nm and 40 nm.

[0124] FIG. 3B is a schematic diagram illustrating a cross-sectional view of the HAR structure on the substrate shown in FIG. 3A after atomic layer etching according to some embodiments, in which the silicon nitride layer 320 is selectively etched to form a recess without attacking the adjacent silicon oxide or silicon substrate. The depth of the recess, measured horizontally from the surface of the unetched silicon nitride layer in FIG. 3A, may range from about 1 nm to about 20 nm. The process of etching the silicon nitride layer 320 may be described by the process flow shown in FIG. 4. A semiconductor substrate including one or more HAR structures including one or more silicon nitride layers is provided in a reaction chamber (operation 402). The reaction chamber temperature may be about 20° C., and the chamber pressure may be about 10 Torr. In operation 404, water vapor is provided inside the chamber to adsorb one or more monolayers of water molecules onto the surface of the HAR structure 300 including the silicon nitride layer 320. In operation 406, gaseous phosphine is provided to the adsorbed water layer to form phosphoric acid on the structure surface. In operation 408, an oxidizer, such as oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO), nitrous oxide (NO), nitric oxide (NO), nitrogen dioxide (NO), and / or mixtures thereof, is then supplied to the surface of the HAR structure 300 to oxidize any unreacted phosphine to PO, which may react with the water supplied in operation 404 or with water in the reaction chamber to produce phosphoric acid in situ. In some embodiments, the amount of silicon nitride removed by the phosphoric acid may depend on the temperature of the reaction chamber (or substrate temperature) and may not be significant in operations 406-408. Note that operations 406 and 408 may be configured to occur simultaneously or substantially simultaneously.

[0125] Water vapor may then be supplied to the surface of the structure 300 (operation 410), and the substrate temperature may be adjusted to above 100°C, or between about 100°C and about 180°C, or between about 120°C and about 180°C (operation 412). Supplying additional water at a higher temperature increases the amount of phosphoric acid produced and also increases the reaction of phosphoric acid with the silicon nitride layer. Operation 412 includes significantly etching the silicon nitride layer 320. The phosphoric acid selectively etches the silicon nitride layer 320 over the adjacent silicon oxide 310 and / or silicon substrate 330. The silicon nitride layer 320 is etched from the surface, forming a recess, as shown in FIG. 3B. The etching of the silicon nitride layer may proceed significantly in the horizontal direction. The extent of etching of the silicon nitride layer may be determined, for example, by the amount of water vapor, the substrate temperature, and / or the etching time. The removal of the silicon nitride by the phosphoric acid produces one or more etching byproducts. Etch by-products may include silicon, e.g., orthosilicic acid (Si(OH)4), or phosphorus, e.g., phosphorus oxide (PO5). The etch by-products may remain on the surface of the silicon nitride layer in the HAR structure. In operation 414, the etch by-products may be removed from the surface of the silicon nitride layer by heating the substrate to above about 100°C, or above about 120°C, or between about 100°C and about 120°C, or above about 130°C, or above about 140°C, while reacting the etch by-products with a suitable etching compound, such as hydrogen fluoride, which may dissociate the etch by-products into volatile by-products. Alternatively, etch products such as PO5 may be removed by thermal sublimation above about 360°C, or above about 375°C, or above about 400°C. PO5 may be removed by reacting with hydrogen fluoride to produce PF5. Depending on the depth of the recess desired in the silicon nitride layer, operations 404-414 (or operations 406-414) may be optionally repeated until the desired portion of the silicon nitride layer has been etched.

[0126] In some embodiments, the atomic layer etch process eliminates the supply of reactants in liquid form. Instead, only gaseous reactants are supplied into the chamber, and gaseous etch chemistry is generated in situ, enabling a uniform etch reaction across the surface locations of the silicon nitride layer. In high-density memory devices with smaller cell sizes and increased cell counts, capillary forces of liquid etch chemistry from wet etching can affect feature or stack stability. Nitride etch processes in some embodiments may not be affected by capillary forces due to the nature of the gaseous reactants involved. Additionally, the etch process allows for control of etching down to angstrom-scale levels by controlling parameters including water vapor flow rate and duration, substrate temperature, or duration.

[0127] The foregoing embodiments have been described in some detail for purposes of clarity of understanding. However, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways of implementing the processes, systems, and apparatus of the present embodiments. Therefore, the present embodiments should be considered as illustrative and not restrictive, and the present embodiments are not limited to the details given herein.

Claims

1. 1. A method of treating a silicon nitride layer, comprising: (a) generating phosphoric acid on the surface of the silicon nitride layer; (b) treating the surface of the silicon nitride layer with the phosphoric acid. A method comprising:

2. 10. The method of claim 1 further comprising:

10. The method of claim 1, further comprising, prior to (a), (c) providing water vapor to form one or more monolayers of water molecules on the surface of the silicon nitride layer.

3. 3. The method of claim 1 or 2, The method, wherein the temperature of the surface of the silicon nitride layer ranges from about 0° C. to about 100° C., and the pressure at the surface of the silicon nitride layer ranges from about 1 Torr to about 100 Torr.

4. 4. The method according to any one of claims 1 to 3, The generating of phosphoric acid includes providing a first reactant; providing a second reactant; reacting the first reactant with the second reactant to form the phosphoric acid; The method of claim 1, wherein the first reactant comprises phosphorus.

5. 5. The method of claim 4, The first reactant is phosphine, diphosphate trioxide (P 2 O 3 ), phosphorus trichloride, phosphorus oxychloride, methoxyphosphine, alkyl phosphine halide, trimethylphosphine, triethylphosphine, tripropylphosphine, and / or mixtures thereof.

6. 5. The method of claim 4, The second reactant is oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), nitric oxide (N 2 O), nitrogen dioxide (NO 2 ), and / or mixtures thereof.

7. An apparatus for processing a substrate, comprising: a process chamber for processing the substrate; a pedestal including one or more heating elements for heating the substrate; a gas distribution unit for delivering one or more gaseous reactants to the substrate; a controller, controlling the gas distribution unit to control the flow rate and duration of the one or more gaseous reactants and / or vapors; a controller configured to control operation of the heating element to control the temperature of the substrate; An apparatus comprising:

8. 8. The apparatus of claim 7, The apparatus, wherein the one or more heating elements are located on a backside of the substrate.

9. 8. The apparatus of claim 7, The apparatus, wherein the one or more heating elements comprise one or more light-emitting diode (LED) units.

10. 8. The apparatus of claim 7, The one or more gaseous reactants may be water vapor, phosphine, diphosphate trioxide (P 2 O 3 a first reactant selected from the group consisting of phosphorus trichloride, phosphorus oxychloride, methoxyphosphine, alkyl phosphine halide, trimethylphosphine, triethylphosphine, tripropylphosphine, and / or mixtures thereof; oxygen, ozone, carbon monoxide (CO), carbon dioxide (CO 2 ), nitrous oxide (N 2 O), nitric oxide (NO), nitrogen dioxide (NO 2 ), and / or mixtures thereof, or hydrogen fluoride.

Images