Method for separating semiconductor dies

Abstract

A method for separating semiconductor dies is described. The method can separate individual semiconductor dies (115) from a semiconductor wafer (110) without using a blade. The method includes a plasma etch process (155) that uses a metal structure (145) formed on the backside of the wafer (110) as a mask to remove portions of the semiconductor wafer (110) from the backside. The portions removed by the plasma etch process (155) correspond to the scribe lines (120) between the semiconductor dies (115). The plasma etch process (155) terminates at a dielectric layer (125) formed on the front side of the wafer (110). The dielectric layer (125) may be cut to complete the separation process. An ultrasonic water jet process may also be used to remove burrs from the cut dielectric layer (125).

Description

[Technical Field]

[0001] The present description relates generally to the field of semiconductor packaging, and more particularly to methods for separating semiconductor dies. [Background technology]

[0002] A semiconductor package is a metal, plastic, glass, or ceramic enclosure that contains one or more semiconductor dies. The package provides conductive members (e.g., leads) that connect the semiconductor die to the external environment, such as a printed circuit board (PCB). The package also protects the semiconductor die from hazards such as mechanical shock or chemical contamination. Semiconductor dies are fabricated on semiconductor wafers before being diced into individual dies and packaged. The dicing process requires certain areas, sometimes referred to as scribe lines, reserved between the semiconductor dies. Scribe lines are configured to accommodate various results related to the nature of the technique used for dicing. Mechanical dicing techniques typically utilize blades and faces to reduce the area of ​​the semiconductor wafer occupied by the scribe lines. Summary of the Invention

[0003] A method for separating semiconductor dies is described. This summary is not an extensive overview of the disclosure and is not intended to identify key or critical elements of the disclosure or to delineate the scope of the disclosure. Rather, the primary purpose of this summary is to present some concepts of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

[0004] In some examples, a method includes: dividing a metal layer formed on a backside of a semiconductor substrate including a plurality of dies on a front side opposite the backside of the semiconductor substrate, wherein dividing the metal layer results in exposing a scribe area of ​​the semiconductor substrate; applying a plasma etch process configured to remove the exposed scribe area, wherein applying the plasma etch process results in exposing a portion of a dielectric layer disposed on the front side of the semiconductor substrate; and cutting the exposed portion of the dielectric layer.

[0005] In some examples, a method includes forming a sacrificial structure on a backside of a semiconductor substrate including a plurality of dies on a front side opposite the backside of the semiconductor substrate, the sacrificial structure covering a scribe area of ​​the semiconductor substrate; forming a metal layer on the sacrificial structure and on the backside of the semiconductor substrate not covered by the sacrificial structure; removing the sacrificial structure and a portion of the metal layer formed on the sacrificial structure, where removing the sacrificial structure results in exposing the scribe area; removing the scribe area of ​​the semiconductor substrate, where removing the scribe area of ​​the semiconductor substrate results in exposing a portion of a dielectric layer located on the surface of the semiconductor substrate from the backside; and breaking the exposed portion of the dielectric layer.

[0006] In some examples, the semiconductor die includes a semiconductor substrate including integrated circuit elements on a front side of the semiconductor substrate and a metal structure formed on a back side of the semiconductor substrate opposite the front side, wherein a sidewall profile of the semiconductor substrate includes a plurality of ridges. [Brief explanation of the drawings]

[0007] [Figure 1A] The process of separating the semiconductor dies in the example of this description is illustrated. [Figure 1B] The process of separating the semiconductor dies in the example of this description is illustrated. [Figure 1C] The process of separating the semiconductor dies in the example of this description is illustrated. [Figure 1D] The process of separating the semiconductor dies in the example of this description is illustrated. [Figure 1E] The process of separating the semiconductor dies in the example of this description is illustrated. [Figure 1F] The process of separating the semiconductor dies in the example of this description is illustrated. [Figure 1G] The process of separating the semiconductor dies in the example of this description is illustrated. [Figure 1H] The process of separating the semiconductor dies in the example of this description is illustrated. [Figure 1I] The process of separating the semiconductor dies in the example of this description is illustrated. [Figure 1J] The process of separating the semiconductor dies in the example of this description is illustrated. [Figure 1K] The process of separating the semiconductor dies in the example of this description is illustrated. [Figure 1L] The process of separating the semiconductor dies in the example of this description is illustrated.

[0008] [Figure 2] 1 is a three-dimensional schematic diagram of a sacrificial structure formed on a semiconductor substrate in the example of the present description.

[0009] [Figure 3A] FIG. 2 is a plan view of a semiconductor substrate in the example of the present description. [Figure 3B] 1 is a cross-sectional view of a semiconductor substrate in an example of the present description.

[0010] [Figure 4] FIG. 2 is a three-dimensional schematic diagram of a semiconductor die in the presently described example.

[0011] [Figure 5A] 1 is a cross-sectional schematic diagram of a semiconductor die in accordance with an example of the present description. [Figure 5B] 1 is a cross-sectional schematic diagram of a semiconductor die in accordance with an example of the present description.

[0012] [Figure 6] 1 is a flowchart illustrating a method for separating semiconductor dies in accordance with the presently described embodiments. [Figure 7] 1 is a flowchart illustrating a method for separating semiconductor dies in accordance with the presently described embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0013] The present description will be described with reference to the accompanying drawings. In these drawings, components are not drawn to scale. Instead, emphasis is placed on clearly illustrating the overall features and principles of the present description. To provide an understanding of the present disclosure, numerous specific details and relationships are described with reference to illustrative examples in the drawings. These drawings and examples are not intended to limit the scope of the description to such examples, and other examples are possible by replacing or modifying at least some of the elements or process steps described or illustrated. Furthermore, where described elements can be implemented partially or completely using known components or process steps, portions of such components or process steps that facilitate understanding of the present description will be described, and detailed descriptions of other portions of such components or process steps will be omitted so as not to obscure the present disclosure.

[0014] As used in this description, terms such as "first" and "second" are used to arbitrarily distinguish between elements that such terms describe. Therefore, these terms in this description and claims do not indicate any temporal or other priority of such elements. Additionally, terms such as "front," "back," "top," "bottom," "above," "below," "vertical," "horizontal," "lateral," "below," "up," "upper," and "lower" are used to refer to the relative direction or position of features in a semiconductor device given the orientation shown in the figures. For example, "top" or "topmost" can refer to a feature that is located closer to the top of the page than another feature. Terms so used are interchangeable under appropriate circumstances, such that examples of the technology described herein can operate in other orientations than those illustrated or otherwise described herein, for example.

[0015] The semiconductor die or devices, integrated circuit elements, or integrated circuit (IC) components described herein may be formed on a semiconductor substrate (or die) including various semiconductor materials, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, silicon carbide, etc. In some cases, the substrate refers to a semiconductor wafer. The various structures described herein can be formed using semiconductor processing techniques. Layers including various materials can be formed on a semiconductor substrate using, for example, deposition techniques (e.g., chemical vapor deposition, physical vapor deposition, atomic layer deposition, spin coating, plating), thermal processing techniques (e.g., oxidation, nitridation, epitaxy), and / or other suitable techniques. Similarly, portions of layers can be selectively removed using, for example, etching techniques (e.g., plasma (or dry) etching, wet etching), chemical-mechanical planarization, and / or other suitable techniques, some of which may be combined with photolithography steps.

[0016] A method for separating semiconductor dies is described. The method can separate (die or singulate) individual semiconductor dies from a semiconductor wafer without using a blade (or saw) or a laser. The method also facilitates forming a metal layer on the backside of the semiconductor die (which may be referred to as backside metallization (BSM)), which may be beneficial for certain semiconductor devices or applications, such as power field-effect transistor (FET) devices or applications. The method does not require modifications to various structures present in the scribe lines, which may be referred to as scribe line structures. The method also allows for scribe line widths to be smaller than those required by typical mechanical dicing processes. The method can facilitate reducing the final substrate thickness to be thinner than that required by typical mechanical dicing processes to maintain the structural integrity of the semiconductor die. Reducing the substrate thickness may be beneficial for certain semiconductor devices, for example, reducing the electrical resistance (Rds) between the source and drain of a power FET.

[0017] 1A-1L illustrate various steps for separating semiconductor dies in the described example. FIG. 1A shows a semiconductor substrate 110 having a first surface 111 (top surface, surface, top side, front side) and a second surface 112 (bottom surface, back side, bottom side, back side) opposite the first surface 111. The semiconductor substrate 110 may be a semiconductor wafer having a thickness (denoted as T1) in the range of about 600 to about 800 microns. The semiconductor substrate 110 may include multiple semiconductor dies 115 (also individually identified as semiconductor dies 115a-c). While the semiconductor substrate 110 is shown as having three semiconductor dies 115 for illustrative purposes only, the semiconductor substrate 110 may include many more semiconductor dies 115, e.g., hundreds of semiconductor dies 115 or more. The semiconductor substrate 110 (or individual semiconductor dies 115) includes integrated circuit elements (not shown) on the first surface 111. In some examples, the integrated circuit element includes a power FET or a circuit having one or more power FETs.

[0018] The semiconductor substrate 110 includes scribe lines 120 (also individually identified as scribe lines 120 a / b) between the semiconductor dies 115. The scribe lines (which may also be referred to as streets, dicing lanes, etc.) may have a width “W,” as shown in FIG. 1A . The scribe line width may be configured to accommodate various aspects of wafer dicing techniques. For example, mechanical dicing techniques using a blade may require the scribe line width to be at least about 80 microns or more to accommodate the width of the kerf created by the blade and to avoid undesirable mechanical effects on the semiconductor die 115, such as cracks propagating toward the integrated circuit elements or chipping at the edge of the semiconductor die. Chips during the mechanical dicing process may reach a size of about 30 microns or more. As described in more detail herein, this method can separate the semiconductor die 115 from the semiconductor substrate 110 with a scribe line width of about 50 microns, 30 microns, 20 microns, or even less (e.g., 10 microns or less).

[0019] FIG. 1A also shows a dielectric layer 125 formed on the first surface 111 of the semiconductor substrate 110. The dielectric layer 125 may include one or more interlevel metallization or multilevel metallization (MLM) layers. For example, the dielectric layer 125 includes one or more conductive layers (e.g., four or five layers of metallization) including aluminum or copper, as well as via structures (e.g., tungsten vias, copper vias) connecting the one or more conductive layers. The dielectric layer 125 also includes various dielectric layers that provide insulation between conductive layers, such as silicon oxide (e.g., SiO), tetraethoxysilane (TEOS), silicon nitride (e.g., SiN), silicon oxynitride (e.g., SiON). The MLM layers of the dielectric layer 125 are connected to the integrated circuit elements of the corresponding die 115.

[0020] The dielectric layer 125 corresponding to the scribe line 120 may include various structures (sometimes referred to as scribe line structures) constructed with the MLM layer. For example, the scribe line structures may include in-line electrical test structures, process monitor structures (e.g., for measuring critical dimensions or overlay between layers, for measuring thicknesses of various layers), and dummy fill features for process uniformity (e.g., during dry etching process steps, chemical mechanical polishing process steps). Thus, the scribe line structures may include various metal layers or structures.

[0021] Metal layers or structures present in the dielectric layer 125 can pose challenges for utilizing laser or plasma processes (e.g., laser dicing techniques, plasma dicing techniques) because the metal layers (or metal structures) can significantly interfere with the laser or plasma dicing process. Laser or plasma dicing techniques may be considered advantageous over mechanical dicing techniques (e.g., in reducing scribe line widths), but may require process modifications to remove the metal layer within the scribe line structures. As described in more detail herein, these methods can separate the semiconductor die 115 despite the scribe line structures (with or without the metal layer).

[0022] 1B shows the semiconductor substrate 110 thinned from the backside 112 to a final thickness (denoted as T2). In some examples, a first adhesive tape 130 (attached to a frame ring, not shown) can be attached to the dielectric layer 125. The semiconductor substrate 110 can then be thinned (e.g., ground) from the backside 112. The first adhesive tape 130 is sometimes referred to as a backgrind tape (BG tape). The final thickness of the semiconductor substrate 110 can be determined based on the dicing technique used to separate the individual semiconductor dies 115 from the semiconductor substrate 110.

[0023] For mechanical dicing techniques using a blade, the final thickness may be about 4 mils (i.e., about 100 μm) or greater to accommodate the various mechanical forces exerted on the semiconductor substrate 110 during the mechanical dicing process. As described in more detail herein, this method may provide a reduced final thickness (e.g., less than 4 mils) of the semiconductor substrate 110 due, at least in part, to the absence of a blade used to separate the semiconductor die 115. For example, the final thickness (T2) of the semiconductor substrate 110 may be 3 mils, 2 mils, or even 1 mil or less. A reduced final thickness of the semiconductor substrate 110 (e.g., as compared to the final thickness for mechanical dicing) may be advantageous for certain semiconductor devices or operations, such as, for example, power FET devices or circuits including one or more power FETs.

[0024] 1C-1F each illustrate a method of forming a BSM structure covering the backside of semiconductor die 115. As shown in FIG. 1F, scribe lines 120 between semiconductor die 115 are not covered by the BSM structure. In other words, scribe lines 120 are exposed to subsequent process steps, such as the plasma etching step described with reference to FIG. 1H.

[0025] FIG. 1C shows that a second adhesive tape 135 (attached to a frame ring 136) is attached to the first adhesive tape 130. Next, as shown in FIG. 1D, a sacrificial structure 140 may be formed on the backside 112 of the semiconductor substrate 110. The sacrificial structure 140 may be configured to cover the scribe line 120. FIG. 2 shows a three-dimensional (3D) schematic diagram of the sacrificial structure 140 covering the scribe area. In some examples, the sacrificial structure 140 may be formed based on a photolithography process. In such examples, the sacrificial structure 140 may include photoresist. FIG. 1E shows that the first and second adhesive tapes 130 and 135 have been removed (detached) in preparation for subsequent process steps.

[0026] FIG. 1F shows that BSM structures 145 (also individually identified as BSM structures 145a-c) are formed on the backside 112 of the semiconductor substrate 110 based on the sacrificial structures 140. For example, a metal layer can be deposited on the backside 112 of the semiconductor substrate 110 having the sacrificial structures 140. In other words, a metal layer can be formed on the sacrificial structures 140 and on the backside 112 of the semiconductor substrate 110 not covered by the sacrificial structures 140. Subsequently, the sacrificial structures 140 can be removed such that the portion of the metal layer formed on the sacrificial structures 140 is removed. In this manner, the BSM structures 145 can be formed on the backside 112 of each semiconductor die 115. In some examples, the BSM structures 145 can be approximately 1 to 3 microns thick. The scribe lines 120 are exposed (i.e., not covered by the BSM structures 145) as a result of removing the sacrificial structures 140. As used herein, the term "approximately" can refer to a variation of ±5% to ±10% of the stated value, in some cases. In other cases, the term "about" may refer to a variation of ±10% to ±20% of the stated value.

[0027] Although the above-described exemplary process steps utilize sacrificial structures (e.g., photoresist structures) to section a metal layer deposited on the backside 112 of the semiconductor substrate 110, the present description is not limited thereto. For example, a blanket metal layer can be deposited on the backside 112 of the semiconductor substrate 110 without forming a sacrificial structure. A photolithography process can then be performed on the blanket metal layer to cover the blanket metal layer corresponding to the individual semiconductor dies 115. An etch process (e.g., a dry etch process) can be applied to the blanket metal layer to remove portions of the metal layer and expose the scribe lines. The photoresist covering the metal layer corresponding to the individual semiconductor dies 115 can then be removed to create a BSM structure 145 on the backside 112 of the semiconductor substrate 110, as shown in FIG. 1F.

[0028] FIG. 1G shows that the semiconductor substrate 110, with the BSM structure 145 on the backside 112, is mounted on a third adhesive tape 150 (attached to a frame ring 151). FIG. 1H shows that portions of the semiconductor substrate 110 are removed using a plasma etch process. The plasma etch process may have an etch selectivity configured to preserve the BSM structure 145. The plasma etch process may also have an etch selectivity configured to preserve the dielectric layer 125. As a result of applying the plasma etch process to the semiconductor substrate 110 from the backside 112, the individual semiconductor dies 115 are separated (singulated, diced) from the semiconductor substrate 110. In other words, portions of the semiconductor substrate 110 corresponding to the scribe lines 120 are removed by the flux 155 of the plasma etch process. However, the semiconductor dies 115 remain connected to each other through the dielectric layer 125.

[0029] In this regard, the plasma etch process uses the BSM structure 145 as a mask based on etch selectivity to the BSM structure 145, which protects the semiconductor substrate 110 corresponding to the semiconductor die 115 during the plasma etch process. Thus, one or more edges of the BSM structure 145 may be aligned to corresponding edges of the semiconductor substrate 110 of the semiconductor die 115, as shown in FIG. 1H . In other words, one or more edges of the semiconductor substrate 110 of the semiconductor die 115 may be self-aligned to corresponding edges of the BSM structure 145. Also, the semiconductor substrate 110 of the semiconductor die 115 may have a cross-sectional area (i.e., a cross-sectional area, footprint substantially parallel to the backside 112 of the semiconductor substrate 110) that is substantially the same as the cross-sectional area of ​​the BSM structure 145, for example, within 5% or less, 10% or less, 15% or less, etc.

[0030] Considering the etch selectivity configured to preserve the dielectric layer 125, the plasma etch process can be considered to have stopped when the dielectric layer 125 is exposed from the backside 112, resulting in removal of the semiconductor substrate 110 in the scribe line area. The etch selectivity to the dielectric layer 125 can facilitate managing variations in the final thickness of the semiconductor substrate 110, such as variations in the final thickness T2 after a backgrinding process as shown in FIG. 1B. For example, the plasma etch process can be considered to have stopped locally in a first region of the semiconductor substrate 110, while the plasma etch process can still actively proceed in a second region of the semiconductor substrate 110, with the first region having a smaller final thickness than the second region. In some examples, the plasma etch process can be applied for a predetermined amount of time, e.g., a fixed-time etch process. In other examples, the time to apply the plasma etch process can be dynamically determined based on determining a specific percentage of the dielectric layer 125 that is exposed (e.g., an endpoint etch process).

[0031] The plasma etch process may include alternating deposition and etching steps. The etching step may be configured primarily to remove semiconductor material from the semiconductor substrate 110, for example, by forming by-products of the plasma etch process that include the semiconductor material. Alternatively, the deposition step may be configured primarily to deposit certain by-products of the plasma etch process (which may also be referred to as polymers) on the sidewalls of the semiconductor substrate 110. In this manner, the sidewalls of the semiconductor substrate 110 remaining below the BSM structure 145 may remain substantially perpendicular to the backside 112 of the semiconductor substrate 110. In some examples, the plasma etch process includes fluorine (F), for example, a fluorine-based plasma etch process generates a flux 155 that includes F atoms.

[0032] As a result of alternating etching and deposition steps, the sidewall profile of the semiconductor substrate 110 can be non-uniform (not shown in FIG. 1H), as will be described in more detail with reference to FIG. 3B. In some examples, the non-uniform sidewall profile comprises a plurality of raised lines substantially parallel to the backside 112 of the semiconductor substrate 110. In some examples, the non-uniform sidewall profile comprises a ribbed surface, a wavy surface, a surface with ridges, a surface with peaks and valleys, or a combination thereof.

[0033] FIG. 1I shows that after completing the plasma etching process steps described above with reference to FIG. 1H, fourth adhesive tape 160 (attached to frame ring 161) is attached to BSM structure 145. FIG. 1I also shows cutting third adhesive tape 150 (as indicated by the two triangles) to remove frame ring 151. FIG. 1J shows that the remaining portion of third adhesive tape 150 is removed (e.g., peeled) from dielectric layer 125. After removing third adhesive tape 150, dielectric layer 125 exposed from backside 112 is the only structure connecting individual semiconductor dies 110 to one another.

[0034] 1K shows that the exposed portions of the dielectric layer 125 can be cut (broken) by pulling the fourth adhesive tape 160, as indicated by the two horizontal arrows pointing in opposite directions. Physically separating (breaking) the exposed portions of the dielectric layer 125 does not depend on whether the dielectric layer 125 corresponding to the scribe line 120 includes any scribe line structures or whether the scribe line structures (if any) include a metal layer. Thus, this method can provide for separating the individual semiconductor dies 115 regardless of any metal layers or structures present in the scribe line 120.

[0035] As a result of cutting (breaking) the exposed portions of dielectric layer 125, dielectric layer 125 may include one or more portions 126 that extend beyond the edge of semiconductor substrate 110 of the individual semiconductor die 115. Portions 126 may be considered to be free-standing beyond the edge of semiconductor substrate 110 or to hang over spaces not supported by semiconductor substrate 110. Portions 126 are sometimes referred to as burrs in dielectric layer 125.

[0036] 1K, the semiconductor die 115 including the burr 126 can be considered ready for the remaining assembly process steps, such as picking up from adhesive tape 160 mounted on a lead frame, forming wire bonds, forming a mold structure to protect the semiconductor die 115, etc. For example, if the width of the scribe line 120 is about 10 microns or less, the burr 126 may remain with the semiconductor die 115, and the ultrasonic waterjet process described with reference to FIG. 1L, for example, may be omitted. Also, scribe lines that are about 10 microns wide (or less) may not include a scribe line structure (with or without a metal layer).

[0037] FIG. 1L shows that the burr 126 (or residual expansion debris) on the dielectric layer 125 may be removed. FIG. 4 also shows a 3D schematic of the semiconductor die 115 after the burr 126 has been removed. For example, an ultrasonic waterjet process 165 may be used to remove the burr 126 from the dielectric layer 125. In some examples, the ultrasonic waterjet process 165 includes applying ultrasonic vibrations and pressure to a water stream. In some examples, the ultrasonic vibrations may be in the range of approximately 500 to 3,000 hertz (Hz). In some examples, the pressure may be in the range of approximately 10 to 40 pounds per square inch (psi). The semiconductor die 115 shown in FIG. 1L is ready for the remaining assembly process steps, such as picking up from an adhesive tape 160 attached to a lead frame, forming wire bonds, and forming a mold structure to protect the semiconductor die 115.

[0038] As described herein, separating the semiconductor die 115 from the semiconductor substrate 110 in the described examples eliminates mechanical sawing (dicing) of the semiconductor substrate 110. Thus, the final thickness of the semiconductor substrate 110 can be smaller (thinner) than the typical thickness required by mechanical dicing techniques (e.g., on the order of 4 mils to withstand mechanical stress). For example, the final thickness of the semiconductor substrate 110 (e.g., T2 described with reference to FIG. 1B ) can be 3 mils, 2 mils, 1 mil, or less.

[0039] Additionally, a thinner final thickness of semiconductor substrate 110 is expected to provide additional benefits. For example, a thinner final thickness tends to reduce the aspect ratio of the plasma etch process described with reference to FIG. 1H when, for example, the width of scribe line 120 is fixed. The reduced aspect ratio may facilitate maintaining a sidewall profile substantially perpendicular to the backside of semiconductor substrate 110. Additionally, a thinner final thickness may facilitate reduced scribe line width, reduced throughput time for the plasma etch process, reduced resistance between the source and drain of a power FET, etc.

[0040] 2 is a three-dimensional (3D) schematic diagram of a sacrificial structure (e.g., sacrificial structure 140) formed on a semiconductor substrate (e.g., semiconductor substrate 110) in the described example. As described above with reference to FIG. 1E, sacrificial structure 140 covers scribe lines 120 (scribe areas) of semiconductor substrate 110. In some examples, sacrificial structure 140 includes photoresist. As described above with reference to FIG. 1F, a BSM structure can be formed on the backside 112 of semiconductor substrate 110 that is not covered by sacrificial structure 140, i.e., the area corresponding to semiconductor die 115.

[0041] 3A and 3B are plan and cross-sectional views of a semiconductor substrate (e.g., semiconductor substrate 110) in the example described herein. FIG. 3A can be considered a top view of the backside 112 of the semiconductor die 115 after completing the plasma etch process described with reference to FIG. 1H. FIG. 3A shows two semiconductor dies 115a and 115b and a scribe line 120 between them. Portions of the semiconductor substrate 110 corresponding to the scribe line 120 have been removed by the plasma etch process. The backsides 112 of the semiconductor dies 115a / b are covered with BSM structures 145a / b, respectively. FIG. 3A also shows chips 370 formed on the BSM structures 145a / b as a result of the plasma etch process. The chips 370 may include undercuts of the BSM structures 145a / b. The chips 370 may extend irregularly from the edges of the BSM structures 145a / b toward the center of the semiconductor die 115 to a distance C, as shown in FIG. 3A. In some examples, the distance C may vary between 1 and 3 microns after completing the plasma etch process.

[0042] FIG. 3B can be considered a cross-sectional view of the semiconductor substrate 110 near the backside 112 after the plasma etch process described with reference to FIG. 1H is completed. FIG. 3B shows the BSM structure 145 and a portion of the semiconductor substrate 110 covered (protected) by the BSM structure 145 during the plasma etch process. Thus, an edge of at least one die of the BSM structure 145 aligns with a corresponding edge of the semiconductor substrate 110. The plasma etch process can also form a non-uniform sidewall profile of the semiconductor substrate 110. The non-uniform sidewall profile can be considered a result of the plasma etch process progressing through the semiconductor substrate 110 by alternating multiple cycles of etching and deposition steps. The non-uniform sidewall profile includes valleys 375 (trenches) and ridges 376 (peaks or raised lines relative to the valleys 375). Thus, the non-uniform sidewall profile can be considered to include a ribbed and / or wavy surface.

[0043] FIG. 4 is a 3D schematic diagram of a semiconductor die (e.g., semiconductor die 115) in the described example. FIG. 4 can be considered a 3D perspective view showing the front side 111 of the semiconductor die 115 after completing the ultrasonic waterjet process described in connection with FIG. 1L. Four corners of the semiconductor die 115 and scribe lines 120 between them are shown in FIG. 4. Portions of the semiconductor substrate 110 corresponding to the scribe lines 120 have been removed by the plasma etch process described with reference to FIG. 1H. Also, burrs 126 of the dielectric layer 125 have been removed by the ultrasonic waterjet process described with reference to FIG. 1L. Thus, one or more edges of the dielectric layer 125 are aligned with corresponding edges of the semiconductor substrate 110 of the semiconductor die 115. The semiconductor die 115 in FIG. 4 includes seal ring structures 480 (sometimes referred to as etch ring structures), each configured to surround the semiconductor die 115. After completing the ultrasonic waterjet process, the semiconductor die 115 is attached only to the fourth tape 160, as described with reference to FIG. 1L. Therefore, the bottom of the scribe line 120 can be considered as the fourth tape 160. The non-uniform sidewall profile of the semiconductor die 115 is omitted in FIG.

[0044] 5A and 5B are cross-sectional schematic diagrams of a semiconductor die (e.g., semiconductor die 115) in an example of the present description. FIG. 5A may be considered to illustrate the semiconductor die 115 shown in FIG. 1L removed from adhesive tape 160 after completing an ultrasonic water jet process to remove burrs 126. Semiconductor die 115 includes a semiconductor substrate (e.g., semiconductor substrate 110) including integrated circuit elements on a front side (e.g., front side 111) of the semiconductor substrate and a metal structure (e.g., BSM structure 145) formed on a back side (e.g., back side 112) of the semiconductor substrate opposite the front side. The semiconductor substrate includes a sidewall profile that includes a series of ridges (e.g., ridge 376).

[0045] In some examples, the ridges are substantially parallel to the backside of the semiconductor substrate. In some examples, the ridges surround the semiconductor substrate. Also, the sidewall profile can be substantially perpendicular to the backside of the semiconductor substrate. In some examples, the sidewall profile includes a ribbed surface, a wavy surface, a surface with ridges, a surface with peaks and valleys, or a combination thereof.

[0046] In some examples, the metal structure includes at least one edge aligned to a corresponding edge of the semiconductor substrate. In some examples, the semiconductor substrate has a first cross-sectional area (footprint) and the metal structure has a second cross-sectional area (footprint) substantially the same as the first cross-sectional area. In some examples, the semiconductor die also includes a dielectric layer (e.g., dielectric layer 125) on the front side of the semiconductor substrate. The dielectric layer includes one or more interlevel metallization (MLM) layers. The MLM layers can be coupled to integrated circuit elements of the semiconductor die. In some examples, at least one edge of the dielectric layer is aligned to a corresponding edge of the semiconductor substrate. In some examples, the integrated circuit elements include power FETs.

[0047] 5B may be considered to illustrate the semiconductor die 115 shown in FIG. 1K removed from the adhesive tape 160 without the ultrasonic water jet process. Thus, the semiconductor die 115 shown in FIG. 5B includes at least one die edge of the dielectric layer extending beyond a corresponding edge of the semiconductor substrate.

[0048] FIG. 6 is a flowchart 600 illustrating a method for separating semiconductor dies according to embodiments of the present disclosure. Flowchart 600 includes embodiments of the methods described with reference to FIGS. 1A-4G. The method includes dividing a metal layer formed on a backside of a semiconductor substrate including multiple dies on a front side opposite the backside, where dividing the metal layer exposes a scribe area of ​​the semiconductor substrate (Box 610). The method further includes applying a plasma etch process configured to remove the exposed scribe area, where applying the plasma etch process results in exposing a portion of a dielectric layer disposed on the front side of the semiconductor substrate (Box 615). The method further includes cutting the exposed portion of the dielectric layer (Box 620).

[0049] In some examples, the plasma etch process has an etch selectivity configured to preserve the metal layer. In some examples, the plasma etch process has an etch selectivity configured to preserve the dielectric layer. In some examples, the plasma etch process includes alternating deposition and etch steps. In some examples, the dielectric layer includes one or more interlevel metallization layers. In some examples, the metal layer is segmented to form multiple metal structures corresponding to multiple dies. In some examples, the plasma etch process utilizes the metal structures as a mask to protect the semiconductor substrate.

[0050] In some examples, each one of the metal structures includes at least one edge that is aligned with an edge of a corresponding one of the dies. In some examples, applying a plasma etch process forms a non-uniform sidewall profile for the plurality of individual dies. In some examples, the non-uniform sidewall profile includes a plurality of raised lines that are substantially parallel to the backside of the semiconductor substrate. In some examples, the non-uniform sidewall profile is substantially perpendicular to the backside of the semiconductor substrate. In some examples, the non-uniform sidewall profile includes a ribbed surface, a wavy surface, a surface with ridges, a surface with peaks and valleys, or a combination thereof.

[0051] In some examples, the method further includes applying an ultrasonic waterjet process configured to remove burrs from the dielectric layer based on cutting the exposed portions of the dielectric layer. In some examples, the ultrasonic waterjet process includes applying ultrasonic vibrations and pressure to a water stream, the ultrasonic vibrations being in the range of approximately 500 to 3,000 hertz (Hz) and the pressure being in the range of approximately 10 to 40 pounds per square inch (psi). In some examples, the method further includes attaching tape to a first surface of the dielectric layer opposite the second surface exposed to the plasma etch process, wherein cutting the exposed portions of the dielectric layer includes expanding the tape attached to the first surface of the dielectric layer. In some examples, the method further includes thinning the semiconductor substrate from the backside before forming a metal layer on the backside of the semiconductor substrate.

[0052] In some examples, dividing the metal layer includes removing a sacrificial structure located between the metal layer and the scribe area of ​​the semiconductor substrate. In some examples, the sacrificial structure includes photoresist. In some examples, dividing the metal layer includes forming a plurality of mask structures on the metal layer corresponding to the plurality of dies and removing portions of the metal layer not covered by the plurality of mask structures to expose the scribe area of ​​the semiconductor substrate.

[0053] FIG. 7 is a flowchart 700 illustrating a method for separating semiconductor dies according to various embodiments herein. Flowchart 700 includes embodiments of the methods described with reference to FIGS. 1A-4. The method includes forming a sacrificial structure on a backside of a semiconductor substrate including multiple dies on a front side opposite the backside, the sacrificial structure covering a scribe area of ​​the semiconductor substrate (Box 710). The method further includes forming a metal layer over the sacrificial structure and the backside of the semiconductor substrate not covered by the sacrificial structure (Box 715). The method includes removing the sacrificial structure and a portion of the metal layer formed on the sacrificial structure, the scribe area being exposed as a result of removing the sacrificial structure (Box 720). The method further includes removing the scribe area of ​​the semiconductor substrate, the removal of the scribe area of ​​the semiconductor substrate exposing a portion of a dielectric layer located on the front side of the semiconductor substrate from the backside (Box 725). The method further includes breaking the exposed portion of the dielectric layer (Box 730).

[0054] In some examples, the sacrificial structure includes photoresist. In some examples, removing portions of the metal layer forms a plurality of metal structures corresponding to the plurality of dies. In some examples, each one of the metal structures includes at least one edge aligned with an edge of a corresponding one of the dies. In some examples, removing the scribe area of ​​the semiconductor substrate includes applying a plasma process having alternating deposition and etching steps. In some examples, removing the scribe area of ​​the semiconductor substrate forms a non-uniform sidewall profile of the plurality of individual dies. In some examples, the non-uniform sidewall profile includes a plurality of raised lines substantially parallel to the backside of the semiconductor substrate.

[0055] In some examples, the non-uniform sidewall profile is substantially perpendicular to the backside of the semiconductor substrate. In some examples, the exposed portion of the dielectric layer includes one or more interlevel metallization layers. In some examples, the method further includes deburring the fractured portion of the dielectric layer. In some examples, deburring includes utilizing an ultrasonic water jet process that applies ultrasonic vibrations and pressure to a water stream, the ultrasonic vibrations being in the range of about 500 to 3,000 hertz (Hz) and the pressure being in the range of about 10 to 40 pounds per square inch (psi).

[0056] In some examples, the method further includes thinning the semiconductor substrate from the backside before forming the sacrificial structure on the backside of the semiconductor substrate. In some examples, the method further includes attaching tape to the dielectric layer after removing the scribe area of ​​the semiconductor substrate, and fracturing the exposed portion of the dielectric layer includes expanding the tape attached to the dielectric layer.

[0057] While various examples of the present description have been described above, they are presented by way of example and not limitation. Numerous modifications to the described examples may be made in the disclosure herein without departing from the spirit or scope of the description. Also, while various features or components are shown in the illustrated examples as having a particular arrangement or configuration, other arrangements and configurations are possible. Also, aspects of the present technology that are described in the context of example embodiments may be combined or eliminated in other examples. Thus, the breadth and scope of the present description should not be limited by any of the above-described examples.

Claims

1. 1. A method comprising: sectioning a metal layer formed on a backside of a semiconductor substrate, the semiconductor substrate including a plurality of dies on a front side opposite the backside, and scribe areas of the semiconductor substrate being exposed as a result of sectioning the metal layer; applying a plasma etch process configured to remove the exposed scribe area, wherein a portion of a dielectric layer disposed on the front side of the semiconductor substrate is exposed as a result of applying the plasma etch process; cutting the exposed portion of the dielectric layer; A method comprising:

2. 10. The method of claim 1, wherein the plasma etch process has an etch selectivity configured to preserve the metal layer.

3. 10. The method of claim 1, wherein the plasma etch process has an etch selectivity configured to preserve the dielectric layer.

4. 10. The method of claim 1, wherein the plasma etch process comprises alternating deposition and etching steps.

5. The method of claim 1 , wherein the dielectric layer comprises one or more interlevel metallization layers.

6. 10. The method of claim 1, wherein partitioning the metal layer forms a plurality of metal structures corresponding to the plurality of dies.

7. 7. The method of claim 6, wherein the plasma etch process utilizes the metal structure as a mask to protect the semiconductor substrate.

8. 7. The method of claim 6, wherein each one of the metal structures includes at least one edge that is aligned with an edge of a corresponding one of the dies.

9. 10. The method of claim 1, wherein applying the plasma etch process forms non-uniform sidewall profiles of the plurality of individual dies.

10. 10. The method of claim 9, wherein the non-uniform sidewall profile comprises a plurality of raised lines substantially parallel to the backside of the semiconductor substrate.

11. 10. The method of claim 9, wherein the non-uniform sidewall profile is substantially perpendicular to the backside of the semiconductor substrate.

12. 10. The method of claim 9, wherein the non-uniform sidewall profile comprises a ribbed surface, a wavy surface, a surface with ridges, a surface with peaks and valleys, or a combination thereof.

13. 10. The method of claim 1, further comprising applying an ultrasonic water jet process configured to deburr the dielectric layer based on cutting the exposed portion of the dielectric layer.

14. 14. The method of claim 13, wherein the ultrasonic waterjet process includes applying ultrasonic vibrations and pressure to a stream of water, the ultrasonic vibrations being in the range of about 500 to 3,000 hertz (Hz) and the pressure being in the range of about 10 to 40 pounds per square inch (psi).

15. 10. The method of claim 1 further comprising: Attaching a tape to a first surface of the dielectric layer opposite a second surface exposed as a result of a plasma etch process, and cutting the exposed portion of the dielectric layer includes expanding the tape attached to the first surface of the dielectric layer.

16. 10. The method of claim 1, further comprising thinning the semiconductor substrate from the backside before forming the metal layer on the backside of the semiconductor substrate.

17. 10. The method of claim 1, wherein segmenting the metal layer includes removing a sacrificial structure located between the metal layer and the scribe area of ​​the semiconductor substrate.

18. 20. The method of claim 17, wherein the sacrificial structure comprises photoresist.

19. 10. The method of claim 1, wherein segmenting the metal layer comprises: forming a plurality of mask structures on the metal layer, each one of the plurality of mask structures corresponding to a respective one of the dies; removing portions of the metal layer not covered by the plurality of mask structures so as to expose the scribe area of ​​the semiconductor substrate; A method comprising:

20. 1. A method comprising: forming a sacrificial structure on a backside of a semiconductor substrate including a plurality of dies on a front side opposite a backside, the sacrificial structure covering a scribe area of ​​the semiconductor substrate; forming a metal layer over the sacrificial structure and the backside of the semiconductor substrate not covered by the sacrificial structure; removing the sacrificial structure and a portion of the metal layer formed on the sacrificial structure, the scribe area being exposed as a result of removing the sacrificial structure; removing the scribe area of ​​the semiconductor substrate, wherein a portion of a dielectric layer located on the front side of the semiconductor substrate is exposed from the back side as a result of removing the scribe area of ​​the semiconductor substrate; breaking the exposed portion of the dielectric layer; A method comprising:

21. 21. The method of claim 20, wherein the sacrificial structure comprises photoresist.

22. 21. The method of claim 20, wherein removing the portions of the metal layer forms a plurality of metal structures corresponding to the plurality of dies.

23. 23. The method of claim 22, wherein each one of the metal structures includes at least one edge that is aligned with an edge of a corresponding one of the dies.

24. 21. The method of claim 20, wherein removing the scribe area of ​​the semiconductor substrate comprises applying a plasma process having alternating deposition and etching steps.

25. 21. The method of claim 20, wherein removing the scribe areas of the semiconductor substrate forms a non-uniform sidewall profile of each of the plurality of dies.

26. 26. The method of claim 25, wherein the non-uniform sidewall profile comprises a plurality of raised lines substantially parallel to the backside of the semiconductor substrate.

27. 26. The method of claim 25, wherein the non-uniform sidewall profile is substantially perpendicular to the backside of the semiconductor substrate.

28. 21. The method of claim 20, wherein the portion of the dielectric layer that is exposed comprises one or more interlevel metallization layers.

29. 21. The method of claim 20, further comprising deburring the portion of the dielectric layer that is broken.

30. 30. The method of claim 29, wherein removing the burrs comprises utilizing an ultrasonic water jet process that applies ultrasonic vibrations and pressure to a stream of water, the ultrasonic vibrations being in the range of approximately 500 to 3,000 hertz (Hz) and the pressure being in the range of approximately 10 to 40 pounds per square inch (psi).

31. 21. The method of claim 20, further comprising thinning the semiconductor substrate from the backside before forming the sacrificial structure on the backside of the semiconductor substrate.

32. 21. The method of claim 20, further comprising attaching a tape to the dielectric layer after removing the scribe area of ​​the semiconductor substrate, and wherein breaking the exposed portion of the dielectric layer comprises expanding the tape attached to the dielectric layer.

33. 1. A semiconductor die comprising: a semiconductor substrate including integrated circuit elements on a front side of the semiconductor substrate; a metal structure formed on a backside of the semiconductor substrate opposite the frontside, the metal structure having a sidewall profile including a plurality of ridges; a semiconductor die including:

34. 34. The semiconductor die of claim 33, wherein the plurality of ridges are substantially parallel to the backside of the semiconductor substrate.

35. 34. The semiconductor die of claim 33, wherein the plurality of ridges surround the semiconductor substrate.

36. 34. The semiconductor die of claim 33, wherein the sidewall profile is substantially perpendicular to the backside of the semiconductor substrate.

37. 34. The semiconductor die of claim 33, wherein the sidewall profile comprises a ridged surface, a wavy surface, a surface with ridges, a surface with peaks and valleys, or a combination thereof.

38. 34. The semiconductor die of claim 33, wherein the metal structure includes at least one edge that is aligned to a corresponding edge of the semiconductor substrate.

39. 34. The semiconductor die of claim 33, the semiconductor substrate has a first cross-sectional area; the metal structure has a second cross-sectional area substantially the same as the first cross-sectional area; Semiconductor die.

40. 34. The semiconductor die of claim 33, a dielectric layer on the front side of the semiconductor substrate, the dielectric layer further comprising one or more interlevel metallization layers.

41. 41. The semiconductor die of claim 40, wherein at least one edge of the dielectric layer is aligned to a corresponding edge of the semiconductor substrate.

42. 41. The semiconductor die of claim 40, wherein at least one edge of the dielectric layer extends beyond a corresponding edge of the semiconductor substrate.

43. 34. The semiconductor die of claim 33, wherein the integrated circuit element comprises a power field effect transistor (FET).

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