Wet etching process and method for forming air gaps between metal interconnects - Patents.com

Abstract

The present disclosure provides embodiments of improved process flows and methods for forming air gaps between metal interconnects. More specifically, the present disclosure provides improved process flows and methods that utilize a wet etching process to form recesses between metal interconnects formed in a patterned substrate. Unlike conventional air gap integration methods, the improved process flows and methods described herein utilize the critical dimension (CD)-dependent etching provided by the wet etching process to etch inter-metal dielectric material formed between metal interconnects at a faster rate than the inter-metal dielectric material is etched in the surrounding areas of the patterned substrate. This allows the improved process flows and methods described herein to form recesses (and subsequently form air gaps) between metal interconnects without using a dry etching process.

Description

[Technical Field]

[0001] Cross-references to related patents and applications This application claims priority to and the benefit of the filing date of U.S. Non-Provisional Patent Application No. 17 / 942,378, filed September 12, 2022, which is incorporated herein by reference in its entirety.

[0002] This disclosure relates to integrated circuit (IC) processing. In particular, this disclosure provides improved processes and methods for forming air gaps between interconnects on IC chips. [Background technology]

[0003] The continued scaling of integrated circuit (IC) chips has significantly increased the parasitic resistance and capacitance of multilevel interconnects. To reduce capacitance, improve circuit performance, and reduce power consumption, low-k dielectric materials are commonly used as intermetal dielectrics (IMDs) and interlayer dielectrics (ILDs) between metal (e.g., copper or aluminum) interconnects. However, the use of low-k dielectric materials is challenging due to their mechanical strength and process resistance properties, which typically decrease as the k value decreases.

[0004] As an alternative to low-k dielectric materials, low-k values ​​can also be achieved by removing all material from the IMD, thus creating air gaps between metal interconnects. Various air-gap integration techniques have been utilized in the fabrication of multilevel metal interconnects. All air-gap integration processes can be categorized into the following: 1) partial or complete removal of IMD material between metal lines, followed by non-conformal CVD deposition and planarization by chemical-mechanical polishing (CMP), and 2) damascene integration of metal lines with a sacrificial IMD layer that is selectively removed through a permeable dielectric cap.

[0005] Non-conformal CVD processes allow for selective formation of air gaps between metal interconnects while leaving dielectric material in other locations, helping to preserve the mechanical strength of the air-gap interconnects. When sacrificial IMD techniques are used to form air gaps in multilayer interconnect structures, permeable dielectric caps allow for the removal of all sacrificial IMD layers across multiple metal levels after the stack is fully completed. However, sacrificial IMD layers can also be removed after each metal layer is completed. In sacrificial IMD processes, protective caps are typically applied to the metal lines to protect them during the removal of the sacrificial IMD layers.

[0006] One of the biggest concerns regarding air-gap integration in multilevel interconnects is the mechanical integrity of the entire IC stack. Due to the weak mechanical properties of dielectric materials, subsequent packaging process steps (such as wire bonding and molding) can cause cracks within the IC stack, which can lead to short- or long-term electrical failures. Therefore, an IC stack with good mechanical properties is essential for the chips to survive packaging. When air gaps are formed using sacrificial IMD techniques, the mechanical strength of the stack is solely dependent on the metal lines and other cap / barrier dielectrics. Accurate placement of air gaps at specific locations in each metal level is crucial and determines the mechanical integrity of the air-gap interconnect. However, because the CVD dielectric contributes to the stack's mechanical strength over a larger space, non-conformal CVD processes present fewer mechanical integrity issues compared to sacrificial IMD processes.

[0007] 9 (PRIOR ART) illustrates a conventional air gap integration process 10 commonly used to form air gaps in multi-layer interconnects. As shown in FIG. 9(a), the conventional gap integration process 10 may generally begin after using a dual damascene (DD) process to form multiple copper interconnects 15 in a first inter-metal dielectric (IMD) layer 20 formed on one or more underlying layers 25, and performing a chemical mechanical polishing (CMP) process to planarize the first IMD layer 20 to form a planarized surface 30.

[0008] In the conventional air gap integration process 10 shown in FIG. 9 , a portion of the first IMD layer 20 sandwiched between two or more copper interconnects 15 is recessed using a combination of patterning, dry etching, and wet etching processes. As shown in FIG. 9( b), for example, the first IMD layer 20 is recessed using a hard mask (HM) 40, which is patterned by an additional photomask (not shown) for the air gaps to be formed later. The edges of the hard mask 40 overlie the two copper interconnects 15 and form HM open areas that cover one or more spaces between the two or more copper interconnects 15. In the recess formation step shown in FIG. 9( b), the portion of the first IMD layer 20 within the HM open areas is etched away in a self-aligned manner, forming recesses 35 between the interconnects.

[0009] The portions of the first IMD layer 20 in the HM open areas are typically etched by exposing the substrate to a dry etching process or a combination of dry and wet etching processes. In one example process flow, a highly selective dry etching process may be used initially to minimize damage to the copper interconnects 15. However, dry etching processes suffer from etch stop, making it difficult to recess the recesses deep enough to achieve the target recess depth. Therefore, in some process flows, multiple wet etching processes and / or thermal treatments may be performed after the initial dry etching process to compensate for insufficient recess depth. In one example process flow, a first hydrofluoric acid (HF) strip may be performed after the dry etching to remove the dense layer at the bottom of the dry-etched recess. As shown in FIG. 9(b), after the first HF strip, partial pressure ammonia (pNH3) and a second HF strip may be performed to reach the target recess depth and form the recess 35.

[0010] Once the recess 35 is formed to the desired recess depth, non-conformal CV deposition can be used to deposit an air gap liner 50 and a second IMD layer 55, as shown in FIG. 9(c). The air gap liner 50 covers the entire first metal layer, including the recess pattern, and a subsequent IMD deposition process closes the recess 35 via pinching at the top of the IMD recess, forming an air gap 45. After the second IMD layer 55 is deposited on the first metal layer, steps 9(a)-9(c) of the conventional air gap integration process 10 can be repeated to form the air gap 45 in the next metal layer, as shown in FIG. 9(d). Summary of the Invention [Problem to be solved by the invention]

[0011] The conventional air gap integration process 10 shown in Figure 9 utilizes multiple steps after CMP—hard mask patterning, dry etching, and wet etching—to form air gaps 45 between copper interconnects 15. While the recess formation step shown in Figure 9(b) uses a highly selective dry etching process, the dry etching process can still damage the copper interconnects 15 (leading to reduced resistance) and the first IMD layer 20 (leading to reduced capacitance and defect generation). To avoid such damage, there is a continuing need for improved processes and methods for forming air gaps between interconnect structures. [Means for solving the problem]

[0012] The present disclosure provides various embodiments of improved process flows and methods for forming air gaps between metal interconnects. More specifically, the present disclosure provides improved process flows and methods that utilize a wet etching process to form recesses between metal interconnects formed in a patterned substrate. Unlike conventional air gap integration methods, the improved process flows and methods described herein utilize the critical dimension (CD)-dependent etching provided by the wet etching process to etch inter-metal dielectric material formed between metal interconnects at a faster rate than the inter-metal dielectric material is etched in surrounding areas of the patterned substrate. This allows the improved process flows and methods described herein to form recesses (and subsequently form air gaps) between metal interconnects without using a dry etching process.

[0013] In one embodiment, a method for forming air gaps between metal interconnects is provided. Generally, the method may include providing a patterned substrate having a plurality of metal interconnects formed in a first dielectric material layer, wherein a critical dimension (CD) between the metal interconnects is small compared to a surrounding area of ​​the patterned substrate; and exposing the patterned substrate to an etching solution to etch the first dielectric material layer and form recesses between the plurality of metal interconnects, the etching removing portions of the first dielectric material layer disposed between the plurality of metal interconnects at a faster etch rate than the first dielectric material layer is removed in the surrounding area of ​​the patterned substrate. The method may continue etching the first dielectric material layer with the etching solution until the recesses formed between the plurality of metal interconnects reach a target recess depth. After the recesses are formed to the target recess depth, the method may include depositing a second dielectric material layer on the patterned substrate, the depositing step closing the recesses formed between the plurality of metal interconnects to form air gaps between the plurality of metal interconnects.

[0014] In some embodiments, the above-described method may include one or more planarization steps. For example, before exposing the patterned substrate to the etching solution, the method may further include planarizing the patterned substrate to expose the plurality of metal interconnects and to provide a first planarized surface for the first dielectric material layer. After a second dielectric material layer is deposited on the patterned substrate, the method may further include planarizing the second dielectric material layer to provide a second planarized surface and depositing an air gap liner on the second planarized surface.

[0015] A variety of etching solutions may be used to etch the first dielectric layer in the methods described herein, however, the particular etching solution used to etch the first dielectric layer may generally depend on a variety of factors, including, but not limited to, the primary reactive species used in the etching solution, the surface potential of the wall material adjacent to the first dielectric layer being etched when the wall material is exposed to an aqueous solution of a particular pH, and the ability to modify the surface potential of the wall material by adjusting the pH of the etching solution and / or adding a surfactant.

[0016] In some embodiments, the wall material of the plurality of metal interconnects may exhibit a negative surface potential when exposed to an aqueous solution of a particular pH. In such embodiments, exposing the patterned substrate to an etching solution may optionally include exposing the patterned substrate to a non-aqueous organic-based etching solution comprising an organic solvent and an etchant chemical comprising anions as the primary reactive species. When the patterned substrate is exposed to a non-aqueous organic-based etching solution comprising anions as the primary reactive species, the non-aqueous organic-based etching solution may increase the etch rate of portions of the first dielectric material layer disposed between the plurality of metal interconnects compared to the etch rate of the first dielectric material layer in the surrounding areas of the patterned substrate.

[0017] In other embodiments, the wall material of the plurality of metal interconnects may exhibit a positive surface potential when exposed to an aqueous solution at a particular pH. In such embodiments, exposing the patterned substrate to an etching solution may include exposing the patterned substrate to an aqueous-based etching solution comprising an etchant chemical and an aqueous solvent or a non-aqueous organic-based etching solution comprising an etchant chemical and an organic solvent, depending on the predominant reactive species utilized in the etchant chemical. For example, exposing the patterned substrate to an etching solution may include (a) exposing the patterned substrate to an aqueous-based etching solution or a non-aqueous organic-based etching solution when the etchant chemical comprises anions as the predominant reactive species, or (b) exposing the patterned substrate to an aqueous-based etching solution when the etchant chemical comprises cations as the predominant reactive species. When the patterned substrate is exposed to an aqueous-based etching solution or a non-aqueous organic-based etching solution, the aqueous-based etching solution or the non-aqueous organic-based etching solution may increase the etch rate of portions of the first dielectric material layer disposed between the plurality of metal interconnects compared to the etch rate of the first dielectric material layer in the surrounding areas of the patterned substrate.

[0018] In one embodiment, the etchant chemicals used in the non-aqueous organic-based etching solution may include one or more of hydrofluoric acid (HF), ammonium hydroxide (NH4OH), hydrochloric acid (HCl), hydrogen peroxide (HO2), nitric acid (HNO3), phosphoric acid (H3PO4), potassium hydroxide (KOH), and tetramethylammonium hydroxide (TMAH). Organic solvents used in the non-aqueous organic-based etching solution may include methanol (C4O), ethanol (C2H6O), isopropyl alcohol (C3H8O), benzyl alcohol (C7H8O), ethylene glycol (C2H6O2), acetic acid (CH3COOH), acetone (C3H6O), propylene carbonate (C4H6O3), n-hexane (C6H 14 ), cyclohexane (CH 12 ), diethyl ether (C4H 10O), tetrahydrofuran (C4H8O), benzene (C6H6), toluene (C7H8), dichloromethane (CH2Cl2), trichloroethylene (C2HCl3), 1,1,1-trichloroethane (C2H3Cl3), 1,2-dichloroethane (C2H4Cl2), N-methyl-2-pyrrolidone (C5HNO), dimethyl sulfoxide (C2H6OS), ethyl lactate (C5H 10 O3), ethanolamine (C2H7NO) and propylene glycol methyl ether acetate (C6H 12 O3).

[0019] In other embodiments, exposing the patterned substrate to an etching solution may include exposing the patterned substrate to an aqueous-based etching solution comprising an aqueous solvent and an etchant chemical comprising cations as primary reactive species. When the patterned substrate is exposed to the aqueous-based etching solution comprising cations as primary reactive species, the aqueous-based etching solution may increase the etch rate of portions of the first dielectric material layer disposed between the plurality of metal interconnects compared to the etch rate of the first dielectric material layer in surrounding areas of the patterned substrate.

[0020] According to another embodiment, another method for forming air gaps between metal interconnects is provided herein. Generally, the method may include providing a patterned substrate having a plurality of metal interconnects formed in a first dielectric material layer, wherein a critical dimension (CD) between the metal interconnects is small compared to a surrounding area of ​​the patterned substrate; and exposing the patterned substrate to a non-aqueous organic-based etching solution to etch the first dielectric material layer and form recesses between the plurality of metal interconnects, wherein the non-aqueous organic-based etching solution etches portions of the first dielectric material layer disposed between the plurality of metal interconnects faster than the first dielectric material layer is etched in the surrounding area of ​​the patterned substrate. The method may continue etching the first dielectric material layer with the non-aqueous organic-based etching solution until the recesses formed between the plurality of metal interconnects reach a target recess depth. After the recesses are formed to the target recess depth, the method may include depositing a second dielectric material layer on the patterned substrate, said depositing step closing the recesses formed between the plurality of metal interconnects to form air gaps between the plurality of metal interconnects.

[0021] In some embodiments, the non-aqueous organic-based etching solution used to etch the first dielectric material layer may include an etchant chemical and an organic solvent. The etchant chemical may include one or more of hydrofluoric acid (HF), ammonium hydroxide (NH4OH), hydrochloric acid (HCl), hydrogen peroxide (HO), nitric acid (HNO3), phosphoric acid (H3PO4), potassium hydroxide (KOH), and tetramethylammonium hydroxide (TMAH). The organic solvent may include methanol (CHO), ethanol (C2H6O), isopropyl alcohol (C3H8O), benzyl alcohol (C7H8O), ethylene glycol (C2H6O2), acetic acid (CH3COOH), acetone (C3H6O), propylene carbonate (C4H6O3), n-hexane (C6H 14 ), cyclohexane (CH 12 ), diethyl ether (C4H 10O), tetrahydrofuran (C4H8O), benzene (C6H6), toluene (C7H8), dichloromethane (CH2Cl2), trichloroethylene (C2HCl3), 1,1,1-trichloroethane (C2H3Cl3), 1,2-dichloroethane (C2H4Cl2), N-methyl-2-pyrrolidone (C5H9NO), dimethyl sulfoxide (C2H6OS), ethyl lactate (C5H 10 O3), ethanolamine (C2H7NO) and propylene glycol methyl ether acetate (C6H 12 O3).

[0022] As previously mentioned, the etching solution used to etch the first dielectric layer may depend, at least in part, on the predominant reactive species used in the etching solution and the surface potential of the wall material adjacent to the first dielectric layer being etched. In some embodiments, the wall material of the plurality of metal interconnects may exhibit a negative surface potential when exposed to an aqueous solution of a particular pH. If the wall material exhibits a negative surface potential and the etchant chemistry utilized in the non-aqueous organic-based etching solution includes anions as the predominant reactive species, exposing the patterned substrate to the non-aqueous organic-based etching solution may increase the etch rate of the portions of the first dielectric layer disposed between the plurality of metal interconnects compared to the etch rate of the first dielectric layer in the surrounding areas of the patterned substrate. [Effects of the Invention]

[0023] The methods described herein may offer various advantages over conventional methods used to form air gaps between metal interconnects. Unlike conventional methods, the methods described herein use a wet etching process to form recesses between the metal interconnects. In the methods described herein, the recesses formed between the multiple metal interconnects reach a target recess depth without using a dry etching process. This reduces the number of processing steps required to form the recesses to the target recess depth and avoids damage to the metal interconnects and the dielectric material surrounding the recesses. Additionally, the described methods continue to etch the first dielectric material layer with an etching solution to completely remove portions of the first dielectric material layer disposed between the multiple metal interconnects, while preserving the thickness of the first dielectric material layer in the peripheral regions of the patterned substrate. This allows the methods described herein to maintain the mechanical integrity of the subsequently formed air gap interconnects. [Brief explanation of the drawings]

[0024] A more detailed understanding of the present invention and its advantages will be obtained by referring to the following description in conjunction with the accompanying drawings, in which like reference numerals indicate like features, and in which it is to be noted, however, that the accompanying drawings only illustrate exemplary embodiments of the disclosed concepts and are not intended to limit the scope of the present invention, as the disclosed concepts may encompass other embodiments that are equally effective.

[0025] [Figure 1A] 1A-1C are cross-sectional views through a substrate having features of different critical dimensions (CDs) illustrating CD-dependent etching of material within the features when the substrate is exposed to a non-aqueous organic-based etching solution. [Figure 1B] 1A-1C are cross-sectional views through a substrate having features of different critical dimensions (CDs) illustrating CD-dependent etching of material within the features when the substrate is exposed to an aqueous-based etching solution. [Figure 2] 1 is a graph showing normalized etch rate versus feature CD when a substrate is exposed to a non-aqueous organic-based etch solution and an aqueous-based etch solution. [Figure 3] FIG. 1 is a schematic diagram illustrating the zeta potential and the electrical double layer (EDL) that exists between the charged wall surface and the etching solution. [Figure 4] 1 is a graph showing zeta potential versus pH for various wall materials. [Figure 5] 1 is a graph showing zeta potential versus pH for various etching solutions and wall materials. [Figure 6] FIG. 1 is a cross-sectional view of a patterned substrate having a plurality of metal interconnects formed in a dielectric material layer, illustrating one embodiment of an improved process utilizing the techniques described herein to form air gaps between the metal interconnects. [Figure 7] FIG. 1 is a flow chart diagram illustrating one embodiment of a method utilizing the techniques described herein to form air gaps between metal interconnects. [Figure 8] FIG. 10 is a flow chart diagram illustrating another embodiment of a method utilizing the techniques described herein to form air gaps between metal interconnects. [Figure 9] 2 (PRIOR ART) illustrates a conventional non-conformal CVD process commonly used to form air gaps in multi-layer interconnects. DETAILED DESCRIPTION OF THE INVENTION

[0026] The present disclosure provides various embodiments of improved process flows and methods for forming air gaps between metal interconnects. More specifically, the present disclosure provides improved process flows and methods that utilize a wet etching process to form recesses between metal interconnects formed in a patterned substrate. Unlike conventional air gap integration methods, the improved process flows and methods described herein utilize the critical dimension (CD)-dependent etching provided by the wet etching process to etch inter-metal dielectric material formed between metal interconnects at a faster rate than the inter-metal dielectric material is etched in surrounding areas of the patterned substrate. This allows the improved process flows and methods described herein to form recesses (and subsequently form air gaps) between metal interconnects without using a dry etching process.

[0027] In embodiments disclosed herein, a patterned substrate is provided having a plurality of metal interconnects formed in a first dielectric material layer, where the critical dimension (CD) between the metal interconnects is small compared to other areas of the patterned substrate surrounding the metal interconnects. A wet etching process is then used to form recesses in the first dielectric material layer between the plurality of metal interconnects. During the wet etching process, the patterned substrate is exposed to an etching solution that reacts with the first dielectric material layer and promotes dissolution of the reaction products, etching the first dielectric material layer and forming the recesses between the metal interconnects.

[0028] When etching the first dielectric material layer, the rate at which material is removed from the patterned substrate (i.e., the etch rate) can differ compared to the surrounding areas of the patterned substrate depending on various factors, such as the CD of the recesses formed between the metal interconnects, the etchant chemistry used in the etching solution, the solvent used in the etching solution, the ratio of etchant chemistry to solvent used in the etching solution, the pH of the etching solution, and the wall material adjacent to the material being etched. The difference in etch rate is known in the art as CD-dependent etching.

[0029] Because the CD between the metal interconnects is small compared to the peripheral regions of the patterned substrate, the wet etching process described herein removes portions of the first dielectric material layer disposed between the metal interconnects at a faster etch rate than the first dielectric material layer is removed in the peripheral regions of the patterned substrate. The difference in etch rates allows the wet etching process described herein to completely remove portions of the first dielectric material layer disposed between the metal interconnects, thus forming recesses that reach a target recess depth while retaining at least a portion of the first dielectric material layer in the peripheral regions of the patterned substrate. After the recesses formed between the metal interconnects reach the target recess depth, a second dielectric material layer can be deposited on the patterned substrate to close (or "pick out") the recesses and form air gaps between the metal interconnects.

[0030] By utilizing a CD-dependent wet etch and continuing the wet etch process until the recess formed between the metal interconnects reaches a target recess depth, the improved process flows and methods described herein form recesses between the metal interconnects (and subsequently form air gaps) without using a dry etch process. In this manner, the improved process flows and methods described herein reduce the number of processing steps required to form the recesses between the metal interconnects (by eliminating the hard mask patterning and dry etch process steps used in conventional air gap integration methods) and avoid damage to the metal interconnects and dielectric materials while maintaining the mechanical integrity of the air gap interconnects.

[0031] The wet etching process described herein can utilize a variety of etching solutions. For example, a non-aqueous organic-based etching solution or an aqueous-based etching solution can be used to etch the first dielectric material layer and form recesses between the metal interconnects. The etching solution used to etch the first dielectric layer can depend on various factors, including, but not limited to, the primary reactive species used in the etching solution, the surface potential of the wall material adjacent to the first dielectric material layer being etched when the wall material is exposed to an aqueous solution, and the ability to modify the surface potential of the wall material by adjusting the pH of the etching solution or adding a surfactant. In some embodiments, the wall material adjacent to the first dielectric material layer being etched can exhibit a negative surface potential when exposed to an aqueous solution. In such embodiments, the wet etching process disclosed herein can etch the first dielectric material layer faster within the recesses and slower within the surrounding areas of the substrate by using (a) a non-aqueous organic-based etching solution comprising an organic solvent and an etchant chemical comprising anions as the primary reactive species, or (b) an aqueous-based etching solution comprising an aqueous solvent and an etchant chemical comprising cations as the primary reactive species.

[0032] 1A-1B and 2 illustrate CD-dependent etching of deposited materials within features having different CDs and across more planar regions of a substrate when the substrate is exposed to a non-aqueous organic-based etching solution 130 (FIGS. 1A and 2) and an aqueous-based etching solution 140 (FIGS. 1B and 2). As used herein, an aqueous-based etching solution 140 is a solution that includes one or more etchant chemicals mixed with an aqueous solvent (e.g., water (HO) or deionized water). Meanwhile, a non-aqueous organic-based etching solution 130 is a solution that includes one or more etchant chemicals mixed with an organic solvent. In some embodiments, the non-aqueous organic-based etching solution 130 may include an etchant chemical that includes water (e.g., hydrofluoric acid (HF) containing, e.g., 49% HF and 51% water, or ammonium hydroxide (NHOH) containing, e.g., 29% NHOH and 71% water, by weight), and thus may include a minimal amount of water.

[0033] 1A-1B, the substrate 100 includes a plurality of structures 105 (e.g., metal lines, fins, etc.) extending above the surface of the substrate. Each of the plurality of structures 105 is separated by a feature 115 (e.g., a gap, trench, hole, etc.). The critical dimensions (CDs) of the features 115 may be the same or different, as shown in FIGS. 1A-1B. In the exemplary embodiment shown in FIGS. 1A-1B, the substrate 100 is shown as having a first feature 115a having a smaller CD (CD1) and a second feature 115b having a larger CD (CD2). The CDs of the plurality of features 115 are relatively small (e.g., less than 100 nm) compared to the planar regions 120 of the substrate 100 that surround the plurality of structures 105.

[0034] A material 125 to be etched is deposited on the surface of the substrate 100 and within the structures 105 and features 115 formed between the structures 105. The material 125 may include a variety of semiconductor materials. For example, the material 125 may be an oxide, a dielectric material, silicon, or a metal. In one example, the material 125 may be a silicon oxide (e.g., silicon dioxide, SiO2, etc.). Other oxides and dielectric materials, including low-k dielectric materials, may also be formed and etched within the features 105.

[0035] 1A, the substrate 100 is exposed to a non-aqueous, organic-based etching solution 130 that includes one or more etchant chemicals and an organic solvent. Examples of etching chemicals that may be included in the non-aqueous, organic-based etching solution 130 include, but are not limited to, hydrofluoric acid (HF), ammonium hydroxide (NH4OH), hydrochloric acid (HCl), hydrogen peroxide (HO2), nitric acid (HNO3), phosphoric acid (H3PO4), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), and other etching chemicals that include anions (negatively charged ions) as the primary reactive species.

[0036] A variety of organic solvents can be used in the non-aqueous organic-based etching solution 130 described herein. Examples of organic solvents that can be included in the non-aqueous organic-based etching solution 130 include, but are not limited to, various alcohols (e.g., methanol (CHO), ethanol (CHO), isopropyl alcohol (CHO), benzyl alcohol (CHO), etc.), polyhydric alcohols (e.g., ethylene glycol (CHO)), acetic acid (CHCOOH), ketones (e.g., acetone CHO), propylene carbonate (CHO), and the like. 14 O3), alkanes (e.g., n-hexane (C6H6), cyclohexane (C6H 12 ), ethers (e.g., diethyl ether (CH 10 O), tetrahydrofuran (C4H8O), etc.), aromatic hydrocarbons (e.g., benzene (C6H6), toluene (C7H8), etc.), halogen compounds (e.g., dichloromethane (CH2Cl2), trichloroethylene (C2HCl3), 1,1,1-trichloroethane (C2H3Cl3), 1,2-dichloroethane (C2H4Cl2), etc.), nitrogen compounds (e.g., N-methyl-2-pyrrolidone (C5H9NO), etc.), sulfate compounds (e.g., dimethyl sulfoxide (C2H6OS), etc.), and ethyl lactate (C5H 10 O3), ethanolamine (C2H7NO) and propylene glycol methyl ether acetate (C6H 12 Other volatile carbon-based solvents include HCl, HCl, and HClO3.

[0037] In some embodiments, the non-aqueous organic-based etching solution 130 can include an etchant chemical containing anions as the primary reactive species (e.g., hydrofluoric acid, ammonium hydroxide, or hydrochloric acid) mixed with an alcohol (e.g., isopropyl alcohol, IPA), a polyhydric alcohol (e.g., ethylene glycol, EG), acetic acid, AA, or a ketone (e.g., propylene carbonate, PC). In at least one preferred embodiment, the non-aqueous organic-based etching solution 130 can include hydrofluoric acid mixed with IPA, AA, EG, or PC. Other organic solvents described herein can also be mixed with hydrofluoric acid or other etchant chemicals containing anions as the primary reactive species (e.g., NH4OH or HCl). The etchant chemicals described herein can be mixed with many different organic solvents, although the compatibility and solubility of the etchant chemical and the organic solvent must be carefully considered.

[0038] When substrate 100 is exposed to a non-aqueous organic-based etching solution 130 that includes anions as the primary reactive species, depending on the pH of the etching solution and the wall material 110 used to form feature 115, the portion of feature 115 exposed to non-aqueous organic-based etching solution 130 may exhibit a positive surface potential, as shown in Figure 1A. For example, if substrate 100 is exposed to a non-aqueous organic-based etching solution 130 that includes hydrofluoric acid mixed with an organic solvent (e.g., IPA, AA, EG, or PC) and the wall material 110 includes a silicon-containing material such as amorphous silicon (a-Si), polysilicon (poly-Si), silicon nitride (SiN), silicon carbon nitride (SiCN), or silicon oxynitride (SiON), the exposed portion of feature 115 may exhibit a positive surface potential (as shown in Figure 1A). In some cases, the exposed portions of the features 115 may also exhibit a positive surface potential when the conductive wall material 110, such as copper (Cu), aluminum (Al), etc., is exposed to the non-aqueous, organic-based etching solution 130.

[0039] As shown in FIG. 1A and described above, when substrate 100 is exposed to non-aqueous, organic-based etching solution 130, anions in the etchant chemical are attracted to the positively charged surface. This increases the local concentration of anions in feature 115, which in turn increases the etch rate of material 125 deposited in feature 115 compared to flatter regions 120 of substrate 100. Thus, material 125 etches faster in features 115 and slower in flatter regions 120 of substrate 100 surrounding structures 105. This is shown schematically in graph 200 in FIGS. 1A and 2. As shown in FIG. 1A, when features 115 of different CDs are formed within structures 105, the increase in etch rate is more pronounced in features with smaller CDs (e.g., feature 115a) and less pronounced in features with larger CDs (e.g., feature 115b). However, the etch rate within feature 115 is significantly faster than the etch rate achieved over the flatter regions 120 of substrate 100 .

[0040] 1B, the substrate 100 is exposed to an aqueous-based etching solution 140 that includes one or more etchant chemicals and an aqueous solvent. As previously described, the aqueous-based etching solution 140 is a solution that includes an etchant chemical mixed with an aqueous solvent (e.g., water (H2O) or deionized water). Examples of etchant chemicals that may be included in the aqueous-based etching solution 140 include, but are not limited to, hydrofluoric acid (HF), ammonium hydroxide (NH4OH), hydrochloric acid (HCl), hydrogen peroxide (H2O2), nitric acid (HNO3), phosphoric acid (H3PO4), potassium hydroxide (KOH), tetramethylammonium hydroxide (TMAH), and other etchant chemicals that include anions (negatively charged ions) as the primary active species.

[0041] When substrate 100 is exposed to an aqueous-based etching solution 140 containing anions as the primary reactive species, as shown in FIG. 1B, depending on the pH of the etching solution and the wall material 110 used to form feature 115, the portion of feature 115 exposed to aqueous-based etching solution 140 may exhibit a negative surface potential. For example, if substrate 100 is exposed to aqueous-based etching solution 140 containing hydrofluoric acid mixed with water and the wall material 110 includes a silicon-containing material (such as a-Si, poly-Si, SiCN, or SiON) or a conductive material (such as Cu or Al), the exposed portion of feature 115 may exhibit a negative surface potential (as shown in FIG. 1B). However, when substrate 100 is exposed to aqueous-based etching solution 140 containing hydrofluoric acid mixed with water, other silicon-containing materials, such as silicon nitride (SiN), may exhibit a positive surface potential (not shown in FIG. 1B). This is illustrated in FIG. 5 and described in more detail below.

[0042] As shown in FIG. 1B and described above, when substrate 100 is exposed to aqueous-based etching solution 140, the negative surface potential of wall material 110 repels anions in the etchant chemical, reducing their local concentration within feature 115 and thus reducing the etch rate of material 125 deposited within feature 115. As shown in FIG. 1B , when features 115 of different CDs are formed within multiple structures 105, the reduction in etch rate is more pronounced in features with smaller CDs (e.g., feature 115a) and less pronounced in features with larger CDs (e.g., feature 115b). As a result, material 125 etches slower in features with smaller CDs (e.g., feature 105a) and faster in features with larger CDs (e.g., feature 105b). As shown in FIG. 1B , the etch rate across flatter regions 120 of the substrate is significantly faster than the etch rate within feature 115.

[0043] When etching material 125 formed in multiple features 115, the etch rate of material 125 can vary depending on various factors, including the critical dimension (CD) of feature 115, the particular etchant chemistry and / or reactive species used in the etching solution, the particular solvent used in the etching solution, the ratio of etchant chemical to solvent used in the etching solution, and / or the pH of the etching solution. In addition to these factors, the electrical potential of wall material 110 adjacent to the material 125 being etched can also affect the etch rate of material 125, depending on the etching solution used.

[0044] 1A-1B and 2, non-aqueous organic-based etching solution 130 and aqueous-based etching solution 140 can sometimes have opposite effects on etch rate. When non-aqueous organic-based etching solution 130 is used to etch material 125, the etch rate increases in features with smaller CDs (such as feature 115a) and decreases in features with larger CDs (such as feature 115b). However, the opposite is true when aqueous-based etching solution 140 is used to etch material 125. This may be due, at least in part, to the zeta potential and the electrical double layer (EDL) that exists between wall material 110 and the etching solution.

[0045] FIG. 3 is a schematic diagram illustrating the zeta potential and the electric double layer that exists between the wall material and the etching solution. The etching solution contains cations (positively charged ions) and anions (negatively charged ions). When the etching solution contacts a wall material with a negative surface potential, as shown in FIG. 3, the cations in the etching solution are attracted to and adsorbed onto the wall material by electrostatic and / or van der Waals forces. The opposite is true when the etching solution contacts a wall material with a positive surface potential (i.e., the anions in the etching solution are attracted to and adsorbed onto the wall material). This attraction creates an electric double layer (i.e., a layer that does not satisfy electroneutrality) between the wall material and the etching solution.

[0046] According to the Stern model, the electric double layer (EDL) is divided into two parts separated by a plane called the Stern plane. The centers of adsorbed ions are located in the Stern layer between the wall surface and the Stern plane. Ions with centers located beyond the Stern plane form a diffuse layer of the EDL. As shown in Figure 3, the electric potential (Ψ) near the wall surface is divided into two parts: Ψ and Ψ δ (potential at the Stern plane) and varies linearly between Ψ within and beyond the diffusion layer. δ The zeta potential (ζ) decays exponentially with distance from ζ to zero. The zeta potential (ζ) is the potential that exists at the shear plane between the charged wall surface and the etching solution. The zeta potential (ζ) can be positive, zero, or negative, depending on the wall material and the pH of the etching solution.

[0047] FIG. 4 shows a graph 400 illustrating the zeta potential (expressed in mV) versus pH for various wall materials. As shown in FIG. 4, the zeta potential generally increases with decreasing pH and decreases with increasing pH. In some embodiments, the zeta potential between the charged wall surface and the etching solution can be altered by changing the pH of the etching solution (e.g., changing the etchant chemical used in the etching solution or adding an acid or base to the etching solution), as shown in FIG. 4. In other embodiments, the zeta potential between the charged wall surface and the etching solution can be altered by adding a surfactant to the etching solution. In yet another embodiment, the zeta potential between the charged wall surface and the etching solution can be altered by utilizing an organic solvent instead of an aqueous solvent in the etching solution (depending on the pH of the etching solution). This is illustrated in graph 500 shown in FIG. 5.

[0048] Graph 500 shown in FIG. 5 illustrates the zeta potential versus pH for various etching solutions and wall materials (e.g., SiN, a-Si, and SiCN). When hydrofluoric acid (HF) is mixed with an aqueous solvent and used as the etching solution, the zeta potential (denoted by Δ) between the etching solution and the wall material is (a) negative for a-Si and SiCN (resulting in a negatively charged wall surface), and (b) positive for SiN (resulting in a positively charged wall surface). When hydrofluoric acid is mixed with an organic solvent instead of an aqueous solvent, the zeta potential (denoted by ●) is positive for a-Si, SiCN, and SiN (resulting in a positively charged wall surface). Graph 500 shown in FIG. 5 illustrates that the organic solvent has little or no effect on the zeta potential between the etching solution and the already positively charged wall surface, but that the zeta potential between the etching solution and the negatively charged wall surface can (possibly) be altered to a positive surface potential by using an organic solvent instead of an aqueous solvent in the etching solution. This difference in zeta potential may explain, at least in part, the opposing effects that aqueous-based and non-aqueous organic-based etching solutions have on etch rates when etching features with different CDs.

[0049] In graph 500 shown in FIG. 5, an organic solvent is utilized in the HF etching solution to change the zeta potential of negatively charged a-Si or SiCN wall surfaces to a positive surface potential. However, the use of an organic solvent may not be sufficient to shift the zeta potential from a negative surface potential to a positive surface potential on all wall surfaces. In some cases, adjusting the pH of the organic-based etching solution (e.g., by changing the etchant chemistry used in the etching solution or by adding an acid or base to the etching solution) can further adjust the zeta potential to achieve a positive surface potential and the desired CD-dependent etching effect. If the pH cannot be changed (e.g., due to compatibility concerns), a surfactant can be added to the organic-based etching solution to adjust the zeta potential and achieve the desired CD-dependent etching effect. In some cases, all three methods (organic solvents, pH adjustment, and surfactant addition) can be used to induce or enhance the CD-dependent trend.

[0050] In the description provided above, organic-based etching solutions are used (with or without pH adjustment and surfactant addition) to increase the etch rate of materials formed in smaller CD features when: (a) the organic-based etching solution contains anions as the primary reactive species, and (b) the material being etched is adjacent to a wall material that exhibits a negative surface potential in aqueous solution. However, organic-based etching solutions may not provide the desired CD-dependent etching effect in all embodiments. In some embodiments, aqueous-based etching solutions may be used to increase the etch rate of materials formed in smaller CD features when cations are used as the primary reactive species. In some embodiments, the pH can be adjusted and / or surfactants can be added to aqueous-based etching solutions containing cations as the primary reactive species to provide the desired CD-dependent etching effect.

[0051] As described herein, when using different etching solutions, different wall materials, and different CDs, one mechanism that can cause etch rate variations is a mechanism related to surface potential. However, the techniques described herein are not strictly limited to such techniques. Thus, the CD-dependent etch rates described herein can be achieved through other mechanisms, and the etch rate advantages described and obtained using the techniques provided herein are not limited to a particular surface potential mechanism. Rather, other mechanisms can also be utilized to advantage.

[0052] The present disclosure takes advantage of the difference in etch rates that occurs when a wet etching process is used to etch material formed within features (e.g., recesses, trenches, holes, slits, etc.) with relatively small CDs compared to surrounding areas of a substrate. In the present disclosure, the wet etching process is used to form recesses between multiple metal interconnects formed in a first dielectric material layer (e.g., a first IMD layer) of a patterned substrate. During the wet etching process, the patterned substrate is exposed to an etching solution, which removes portions of the first dielectric material layer located between the multiple metal interconnects at a faster etch rate than the first dielectric material layer is removed in surrounding areas of the patterned substrate. The wet etching process disclosed herein continues to etch the first dielectric material layer with the etching solution until the recesses formed between the metal interconnects reach a target recess depth. Once the recesses are formed to the target recess depth, a second dielectric material layer is deposited on the patterned substrate to close (or "pick out") the recesses formed between the metal interconnects and form air gaps between the metal interconnects.

[0053] Unlike conventional air gap integration methods that utilize a combination of hard mask patterning, dry etching, and wet etching processes to form recesses between metal interconnects, the present disclosure provides an integrated wet etching process that completely removes the dielectric material formed between the metal interconnects while retaining at least a portion of the dielectric material in the surrounding areas of the patterned substrate, thereby reducing the number of processing steps required to form the recesses to a target recess depth and avoiding damage to the metal interconnects and the dielectric material surrounding the recesses while maintaining the mechanical integrity of the subsequently formed air gap interconnects.

[0054] 6-8 illustrate various embodiments of an improved process 600 and methods 700 and 800 that utilize the techniques described herein to form air gaps between metal interconnects. It will be appreciated that the embodiments illustrated in FIGS. 6-8 are exemplary only, and that additional processes and methods may utilize the techniques described herein. Furthermore, the steps illustrated in the figures are not intended to be exclusive, and additional processing steps may be added to the embodiments illustrated in FIGS. 6-8. Furthermore, the order of steps is not limited to the order shown in the figures, as different orders may occur and / or various steps may be performed in combination or simultaneously.

[0055] 6, 7, and 8, the improved process 600 and methods 700, 800 may generally begin by providing a patterned substrate having a plurality of metal interconnects 610 formed in a first dielectric material layer 620 (e.g., a first IMD layer) (FIG. 6(a), step 710 of FIG. 7, and step 810 of FIG. 8). As shown in FIG. 6(a), the critical dimension (CD1) between the metal interconnects 610 may be small compared to the surrounding area 650 (CD2) of the patterned substrate.

[0056] The metal interconnect 610 shown in FIG. 6( a) can be formed from a variety of conductive materials, such as aluminum (Al) or copper (Cu), that are commonly used to form metal interconnects in integrated circuits. The metal interconnect 610 generally includes a conductive metal core (e.g., a Cu core), which may be surrounded by one or more layers, such as a barrier layer (to prevent metal diffusion into dielectric layers) and a liner layer (to improve barrier adhesion to the metal core). In one embodiment, a copper interconnect can be formed in a patterned substrate by forming a tantalum nitride barrier, a tantalum liner, a copper seed layer (to initiate metal filling / plating), and finally a bulk (core conductive) copper metal.

[0057] The first dielectric material layer 620 shown in FIG. 6(a) may include a variety of dielectric materials. For example, the first dielectric material layer 620 may include an oxide (e.g., silicon dioxide, SiO2, etc.) or a low-k dielectric material having a dielectric constant (k) lower than that of silicon dioxide (k=3.9). The first dielectric material layer 620 may be formed over one or more underlying layers 630, as known in the art. As shown in FIG. 6(a), the first dielectric material layer 620 may be planarized to expose the plurality of metal interconnects 610 and provide the first dielectric material layer 620 with a planarized surface 640. In some embodiments, a chemical-mechanical polishing (CMP) process may be used to planarize the surface.

[0058] Once a patterned substrate is provided, as shown in FIG. 6(a), the improved process 600 and methods 700, 800 can expose the patterned substrate to an etching solution 660 to etch the first dielectric material layer 620 and form recesses 670 between the metal interconnects 610, as shown in FIG. 6(b), step 720 of FIG. 7, and step 820 of FIG. 8. In some embodiments, the patterned substrate can be exposed to a non-aqueous, organic-based etching solution that includes an organic solvent and an etchant chemical that includes anions (negatively charged ions) as the primary reactive species. In other embodiments, the patterned substrate can be exposed to an aqueous-based etching solution that includes an aqueous solvent and an etchant chemical that includes cations (positively charged ions) as the primary reactive species.

[0059] 6(b), step 720 of FIG. 7, and step 820 of FIG. 8, when the patterned substrate is exposed to the etching solution 660, the portions of the first dielectric material layer 620 disposed between the metal interconnects 610 are removed at a faster rate (i.e., a faster etch rate) than the first dielectric material layer 620 is removed in the peripheral regions 650 of the patterned substrate. The increased etch rate between the metal interconnects 610 is due, at least in part, to the critical dimension (CD1) between the metal interconnects 610 compared to the peripheral regions 650 of the patterned substrate.

[0060] As shown in Figure 6(a), for example, the critical dimension (CD1) between the metal interconnects 610 may be relatively small compared to the peripheral region 650 (CD2) of the patterned substrate. As shown in Figure 6(c), because the CD (CD1) between the metal interconnects 610 is smaller than the peripheral region 650 of the patterned substrate, the etching solution 660 removes the first dielectric material layer 620 faster between the metal interconnects 610 than in the peripheral region 650. The faster etch rate between the metal interconnects 610 forms recesses 670 between the metal interconnects 610 having a recess depth (D2) that is greater than the etch depth (D1) achieved in the peripheral region 650.

[0061] As shown in FIG. 6(d), step 730 of FIG. 7, and step 830 of FIG. 8, the wet etching process is performed to remove the recess 670 to the target recess depth (D T ) is reached. As used herein, a "target recess depth" is substantially equal to the height or thickness of the metal interconnects 610, as shown in FIG. 6(d). Due to the faster etch rate achieved between the metal interconnects 610, the recesses 670 may etch to the target recess depth ( T ) until the recess 670 reaches the target recess depth (D T ), the improved process 600 and methods 700, 800 described herein completely remove the portions of the first dielectric material layer 620 located between the metal interconnects 610 while retaining a particular thickness (T) of the first dielectric material layer 620 in the periphery 650 of the patterned substrate.

[0062] 6(b)-(d) can utilize a variety of etching solutions. For example, a non-aqueous organic-based etching solution or an aqueous-based etching solution can be used to etch the first dielectric material layer 620 and form recesses 670 between the metal interconnects 610. The particular etching solution 660 used in the wet etching process can be selected based on a variety of factors, including, but not limited to, the desired etch rate of the first dielectric material layer 620, the critical dimension (CD1) between the metal interconnects 610, and the surface potential of the wall material adjacent to the dielectric material layer being etched when the wall material is exposed to an aqueous solution at a particular pH.

[0063] As previously mentioned, the metal interconnect 610 may include a conductive metal core (e.g., a Cu core) that may be surrounded by one or more layers (e.g., barrier and / or liner layers, etc.). In some embodiments, the wall material of the conductive metal core (or the barrier / liner layers surrounding the conductive metal core) may exhibit a negative surface potential when exposed to an aqueous solution at a particular pH. In some embodiments, the negative surface potential of the wall material may affect the etch rate of the dielectric material layer being etched, depending on the etching solution used to etch the dielectric material layer.

[0064] In some embodiments, the wet etching process shown in FIGS. 6(b)-(d) can form recesses 670 between the metal interconnects 610 by using a non-aqueous organic-based etching solution containing an organic solvent and an etchant chemical containing anions (negatively charged ions) as the primary reactive species. Examples of etchant chemicals containing organic solvents and anions as the primary reactive species are listed above. When a patterned substrate is exposed to a non-aqueous organic-based etching solution containing anions as the primary reactive species, the non-aqueous organic-based etching solution can cause the exposed portions of the wall material to exhibit a positive surface potential, which attracts the anions in the etchant chemical. This attraction can increase the local concentration of anions within the recesses 670, thereby increasing the etch rate of the portions of the first dielectric material layer 620 disposed between the metal interconnects 610 compared to the etch rate of the first dielectric material layer 620 in the surrounding region 650 of the patterned substrate.

[0065] In another embodiment, the wet etching process shown in Figures 6(b)-(d) can form recesses 670 between the metal interconnects 610 using an aqueous-based etching solution including an aqueous solvent (i.e., water) and an etchant chemistry that includes cations (positively charged ions) as the primary reactive species. When a patterned substrate is exposed to an aqueous-based etching solution that includes cations as the primary reactive species, the aqueous-based etching solution can cause the exposed portions of the wall material to exhibit a negative surface potential, which attracts the cations in the etchant chemistry. This attraction can increase the local concentration of cations within the recesses 670, thereby increasing the etch rate of the portions of the first dielectric material layer 620 disposed between the metal interconnects 610 compared to the etch rate of the first dielectric material layer 620 in the surrounding region 650 of the patterned substrate.

[0066] The wet etching process illustrated in Figures 6(b)-(d) utilizes an etching solution 660 (e.g., a non-aqueous organic-based etching solution with anions as the primary reactive species or an aqueous-based etching solution with cations as the primary reactive species) that provides a faster etch rate between the metal interconnects 610 than in the peripheral region 650 of the patterned substrate. In doing so, the wet etching process illustrated in Figures 6(b)-(d) maintains a particular thickness (T) of the first dielectric material layer 620 in the peripheral region 650 of the patterned substrate while forming the recesses 670 to a target recess depth (D T ) can be formed.

[0067] The aforementioned etching solutions provide faster etching rates between the metal interconnects 610 than in the surrounding area 650 of the patterned substrate when the material being etched (e.g., the first dielectric material layer 620) is adjacent to a wall material that exhibits a negative surface charge when exposed to an aqueous solution of a particular pH. However, the etching solution 660 is not strictly limited to the aforementioned exemplary etching solutions. When the material being etched (e.g., the first dielectric material layer 620) is adjacent to a wall material that exhibits a positive surface charge in an aqueous solution of a particular pH, an alternative etching solution 660 may be used to provide faster etching rates between the metal interconnects 610 than in the surrounding area 650 of the patterned substrate. For example, when the wall surface is positively charged in an aqueous solution, the etching solution 660 may alternatively include (a) an aqueous-based or non-aqueous organic-based etching solution containing anions as the primary reactive species, or (b) an aqueous-based etching solution containing cations as the primary reactive species. In some embodiments, the pH of the etching solution 660 can be adjusted and / or surfactants can be added to the etching solution 660 to modify the surface potential of the wall material adjacent to the material being etched and provide the desired CD-dependent etching effect.

[0068] The wet etching process shown in Figure 6(b)-(d) was used to achieve the target recess depth (D T), the improved process 600 and methods 700, 800 can deposit a second dielectric material layer 680 on the patterned substrate to close (or "pick out") the recess 670 and form air gaps 690 between the metal interconnects 610, as shown in FIG. 6(e), step 740 of FIG. 7, and step 840 of FIG. 8. In some embodiments, the second dielectric material layer 680 can be planarized to provide a second planarized surface 685, as shown in FIG. 6(f), after which an air gap liner 695 is deposited on the second planarized surface 685, as further shown in FIG. 6(g). The second dielectric material layer 680 and the air gap liner 695 can be deposited in FIGS. 6(e) and 6(g) using a variety of known deposition techniques. For example, the second dielectric material layer 680 and the air gap liner 695 may be deposited by spin-on, chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like.

[0069] The process steps illustrated in Figures 6(a)-(g) may generally be used to form air gaps 690 between two or more of the metal interconnects 610 formed in a first metal layer. In some embodiments, the process steps illustrated in Figures 6(a)-(g) may be repeated one or more times to form air gaps 690 between the metal interconnects 610 formed in one or more subsequently formed metal layers overlying the first metal layer. For example, Figure 6(h) illustrates the formation of air gaps 690 between metal interconnects formed in a second metal layer overlying the first metal layer. In some embodiments, the process steps illustrated in Figures 6(a)-(g) may be repeated multiple times to form air gaps 690 in multiple metal layers, which are stacked on top of each other to form a multi-layer interconnect structure.

[0070] The improved process flow 600 and methods 700, 800 disclosed herein may generally be used to form air gaps 690 between metal interconnects 610 formed in one or more metal layers of a patterned substrate. Unlike conventional air gap integration techniques that utilize a combination of hard mask patterning, dry etching, and wet etching processes to form recesses between the metal interconnects, the improved process 600 and methods 700, 800 described herein utilize the integrated wet etching process of Figures 6(b)-(d) to form recesses 670 between the metal interconnects 610. As previously mentioned, the wet etching process illustrated in Figures 6(b)-(d) uses an etching solution 660 to completely remove the dielectric material disposed between the metal interconnects 610 while retaining at least a portion of the dielectric material in the peripheral regions 650 of the patterned substrate. 6(b)-(d), utilizing a wet etching process, the improved processes 600 and methods 700, 800 described herein form recesses 670 between the metal interconnects 610 without using a dry etching process. By avoiding the dry etching process, the improved processes 600 and methods 700, 800 (a) reduce the number of processing steps required to form the recesses 670 between the metal interconnects 610, (b) avoid damage to the metal interconnects 610 and the dielectric material layers 620, 680, and (c) maintain the mechanical integrity of the air gap interconnects formed within the multilayer interconnect structure. As a result, the improved processes 600 and methods 700, 800 described herein offer several advantages over conventional air gap integration techniques.

[0071] As used herein, the term "substrate" refers to and includes a base material or base structure upon which a material is formed. A substrate can include any material portion or structure of a device (especially a semiconductor or other electronic device), such as a base substrate structure (e.g., a semiconductor substrate) or a layer on or overlying the base substrate structure (e.g., a thin film). Thus, the term "substrate" is not intended to be limited to any particular base structure, underlying or overlying layer, patterned or unpatterned layer. Rather, the term "substrate" is intended to include any such layer or base structure and any combination of layers and / or base structures.

[0072] It will be understood that the substrates described herein can include a single material, multiple layers of different materials, one or more layers having regions of different materials or structures therein, etc. These materials can include semiconductors, insulators, conductors, or combinations thereof. For example, the substrate can be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, features, or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate containing a layer of semiconductor material. As used herein, the term "bulk substrate" refers to and includes not only silicon wafers, but also silicon-on-insulator ("SOI") substrates such as silicon-on-sapphire ("SOS") substrates and silicon-on-glass ("SOG") substrates, epitaxial layers of silicon on a base semiconductor substrate, and other semiconductor or optoelectronic materials such as silicon germanium, germanium, gallium arsenide, gallium nitride, and indium phosphide. The substrate can be doped or undoped.

[0073] It should be noted that throughout this specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with this embodiment is included in at least one embodiment of the invention, but do not mean that it is present in all embodiments. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily refer to the same embodiment of the invention. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. In other embodiments, various additional layers and / or structures may be included and / or described features may be omitted.

[0074] Those skilled in the art will understand that the various embodiments described herein can be practiced without one or more of the specific details, or with other alternative and / or additional methods, materials, or components. In other instances, well-known structural, material, or operational details have not been shown or described so as not to obscure aspects of the various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are disclosed in order to provide a detailed understanding of the invention. Nevertheless, the invention can be practiced without the specific details. Furthermore, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

[0075] Further variations and alternative embodiments of the processes and methods described herein will be apparent to those skilled in the art in view of this description. Accordingly, it will be appreciated that the processes and methods described herein are not limited to the examples set forth herein. It is understood that the forms of the processes and methods described herein are to be construed as illustrative embodiments. Various modifications to the implementations may be made. Thus, while the present invention is described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the present invention. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive, and it is intended that such modifications be included within the scope of the present invention. Furthermore, any benefits, advantages, or solutions to problems described herein with respect to particular embodiments are not intended to be construed as essential, required, or essential features or elements of any or all claims.

Claims

1. 1. A method for forming an air gap between metal interconnects, comprising: providing a patterned substrate having a plurality of metal interconnects formed in a first dielectric material layer, wherein a critical dimension (CD) between the metal interconnects is small compared to surrounding areas of the patterned substrate; exposing the patterned substrate to an etching solution to etch the first dielectric material layer and form recesses between the plurality of metal interconnects, the etching removing portions of the first dielectric material layer located between the plurality of metal interconnects at an etch rate that is faster than the first dielectric material layer is removed in the surrounding area of ​​the patterned substrate; continuing to etch the first dielectric material layer with the etching solution until the recesses formed between the plurality of metal interconnects reach a target recess depth; depositing a second layer of dielectric material on the patterned substrate, closing the recesses formed between the plurality of metal interconnects to form air gaps between the plurality of metal interconnects.

2. 10. The method of claim 1, further comprising planarizing the patterned substrate prior to exposing the patterned substrate to expose the plurality of metal interconnects and to provide a planarized surface for the first dielectric material layer.

3. 10. The method of claim 1, further comprising, after depositing the second dielectric material layer on the patterned substrate, planarizing the second dielectric material layer to provide a planarized surface; and depositing an air gap liner on the planarized surface.

4. 2. The method of claim 1, wherein the step of continuing to etch the first dielectric material layer with the etching solution completely removes the portions of the first dielectric material layer disposed between the plurality of metal interconnects while preserving a thickness of the first dielectric material layer in the periphery area of ​​the patterned substrate.

5. The method of claim 1 , wherein the etching solution is a non-aqueous, organic-based etching solution comprising an etchant chemical and an organic solvent.

6. The etchant chemicals include hydrofluoric acid (HF), ammonium hydroxide (NH ４ OH), hydrochloric acid (HCl), hydrogen peroxide (H ２ O ２ ), nitric acid (HNO ３ ), phosphoric acid (H ３ P.O. ４ 6. The method of claim 5, wherein the solvent comprises one or more of: potassium hydroxide (KOH), and tetramethylammonium hydroxide (TMAH).

7. The organic solvent is methanol (CH ４ O), ethanol (C ２ H ６ O), isopropyl alcohol (C ３ H ８ O), benzyl alcohol (C ７ H ８ O), ethylene glycol (C ２ H ６ O ２ ), acetic acid (CH ３ COOH), acetone (C ３ H ６ O), propylene carbonate (C ４ H ６ O ３ ), n-hexane (C ６ H １４ ), cyclohexane (C ６ H １２ ), diethyl ether (C ４ H １０ O), tetrahydrofuran (C ４ H ８ O), benzene (C ６ H ６ ), toluene (C ７ H ８ ), dichloromethane (CH ２ Cl ２ ), trichloroethylene (C ２ HCl ３ ), 1,1,1-trichloroethane (C ２ H ３ Cl ３ ), 1,2-dichloroethane (C ２ H ４ Cl ２ ), N-methyl-2-pyrrolidone (C ５ H ９ NO), dimethyl sulfoxide (C ２ H ６ OS), ethyl lactate (C ５ H １０ O ３ ), ethanolamine (C ２ H ７ NO) and propylene glycol methyl ether acetate (C ６ H １２ O ３ 6. The method of claim 5, comprising one or more of:

8. The method of claim 1 , wherein the wall material of the plurality of metallic interconnects exhibits a negative surface potential when exposed to an aqueous solution at a particular pH.

9. 10. The method of claim 8, wherein exposing the patterned substrate to the etching solution comprises exposing the patterned substrate to a non-aqueous, organic-based etching solution comprising an etchant chemical and an organic solvent, wherein the etchant chemical comprises anions as the primary reactive species.

10. 10. The method of claim 9, wherein the step of exposing the patterned substrate to the non-aqueous organic-based etching solution increases an etch rate of the portions of the first dielectric material layer disposed between the plurality of metal interconnects compared to an etch rate of the first dielectric material layer in the peripheral regions of the patterned substrate.

11. 10. The method of claim 8, wherein exposing the patterned substrate to the etching solution comprises exposing the patterned substrate to an aqueous-based etching solution comprising an etchant chemical and an aqueous solvent, the etchant chemical comprising cations as primary reactive species.

12. 12. The method of claim 11 , wherein the step of exposing the patterned substrate to the aqueous-based etching solution increases an etch rate of the portions of the first dielectric material layer disposed between the plurality of metal interconnects compared to an etch rate of the first dielectric material layer in the peripheral regions of the patterned substrate.

13. The method of claim 1 , wherein the wall material of the plurality of metallic interconnects exhibits a positive surface potential when exposed to an aqueous solution at a particular pH.

14. 14. The method of claim 13, wherein exposing the patterned substrate to the etching solution comprises exposing the patterned substrate to an aqueous-based etching solution comprising an etchant chemical and an aqueous solvent or a non-aqueous, organic-based etching solution comprising the etchant chemical and an organic solvent.

15. The step of exposing the patterned substrate to the etching solution comprises: exposing the patterned substrate to the aqueous-based etching solution or the non-aqueous organic-based etching solution when the etchant chemical contains anions as the primary reactive species; and exposing the patterned substrate to the aqueous-based etching solution when the etchant chemical contains cations as the primary reactive species.

16. 16. The method of claim 15, wherein the step of exposing the patterned substrate to the aqueous-based etching solution or the non-aqueous organic-based etching solution increases an etch rate of the portions of the first dielectric material layer disposed between the plurality of metal interconnects compared to an etch rate of the first dielectric material layer in the surrounding areas of the patterned substrate.

17. The method of claim 1 , wherein the recesses formed between the plurality of metal interconnects reach the target recess depth without the use of a dry etching process.

18. 1. A method for forming an air gap between metal interconnects, comprising: providing a patterned substrate having a plurality of metal interconnects formed in a first dielectric material layer, wherein a critical dimension (CD) between the metal interconnects is small compared to surrounding areas of the patterned substrate; exposing the patterned substrate to a non-aqueous organic-based etching solution to etch the first dielectric material layer and form recesses between the plurality of metal interconnects, the non-aqueous organic-based etching solution etching portions of the first dielectric material layer disposed between the plurality of metal interconnects faster than the first dielectric material layer is etched in the surrounding areas of the patterned substrate; continuing to etch the first dielectric material layer with the non-aqueous organic-based etching solution until the recesses formed between the plurality of metal interconnects reach a target recess depth; depositing a second layer of dielectric material on the patterned substrate, closing the recesses formed between the plurality of metal interconnects to form air gaps between the plurality of metal interconnects.

19. 20. The method of claim 18, wherein the step of continuing to etch the first dielectric material layer with the non-aqueous organic-based etching solution completely removes the portions of the first dielectric material layer disposed between the plurality of metal interconnects while preserving a thickness of the first dielectric material layer in the perimeter region of the patterned substrate.

20. 20. The method of claim 18, wherein the non-aqueous organic-based etching solution comprises an etchant chemical and an organic solvent.

21. The etchant chemicals include hydrofluoric acid (HF), ammonium hydroxide (NH ４ OH), hydrochloric acid (HCl), hydrogen peroxide (H ２ O ２ ), nitric acid (HNO ３ ), phosphoric acid (H ３ P.O. ４ 21. The method of claim 20, wherein the solvent comprises one or more of: potassium hydroxide (KOH), and tetramethylammonium hydroxide (TMAH).

22. The organic solvent is methanol (CH ４ O), ethanol (C ２ H ６ O), isopropyl alcohol (C ３ H ８ O), benzyl alcohol (C ７ H ８ O), ethylene glycol (C ２ H ６ O ２ ), acetic acid (CH ３ COOH), acetone (C ３ H ６ O), propylene carbonate (C ４ H ６ O ３ ), n-hexane (C ６ H １４ ), cyclohexane (C ６ H １２ ), diethyl ether (C ４ H １０ O), tetrahydrofuran (C ４ H ８ O), benzene (C ６ H ６ ), toluene (C ７ H ８ ), dichloromethane (CH ２ Cl ２ ), trichloroethylene (C ２ HCl ３ ), 1,1,1-trichloroethane (C ２ H ３ Cl ３ ), 1,2-dichloroethane (C ２ H ４ Cl ２ ), N-methyl-2-pyrrolidone (C ５ H ９ NO), dimethyl sulfoxide (C ２ H ６ OS), ethyl lactate (C ５ H １０ O ３ ), ethanolamine (C ２ H ７ NO) and propylene glycol methyl ether acetate (C ６ H １２ O ３ 21. The method of claim 20, comprising one or more of:

23. 21. The method of claim 20, wherein a wall material of the plurality of metal interconnects exhibits a negative surface potential when exposed to an aqueous solution at a particular pH, the etchant chemical comprises anions as a primary reactive species, and the step of exposing the patterned substrate to the non-aqueous organic-based etching solution increases the etch rate of the portions of the first dielectric material layer disposed between the plurality of metal interconnects compared to the etch rate of the first dielectric material layer in the surrounding areas of the patterned substrate.

24. 20. The method of claim 18, wherein the recesses formed between the plurality of metal interconnects reach the target recess depth without the use of a dry etching process.

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