Analog-to-Digital Conversion

Abstract

A method, system, and apparatus for an analog-to-digital converter includes an MSB DAC array configured to generate sample values ​​for each of one or more most significant bits of an output ADC value, a first LSB DAC array configured to generate sample values ​​for each of one or more least significant bits of the output ADC value, and a second LSB DAC array configured to generate sample values ​​for each of the one or more least significant bits of the output ADC value, wherein each of the first LSB DAC array and the second LSB DAC array is configured to alternately generate an output ADC bit value and a mismatch error value for the output ADC bit value.

Description

[Background technology]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS background A successive approximation (SAR) analog-to-digital converter (ADC) uses a binary search to convert a continuous analog waveform into a discrete digital representation. The most significant bit (MSB) of the ADC is used as the approximation that is compared to the sample value. In the binary search, the MSB is half the maximum value the ADC can provide. If the sample value is greater than the MSB, then the MSB is retained and the next consecutive bit is added to the approximation. In the binary search, the next consecutive bit is half the MSB. This process continues until the approximation of the retained bit is greater than the sample value. If the approximation is greater than the sample value, then the most recently added bit is not retained in the approximation. As each individual bit is retained or removed from the approximation, the approximation approaches the sample value.

[0002] For example, linearity in the signal-to-noise and distortion ratio (SNDR) is an important metric that can represent or be used to determine the accuracy of analog-to-digital conversion. One way to improve linearity in a SAR ADC is by using data-weighted averaging (DWA) on the MSB. DWA involves switching in multiple capacitors of the same value. Using multiple capacitors of the same value can be useful because the average value of multiple capacitors is more likely to be closer to the desired MSB value than a single capacitor (e.g., due to manufacturing tolerances). However, DWA is generally only useful for digital-to-analog converters (DACs) for temperature measurements, where the DAC is not scaled. If the DAC includes scaling, such as binary scaling, the linearity performance of DWA degrades.

[0003] Another method for improving linearity in SAR ADCs involves using mismatch error shaping (MES). MES works by sampling from the top plate of the ADC's capacitor, adding the LSB error from the previous sample to the current input in the analog domain, and then removing the same error from the digital domain. However, traditional MES is only useful with top-plate sampling and is incompatible with bottom-plate sampling. Summary of the Invention

[0004] This specification describes an ADC that uses bottom plate sampling to convert a continuous analog waveform into a discrete digital representation. The ADC includes a first DAC array that provides the MSB of the conversion, and a second and third DAC array that can each provide the LSB of the conversion. The ADC can be switched between two configurations, where one of the LSB DAC arrays provides the LSB of the conversion and the other LSB DAC array provides the error of the previous conversion. Switching between the two configurations allows the ADC to use bottom plate sampling, which provides high linearity, and with mismatch error shaping, which improves conversion accuracy when mismatched capacitors are present.

[0005] Certain embodiments of the subject matter described herein can be implemented to achieve one or more of the following advantages. For example, certain embodiments increase the linearity of the conversion, for example, through bottom plate sampling. Additionally, some embodiments reduce errors in the MSBs of the conversion, for example, through weighted averaging of the data. Other advantageous embodiments enable bottom plate sampling and mismatch error shaping, which further increases the linearity of the conversion.

[0006] In one aspect, an analog-to-digital converter (ADC) includes a most significant bit (MSB) digital-to-analog converter (DAC) array configured to generate respective sample values ​​for one or more most significant bits of an output analog-to-digital value, a first least significant bit (LSB) DAC array configured to generate respective sample values ​​for one or more least significant bits of the output ADC value, and a second LSB DAC array configured to generate respective sample values ​​for one or more least significant bits of the output ADC value, wherein each DAC array of the first LSB DAC array and the second LSB DAC array is configured to alternately generate an output ADC bit value and a mismatch error value for the output ADC bit value.

[0007] In some implementations, the MSB DAC array is configured to generate sample values ​​using data weighted averaging.

[0008] In some implementations, the first LSB DAC and the second LSB DAC are configured to generate their respective sample values ​​using bottom plate sampling.

[0009] In some implementations, the first LSB DAC and the second LSB DAC are configured to generate their respective sample values ​​using mismatch error shaping in conjunction with bottom plate sampling.

[0010] In some implementations, the MSB DAC array includes a plurality of capacitors having substantially the same value, each of the plurality of capacitors representing one-half of the maximum value produced by the analog-to-digital converter.

[0011] In some implementations, the first LSB DAC array includes a plurality of capacitors having substantially different values, each of the plurality of capacitors having a value less than a most significant bit of the output ADC value.

[0012] In some implementations, each of the plurality of capacitors in the first LSB DAC array follows a doubling sequence.

[0013] In some implementations, the first LSB DAC array includes a plurality of capacitors and the second LSB DAC array includes a plurality of capacitors that are substantially the same as the capacitors of the first LSB DAC array.

[0014] The details of one or more embodiments of the subject matter herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram of an exemplary system. [Figure 2A] 1 shows a simulation of an exemplary system. [Figure 2B] 2B is a plot showing the signal-to-noise-plus-distortion ratio of the system of FIG. 2A. [Figure 3] 1 is a flowchart of an exemplary process for sampling an analog-to-digital converter. [Figure 4] 1 is a model of the behavior of a bottom plate sampled ADC. DETAILED DESCRIPTION OF THE INVENTION

[0016] Like reference symbols and designations in the various drawings refer to like elements.

[0017] 1 is a diagram of an exemplary system 100. The system 100 includes an analog-to-digital converter (ADC) 100 in a first configuration 102 and a second configuration 104. The system 100 can switch between the first configuration 102 and the second configuration 104 to provide high linearity for a successive approximation (SAR) ADC.

[0018] In the first configuration 102, multiple digital-to-analog converter (DAC) arrays 106, 108, and 110 are electrically connected to a comparator 112. Each DAC array 106, 108, and 110 includes a capacitor capable of providing a voltage value to the comparator 112. The first DAC array 106 includes one or more capacitors with the same capacitance value, thereby providing substantially the same voltage value to the comparator 112. Providing the same value to multiple capacitors can reduce errors resulting from capacitance values, for example, due to manufacturing tolerances. For example, data weighted averaging (DWA) can utilize multiple capacitors with substantially the same capacitance value to reduce errors from slight variations in capacitance values. Each capacitor in the first DAC array 106 represents a most significant bit (MSB) of the conversion. The MSB is half the maximum value that the ADC can provide.

[0019] The second DAC array 108 includes one or more capacitors. In embodiments with multiple capacitors, each capacitor has a different capacitance value. For example, the capacitors can provide voltages that follow a doubling sequence, e.g., the capacitor value doubles along the array. In some examples, the voltages do not follow a doubling sequence. For example, each capacitor can provide a voltage that is greater than the previous capacitor by a predetermined step value, e.g., 1 volt, 10 volts, or 100 volts.

[0020] The capacitors of the second DAC array 108 represent the least significant bits (LSBs) of the conversion. For example, the LSB can be any value less than the MSB. In some implementations, the MSB provides the most bit in the binary search, and the LSB provides one bit less than the MSB. In other implementations, the MSB provides the most bit in the binary search, and the LSBs each provide 10 bits less than the MSB. Each additional bit provided by the LSB makes the conversion more accurate. For example, because the ADC is limited to the accuracy of the LSB, providing 10 bits in the LSB is more accurate than providing 1 bit. In some implementations, the LSB can provide between 1 and 10 additional bits.

[0021] The largest capacitor in the second DAC array 108 may provide half the capacitance of the capacitors in the first DAC array 106. For example, if the largest capacitor in the second DAC array provides 16 volts, then each capacitor in the first DAC array may provide 32 volts. The third DAC array 110 is substantially identical to the second DAC array 108 and includes capacitors having the same capacitance values ​​as the second DAC array 108.

[0022] The system 100 of the first configuration 102 can determine a digital output of an incoming signal sample 114 using a binary search process. A comparator 112 compares the incoming signal sample 114 to an approximation of a first capacitance value provided by one of the capacitors of the first DAC array 106. If the comparator determines that the sample value is greater than the first capacitance provided by the first DAC array 106, then the first capacitance is retained and a second capacitance provided by the largest capacitor of the second DAC array is added to the approximation. However, if the comparator determines that the sample value is not greater than the first capacitance, then the first capacitance is omitted and the sample is compared to the approximation of the second capacitance. This process is repeated until all of the capacitors of the second DAC array have either been added to or omitted from the approximation. Each configuration 102, 104 functions by sampling the bottom plates of the capacitors in the DAC array. Sampling the bottom plates is advantageous and increases the linearity of the conversion.

[0023] Due to errors in the capacitance value of the capacitors (e.g., due to manufacturing tolerances), the ADC may have a corresponding error in the conversion. This error is also referred to as a mismatch error. The system 100 provides two configurations 102, 104, and after each sampling iteration, by switching between the two configurations 102, 104, for example, using a switch, allows the bottom plate sampling to subtract an error in LSBs from the next successive sample. For example, the configuration 102 can provide a second input 116 in the third DAC array 110, thereby providing a voltage corresponding to the error in LSBs in the previous sample. In the next iteration, the system utilizes the configuration 104. In the configuration 104, the second input 118 is provided in the second DAC array 108. The second input 118 provides a voltage corresponding to the error in LSBs in the previous sample. In other words, in each iteration in which the second DAC array is used to approximate the value of a sample, for example, through successive approximation, the third DAC array receives the previous error in LSBs as input 116. For each iteration in which the third DAC array is used to approximate the value of the sample, the second DAC array receives the previous error in LSBs as input 118. These additional inputs and DAC arrays allow for the error in LSBs to be taken into account while still providing bottom plate sampling. Both of these features increase the linearity of the conversion, e.g., increasing the SNDR and accuracy of the conversion.

[0024] Three signals 122, 124, and 126 are shown at the bottom of FIG. 1. Signals 122, 124, and 126 indicate that the timing of the switch closures is adjusted to achieve the described LSB correction and alternating switching between the two LSB-DACs. Signal 122 represents the input signal 114. The increase in signal 122 is the sample voltage converted by the ADC. Signal 124 represents the sample voltage, e.g., input signal 122, and the additional error input 116 to the ADC 100. As shown, signal 124 is slightly larger than input signal 122. Signal 124 is slightly larger because it includes the LSB error as an additional input. Signal 126 represents the output of the ADC 100 as a result of signal 124. The ADC 100 converts signal 124, e.g., input signal 114 plus error 116, into a digital signal. The ADC 100 outputs signal 126 after receiving signal 124 as an input. This is repeated for each cycle of sampling, for example, cycles N, N+1, etc.

[0025] FIG. 2A shows the results of a simulation of an analog-to-digital converter 200 using the techniques described herein. The ADC 200 has capacitors with values ​​that simulate manufacturing variations that would be encountered when using an actual physical device. Ideally, the capacitors would provide exactly the intended capacitance value. However, in real-world systems, capacitors may provide values ​​that differ slightly from the intended capacitance value. The different values ​​in the simulated converter 200 simulate variations in capacitance due to, for example, manufacturing tolerances. In the ADC 200, the first capacitor 202 provides a capacitance value that is four-fifths of the capacitance value of the corresponding capacitor 204. The first capacitor 202 and the second capacitor 204 may have the same intended value. Similarly, the third capacitor 206 provides a capacitance value that is three-fifths of the capacitance value of the corresponding capacitor 208, even though the third capacitor 206 and the fourth capacitor 208 may have the same intended value. By providing capacitors with slightly different values, the simulated converter 200 provides a simulation of a real-world converter.

[0026] FIG. 2B illustrates the linearity, and particularly the SNDR, of ADC 200 using different sampling techniques. For example, sample 210 illustrates the SNDR of ADC 200 without using the above-described techniques. Sample 210 illustrates the SNDR of an ADC that does not compensate for mismatch errors between capacitors 202 and 204 and between capacitors 206 and 208. SNDR is calculated by integrating noise and distortion from 0 kHz to 20 kHz. As illustrated, the SNDR of sample 210 is 56.6 decibels (dB). After converting the received signal and providing desired signal 212, sample 210 also provides multiple undesired signals 214 corresponding to harmonics, such as the third harmonic, the fifth harmonic, etc. Each of the undesired signals 214 reduces the linearity and SNDR of sample 210.

[0027] In comparison, sample 216 shows the SNDR of ADC 200 while using the technique described above (i.e., switching between the first and second configurations to subtract the LSB error). Sample 216 shows the SNDR of the ADC while compensating for the error between capacitors 202, 204 and between capacitors 206, 208. As shown, the SNDR of sample 214 is 71.1 dB. After providing desired signal 212, sample 216 does not provide the undesired signal 214 provided by sample 210. With undesired signal 214 reduced, the linearity and SNDR of sample 216 are significantly improved, indicating that sample 216 is a more accurate representation of the signal.

[0028] 3 illustrates a flowchart of an example process 300 for sampling an analog-to-digital converter. The example process may be performed by one or more components of an analog-to-digital converter. The example process is described as being performed by, for example, ADC 100 of FIG. 1 , suitably configured in accordance with this specification.

[0029] Initially, the ADC receives an analog signal in a first configuration (302). For example, the first configuration may be similar to configuration 102 of system 100 described above. The first configuration may function by sampling the bottom plates of the capacitors in the DAC array. Sampling the bottom plates is advantageous and increases the linearity of the conversion.

[0030] The ADC determines a digital output of the received analog signal (304). For example, determining the digital output may include successive approximation. As described above, the ADC may include a multiple DAC array to determine the digital output through a binary search process.

[0031] The ADC determines an error in the digital output (306). For example, determining the error can include determining an error in the least significant bit (LSB) of the sample. Determining the error in the least significant bit (LSB) can include retaining the previous LSB code, i.e., which capacitor contributed to the approximation, during sampling.

[0032] The ADC switches from the first configuration to the second configuration 308. For example, the second configuration may be similar to configuration 104 described above. The ADC can switch between the first and second configurations as described above.

[0033] The ADC receives the analog signal in a second configuration 310. For example, the second configuration can have an input for receiving the analog signal, as described above.

[0034] The ADC provides a voltage corresponding to the determined error (312). For example, as described above, the arrangement 104 provides a second input 118 to provide a voltage corresponding to the error in LSBs in the previous sample. In some implementations, the input voltage may be the error in LSBs with the opposite polarity.

[0035] The ADC determines a digital output of the analog signal 314. If the ADC is provided with the previous mismatch error in LSB as an additional input, the determined digital output takes the error into account while providing bottom plate sampling as described above.

[0036] Figure 4 shows a behavioral model 400 of a bottom-plate sampled SAR-ADC. For example, the ADC can alternate (ping-pong) between the two LSB DACs as described above. Both mismatch errors can be filtered with a first-order high-pass filter. As shown, when either LSB DAC receives a signal, the previous error is added as an additional input. For example, LSB The signal 402 received at [n-1] 404 is the signal with the previous error E added to it. 1(または2) [n] 406. The next LSB signal 408 is LSB [n] Received at 410 and the previous error E 2(または1) [n] 412 is added as an additional input. As shown, the error is 1(または2) 406 and E 2(または1) 412. This indicates that the process switches between the two LSB DACs, so the error corresponds to the opposite DAC.

[0037] Embodiments of the subject matter and functional operations described herein can be implemented in digital electronic circuitry in computer hardware including the structures disclosed herein and their structural equivalents, or one or more combinations thereof. The processes and logic flows can also be performed by special purpose logic circuitry (e.g., FPGAs or ASICs) or by a combination of special purpose logic circuitry and one or more programmed computers.

[0038] In addition to the above-mentioned embodiments, the following embodiments are also innovative.

[0039] Embodiment 1 is a most significant bit (MSB) digital-to-analog converter (DAC) array configured to generate respective sample values ​​for one or more most significant bits of the output analog-to-digital value; a first least significant bit (LSB) DAC array configured to generate a sample value for each of one or more least significant bits of the output ADC value; a second LSB DAC array configured to generate a sample value for each of the one or more least significant bits of the output ADC value; Equipped with each DAC array of the first LSB DAC array and the second LSB DAC array is configured to alternately generate an output ADC bit value and a mismatch error value of the output ADC bit value; It is an analog-to-digital converter (ADC).

[0040] Embodiment 2 is the ADC of embodiment 1, wherein the MSB DAC array is configured to generate the sample values ​​using data weighted averaging.

[0041] Embodiment 3 is the ADC of any one of embodiments 1 to 2, wherein the first LSB DAC array and the second LSB DAC array are configured to generate the respective sample values ​​using bottom plate sampling.

[0042] Example 4 is the ADC of example 3, wherein the first LSB DAC array and the second LSB DAC array are configured to generate their respective sample values ​​using mismatch error shaping with bottom plate sampling.

[0043] Embodiment 5 is the ADC of embodiment 3, wherein the MSB DAC array comprises a plurality of capacitors having substantially the same value, each of the plurality of capacitors representing one-half of a maximum value generated by the analog-to-digital converter.

[0044] Embodiment 6 is the ADC of any one of embodiments 1 to 5, wherein the first LSB DAC array comprises a plurality of capacitors having substantially different values, each of the plurality of capacitors having a value less than a most significant bit of the output ADC value.

[0045] A seventh embodiment is the ADC according to any one of the first to sixth embodiments, wherein each of the plurality of capacitors in the first LSB DAC array follows a doubling sequence.

[0046] Embodiment 8 is the ADC of any one of embodiments 1 to 7, wherein the first LSB DAC array comprises a plurality of capacitors, and the second LSB DAC array includes a plurality of capacitors that are substantially the same as the capacitors of the first LSB DAC array.

[0047]

[0023] Embodiment 9 is a method performed by an analog-to-digital converter (ADC), the method comprising: generating, by a most significant bit (MSB) digital-to-analog converter (DAC) array of the ADC, sample values ​​for each of one or more most significant bits of an output analog-to-digital value; generating, by a first least significant bit (LSB) DAC array of the ADC, sample values ​​for each of one or more least significant bits of the output ADC value; generating, by a second LSB DAC array of the ADC, sample values ​​for each of the one or more least significant bits of the output ADC value; generating an output ADC bit value and a mismatch error value for the output ADC bit value alternately with each of the first LSB DAC array and the second LSB DAC array; Includes.

[0048] Example 10 is the method of example 9, further comprising generating the sample values ​​by the MSB DAC array using data weighted averaging.

[0049] Embodiment 11 is the method of any one of embodiments 9 to 10, wherein generating the respective sample values ​​by the first LSB DAC array and the second LSB DAC array includes generating the sample values ​​using bottom plate sampling.

[0050] Example 12 is the method of example 11, wherein generating the respective sample values ​​by the first LSB DAC array and the second LSB DAC array includes generating the sample values ​​using mismatch error shaping in conjunction with bottom plate sampling.

[0051]

[0023] Embodiment 13 is the method of embodiment 11, wherein the MSB DAC array comprises a plurality of capacitors having substantially the same value, each of the plurality of capacitors representing one-half of the maximum value generated by the analog-to-digital converter.

[0052] Embodiment 14 is the method according to any one of embodiments 9 to 13, wherein the first LSB DAC array comprises a plurality of capacitors having substantially different values, each of the plurality of capacitors having a value less than a most significant bit of the output ADC value.

[0053] Embodiment 15 is the method according to any one of embodiments 9 to 14, wherein each of the plurality of capacitors of the first LSB DAC array follows a doubling sequence.

[0054] Embodiment 16 is the method of any one of embodiments 9 to 15, wherein the first LSB DAC array comprises a plurality of capacitors, and the second LSB DAC array includes a plurality of capacitors that are substantially the same as the capacitors of the first LSB DAC array.

[0055] While the specification contains many specific implementation details, these should not be construed as limitations on the scope of any invention or the scope of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of a particular invention. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features of the invention that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, even if features may be described above as functioning in a particular combination and originally claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to subcombinations or variations of the subcombination.

[0056] Similarly, while operations are shown in the figures in a particular order, this should not be understood as requiring such operations to be performed in the particular order or sequence shown, or that all of the illustrated operations be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated into a single software product or packaged into multiple software products.

[0057] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As an example, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some particular cases, multitasking and parallel processing may be advantageous.

Claims

1. an analog-to-digital converter (ADC), a most significant bit (MSB) digital-to-analog converter (DAC) array configured to generate respective sample values ​​for one or more most significant bits of the output analog-to-digital value; a first least significant bit (LSB) DAC array configured to generate respective sample values ​​for one or more least significant bits of the output ADC value; a second LSB DAC array configured to generate a sample value for each of the one or more least significant bits of the output ADC value; Equipped with an analog-to-digital converter (ADC), wherein each DAC array of the first LSB DAC array and the second LSB DAC array is configured to alternately generate an output ADC bit value and a mismatch error value of the output ADC bit value;

2. The ADC of claim 1 , wherein the MSB DAC array is configured to generate the sample values ​​using data weighted averaging.

3. The ADC of claim 1 or 2, wherein the first LSB DAC array and the second LSB DAC array are configured to generate the respective sample values ​​using bottom plate sampling.

4. The ADC of claim 3 , wherein the first LSB DAC array and the second LSB DAC array are configured to generate their respective sample values ​​using mismatch error shaping in conjunction with bottom plate sampling.

5. 4. The ADC of claim 3, wherein the MSB DAC array comprises a plurality of capacitors having substantially the same value, each of the plurality of capacitors representing one-half of the maximum value produced by the analog-to-digital converter.

6. 3. The ADC of claim 1, wherein the first LSB DAC array comprises a plurality of capacitors having substantially different values, each of the plurality of capacitors having a value less than a most significant bit of the output ADC value.

7. 3. The ADC of claim 1, wherein each of the plurality of capacitors of the first LSB DAC array follows a doubling sequence.

8. 3. The ADC of claim 1, wherein the first LSB DAC array comprises a plurality of capacitors, and the second LSB DAC array includes a plurality of capacitors that are substantially the same as the capacitors of the first LSB DAC array.

9. A method performed by an analog-to-digital converter (ADC), comprising: generating, by a most significant bit (MSB) digital-to-analog converter (DAC) array of the ADC, sample values ​​for each of one or more most significant bits of an output analog-to-digital value; generating, by a first least significant bit (LSB) DAC array of the ADC, sample values ​​for each of one or more least significant bits of the output ADC value; generating, by a second LSB DAC array of the ADC, sample values ​​for each of the one or more least significant bits of the output ADC value; and alternating generation of an output ADC bit value and a mismatch error value for the output ADC bit value by each DAC array of the first LSB DAC array and the second LSB DAC array.

10. 10. The method of claim 9, further comprising generating the sample values ​​by the MSB DAC array using data weighted averaging.

11. 11. The method of claim 9, wherein generating the respective sample values ​​by the first LSB DAC array and the second LSB DAC array comprises generating the sample values ​​using bottom plate sampling.

12. 12. The method of claim 11, wherein generating the respective sample values ​​by the first LSB DAC array and the second LSB DAC array comprises generating the sample values ​​using mismatch error shaping in conjunction with bottom plate sampling.

13. 12. The method of claim 11, wherein the MSB DAC array comprises a plurality of capacitors having substantially the same value, each of the plurality of capacitors representing one-half of the maximum value produced by the analog-to-digital converter.

14. 11. The method of claim 9 or 10, wherein the first LSB DAC array comprises a plurality of capacitors having substantially different values, each of the plurality of capacitors having a value less than a most significant bit of the output ADC value.

15. 11. The method of claim 9 or 10, wherein each of the plurality of capacitors of the first LSB DAC array follows a doubling sequence.

16. 11. The method of claim 9 or 10, wherein the first LSB DAC array comprises a plurality of capacitors, and the second LSB DAC array includes a plurality of capacitors that are substantially the same as the capacitors of the first LSB DAC array.

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