Symbol filtering on the PHY side of the PHY-MAC interface

Abstract

Disclosed embodiments include a method including conveying symbols from a PHY to a MAC via a PHY side of a PHY-MAC interface and filtering one or more symbols at an input of a PHY side of an interface wrapper on the PHY side of the PHY-MAC interface. Disclosed embodiments include an apparatus including a PHY side of the PHY-MAC interface and logic circuitry disposed on the PHY side of the PHY-MAC interface, the logic circuitry including a filter for filtering one or more symbols conveyed via the PHY side of the PHY-MAC interface.

Description

[Technical Field]

[0001] (Priority Claim) This application claims the benefit of the filing date of Chinese Patent Application No. 202210950844.7, entitled "SYMBOL FILTERING AT A PHY-SIDE OF PHY-MAC INTERFACE," filed on August 9, 2022, the disclosure of which is incorporated herein by reference in its entirety.

[0002] FIELD OF THE INVENTION One or more embodiments relate to a physical layer (PHY)-media access controller (MAC) interface, and more particularly, one or more embodiments relate to a PHY-side PHY-MAC interface and a PHY-side interface wrapper with a symbol-filtered input. [Background technology]

[0003] Interconnects are widely used to facilitate communication between devices, subsystems, and systems of a network. Generally speaking, electrical signals are transmitted over a physical medium (such as, without limitation, a bus, coaxial cable, or twisted pair—commonly referred to simply as a "line" or a "bus") by devices coupled to that physical medium.

[0004] According to the Open Systems Interconnection model (OSI model), Ethernet-based computer networking technology uses baseband transmission (i.e., electrical signals are discrete electrical pulses) to transport data packets and ultimately messages communicated between network devices. According to the OSI model, specialized circuitry called a physical layer (PHY) device or controller is used to interface between the analog domain of the line (physical media) and the digital domain of the data link layer (also referred to herein simply as the "link layer"), which operates according to packet signaling. While the data link layer may include one or more sublayers, in Ethernet-based computer networking, the data link layer typically includes at least a media access control (MAC) layer, which provides control abstraction of the physical layer. As a non-limiting example, when transmitting data to another device on the network, the MAC controller may prepare frames for the physical media, add error correction elements, and implement collision avoidance. Additionally, when receiving data from another device, the MAC controller may ensure the integrity of the received data and prepare frames for higher layers.

[0005] There are various network topologies that implement the physical layer and link layer (and may include, without limitation, other layers). The Peripheral Component Interconnect (PCI) standard and the Parallel Advanced Technology Attachment (Parallel ATA), both of which have been in use since the early 1990s, may implement a multi-drop bus topology. The trend since the early 2000s has been to use a point-to-point bus topology; for example, the PCI Express standard (PCIe) and the Serial ATA (SATA) standard implement a point-to-point topology.

[0006] A typical point-to-point bus topology may implement circuits between each device (e.g., without limitation, dedicated point-to-point) or circuits between devices and switches (e.g., without limitation, switched point-to-point). In a multi-drop bus topology, the physical transmission medium is a shared bus, and each network device is coupled to the shared bus via circuitry selected based on, for example, the type of physical media (e.g., without limitation, coaxial or twisted pair).

[0007] Point-to-point bus topologies, such as dedicated point-to-point topologies or switched point-to-point topologies, require more wires, and therefore more expensive materials, than multi-drop topologies, due in part to the larger number of links between devices. In certain applications, such as automobiles, physical constraints may exist that make it difficult to directly connect devices, and thus topologies that do not require direct connections or the same number of direct connections within a network or sub-network (e.g., without limitation, multi-drop topologies) may be less susceptible to or hindered by such constraints.

[0008] Devices in a baseband network (e.g., but not limited to, a multi-drop network) share the same physical transmission medium (a "shared transmission medium") and typically use the entire bandwidth of that medium for transmission (i.e., the signals used in baseband transmission occupy the entire bandwidth of the medium). As a result, only one device in the baseband network may transmit at a given moment. Therefore, medium access control methods may be used to handle contention for such a shared transmission medium. [Brief explanation of the drawings]

[0009] To easily identify the discussion of any particular element or function, the most significant digit(s) of a reference number refers to the figure number in which that element is first introduced. [Figure 1] 1 is a block diagram of an apparatus for filtering symbols conveyed from a PHY towards a MAC via a PHY side of a PHY-MAC interface. [Figure 2] FIG. 1 is a block diagram of the PHY side of a PHY-MAC interface including symbol filtering, according to one or more embodiments. [Figure 3] FIG. 1 is a block diagram of the PHY side of a PHY-MAC interface including symbol filtering, according to one or more embodiments. [Figure 4] FIG. 2 is a block diagram illustrating a symbol filter for filtering based at least in part on detecting a predetermined symbol, an indication of valid data, and an indication of out-of-band data, in accordance with one or more embodiments. [Figure 5] FIG. 2 is a block diagram illustrating a symbol filter for filtering based at least in part on detecting a predetermined symbol, according to one or more embodiments. [Figure 6] FIG. 2 is a block diagram illustrating a symbol filter for filtering based at least in part on an indication of valid data and an indication of out-of-band data, in accordance with one or more embodiments. [Figure 7] FIG. 1 is a flow diagram illustrating a process for filtering symbols on the PHY side of a PHY-MAC interface in accordance with one or more embodiments. [Figure 8] FIG. 10 is a flow diagram illustrating a process for filtering symbols on the PHY side of a PHY-MAC interface based at least in part on detecting predetermined symbols. [Figure 9] FIG. 10 is a flow diagram illustrating a process for filtering symbols at the PHY side of a PHY-MAC interface based at least in part on an indication of out-of-band data, according to one or more embodiments. [Figure 10]FIG. 10 is a flow diagram illustrating a process for filtering symbols on the PHY side of a PHY-MAC interface based at least in part on an indication of valid data and an indication of out-of-band data, in accordance with one or more embodiments. [Figure 11] FIG. 10 is a flow diagram illustrating a process for filtering symbols at the PHY side of a PHY-MAC interface based at least in part on an indication of valid data, according to one or more embodiments. [Figure 12] FIG. 10 is a flow diagram illustrating a process for filtering symbols on the PHY side of a PHY-MAC interface based at least in part on detecting predetermined symbols, indications of valid data, and indications of out-of-band data, in accordance with one or more embodiments. [Figure 13] 1 illustrates a timing diagram of signals according to one or more embodiments. [Figure 14] 1 illustrates a timing diagram of signals according to one or more embodiments. [Figure 15] 1 illustrates a timing diagram of signals according to one or more embodiments. [Figure 16] FIG. 1 is a circuit block diagram that, in some embodiments, can be used to implement various functions, operations, acts, processes, and / or methods disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0010] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and which show, by way of illustration, specific embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present disclosure. However, other embodiments may be utilized, and changes in structure, materials, and processes may be made without departing from the scope of the present disclosure.

[0011] The figures presented herein are not intended to be actual illustrations of any particular method, system, device, or structure, but merely idealized representations used to describe embodiments of the present disclosure. The figures presented herein are not necessarily drawn to scale. Similar structures or components in various figures may retain the same or similar numbering for the convenience of the reader. However, similarity in numbering does not necessarily mean that the structures or components are identical in size, composition, configuration, or any other characteristic.

[0012] The following description may include examples to assist those skilled in the art in practicing the disclosed embodiments. The use of the terms "exemplary," "example," and "for example" means that the associated description is explanatory, and the scope of the present disclosure is intended to encompass examples and legal equivalents. The use of such terms is not intended to limit the embodiments or the scope of the present disclosure to specific components, steps, features, functions, etc.

[0013] It will be readily understood that the components of the embodiments, as generally described and illustrated in the figures herein, could be arranged and designed in a wide variety of different configurations. Thus, the following description of various embodiments is not intended to limit the scope of the disclosure, but is merely representative of various embodiments. While various aspects of the embodiments may be presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

[0014] Furthermore, the specific implementations shown and described are merely examples and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions may be shown in block diagram form so as not to obscure the present disclosure in unnecessary detail. Conversely, the specific implementations shown and described are merely exemplary and should not be construed as the only way to implement the present disclosure, unless otherwise specified herein. In addition, the block definitions and partitioning of logic among various blocks are illustrative of specific implementations. It will be readily apparent to one skilled in the art that the present disclosure can be implemented with numerous other partitioning solutions. For the most part, details regarding timing considerations and the like have been omitted; such details are not necessary to obtain a complete understanding of the present disclosure and are within the capabilities of those skilled in the art.

[0015] Those skilled in the art will understand that information and signals may be represented using any of a variety of different technologies and techniques. Some figures may illustrate a signal as a single signal for clarity of display and explanation. Those skilled in the art will understand that a signal may represent a bus of signals, which may have various bit widths, and that the present disclosure may be implemented with any number of data signals, including a single data signal.

[0016] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed using a general-purpose processor, a special-purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor (also referred to herein as a host processor or simply a host) may be a microprocessor, although the processor may alternatively be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. A general-purpose computer including a processor is considered a special-purpose computer, and a general-purpose computer is configured to execute computing instructions (e.g., software code) related to the embodiments of the present disclosure.

[0017] The embodiments may be described in terms of a process that is depicted as a flowchart, a flow diagram, a structure diagram, or a block diagram. While a flowchart may describe operational acts as a sequential process, many of these acts may occur in a different order, in parallel, or substantially simultaneously. Additionally, the order of acts may be rearranged. A process may correspond to, but is not limited to, a method, a thread, a function, a procedure, a subroutine, or a subprogram. Further, methods disclosed herein may be implemented in hardware, software, or both. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media, including any medium that facilitates transfer of a computer program from one place to another.

[0018] Any reference to elements herein using designations such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitation is expressly stated. Rather, these designations may be used herein as a convenient method of distinguishing between two or more elements or instances of an element. Thus, reference to a first element and a second element does not imply that only two elements may be used or that the first element must precede the second element in any manner. Additionally, unless otherwise specified, a set of elements may include one or more elements.

[0019] As used herein, the term "substantially" when referring to a given parameter, characteristic, or condition means and includes the extent to which one of ordinary skill in the art would understand that the given parameter, characteristic, or condition is met with small variations, such as, for example, within acceptable manufacturing tolerances. As an example, depending on the particular parameter, characteristic, or condition that is substantially met, the parameter, characteristic, or condition may be at least 90% met, at least 95% met, or even at least 99% met.

[0020] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, the elements may be in direct physical or electrical contact, or there may be intervening elements or layers present. In contrast, when an element is described as being "directly coupled" to another element, there are no intervening elements or layers present. The terms "on" and "connected" may be used interchangeably with the term "coupled" herein and have the same meaning unless expressly stated otherwise or the context otherwise indicates otherwise to one of ordinary skill in the art.

[0021] As used herein, the term "pin" means "electrical connector" and should be understood to encompass any structure or device capable of forming at least a portion of an electrical connection, such as, without limitation, an electrical contact, an electromechanical device, or a circuit.

[0022] As used herein, the terms "assert," "de-assert," and their derivatives, when used in reference to a pin, mean to respectively assert or de-assert a signal associated with the pin (e.g., without limitation, a signal specifically assigned to the pin or a signal to which the pin is specifically assigned).

[0023] Vehicles, such as automobiles, trucks, buses, ships, and / or aircraft, may include a vehicle communication network. The complexity of the vehicle communication network may vary depending on the number of electronic devices in the network. For example, an advanced vehicle communication network may include various control modules for engine control, transmission control, safety control (e.g., anti-lock brakes), and emissions control, as non-limiting examples. To support these modules, the automotive industry relies on a variety of communication protocols.

[0024] 10SPE (i.e., 10Mbps Single Pair Ethernet) is a network technology currently under the IEEE 802.3cg™ specification (available from IEEE, Piscataway, New Jersey). 10SPE can be used to provide collision-free, deterministic transmission of symbols in multi-drop networks. The 10SPE specification includes an optional Physical Level Collision Avoidance (PLCA) arbitration sublayer for collision-free transmission.

[0025] In addition to symbols that are part of "payload data," a physical layer (PHY) device may receive symbols that are not part of payload data. Payload data is defined as the entirety of data conveyed by the media access control (MAC) to the PHY for transmission, e.g., a frame of preamble data, frame data, and integrity data. Payload data is also referred to herein as "in-band data," and with respect to symbols, as "in-band symbols." Data other than in-band data is also referred to herein as "out-of-band data," and with respect to symbols, as "out-of-band symbols." As a non-limiting example, a transmitting PLCA PHY (such as some 10SPE PHYs) may insert symbols used for collision avoidance, such as, without limitation, beacon symbols and commit symbols.

[0026] A Media Independent Interface (MII) may be utilized to couple a MAC with various types of PHYs (i.e., PHYs for connecting to different types of physical media for transmission media, such as, without limitation, coax or twisted pair). The MII typically includes a receive data valid ("rx data valid") signal that typically indicates valid received data (in-band data) symbols within the receive data ("rx data"), and a carrier sense signal that typically indicates the detected state of the carrier in the transmission media (e.g., without limitation, active or inactive). The MAC can use the rx data valid and carrier sense signals to infer which symbols, if any, within the rx data are in-band data.

[0027] The MII typically includes a receive error ("rx error") signal along with an rx data valid signal that indicates that a particular symbol contained in the rx data corresponds to out-of-band data. According to 10SPE, when both the rx error signal and the rx data valid signal are deasserted, it indicates that a special PLCA symbol is present in the rx data. In the case of a Carrier Sense Multiple Access (CSMA) MAC or a CSMA with Collision Detection (CSMACD) MAC, the special PLCA symbol is processed by the PLCA Arbitration sublayer in response to signaling by the rx error and rx data valid signals.

[0028] An interface wrapper is a logic circuit that can change (e.g., without limitation, reduce or increase) the signaling or hardware connections of an interface. Sometimes, an interface wrapper is used to change the signaling or hardware interface between a PHY and a MAC, for example, to reduce the number of connections used to couple the PHY and MAC. As a non-limiting example, a Reduced Media Independent Interface (RMII) wrapper may be used to wrap an MII and reduce the number of pins (i.e., hardware connections) and signals in an RMII compared to an MII.

[0029] A typical RMII wrapper assumes that the carrier sense signal and the rx data valid signal are substantially identical and multiplexes the rx data valid signal and the carrier sense signal onto a single output (which may also be characterized as an output for non-exclusive signaling of the carrier sense signal and the rx data valid signal, i.e., "crs dv"). A typical RMII wrapper does not include an rx error signal. If the internal MII carrier sense signal is asserted, the internal MII rx data valid signal is deasserted, and the internal MII rx error signal is asserted, the typical RMII wrapper asserts the crs dv signal based on at least one of the carrier sense signal and the rx data valid signal being asserted. Thus, the RMII wrapper may unintentionally indicate that a symbol is in-band data when it is actually out-of-band data. In this same case, when the MAC receives an asserted crs dv signal, it may merge the in-band and out-of-band data symbols, resulting in corrupted, lost, or useless data, by way of non-limiting example.

[0030] The inventors of the present disclosure understand that, by way of non-limiting example, it may be advantageous to include symbol filtering in an interface wrapper (e.g., without limitation, an RMII wrapper) to increase accurate communication of in-band data (e.g., without limitation, payload data) or out-of-band data (e.g., without limitation, PLCA symbols) over the wrapped interface. The use of the terms "filter," "filtering," or derivatives thereof herein is not intended to require blocking, masking, or not passing symbols, nor is it intended to require circuitry that performs blocking, masking, or not passing symbols. Unless expressly specified otherwise, or unless such a definition would be understood otherwise by one of ordinary skill in the art based on context, the terms "filter," "filtering," or derivatives thereof, should be understood to encompass various techniques, including, but not limited to, passing symbols and modifying or suppressing signals that affect how downstream users interpret, use, or detect in-band or out-of-band symbols (e.g., without limitation, as in-band or out-of-band symbols), as well as blocking, masking, or not passing symbol data.

[0031] 1 is a block diagram of an apparatus 100 for filtering symbols conveyed from a PHY to a MAC over a PHY-MAC interface. The apparatus 100 may also be referred to as an "interface portion 100." The apparatus 100 includes a PHY side 102 of the PHY-MAC interface. The PHY side 102 of the PHY-MAC interface includes logic circuitry 104, which includes a symbol filter 106.

[0032] The PHY side 102 of the PHY-MAC interface is the PHY portion of the interface for facilitating communication of data (e.g., without limitation, frames of data) between the PHY and the MAC. As a non-limiting example, the PHY-MAC interface of the PHY side 102 of the PHY-MAC interface may be an Ethernet PHY-MAC interface.

[0033] The symbol filter 106 of the logic circuit 104 filters one or more symbols conveyed over the PHY side 102 of the PHY-MAC interface. In one or more embodiments, the filtered symbols may be predetermined symbols, symbols identified via specific signaling, or both. Non-limiting examples of predetermined symbols include PLCA symbols, such as beacon symbols or commit symbols, or more generally, out-of-band symbols. Non-limiting examples of suppressing communication include dropping predetermined symbols from a data frame or stream, or more generally, providing signaling to indicate the presence of predetermined symbols or invalid data (which may include providing signaling to indicate the absence of data or valid data), or combinations thereof. Filtering symbols other than out-of-band data is within the scope of this disclosure. Any "ignored symbols," in one or more embodiments, may be filtered in accordance with the embodiments disclosed herein, including in-band data.

[0034] 2 is a block diagram of a PHY side 200 of a PHY-MAC interface including symbol filtering, in accordance with one or more embodiments. The PHY side 200 of the PHY-MAC interface is a non-limiting example of the PHY side 102 of the PHY-MAC interface of FIG.

[0035] The PHY side 200 of the PHY-MAC interface includes an interface 204, which may be the PHY side of an MII, an interface wrapper 206, which may be the PHY side of an RMII wrapper, and a symbol filter 208, which collectively form the PHY side of the wrapped interface 202. The symbol filter 208 is provided at an input 216 of the interface wrapper 206. The input 216 typically receives state signaling, such as emulated state signaling 214 (which may be the same as or different from state signaling 212) generated by the symbol filter 208.

[0036] Various connections (not shown) may carry signaling and data, including data stream 210 and status signaling 212. Data stream 210 is a data stream of symbols (“symbol data”) received by the PHY from a physical transmission medium. Status signaling 212 includes one or more signals indicating one or more of the state of a carrier in the physical transmission medium (e.g., without limitation, the state is “active” (i.e., carrying transmission data such as, without limitation, in-band data or out-of-band data) or “inactive” (i.e., not carrying transmission data such as, without limitation, in-band data or out-of-band data)) or the state of the symbol data of data stream 210 (e.g., without limitation, the symbol is in-band data or out-of-band data). As explained above, a downstream user of emulated status signaling 214 distinguishes between in-band and out-of-band symbols of a data stream (e.g., without limitation, between data stream 210).

[0037] Symbol filter 208 generates and provides emulated state signaling 214 to interface wrapper 206. Symbol filter 208 may generate emulated state signaling 214 at least in part in response to one or more of data stream 210 or state signaling 212, as described herein. In one or more embodiments, by implementing differences between instances of emulated state signaling 214 and instances of state signaling 212, symbol filter 208 may affect how downstream users distinguish between in-band and out-of-band data among data stream 210.

[0038] 3 is a block diagram of an interface portion 300 including symbol filtering, according to one or more embodiments. Interface portion 300 is an exemplary PHY side of a PHY-MAC interface. Among other things, FIG. 3 shows a PHY side 306 of an RMII wrapper with a symbol-filtered input, according to one or more embodiments. Interface portion 300 is a non-limiting example of PHY side 102 of the PHY-MAC interface of FIG. 1 or PHY side 200 of the PHY-MAC interface of FIG. 2.

[0039] The interface portion 300 includes an MII PHY side 304, an RMII wrapper PHY side 306, and a symbol filter 308 that collectively form the RMII PHY side 302. A number of connections couple the MII PHY side 304 with the RMII wrapper PHY side 306, including an internal connection for signals provided to a receive path 320 (i.e., a PHY-to-MAC data path) of the RMII PHY side 302. Signals provided to the receive path 320 include, without limitation, rx data 310, rx data valid 312, rx error 314, and carrier sense 316.

[0040] rx data 310 is associated with receive data ("rx data") received by the PHY from the shared transmission medium and carried from the PHY towards the MAC, and carries a data stream of symbols ("symbol data"). rx data valid 312 is associated with an indication of the presence of valid data (i.e., symbols that are in-band data) in rx data 310, i.e., valid data on the internal connection carrying rx data 310. Timing is associated with the assertion / deassertion of the rx data valid 312 signal, such that when the rx data valid 312 signal is asserted, it indicates when valid data is present on the internal connection carrying rx data 310, and when the rx data valid 312 signal is deasserted, it indicates when valid data is not present on the internal connection carrying rx data 310.

[0041] The rx error 314 is associated with an indication of the presence of out-of-band data (e.g., without limitation, predetermined symbols for communicating the state of a link partner or carrier in a cable) on the internal connection carrying the rx data 310. Timing is associated with the assertion / deassertion of the rx error 314 signal, such that when the rx error 314 signal is asserted, it indicates a time when out-of-band data is present on the internal connection carrying the rx data 310, and when the rx error 314 signal is deasserted, it indicates a time when out-of-band data is not present on the internal connection carrying the rx data 310.

[0042] Carrier sense 316 is related to the state of a detected carrier in a physical medium (e.g., a cable such as, but not limited to, a coaxial or twisted pair type cable). Non-limiting examples of carrier states include "active" and "inactive," as described above.

[0043] The symbol filter 308 is disposed between the MII PHY side 304 and an input 322 of the RMII wrapper PHY side 306 to receive the signals rx data 310, rx data valid 312, rx error 314, and carrier sense 316. In one or more embodiments, the symbol filter 308 may provide (e.g., without limitation, propagate or redrive) some or all of the signals rx data 310, rx data valid 312, rx error 314, and carrier sense 316 toward the input 322 of the RMII wrapper PHY side 306 associated with such signals. The symbol filter 308 may generate an emulated carrier sense 318 at least partially in response to one or more of the rx data 310, rx data valid 312, or rx error 314 signals, as described herein. By implementing the difference between the received carrier sense 316 signal and the output emulated carrier sense 318 signal, the symbol filter 308 can affect how a downstream user (e.g., without limitation, a MAC) distinguishes between in-band and out-of-band data among data streams in the internal connection carrying rx data 310. The effect on how a downstream user distinguishes between in-band and out-of-band data among data streams is referred to herein as symbol filtering.

[0044] 4, 5, and 6 are block diagrams illustrating the configuration of symbol filters that are non-limiting examples of symbol filter 208 of FIG. 2, symbol filter 308 of FIG. 3, or symbol filter 106 of logic circuit 104 of FIG.

[0045] FIG. 4 is a block diagram illustrating a symbol filter 400 for filtering based at least in part on detecting predetermined symbols, indications of valid data, and indications of out-of-band data, in accordance with one or more embodiments.

[0046] The symbol filter 400 includes match logic 402, detection logic 406, and suppression logic 408. The match logic 402 receives a data stream 410. The detection logic 406 and the suppression logic 408 each receive at least some component signals of status signaling 414. The component signals of status signaling 414 received by the detection logic 406 include an rx error signal 416 and, optionally, valid rx data 418. The component signals of status signaling 414 received by the suppression logic 408 include carrier sense 420.

[0047] The match logic 402 detects that one or more symbols 412 in the data stream 410 match one or more predetermined symbols 404. As a non-limiting example, the predetermined symbols 404 may include predetermined symbols associated with out-of-band data (e.g., symbols of predetermined bits or symbols associated with out-of-band data stored in or accessible by the match logic 402), such as, without limitation, a commit symbol, a PLCA symbol, or a beacon symbol. In response to detecting that the one or more symbols 412 match the one or more predetermined symbols 404, the match logic 402 asserts an out-of-band symbol indication 422. Assertion of the out-of-band symbol indication 422 indicates the presence of the one or more predetermined symbols 404 in the data stream 410, and deassertion of the out-of-band symbol indication 422 indicates the absence of the one or more predetermined symbols 404 in the data stream 410.

[0048] As a non-limiting example, the match logic 402 may be a combinational logic circuit that performs a bit-by-bit comparison of the predetermined symbol 404 with the symbol 412 and generates an out-of-band symbol indication 422 that exhibits a first logic level (which may be a high voltage level) in response to a comparison result indicating that the bits (or a suitable number of bits) are the same, and exhibits a second logic level (which may be a low voltage level) in response to a comparison result indicating that the bits (or a suitable number of bits) are different.

[0049] The detection logic 406 detects that the status signaling 414 indicates the presence of out-of-band data in the data stream 410. As described above with respect to the rx error 314, the assertion of the rx error signal 416 indicates that out-of-band data is present in the data stream 410. As described above with respect to the rx data valid 312, the deassertion of the rx data valid 312 indicates that valid data is not present in the data stream 410. The detection logic 406 asserts the out-of-band data signaling indication 426 at least in part in response to detecting both the assertion of the rx error signal 416 and the deassertion of the valid rx data signal 418. As a non-limiting example, the detection logic 406 may be a combinational logic circuit including an AND gate having an input coupled to receive the rx error signal 416 and an input coupled to receive the valid rx data signal 418. In contemplated operation, the AND gate outputs an out-of-band data signaling indication 426 that exhibits a logic high voltage level in response to one or both of the rx error signal 416 and the valid rx data signal 418 exhibiting a logic high voltage (where a logic high voltage level corresponds to assertion and a logic low voltage level corresponds to deassertion), and otherwise exhibits a logic low voltage level. The suppression logic 408 generates an emulated carrier sense 424 to indicate to a downstream user (e.g., without limitation, a MAC) whether one or more symbols in the data stream 410 correspond to out-of-band data. The suppression logic 408 generates an emulated carrier sense 424, which may include signaling to indicate that one or more symbols of the data stream 410 correspond to out-of-band data, at least in part, in response to detecting both the assertion of the out-of-band symbol indication 422 (indicating that one or more symbols 412 matched one or more predetermined symbols 404) and the assertion of the out-of-band data signaling indication 426 (indicating that the status signaling 414 indicated the presence of out-of-band data in the data stream 410). Notably, portions of the emulated carrier sense 424 may be different from the carrier sense 420, while other portions will be substantially the same (i.e., unchanged).

[0050] As a non-limiting example, the suppression logic 408 may be a combinational logic circuit including an AND gate having an input coupled to the output of the match logic 402 to receive the out-of-band symbol indication 422 and an input coupled to the output of the detection logic 406 to receive the out-of-band data signaling indication 426, and a NAND gate having an input coupled to the output of the AND gate and an input coupled to receive the carrier sense 420. In contemplated operation, the AND gate outputs a signal indicating a logic high voltage level in response to one or both of the out-of-band data signaling indication 426 and the out-of-band symbol indication 422 being logic high. Furthermore, the NAND gate outputs an emulated carrier sense 424 indicating a logic low voltage level in response to the carrier sense 420 indicating a logic high voltage level and the output of the AND gate indicating a logic high voltage level.

[0051] FIG. 5 is a block diagram illustrating a symbol filter 500 for filtering based at least in part on detecting predetermined symbols, according to one or more embodiments.

[0052] The symbol filter 500 includes match logic 502 and suppression logic 506. The match logic 502 is coupled to a received data stream 518. Component signals of the status signaling 510 received by the suppression logic 506 include carrier sense 512.

[0053] The match logic 502 detects that one or more symbols 508 in the data stream 518 match one or more predetermined symbols 504. As a non-limiting example, the one or more predetermined symbols 504 may include predetermined out-of-band data, such as, without limitation, a PLCA symbol (e.g., a beacon symbol or a commit symbol). In response to detecting that the one or more symbols 508 match the one or more predetermined symbols 504, the match logic 502 asserts an out-of-band symbol indication 514, which assertion indicates the presence of out-of-band data in the data stream 518.

[0054] As a non-limiting example, match logic 502 may be a combinational logic circuit that performs a bit-by-bit comparison of predetermined symbol 504 and symbol 508 and outputs an out-of-band symbol indication 514 that exhibits a logic high voltage level in response to a comparison result indicating that the bit (or a suitable number of bits) is the same, and exhibits a logic low voltage level in response to a comparison result indicating that the bit (or a suitable number of bits) is different.

[0055] The suppression logic 506 generates an emulated carrier sense 516 to indicate to a downstream user (e.g., without limitation, a MAC) that one or more symbols of the data stream 518 correspond to out-of-band data. The suppression logic 506 generates the emulated carrier sense 516 (including signaling to indicate that one or more symbols of the data stream 518 correspond to out-of-band data) at least in part in response to detecting an assertion of the out-of-band symbol indication 514 (indicating that one or more symbols 508 match one or more predetermined symbols 504). Notably, in various use cases, a portion of the emulated carrier sense 516 may be different from the carrier sense 512, while another portion may be substantially the same (i.e., unchanged).

[0056] As a non-limiting example, the suppression logic 506 may be a combinational logic circuit including a NAND gate having an input coupled to the output of the match logic 502 and an input coupled to receive carrier sense 512. In contemplated operation, the NAND gate outputs an emulated carrier sense 516 indicating a logic low voltage level in response to both the out-of-band data signaling indication 426 and the carrier sense 512 indicating a logic high voltage level.

[0057] FIG. 6 is a block diagram illustrating a symbol filter 600 for filtering based at least in part on an indication of valid data and an indication of out-of-band data, in accordance with one or more embodiments.

[0058] Symbol filter 600 includes detection logic 602 and suppression logic 604. Data stream 606, although shown in FIG. 6, is optional because suppression logic 604 relies on out-of-band data signaling indication 616 from detection logic 602 to generate emulated carrier sense 618, as described herein, but does not rely on direct symbol matching (e.g., without limitation, match logic 402 or match logic 502).

[0059] The detection logic 602 and the suppression logic 604 each receive some of the component signals of the status signaling 608. The component signals of the status signaling 608 received by the detection logic 602 include an rx error 610 and, optionally, a valid rx data 612. The component signals of the status signaling 608 received by the suppression logic 604 include a carrier sense 614.

[0060] The detection logic 602 detects that the status signaling 608 indicates the presence of out-of-band data in the data stream 606 and, at least in part, responds thereto by asserting or deasserting the out-of-band data signaling indication 616. As described above with respect to the rx error 314, the assertion of the rx error 610 indicates that out-of-band data is present in the data stream 606. As described above with respect to the rx data valid 312, the deassertion of the valid rx data 612 indicates that valid data is not present in the data stream 606. The detection logic 602 asserts the out-of-band data signaling indication 616, at least in part, in response to detecting the assertion of the rx error 610 and the deassertion of the valid rx data 612. As a non-limiting example, the detection logic 602 may be a combinational logic circuit including an AND gate having an input coupled to receive the rx error 610 and an input coupled to receive an inverted version of the valid rx data 612. The AND gate outputs an out-of-band data signaling indication 426 indicating a logic high voltage level in response to both the rx error 610 indicating a logic high voltage and the inverted version of the valid rx data signal 418 indicating a logic low voltage, and otherwise outputs an out-of-band data signaling indication 426 indicating a logic low level.

[0061] The suppression logic 604 generates an emulated carrier sense 618 to indicate to a downstream user (e.g., without limitation, a MAC) that one or more symbols of the data stream 606 correspond to out-of-band data. The suppression logic 604 generates the emulated carrier sense 618 (including signaling to indicate that one or more symbols of the data stream 606 correspond to out-of-band data) at least in part in response to detecting the assertion of the out-of-band data signaling indication 616. In particular, a portion of the emulated carrier sense 618 may be different from the carrier sense 614, while another portion remains substantially the same (i.e., unchanged). As a non-limiting example, the suppression logic 604 may be a combinational logic circuit including a NAND gate having an input coupled to the output of the detection logic 602 and an input coupled to receive the carrier sense 614. In contemplated operation, the NAND gate outputs a logic low voltage level in response to both the out-of-band data signaling indication 616 and the carrier sense 614 indicating a logic high voltage level, and otherwise outputs a logic high voltage level.

[0062] 7 is a flow diagram illustrating a process 700 for filtering symbols on the PHY side of a PHY-MAC interface, according to one or more embodiments. Process 700 may be performed by apparatus 100 of FIG. 1, as a non-limiting example.

[0063] At operation 702, the process 700 conveys symbols from the PHY to the MAC via the PHY side of the PHY-MAC interface. At least some of the conveyed symbols are out-of-band data or in-band data. Some of the conveyed symbols may be ignored symbols.

[0064] At operation 704, process 700 filters one or more symbols at the input of an interface wrapper on the PHY side of the PHY-MAC interface. The interface wrapper may be an RMII wrapper, and the PHY side of the PHY-MAC interface may be a wrapped interface, such as, without limitation, an MII wrapped by an RMII.

[0065] 8, 9, 11, 10, and 12 are flow diagrams illustrating suppressing signaling on the PHY side of the PHY-MAC interface to filter symbols, respectively, in accordance with one or more embodiments.

[0066] 8 is a flow diagram illustrating a process 800 for filtering symbols at the PHY side of a PHY-MAC interface based at least in part on detecting a predetermined symbol. Process 800 may be performed by symbol filter 500 at PHY side 200 of the PHY-MAC interface or PHY side 102 of the PHY-MAC interface, as a non-limiting example.

[0067] At operation 802, process 800 detects one or more symbols corresponding to a predetermined symbol. The correspondence between the one or more symbols and the predetermined symbol may be detected at an input to the PHY side of an interface wrapper on the PHY side of the PHY-MAC interface.

[0068] At operation 804, optionally, the predetermined symbol is associated with out-of-band data (e.g., a symbol of a predetermined bit, or a symbol associated with a commit symbol, a PLCA symbol, a beacon symbol, or other out-of-band data stored in or accessible by the match logic 502). At operation 806, optionally, the predetermined symbol is associated with physical layer collision avoidance (PLCA).

[0069] At operation 808, process 800 suppresses signaling to an input of a PHY-side interface wrapper on the PHY side of the PHY-MAC interface, the signaling associated with one or more symbols. As a non-limiting example, the signaling to the input of the PHY-side interface wrapper on the PHY side of the PHY-MAC interface may be suppressed for the same duration that an associated symbol is provided to the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface.

[0070] At operation 810, optionally, the signaling to be suppressed is associated with a state of a carrier of a shared transmission medium.

[0071] FIG. 9 is a flow diagram illustrating a process 900 for filtering symbols on the PHY side of a PHY-MAC interface based at least in part on an indication of out-of-band data, such as the assertion of rx error 610 of FIG. 6, in accordance with one or more embodiments.

[0072] At operation 902, process 900 detects the assertion of an out-of-band data indication, for example, by assertion of out-of-band data signaling indication 616. The assertion may be detected in response to the out-of-band data indication changing state from deasserted to asserted.

[0073] At operation 904, process 900 begins suppressing signaling to an input of the interface wrapper on the PHY side of the PHY-MAC interface at least in part in response to detecting the assertion of the out-of-band data indication. Suppressing signaling may include providing signaling to indicate the presence of a predetermined symbol or invalid data more generally (which may include providing signaling to indicate the absence of data or valid data), or a combination thereof.

[0074] At operation 906, process 900 detects a deassertion of the out-of-band data indication. The deassertion may be detected in response to the out-of-band data indication changing state from asserted to deasserted.

[0075] At operation 908, process 900 stops suppressing signaling to the PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface, at least in part in response to detecting a deassertion of the out-of-band data indication.

[0076] FIG. 10 is a flow diagram illustrating a process 1000 for filtering symbols on the PHY side of a PHY-MAC interface based at least in part on an indication of valid data, such as valid rx data 612 of FIG. 6, and an indication of out-of-band data, such as rx error 610 of FIG. 6, in accordance with one or more embodiments.

[0077] At operation 1002, process 1000 detects at least one of a deassertion of a valid data indication (e.g., without limitation, a deassertion of valid rx data 612 of FIG. 6) or an assertion of an out-of-band data indication (e.g., without limitation, an assertion of rx error 610 of FIG. 6). A deassertion of a valid data indication may be detected in response to the valid data indication (e.g., without limitation, valid rx data 612) changing state from asserted to deasserted, and an assertion of an out-of-band data indication (e.g., without limitation, rx error 610) may be detected in response to the out-of-band data indication changing state from deasserted to asserted.

[0078] At operation 1004, process 1000 begins suppressing signaling to a PHY-side input of an interface wrapper on the PHY side of the PHY-MAC interface (e.g., without limitation, carrier sense 614 of FIG. 6 ) at least in part in response to detecting at least one of a deassertion of a valid data indication or an assertion of an out-of-band data indication.

[0079] At operation 1006, process 1000 detects at least one of an assertion of the valid data indication or a deassertion of the out-of-band data indication. The assertion of the valid data indication may be detected in response to the valid data indication changing state from deasserted to asserted, and the deassertion of the out-of-band data indication may be detected in response to the out-of-band data indication changing state from asserted to deasserted.

[0080] At operation 1008, process 1000 stops suppressing signaling to a PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface, at least in part in response to detecting at least one of an assertion of the valid data indication or a deassertion of the out-of-band data indication.

[0081] FIG. 11 is a flow diagram illustrating a process 1100 for filtering symbols on the PHY side of a PHY-MAC interface based at least in part on an indication of valid data, such as valid rx data 612 of FIG. 6, in accordance with one or more embodiments.

[0082] At operation 1102, process 1100 detects a deassertion of the valid data indication. The deassertion may be detected in response to the valid data indication changing state from asserted to deasserted.

[0083] At operation 1104, process 1100 begins suppressing signaling on the PHY side of the PHY-MAC interface, at least in part in response to detecting the deassertion of the valid data indication.

[0084] In operation 1106, process 1100 detects assertion of a valid data indication at the PHY side of the PHY-MAC interface. The assertion may be detected in response to the valid data indication changing state from deasserted to asserted.

[0085] At operation 1108, process 1100 stops suppressing signaling on the PHY side of the PHY-MAC interface, at least in part in response to detecting the assertion of the valid data indication.

[0086] FIG. 12 is a flow diagram illustrating a process 1200 for filtering symbols on the PHY side of a PHY-MAC interface based at least in part on detecting a predetermined symbol (e.g., without limitation, predetermined symbol 404), an indication of valid data (e.g., without limitation, valid rx data 418 of FIG. 4), and an indication of out-of-band data (e.g., without limitation, rx error signal 416 of FIG. 4), in accordance with one or more embodiments.

[0087] In operation 1202, the process 1200 detects a symbol that corresponds to a predetermined symbol.

[0088] At operation 1204, process 1200 detects at least one of a deassertion of the valid data indication or an assertion of the out-of-band data indication. A deassertion may be detected in response to the valid data indication changing state from asserted to deasserted, and an assertion may be detected in response to the out-of-band data indication changing state from deasserted to asserted.

[0089] At operation 1206, in response at least in part to detecting a symbol corresponding to the predetermined symbol and detecting at least one of deasserting the valid data indication or asserting the out-of-band data indication, initiate suppression of signaling at a PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface corresponding to the detected symbol.

[0090] At least one of an assertion of the valid data indication or a deassertion of the out-of-band data indication is detected in operation 1208. An assertion may be detected in response to the valid data indication changing state from deasserted to asserted, and a deassertion may be detected in response to the out-of-band data indication changing state from asserted to deasserted.

[0091] At operation 1210, at least in part, in response to detecting at least one of assertion of the valid data indication or deassertion of the out-of-band data indication, stop suppressing signaling at a PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface corresponding to one or more symbols.

[0092] 13 illustrates a signal timing diagram 1300 according to one or more embodiments. The timing diagram 1300 shows signals on a cable 1302 (i.e., the transmission medium over which the PHY receives symbols) and the respective signals: rx data 1306, valid rx data 1308, rx error 1310, carrier sense 1312, and emulated carrier sense 1314.

[0093] At time T1, an ignore symbol 1304 is present on the cable 1302, represented as an ignore symbol 1316 in the rx data 1306. Valid rx data 1308 is deasserted 1326 at time T1 because there is no valid data present in the rx data 1306. rx error 1310 is deasserted 1318 at time T1 because, in this example, the ignore symbol is special data (e.g., without limitation, a commit symbol or beacon). Carrier sense 1312 is asserted 1324 because a carrier is active on the cable 1302. Emulated carrier sense 1314 is deasserted 1322 at time T1. Thus, signaling from carrier sense 1312 is suppressed in emulated carrier sense 1314 at time T1 according to the logic described above, i.e., symbol to be ignored 1304 is detected, valid rx data 1308 is not asserted, rx error 1310 is deasserted (1318), or any combination thereof (the dashed line indicates that signaling from carrier sense 1312 is suppressed (or absent, in this particular example)) in emulated carrier sense 1314).

[0094] 14 illustrates a signal timing diagram 1400 in accordance with one or more embodiments. The timing diagram 1400 shows respective signals on the cable 1402, rx data 1410, valid rx data 1418, rx error 1422, carrier sense 1428, and emulated carrier sense 1432.

[0095] At time T1, the first ignore symbol 1404 is present on the cable 1402, and this ignore symbol is represented in the rx data 1410 as the first ignore symbol 1412. The valid rx data 1418 is not asserted (i.e., is deasserted 1444) at time T1 because there is no valid data present in the rx data 1410. The rx error 1422 is deasserted 1424 at time T1 because, in this example, the ignore symbol is special data (e.g., a commit symbol or beacon). The carrier sense 1428 is asserted 1430 at time T1 because there is an active carrier present on the cable 1402. The emulated carrier sense 1432 is deasserted 1440 at time T1. Therefore, the signaling in carrier sense 1428 is suppressed (1434) at time T1 in emulated carrier sense 1432 according to the logic described above, i.e., the first ignorable symbol 1404 is detected, valid rx data 1418 is not asserted, rx error 1422 is deasserted, or any combination thereof (the dashed line indicates that the signaling in emulated carrier sense 1432 is suppressed).

[0096] At time T2, symbol data 1406 is present on cable 1402, and this symbol data is represented in rx data 1410 as symbol data 1414. Valid rx data 1418 is asserted 1420 at time T2 because valid data is present in rx data 1410. rx error 1422 is asserted 1442 at time T2 because, in this example, symbol data 1406 is not special data. Carrier sense 1428 is asserted 1430 at time T1 because a carrier is active on cable 1402. Emulated carrier sense 1432 is asserted 1436 at time T2. Therefore, the signaling of carrier sense 1428 is unsuppressed (not suppressed), which may also be characterized as faithfully propagating the signal in carrier sense 1428 (e.g., the carrier of emulated carrier sense 1432 at time T2).

[0097] At time T3, a second ignore symbol 1408 is present on the cable 1402, and this ignore symbol is represented in the rx data 1410 as a second ignore symbol 1416. The valid rx data 1418 is deasserted 1446 at time T3 because there is no valid data in the rx data 1410. The rx error 1422 is deasserted 1426 at time T3 because, in this example, the symbol data 1406 is not special data. The emulated carrier sense 1432 is deasserted 1438 at time T3. Therefore, the signaling in carrier sense 1428 is suppressed at time T3 in emulated carrier sense 1432 according to the logic described above, i.e., the second ignorable symbol 1416 is detected, valid rx data 1418 is not asserted, rx error 1422 is deasserted (1426), or any combination thereof (the dashed line indicates that the signal in carrier sense 1428 is suppressed in emulated carrier sense 1432).

[0098] In some cases, filtering of ignorable symbols by suppressing signaling in carrier sense 1428 according to one or more embodiments may create or increase an interframe gap (IFG) between frames of in-band symbols from the perspective of a MAC receiving the emulated carrier sense signal 1432. If a frame of out-of-band symbols is indicated as a frame of in-band symbols and the gap between this frame of out-of-band symbols and the immediately preceding or succeeding frame may be less than the IFG, the MAC may erroneously process one or all of the frames. For example, the disclosed filtering of the first ignorable symbol 1412 has the effect of increasing the IFG between the frame of symbol data 1414 and the frame immediately preceding the frame of the first ignorable symbol 1412. The time between T1 and T2 (ΔT) may be characterized as the IFG, or at least a portion of the IFG, between the frame of symbol data 1414 and the frame immediately preceding the frame of the first ignorable symbol 1412. Some embodiments generally relate to guaranteeing the size of the IFG. Thus, in one or more embodiments, the disclosed symbol filtering and suppression may guarantee the size of the interframe gap.

[0099] 15 illustrates a signal timing diagram 1500 in accordance with one or more embodiments. The timing diagram illustrates signals for carrier sense 1508, emulated carrier sense 1510, and receive data 1512.

[0100] Because carrier sense 1508 is asserted and remains asserted at time T1, the first ignorable symbol 1502 is appended to the in-band data 1514 received by the MAC. Similarly, because carrier sense 1508 is asserted and remains asserted at time T2, the second ignorable symbol 1506 is appended to the in-band data 1504. Because emulated carrier sense 1510 is asserted but does not remain asserted at time T2, the first ignorable symbol 1502 is not appended to the in-band data 1514 received by the MAC. Because emulated carrier sense 1510 is asserted but does not remain asserted at time T2, the second ignorable symbol 1506 is not appended to the in-band data 1504.

[0101] Those skilled in the art will appreciate that the functional elements (e.g., functions, operations, actions, processes, and / or methods) of the embodiments disclosed herein may be implemented in any suitable hardware, software, firmware, or combination thereof. Figure 16 illustrates a non-limiting example of how the functional elements disclosed herein may be implemented. In some embodiments, some or all of the functional elements disclosed herein may be performed by hardware specially configured to perform the functional elements.

[0102] FIG. 16 is a block diagram of a circuit 1600 that, in some embodiments, may be used to implement various functions, operations, acts, processes, and / or methods disclosed herein. The circuit 1600 includes one or more processors 1602 (sometimes referred to herein as “processors 1602”) operably coupled to one or more data storage devices (sometimes referred to herein as “storage devices 1604”). The storage devices 1604 include machine-executable code 1606 stored thereon, and the processors 1602 include logic circuitry 1608. The machine-executable code 1606 includes information describing functional elements that may be implemented (e.g., executed) by the logic circuitry 1608. The logic circuitry 1608 is adapted to implement (e.g., execute) the functional elements described by the machine-executable code 1606. The circuitry 1600, when executing the functional elements described by the machine-executable code 1606, should be considered dedicated hardware configured to execute the functional elements disclosed herein. In some embodiments, processor 1602 may be configured to execute the functional elements described by machine-executable code 1606 sequentially, concurrently (e.g., on one or more different hardware platforms), or in one or more parallel processing streams.

[0103] When implemented by the logic circuitry 1608 of the processor 1602, the machine-executable code 1606 is configured to cause the processor 1602 to perform the operations of the embodiments disclosed herein. As a non-limiting example, the machine-executable code 1606 may be configured to cause the processor 1602 to perform some or all of the operations of one or more of process 700, process 800, process 900, process 1000, process 1100, process 1200, timing diagram 1300, timing diagram 1400, or timing diagram 1500.

[0104] Also, by way of non-limiting example, machine-executable code 1606 may be configured to cause processor 1602 to adapt to perform some or all of the features, functions, or operations disclosed herein for one or more of apparatus 100, PHY side 200 of the PHY-MAC interface, interface portion 300, symbol filter 400, symbol filter 500, or symbol filter 600. More specifically, the features, functions, or operations disclosed herein for one or more of PHY side 102 of the PHY-MAC interface, logic circuitry 104 or symbol filter 106, interface 204, interface wrapper 206 or symbol filter 208, PHY side 304 of the MII, PHY side 306 of the RMII wrapper, symbol filter 308, match logic 402, detection logic 406 or suppression logic 408, match logic 502 or suppression logic 506, or detection logic 602 or suppression logic 604.

[0105] The processor 1602 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. While a general-purpose computer including a processor is considered a special-purpose computer, the general-purpose computer is also configured to execute functional elements corresponding to machine-executable code 1606 (e.g., software code, firmware code, hardware description) related to embodiments of the present disclosure. Note that while the general-purpose processor (sometimes referred to herein as a host processor or simply host) may be a microprocessor, the processor 1602 may alternatively include any conventional processor, controller, microcontroller, or state machine. The processor 1602 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in combination with a DSP core, or any other such configuration.

[0106] In some embodiments, memory 1604 includes volatile data storage (e.g., random access memory (RAM)), non-volatile data storage (e.g., flash memory, hard disk drive, solid state drive, erasable programmable read-only memory (EPROM), etc.). In some embodiments, processor 1602 and memory 1604 may be implemented in a single device (e.g., a semiconductor device product, a system-on-chip (SOC), etc.). In some embodiments, processor 1602 and memory 1604 may be implemented in separate devices.

[0107] In some embodiments, machine-executable code 1606 may include computer-readable instructions (e.g., software code, firmware code). As a non-limiting example, the computer-readable instructions may be stored by storage device 1604, accessed directly by processor 1602, and executed by processor 1602 using at least logic circuitry 1608. Also, as a non-limiting example, the computer-readable instructions may be stored in storage device 1604, transferred for execution to a memory device (not shown), and executed by processor 1602 using at least logic circuitry 1608. Thus, in some embodiments, logic circuitry 1608 includes electrically configurable logic circuitry 1608.

[0108] In some embodiments, machine-executable code 1606 may describe hardware (e.g., circuits) to be implemented in logic circuitry 1608 to perform the functional elements. This hardware may be described at any of a variety of levels of abstraction, from low-level transistor layouts to high-level description languages. At high levels of abstraction, a hardware description language (HDL) such as the IEEE Standard Hardware Description Language (HDL) may be used. As non-limiting examples, Verilog, SystemVerilog, or very large scale integration (VLSI) hardware description language (VHDL) may be used.

[0109] The HDL description may be converted into a description at any of a number of other levels of abstraction, as desired. As a non-limiting example, the high-level description may be converted into a logic-level description, such as a register-transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, the micro-operations performed by hardware logic circuits (e.g., without limitation, gates, flip-flops, registers) of logic circuit 1608 may be described in RTL and then converted by a synthesis tool into a GL description, which may be converted by a place-and-route tool into a layout-level description that corresponds to the physical layout of an integrated circuit of programmable logic devices, discrete gate or transistor logic, discrete hardware components, or combinations thereof. As a result, in some embodiments, machine-executable code 1606 may include HDL, RTL, a GL description, a mask-level description, other hardware descriptions, or any combination thereof.

[0110] In embodiments in which machine-executable code 1606 includes a hardware description (at any level of abstraction), a system (not shown, but including storage 1604) may be configured to implement the hardware description described by machine-executable code 1606. As a non-limiting example, processor 1602 may include a programmable logic device (e.g., an FPGA or PLC), and logic circuitry 1608 may be electronically controlled to implement circuitry in logic circuitry 1608 that corresponds to the hardware description. Also, as a non-limiting example, logic circuitry 1608 may include hardwired logic manufactured by a manufacturing system (not shown, but including storage 1604) according to the hardware description in machine-executable code 1606.

[0111] Regardless of whether the machine-executable code 1606 includes computer-readable instructions or a hardware description, the logic circuitry 1608, when implementing the functional elements of the machine-executable code 1606, is adapted to perform the functional elements described by the machine-executable code 1606. Note that the hardware description may not directly describe the functional elements, but rather the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description can perform.

[0112] The terms used in this disclosure, and particularly in the appended claims (e.g., the body of the appended claims), are generally intended as "open" terms (e.g., the term "including" should be interpreted as "including, but not limited to," the term "having" should be interpreted as "having at least," the term "includes" should be interpreted as "includes, but is not limited to," etc.).

[0113] Additionally, if a specific number of introduced claim recitations is intended, such intention will be expressly recited in the claim; absent such recitation, no such intention exists. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed as limiting any particular claim that includes such introduced claim recitations to embodiments that include only one of such recitations (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"), even if the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article such as "a" or "an" (e.g., "a" and / or "an" should be construed to mean "at least one" or "one or more"). The same is true for the use of express articles used to introduce claim recitations.

[0114] Additionally, even when a specific number of introduced claim recitations are explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g., the explicit recitation of "two recitations" without other modifiers means at least two recitations or more than two recitations). Furthermore, when conventions similar to "at least one of A, B, and C, etc." or "one or more of A, B, and C, etc." are used, it is generally intended that such constructions include A only, B only, C only, A and B together, A and C together, B and C together, or A, B, and C together. As used herein, "each" means part or whole, and "each and every" means whole.

[0115] Furthermore, any disjunction or phrase presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one of the terms, either of the terms, or both terms. For example, the phrase "A or B" should be understood to include the possibilities of "A" or "B" or "A and B."

[0116] Further non-limiting examples of the present disclosure are as follows. Example 1: A method comprising: conveying symbols from a PHY towards a MAC via a PHY side of a PHY-MAC interface; and filtering one or more symbols at an input of the PHY side of an interface wrapper on the PHY side of the PHY-MAC interface.

[0117] Example 2: The method described in Example 1, wherein the step of filtering one or more symbols present at a PHY-side input of an interface wrapper on the PHY side of the PHY-MAC interface includes the steps of detecting a symbol corresponding to a predetermined symbol and suppressing signaling to the PHY-side input of the interface wrapper associated with the symbol.

[0118] Example 3: The method of any of Examples 1 and 2, wherein the predetermined symbol is associated with out-of-band data.

[0119] Example 4: The method of any of Examples 1 to 3, wherein the predetermined symbols are associated with physical layer collision avoidance.

[0120] Example 5: The method of any one of Examples 1 to 4, wherein the signaling is associated with the state of a carrier of a shared transmission medium.

[0121] Example 6: A method as described in any one of Examples 1 to 5, wherein the step of filtering one or more symbols present at a PHY-side input of an interface wrapper on the PHY side of the PHY-MAC interface includes the steps of detecting an assertion of an out-of-band data indication, and initiating a step of suppressing signaling at the PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface at least in part in response to the step of detecting the assertion of the out-of-band data indication, and detecting a deassertion of the out-of-band data indication, and stopping the step of suppressing signaling at the PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface at least in part in response to the step of detecting the deassertion of the out-of-band data indication.

[0122] Example 7: A method as described in any one of Examples 1 to 6, wherein the step of filtering one or more symbols present at a PHY-side input of an interface wrapper on the PHY side of the PHY-MAC interface includes: detecting a deassertion of a valid data indication; and initiating a step of suppressing signaling at the PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface in response to at least part of the step of detecting the deassertion of the valid data indication; and detecting an assertion of a valid data indication; and stopping the step of suppressing signaling at the PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface in response to at least part of the step of detecting the assertion of the valid data indication.

[0123] Example 8: A method as described in any one of Examples 1 to 7, wherein the step of filtering one or more symbols present at a PHY-side input of an interface wrapper on the PHY side of the PHY-MAC interface includes: detecting a deassertion of a valid data indication and an assertion of an out-of-band data indication; initiating a step of suppressing signaling at a PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface at least in part in response to the step of detecting a deassertion of the valid data indication and an assertion of the out-of-band data indication; and detecting a deassertion of the valid data indication and an out-of-band data indication; and stopping the step of suppressing signaling at a PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface at least in part in response to the step of detecting a deassertion of the valid data indication and an assertion of the out-of-band data indication.

[0124] Example 9: The method of any one of Examples 1 to 8, wherein the step of filtering one or more symbols present at a PHY-side input of an interface wrapper on the PHY side of the PHY-MAC interface includes: detecting a symbol corresponding to a predetermined symbol; detecting at least one of a deassertion of a valid data indication or an assertion of an out-of-band data indication; initiating a step of suppressing signaling at a PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface corresponding to the symbol, at least in part, in response to the step of deasserting the valid data indication or the assertion of the out-of-band data indication; and stopping the step of suppressing signaling at a PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface corresponding to the symbol, at least in part, in response to the step of asserting the valid data indication or the deassertion of the out-of-band data indication.

[0125] Example 10: An apparatus comprising: a PHY side of a PHY-MAC interface; and logic circuitry provided on the PHY side of the PHY-MAC interface, the logic circuitry including a filter for filtering one or more symbols conveyed over the PHY side of the PHY-MAC interface.

[0126] Example 11: The apparatus of Example 10, wherein the PHY side of the PHY-MAC interface includes a PHY side of the interface and a PHY side of an interface wrapper, and the filter is coupled to filter an input of the PHY side of the interface wrapper.

[0127] Example 12: The apparatus of any of Examples 10 and 11, wherein the filter filters one or more symbols at least partially in response to detecting out-of-band data.

[0128] Example 13: The apparatus of any of Examples 10 to 12, wherein the filter includes detection logic for detecting one or both of an assertion of an indication of out-of-band data or a deassertion of an indication of valid data, match logic for detecting a symbol corresponding to a predetermined symbol, and suppression logic for suppressing signaling at a PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface at least partially in response to the detection by the detection logic and the detection by the match logic.

[0129] Example 14: The apparatus of any of Examples 10 to 13, wherein the suppressed signaling is associated with a detected carrier state of the shared transmission medium.

[0130] Example 15: The apparatus of any of Examples 10 to 14, wherein the filter includes match logic for detecting a symbol corresponding to a predetermined symbol, and suppression logic for suppressing signaling at a PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface at least partially in response to the detection by the match logic.

[0131] Example 16: The apparatus of any of Examples 10 to 15, wherein the filter includes detection logic for detecting one or both of an assertion of an indication of out-of-band data or an assertion of an indication of valid data, and suppression logic for suppressing signaling at a PHY-side input of the interface wrapper on the PHY side of the PHY-MAC interface at least partially in response to detection by the detection logic.

[0132] Example 17: The apparatus of any of Examples 10 to 16, wherein the PHY side of the interface wrapper is a reduced media independent interface wrapper.

[0133] Example 18: The apparatus according to any one of Examples 10 to 17, wherein the filtered symbols are physical layer collision avoidance symbols.

[0134] The filtered symbols are physical layer collision avoidance symbols. 10.

[0135] While the present disclosure has been described herein with reference to certain illustrated embodiments, those skilled in the art will recognize and appreciate that the present invention is not so limited. Rather, numerous additions, deletions, and modifications may be made to the illustrated and described embodiments without departing from the scope of the present invention as claimed below, along with their legal equivalents. In addition, features of one embodiment may be combined, as contemplated by the inventor, with features of other disclosed embodiments and still fall within the scope of the present disclosure.

Claims

1. 1. A method comprising: conveying symbols from the PHY towards the MAC via the PHY side of the PHY-MAC interface; filtering one or more symbols at an input of a PHY-side interface wrapper on the PHY side of the PHY-MAC interface.

2. The step of filtering one or more symbols present at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface comprises: detecting a symbol corresponding to a predetermined symbol; and suppressing signaling to the input on the PHY side of the interface wrapper associated with the symbol.

3. The method of claim 2 , wherein the predetermined symbol is associated with out-of-band data.

4. The method of claim 2 , wherein the predetermined symbol is associated with physical layer collision avoidance.

5. The method of claim 2 , wherein the signaling is associated with a state of a carrier of a shared transmission medium.

6. The step of filtering one or more symbols present at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface comprises: detecting assertion of an out-of-band data indication; initiating, at least in part in response to the detecting the assertion of the out-of-band data indication, suppressing signaling at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface; detecting a deassertion of the out-of-band data indication; and ceasing the step of suppressing signaling at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface in response at least in part to the step of detecting the deassertion of the out-of-band data indication.

7. The step of filtering one or more symbols present at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface comprises: detecting a deassertion of the valid data indication; initiating, at least in part in response to the detecting the deassertion of the valid data indication, suppressing signaling at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface; detecting assertion of a valid data indication; and ceasing, at least in part, in response to the detecting the assertion of the valid data indication, suppressing signaling at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface.

8. The step of filtering one or more symbols present at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface comprises: detecting a deassertion of a valid data indication and an assertion of an out-of-band data indication; initiating, at least in part in response to the detecting the deassertion of the valid data indication and the assertion of the out-of-band data indication, suppressing signaling at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface; detecting assertion of a valid data indication and deassertion of an out-of-band data indication; and ceasing the step of suppressing signaling at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface in response at least in part to the step of detecting the assertion of the valid data indication and the deassertion of the out-of-band data indication.

9. The step of filtering one or more symbols present at an input on a PHY side of an interface wrapper on a PHY side of the PHY-MAC interface comprises: detecting a symbol corresponding to a predetermined symbol; detecting at least one of a deassertion of a valid data indication or an assertion of an out-of-band data indication; initiating, at least in part in response to the detecting at least one of deasserting a valid data indication or asserting the out-of-band data indication, suppressing signaling at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface corresponding to the symbol; detecting at least one of an assertion of a valid data indication or a deassertion of an out-of-band data indication; and ceasing suppressing signaling at the input of the PHY side of the interface wrapper of the PHY side of the PHY-MAC interface corresponding to the symbol, at least in part in response to detecting at least one of the assertion of the valid data indication or the deassertion of the out-of-band data indication.

10. 1. An apparatus comprising: the PHY side of the PHY-MAC interface; logic circuitry provided on a PHY side of the PHY-MAC interface, the logic circuitry including a filter for filtering one or more symbols conveyed over the PHY side of the PHY-MAC interface.

11. The PHY side of the PHY-MAC interface is the PHY side of the interface; a PHY side of the interface wrapper; The apparatus of claim 10 , wherein the filter is coupled to filter an input on a PHY side of the interface wrapper.

12. 12. The apparatus of claim 11, wherein the filter filters one or more symbols at least in part in response to detecting out-of-band data.

13. The filter is detection logic for detecting one or both of an assertion of an indication of out-of-band data or a deassertion of an indication of valid data; Matching logic for detecting symbols corresponding to predetermined symbols; suppression logic for suppressing signaling at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface in response at least in part to detection by the detection logic and detection by the match logic.

14. The apparatus of claim 13 , wherein the suppressed signaling is associated with detected carrier conditions of the shared transmission medium.

15. The filter is Matching logic for detecting symbols corresponding to predetermined symbols; suppression logic for suppressing signaling at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface in response at least in part to a detection by the match logic.

16. The filter is detection logic for detecting one or both of an assertion of an indication of out-of-band data or an assertion of an indication of valid data; suppression logic for suppressing signaling at the input of the PHY side of the interface wrapper on the PHY side of the PHY-MAC interface in response at least in part to detection by the detection logic.

17. The apparatus of claim 11 , wherein the PHY side of the interface wrapper is a reduced media independent interface wrapper.

18. The apparatus of claim 10 , wherein the filtered symbols are physical layer collision avoidance symbols.

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