Method and system for dynamically improving low task storage depth latency in solid state drive devices

Abstract

A system and method are provided for dynamically changing the operating clock frequency of a circuit. Control circuitry determines a first workload value for the circuit operating at a first clock frequency. The control circuitry then detects a second workload value for the circuit that is less than the first workload value. If the control circuitry detects the second workload value, the control circuitry calculates a second clock frequency that is greater than the first clock frequency. The control circuitry then operates the circuit at the second clock frequency.

Description

[Technical Field]

[0001] The present disclosure relates to storage device systems and methods for dynamically changing the operating clock frequency of a circuit, and more particularly to determining the operating clock frequency based on low queue workload in the circuit. Summary of the Invention

[0002] According to the present disclosure, systems and methods are provided for improving the operational quality of a circuit (e.g., improving the latency of the circuit when task storage for the circuit has a low workload). In some embodiments, the circuit (e.g., of a hardware accelerator in a storage device) includes at least one pipeline processor having task storage of instructions for execution by the at least one processor. In some embodiments, the circuit may be any other suitable circuit.

[0003] In some embodiments, the method may include using control circuitry to determine a first workload value for the circuit operating at a first clock frequency. The method further includes using the control circuitry to detect a second workload value for the circuit that is less than the first workload value. If the control circuitry detects the second workload value, the control circuitry calculates a second clock frequency that is greater than the first clock frequency. The control circuitry then operates the circuit at the second clock frequency.

[0004] In some embodiments, the control circuitry also determines a third workload value for the circuit operating at the third clock frequency. The control circuitry further detects a fourth workload value greater than the third workload value. In this instance, in response to the control circuitry detecting the fourth workload value greater than the third workload value, the control circuitry calculates a fourth clock frequency less than the third clock frequency. If a fourth clock frequency is calculated, the control circuitry operates the circuit at the fourth clock frequency. In some embodiments, the circuit may be a solid-state drive (SSD) pipeline accelerator or a network controller pipeline hardware accelerator.

[0005] In some embodiments, the first and second workload values ​​are measured by the number of instructions scheduled for execution by the circuit. In some embodiments, the workload value is measured by the number of instructions scheduled for execution by the circuit. In some embodiments, the instructions or instructions are stored in a task storage communicatively coupled to the circuit. In some embodiments, the instructions or instructions may be stored in the task storage (e.g., a buffer, a stack, a queue) before being executed by the circuit.

[0006] In some embodiments, the control circuitry may calculate the second clock frequency by using a linear function. For example, the linear function may be a relationship between the operating clock frequency of the circuit and the workload value. In some embodiments, using the linear function to calculate the second clock frequency is further based on a ratio of the minimum operable clock frequency of the circuit, the maximum operable clock frequency of the circuit, and the second workload value to a maximum workload capacity of the task storage. In some embodiments, calculating the second clock frequency includes comparing the second workload value to a reference workload value. If the control circuitry determines that the second workload value is less than the reference workload value, the control circuitry operates the circuit at a third clock frequency. If the control circuitry determines that the second workload value is greater than the reference workload value, the control circuitry operates the circuit at a fourth clock frequency that is lower than the third clock frequency. In some embodiments, calculating the second clock frequency includes determining a range from a plurality of ranges of workload values ​​corresponding to the second workload value. In this embodiment, each range of the plurality of ranges of workload values ​​corresponds to a respective clock frequency. If the range of workload values ​​is determined, the control circuitry selects the clock frequency to be the second clock frequency.

[0007] In some embodiments, the control circuitry operates the circuit at the second clock frequency by coupling the circuit to a voltage rail from a number of voltage rails based on the second clock frequency, In some embodiments, operating the circuit at the second clock frequency includes varying the voltage of the circuit using a power management integrated circuit (PMIC) coupled to the circuit.

[0008] In some embodiments, a solid-state drive (SSD) storage system is provided having an SSD pipeline accelerator and a storage controller communicatively coupled to the SSD pipeline accelerator. In some embodiments, the storage controller is configured to determine a first workload value for a circuit operating at a first clock frequency and detect a second workload value for the circuit that is less than the first workload value. Once the storage controller detects the second workload value for the circuit, the storage controller calculates a second clock frequency for the circuit that is greater than the first clock frequency and operates the circuit at the second clock frequency. [Brief explanation of the drawings]

[0009] The following description includes discussion of figures having illustrations given as examples of implementations of embodiments of the present invention. The figures should be understood as examples and not as limitations. As used herein, reference to one or more "embodiments" will be understood as describing particular features, structures, and / or characteristics included in at least one implementation of the present invention. Thus, phrases such as "in one embodiment" or "in an alternative embodiment" found herein may describe various embodiments and implementations of the present invention, and may not necessarily all refer to the same embodiment. However, they are not necessarily mutually exclusive.

[0010] [Figure 1] FIG. 2 is an exemplary diagram of control circuitry for dynamically changing circuit clock control based on workload values, according to some embodiments of the present disclosure.

[0011] [Figure 2] FIG. 1 is an exemplary diagram of a system for dynamically changing a clock frequency of a circuit, according to some embodiments of the present disclosure.

[0012] [Figure 3A]1 is an exemplary graph providing an example relationship between workload values ​​and operating frequencies, according to some embodiments of the present disclosure.

[0013] [Figure 3B] 10 is an alternative exemplary graph providing another example relationship between workload values ​​and operating frequencies, according to some embodiments of the present disclosure.

[0014] [Figure 3C] 10 is another example graph providing another example relationship between workload values ​​and operating frequencies, in accordance with some embodiments of the present disclosure.

[0015] [Figure 4] 1 is a flowchart for determining and setting a clock frequency based on a workload value, according to some embodiments of the present disclosure.

[0016] [Figure 5] 10 is another flowchart for determining and setting a clock frequency based on a workload value, according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0017] According to the present disclosure, systems and methods are provided for improving the operation quality of a circuit (e.g., improving latency when an instruction task storage has a small number of instructions). In some embodiments, the task storage may be an instruction buffer, an instruction stack, or an instruction queue for the circuit. A circuit (e.g., a hardware accelerator in a storage device or a network device) may have a pipeline processor having a task storage of instructions for execution by at least one processor. In some embodiments, the pipeline processor may process multiple instructions from the task storage simultaneously, for example, by dividing each processor core into stages (e.g., based on role and available resources). For example, each processor core may be divided into four stages: fetch, decode, execute, and writeback. Each of these stages may operate in parallel on one or more operations of an instruction per clock cycle. However, in general, for each instruction, operations must still proceed sequentially across clock cycles. An instruction decode operation cannot necessarily begin before the instruction fetch operation is completed. Thus, the pipeline processor of this embodiment is capable of executing four different instructions during a single clock cycle. In some alternative embodiments, the pipeline may have more stages or more complex systems or features for reordering, prioritizing, or predicting the outcome of particular instructions buffered for execution. A pipeline processor may also begin processing a next instruction and complete a stage before the previous instruction has finished.

[0018] In one approach, if the instruction or command task storage has a small number of instructions (e.g., below a certain percentage of the total task storage size), the pipeline processor may execute the instructions or commands while operating at a normal or reduced frequency (e.g., at the same or lower frequency than if there were more instructions in the task storage). However, in this approach, the latency of the circuit increases because there are not enough instructions or commands to fill the pipeline.

[0019] To solve this problem, the operation of the circuit can be adjusted to increase the frequency of the circuit when the number of instructions or commands in the task storage is reduced. In this way, the latency of the circuit is reduced in situations where the number of instructions or commands in the task storage is low.

[0020] In some embodiments, a pipeline processor may be a highly parallelized processor capable of quickly handling high-bandwidth instructions (e.g., by beginning simultaneous processing of new instructions before the completion of previous instructions). In one example, multiple instances of a task may be completed in parallel, such that each task of the same type has the same latency. That is, by leveraging parallelism, such a processor may be able to process tasks at a higher rate if it is given more tasks. However, if task storage is low for a task (e.g., instructions or instructions), a parallelized pipeline processor may not be able to fully exploit such parallel processes (e.g., because there may not be enough new instructions to begin processing while previous instructions are being processed). As explained above and below, when such a situation occurs, the frequency of the processor may be increased to reduce the latency of task execution and mitigate the lack of parallelism.

[0021] In some embodiments, the systems and methods of the present disclosure may refer to a solid-state drive (SSD) storage system, which includes an SSD pipeline accelerator and a storage controller or pipeline processor and a network controller for a transport layer protocol (e.g., PCIe).

[0022] A solid-state drive (SSD) is a data storage device that uses integrated circuit assemblies as memory to persistently store data. SSDs have no moving mechanical components, which distinguishes them from traditional electromechanical magnetic disks, such as hard disk drives (HDDs) or floppy disks, which contain rotating disks and movable read / write heads. Compared to electromechanical disks, SSDs are typically more resistant to physical shock, operate quieter, and have shorter access times and lower latency.

[0023] Many types of SSDs use NAND-based flash memory, which retains data without power and includes some type of non-volatile storage technology. SSD Quality of Service (QoS) can refer to predictably low latency and consistently high input / output operations per second (IOPS) while processing read / write input / output (I / O) workloads. This means that latency or I / O instruction completion time must be within a specific range without unexpected outliers. Throughput or I / O speed may also need to be tightly controlled without causing sudden drops in performance levels.

[0024] The subject matter of the present disclosure may be better understood with reference to FIGS.

[0025] FIG. 1 shows an example diagram of control circuitry 100 for dynamically changing a circuit clock by circuit clock control 116 for a circuit (e.g., a hardware accelerator in an SSD drive or a network card) based on a workload value 104 of the circuit. In some embodiments, control circuitry 100 includes a load detector 102 that determines the workload value 104 of a task storage of instructions or commands for the circuit. In some embodiments, the task storage may be an instruction buffer, an instruction stack, or an instruction queue for the circuit. For example, a circuit (e.g., a solid-state drive) has a processor and task storage of instructions to be executed by the processor. In this example, control circuitry 100 may be located within a storage device or may be located external to the storage device. Load detector 102 receives task storage information from the task storage and outputs workload value 104. In some embodiments, workload value 104 is used by clock adjuster 106, which determines an adjusted clock frequency 114 for the storage device. In some embodiments, adjusted clock frequency 114 is also based on minimum operational clock frequency 110 and maximum operational clock frequency 112 for the circuit, which may be set as circuit-specific or adjustable variables that may be requested by control circuitry 100 for clock adjuster 106. In some embodiments, adjusted clock frequency 114 is received by clock control 116, which selects the circuit for which a new circuit clock signal 118 is set to adjusted clock frequency 114. In some embodiments, if control circuitry 100 effects dynamic clock frequency changes on multiple circuits, clock control 116 may use the selected bit to determine to which circuit clock signal to send the new circuit clock signal.

[0026] Any of the load detector 102, the clock adjuster 106, and the clock control 116 may include a processor and memory. In some embodiments, the processor of any of the load detector 102, the clock adjuster 106, and the clock control 116 may include a hardware processor, a software processor, or any combination thereof. In some embodiments, any of the load detector 102, the clock adjuster 106, and the clock control 116 may be hardwired circuitry, a software module emulating hardware (e.g., a logic block), or a combination thereof. In some embodiments, the control circuitry 100 may include a single software processor (e.g., a processor emulated using a virtual machine). Each processor may include a hardware processor, a software processor, or any combination thereof. In some embodiments, the combined processor and memory may be referred to as the control circuitry 100. In some embodiments, a processor alone may be referred to as the control circuitry 100. The memory of the control circuitry 100 may include hardware elements for non-transitory storage of instructions or commands, a history of the workload value 104, and a minimum operational clock frequency 110 and a maximum operational clock frequency 112. In some embodiments, the control circuitry 100 may dynamically change the clock frequencies of multiple circuits, where each respective circuit has task storage and a processor operating at a respective clock frequency. For example, if the workload value decreases, the load detector 102 detects the decrease and determines a smaller workload value 104, which is sent to the clock adjuster 106. The clock adjuster 106 then determines an adjusted clock frequency 114 based on the workload value 104, the minimum operational circuit clock frequency 110, and the maximum operational circuit clock frequency 112. The adjusted clock frequency 114 is then sent to the clock control 116, which sets the circuit's clock signal 118 frequency to the adjusted clock frequency 114.The adjusted clock frequency 114 may be determined by using the techniques and relationships shown in one or more of graphs 300, 310, or 320 of Figures 3A, 3B, and 3B, respectively.

[0027] FIG. 2 illustrates an example diagram of a system 200 for dynamically changing the operating frequency of a circuit, according to some embodiments of the present disclosure. FIG. 2 illustrates an example diagram of a system 200 for dynamically changing the operating frequency of a pipeline processor 212 (e.g., a processor in an SSD drive or a network card), according to some embodiments of the present disclosure. In some embodiments, the system 200 includes control circuitry 202, which determines and sets a new circuit clock frequency 210 for the circuit 204. In some embodiments, the control circuitry 202 may be the same control circuitry 100 as shown in FIG. 1. In some embodiments, the control circuitry 202 may perform the functions of the load detector 102, the clock adjuster 106, and / or the clock adjuster 116 through software, hardware, or a combination thereof. The circuit 204 includes a circuit clock input 206, a task storage 208 for temporarily storing instructions or commands, and a pipeline processor 212. In some embodiments, the task storage 208 may be an instruction buffer, an instruction stack, or an instruction queue for the circuit 204. In some embodiments, the circuit 204 may include a memory 216, which may be located inside or outside the circuit 204. In some embodiments, the pipeline processor 212 is communicatively coupled to a task storage 208 (e.g., a buffer, stack, or queue), a clock signal 206, and the memory 216. Additionally, the pipeline processor 212 is communicatively coupled to a circuit output 214. In some embodiments, the pipeline processor 212 can write to or read from the task storage 208, which temporarily stores instructions or commands that are scheduled for execution. The capacity of the task storage 208 is defined by the maximum number of instructions or commands that can be stored in the task storage 208. In general, the task storage size refers to the number of instructions or commands currently stored in the task storage 208.In some embodiments, status data of task storage 208 (e.g., task storage size and task storage capacity) is received by control circuitry 202 to determine an adjusted operational clock frequency 210, which is set as a new clock signal 206 for circuit 204. For example, control circuitry 202 determines a workload value for circuit 204 operating at a first clock frequency. The first workload value is determined by receiving task storage size data from task storage 208 of circuit 204. A load detector of control circuitry 202 determines the first workload value while circuit 204 operates at the first clock frequency. If the first workload value is determined, control circuitry 202 determines whether there is a change in the workload value. In some embodiments, there may be multiple circuits electrically coupled to control circuitry 202. In these embodiments, control circuitry 202 may be performing multiple determinations in parallel and outputting new clock signals to multiple circuits of the multiple circuits.

[0028] In some embodiments, control circuitry 202 determines adjusted operational clock frequency 210 by an equation or formula. For example, control circuitry 202 may calculate adjusted operational frequency f using the following equation:

number

[0029] For example, the same equation found in the immediately preceding paragraph can be used to calculate an adjusted operational frequency for a circuit having an internal circuit latency of 12 microseconds. The internal circuit latency is the time it takes for the circuit to process an instruction. Additionally, additional latency from the worst-case latency of 50 microseconds (e.g., for a read instruction) may be incurred due to the need to access a memory device (e.g., to read 4 KB of data). Thus, in this example, the approximate total worst-case latency for a read command for 4 KB of read data is approximately 62 microseconds (12 μs + 50 μs). Consequently, in this example, the maximum frequency for the clock signal is approximately 16.1 kilohertz (1 / 62 μs) to process instructions with the worst-case latency. In this example, control circuitry 202 determines a first workload value for a 4 KB read command in task storage for a circuit operating at a first clock frequency (lower than the maximum frequency of 16.1 kilohertz). If the control circuitry 202 determines that the number of 4 KB read commands in the circuit's task storage has decreased to a second workload value, the control circuitry 202 then calculates a second clock frequency that is greater than the first clock frequency but less than a maximum frequency (e.g., a maximum frequency of 16.1 kilohertz). The control circuitry 202 then operates the circuit at the second clock frequency.

[0030] The control circuitry 202 is configured to increase the clock frequency of the circuit when the workload value decreases and decrease the clock frequency of the circuit when the workload value increases. The circuit 204 has a worst-case latency that includes network latency between components, task storage 208 read latency, memory read latency, and processor 212 latency. In some embodiments, the worst-case latency corresponds to a minimum operational circuit clock frequency. This minimum operational circuit clock frequency ensures a minimum throughput even at high workload values. When the workload value decreases, the clock frequency can be increased to achieve higher throughput while the workload value continues to decrease.

[0031] 3A, 3B, and 3C show example graphs 300, 310, and 320 that provide various relationships between workload values ​​and operating frequency, according to some embodiments of the present disclosure. For each graph 300, 310, and 320, the workload independent variable 304, 314, and 324 may also be referred to as the workload value 104 from FIG. 1. In some embodiments, control circuitry (e.g., control circuitry 202) may use the formula or relationship illustrated by graphs 300, 310, and 320 to determine the operating clock frequency 302, 312, and 322 based on the workload value 304, 314, and 324 of the task storage (e.g., task storage 208). In some embodiments, the task storage may be an instruction buffer, instruction stack, or instruction queue for the circuit. In some embodiments, the workload value is the task storage size, or how many instructions or commands are currently stored in the task storage. In some embodiments, the workload value is the percentage of task storage memory that contains stored instructions or commands. Operating frequencies 302, 312, and 322 refer to operating clock frequencies that are set as new clock signals for a circuit (e.g., circuit 204). In FIG. 3A, graph 300 illustrates a linear, inverse relationship between workload 304 and operating frequency 302. For example, operating frequency 302 may be inversely proportional to the ratio of task storage workload 304 to task storage capacity. In this example, because task storage stores more instructions and commands, workload 304 increases and task storage capacity remains constant, thus increasing the ratio. For example, graph 300 may be part of a linear relationship between the operating frequency (f) 302 and workload value (q) 304 of a circuit, such as:

number

[0032] 3B shows a graph 310 with an alternative relationship, where the change in operating frequency 312 becomes smaller with each incremental increase in task storage workload 314. Furthermore, when task storage workload 314 reaches a certain value, the relationship begins to become more linear. Although this hyperbolic correlation is shown in FIG. 3B for the control circuitry, the control circuitry may use any other suitable decreasing hyperbolic function (e.g., a hyperbolic function with a decreasing negative slope) to calculate the adjusted operating frequency.

[0033] FIG. 3C illustrates a graph 320 in which the operating frequency 322 determined by the control circuitry is determined by a step function of the task storage workload 324. There is a range of workload 324 values ​​that corresponds to a single operating frequency 322. In this example graph 320, there are five different workload 324 ranges shown with five corresponding operating frequencies 322. For example, a circuit having a task storage capacity of 8 KB may cause the circuit's control circuitry to determine the circuit's operating frequency 322 as shown in graph 320. For the workload value 324 ranges from 256 KB to 1 KB, the operating frequency 322 is 80 MHz. For the workload value 324 ranges from 1 KB to 3 KB and from 3 KB to 5 KB, the corresponding operating frequencies 322 are 70 MHz and 55 MHz, respectively. Finally, the workload value 324 ranges from 5 KB to 7.5 KB and from 7.5 KB to 8 KB correspond to operating frequencies 322 of 40 MHz and 32 MHz, respectively. The step in the operating frequency 322 may be determined by the control circuitry as the most efficient operating frequency 322 for a given range of workload values ​​324 that does not frequently change the operating frequency 322. Although this step function is shown in FIG. 3C for the control circuitry, the control circuitry may use any other suitable decreasing step function to calculate the adjusted operating frequency.

[0034] In some embodiments, portions of each of these graphs may be used for specific ranges of workload 304, 314, 324 values. For example, within a first range of workload values, the relationship between task storage workload and operating frequency is linear; however, within a second range of workload values, the relationship between task storage workload and operating frequency is hyperbolic. This example illustrates multiple relationship configurations for workloads 304, 314, and 324 and operating frequencies 302, 312, 322 that may be used for a circuit. In some embodiments, the operating frequency 302, 312, 322 may be increased if the workload value is at task storage capacity and requires a higher frequency to avoid a bottleneck in throughput. Furthermore, for each circuit, there exists a maximum operable circuit frequency and a minimum operable circuit frequency, which may be understood as the endpoints of each relationship in graphs 300, 310, and 320.

[0035] 4 illustrates a flowchart 400 for determining and setting a clock frequency based on a workload value, according to some embodiments of the present disclosure. The flowchart illustrates a method performed by control circuitry, which may be the same control circuitry 202 as seen in FIG. 2. In some embodiments, the steps described in flowchart 400 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0036] In stage 402, control circuitry (e.g., control circuitry 202 of FIG. 2) determines a workload value for a circuit operating at a first clock frequency. The first workload value is determined by receiving task storage size data from a task storage (e.g., task storage 208 of FIG. 2) of the circuit (e.g., circuit 204 of FIG. 2). In some embodiments, the task storage may be an instruction buffer, an instruction stack, or an instruction queue for the circuit. A load detector of the control circuitry determines the first workload value while the circuit is operating at the first clock frequency. If the first workload value is determined, the control circuitry determines whether there is a change in the workload value.

[0037] In step 404, the control circuitry determines whether the load detector detects a decrease in the workload value for the circuit. After determining the first workload value, the load detector detects whether the task storage size has decreased to a second workload value since determining the first workload value. If the control circuitry detects a decrease in the workload value, then in step 406, the control circuitry determines a second clock frequency. However, if a decrease in the workload value is not detected, then in step 410, the control circuitry operates the circuit at a clock frequency that is equal to or less than the first clock frequency.

[0038] In step 406, the control circuitry determines a second clock frequency for the circuit. The control circuitry determines the second clock frequency based on the second workload value. A clock adjuster of the control circuitry determines the second clock frequency (e.g., adjusted clock frequency 114 shown in FIG. 1 ) by using the configured relationship between the circuit's operating clock frequency and the workload value of task storage 208. As previously mentioned, the relationship between the circuit's operating clock frequency and the circuit task storage 208 workload value can be a linear relationship, a hyperbolic correlation, based on a step function, or any other suitable relationship. In some embodiments, the relationship between the circuit's operating clock frequency and the task storage workload value can vary. For example, within a first range of workload values, the relationship between the task storage workload and the operating frequency is one relationship, and within a second range of workload values, the relationship between the task storage workload and the operating frequency is another relationship, etc.

[0039] In step 408, the control circuitry operates the circuit at a second clock frequency, where the second clock frequency is greater than the first clock frequency. The clock control of the control circuitry sets the second clock frequency as a new clock signal for the circuit. As previously discussed, because the workload value has decreased, the second clock frequency is therefore greater than the first clock frequency to execute fewer instructions or commands in short bursts of time, which may result in lower latency (e.g., and thus an increased number of instructions or commands executed), for example, by utilizing available circuit power budgets. Furthermore, once the control circuitry has set the new clock signal frequency, the control circuitry then proceeds according to this closed-loop method 400 by determining a new workload value for the circuit at the new first clock frequency, where the new first clock frequency is the immediately preceding second clock frequency. In some embodiments, the control circuitry operating the circuit at the second clock frequency includes coupling the circuit to a voltage rail of a plurality of voltage rails selected based on the second clock frequency. In some embodiments, each voltage rail of the plurality of voltage rails corresponds to a different clock frequency. In some embodiments, coupling the circuit to the voltage rails may include causing a current to flow through the circuit from a selected voltage rail. In some embodiments, the control circuitry may cause the circuit to operate at a second clock frequency by varying the voltage of the circuit using a power management integrated circuit (PMIC) coupled to the circuit. In some embodiments, the PMIC uses adaptive voltage scaling (AVS), which gradually steps the voltage up or down without significantly affecting the performance of the circuit. Generally, when the voltage increases, the clock frequency also increases, and conversely, when the voltage decreases, the clock frequency decreases.

[0040] In step 410, the control circuitry operates the circuit at a clock frequency that is equal to or less than the first clock frequency. In some embodiments, the second workload value is the same as the first workload value, and therefore the control circuitry keeps the circuit clock frequency the same. However, as described in more detail below in the description of FIG. 5, if the workload value increases, the control circuitry operates the circuit at a clock frequency that is less than the first clock frequency. Furthermore, if the control circuitry operates the circuit at the new clock signal frequency, the control circuitry will then proceed with this closed-loop method 400 by determining a new workload value for the circuit at the new first clock frequency.

[0041] 5 shows another flowchart for determining and setting a clock frequency based on a workload value, according to some embodiments of the present disclosure. Flowchart 500 illustrates a method performed by control circuitry, which may be the same control circuitry 202 as seen in FIG. 2. In some embodiments, the steps described in flowchart 500 may be modified, for example, by rearranging, changing, adding, and / or removing steps.

[0042] In stage 502, the control circuitry determines a workload value for the circuit operating at a third clock frequency. The third workload value is determined by receiving task storage size data from a task storage (e.g., task storage 208) of the circuit (e.g., circuit 204). In some embodiments, the task storage may be an instruction buffer, an instruction stack, or an instruction queue for the circuit. A load detector of the control circuitry determines the third workload value while the circuit is operating at the third clock frequency. If the third workload value is determined, the control circuitry determines whether there is a change in the workload value.

[0043] In step 504, the control circuitry determines whether an increase in the workload value for the circuit has been detected. After determining the third workload value, the load detector detects whether the task storage size has increased to a fourth workload value since determining the third workload value. If the control circuitry detects an increase in the workload value, then in step 506, the control circuitry determines a fourth clock frequency. However, if an increase in the workload value is not detected, then in step 510, the control circuitry operates the circuit at a clock frequency that is equal to or greater than the third clock frequency.

[0044] In step 506, the control circuitry determines a fourth clock frequency for the circuit. The control circuitry determines the fourth clock frequency based on the fourth workload value. A clock adjuster of the control circuitry determines the fourth clock frequency (e.g., adjusted clock frequency 114 shown in FIG. 1 ) by using the configured relationship between the circuit's operating clock frequency and the task storage workload value. As previously mentioned, the relationship between the circuit's operating clock frequency and the task storage workload value can be a linear relationship, a hyperbolic correlation, based on a step function, or any other suitable relationship. In some embodiments, the relationship between the circuit's operating clock frequency and the task storage workload value can vary. For example, within a first range of workload values, the relationship between the task storage workload and the operating frequency is one relationship, and within a second range of workload values, the relationship between the task storage workload and the operating frequency is another relationship, etc.

[0045] In step 508, the control circuitry operates the circuit at a fourth clock frequency, where the fourth clock frequency is less than the third clock frequency. The clock control of the control circuitry sets the fourth clock frequency as the circuit's new clock signal. As previously discussed, the workload value may increase, and therefore the fourth clock frequency may be less than the third clock frequency to execute more instructions or commands with less circuit power consumption while maintaining at least a minimum operational circuit clock frequency, which may result in more efficient circuit power consumption. Further, if the control circuitry sets the new clock signal frequency, the control circuitry will then proceed according to this closed-loop method 500 by determining a new workload value for the circuit at the new third clock frequency, where the new third clock frequency is the immediately preceding fourth clock frequency.

[0046] In step 510, the control circuitry operates the circuit at a clock frequency equal to or greater than the third clock frequency. In some embodiments, the fourth workload value is the same as the third workload value, and therefore the control circuitry keeps the circuit clock frequency the same. However, as in method 400, if the workload value decreases, the control circuitry operates the circuit at a clock frequency greater than the third clock frequency. Furthermore, if the control circuitry operates the circuit at the new clock signal frequency, the control circuitry will then proceed with this closed-loop method 500 by determining a new workload value for the circuit at the new third clock frequency.

[0047] 5 refers to third and fourth clock frequencies, it should be noted that, with respect to the operation of the circuit, the third and fourth clock frequencies need not follow in time the first and second clock frequencies referred to in FIG. 4. In one embodiment, circuit operation follows method 400 of FIG. 4, where the circuit operates first at the first clock frequency, then at the second clock frequency, then sometime later at the third clock frequency, and finally at the fourth clock frequency (in one example, the second and third clock frequencies may be the same). In another embodiment, method 500 of FIG. 5 is performed independently from method 400 of FIG. 4. In this embodiment, the circuit operates initially at the third clock frequency and then at the fourth clock frequency. In yet another embodiment, method 500 of FIG. 5 is performed before method 400 of FIG. 4, in which case the circuit operates first at the third clock frequency, then at the fourth clock frequency, then at the first and then at the second clock frequency (e.g., in this example, the fourth and second clock frequencies may be the same).

[0048] In some embodiments, there may be multiple circuits electrically coupled to the control circuitry for either flowchart 400 or 500. In these embodiments, the control circuitry may be performing different steps of the method in parallel for some of the multiple circuits.

[0049] The terms "an embodiment," "embodiment," "embodiments," "the embodiment," "the embodiment," "the embodiment," "one or more embodiments," "some embodiments," and "one embodiment" mean "one or more (but not all) embodiments," unless expressly specified otherwise.

[0050] The terms "including," "comprising," "having," and variations thereof mean "including but not limited to," unless expressly stated otherwise.

[0051] An enumerated list of items does not imply that any or all of the items are mutually exclusive unless expressly stated otherwise.

[0052] The terms "a," "an," and "the" mean "one or more," unless expressly specified otherwise.

[0053] Devices that are in communication with each other need not be in continuous communication with each other unless expressly specified otherwise, and devices that are in communication with each other may communicate directly or indirectly through one or more intermediaries.

[0054] A description of an embodiment having multiple components in communication with each other does not imply that all such components are required. On the contrary, various optional components are described to illustrate a variety of possible embodiments. Furthermore, while process steps, method steps, algorithms, or the like may be described in a sequential order, such processes, methods, and algorithms may be configured to function in alternative orders. In other words, any sequence or order of steps that may be described does not necessarily indicate that the steps must be performed in that order. Steps of processes described herein may be performed in any practical order. Furthermore, some steps may be performed simultaneously.

[0055] Where a single device or article is described herein, it will be readily apparent that more than one device / article (whether or not they cooperate) may be used in place of the single device / article. Similarly, where more than one device or article is described herein (whether or not they cooperate), it will be readily apparent that a single device / article may be used in place of more than one such device or article, or that a different number of devices / articles may be used in place of the number of devices or programs shown. The functions and / or features of a device may alternatively be performed by one or more other devices not expressly described as having such functions / features. Thus, other embodiments need not include the device itself.

[0056] At least certain operations may be depicted in the figures indicating that certain events occur in a particular order. In alternative embodiments, certain operations may be performed in a different order, modified, or removed. Furthermore, steps may be added to the logic described above and still be consistent with the described embodiment. Furthermore, operations described herein may occur sequentially, or certain operations may be processed in parallel. Still further, operations may be performed by a single processing device or by distributed processing devices.

[0057] The foregoing description of various embodiments has been presented for purposes of illustration and description. It is not intended to be exhaustive or to be limited to the precise form disclosed. Many modifications and variations are possible in light of the above teaching.

Claims

1. determining, using control circuitry, a first workload value for the circuit operating at the first clock frequency; using the control circuitry to detect a second workload value for the circuit that is less than the first workload value; and In response to detecting the second workload value for the circuit: using the control circuitry to calculate a second clock frequency for the circuit, the second clock frequency being greater than the first clock frequency; and using said control circuitry to operate said circuit at said second clock frequency; A method comprising:

2. The method of claim 1 , wherein the circuit is one of a solid-state drive (SSD) pipeline hardware accelerator or a network controller pipeline hardware accelerator.

3. 2. The method of claim 1, wherein the first workload value and the second workload value are magnitudes of numbers of instructions scheduled for execution by the circuitry.

4. The method of claim 3 , wherein the instructions are stored in a task storage communicatively coupled to the circuitry.

5. 2. The method of claim 1, wherein calculating the second clock frequency comprises calculating the second clock frequency using a linear function based on the second workload value.

6. Using the linear function for calculating the second clock frequency includes: the minimum operational clock frequency of said circuit; a maximum operable clock frequency of said circuit; and a ratio of the second workload value to a maximum workload capacity of the circuit; The method of claim 5 further based on

7. The step of calculating the second clock frequency comprises: comparing the second workload value against a reference workload value; selecting a third clock frequency as the second clock frequency in response to determining that the second workload value is less than the reference workload value; and selecting a fourth clock frequency as the second clock frequency that is lower than the third clock frequency in response to determining that the second workload value is greater than the reference workload value.

2. The method of claim 1, comprising:

8. The step of calculating the second clock frequency comprises: determining a range from a plurality of ranges of workload values ​​to which the second workload value corresponds, wherein each range of the plurality of ranges of workload values ​​corresponds to a respective clock frequency; and selecting a clock frequency corresponding to the determined range as the second clock frequency.

2. The method of claim 1, comprising:

9. determining a third workload value for the circuit operating at a third clock frequency; detecting a fourth workload value for the circuit that is greater than the third workload value; and In response to detecting the fourth workload value for the circuit: calculating a fourth clock frequency for the circuit, the fourth clock frequency being less than the third clock frequency; and operating the circuit at the fourth clock frequency The method of claim 1 further comprising:

10. 2. The method of claim 1, wherein causing the circuit to operate at the second clock frequency comprises coupling the circuit to a voltage rail of a plurality of voltage rails selected based on the second clock frequency.

11. 10. The method of claim 1, wherein operating the circuit at the second clock frequency comprises changing a voltage of the circuit using a power management integrated circuit (PMIC) coupled to the circuit.

12. circuit; and control circuitry communicatively coupled to the circuit, the control circuitry comprising: determining a first workload value for the circuit operating at the first clock frequency; detecting a second workload value for the circuit that is less than the first workload value; In response to detecting the second workload value for the circuit: calculating a second clock frequency for the circuit that is greater than the first clock frequency; operating the circuit at the second clock frequency This means the system.

13. 13. The system of claim 12, wherein the first workload value and the second workload value are magnitudes of a number of instructions scheduled for execution by the circuitry.

14. The system of claim 13 , wherein the instructions are stored in a task storage communicatively coupled to the circuitry.

15. 13. The system of claim 12, wherein the control circuitry is to calculate the second clock frequency for the circuit by calculating the second clock frequency using a linear function based on the second workload value.

16. The linear function is: the minimum operational clock frequency of said circuit; a maximum operable clock frequency of said circuit; and The ratio of the reduced workload value to the maximum workload capacity of the circuit. The system of claim 15 further based on

17. The control circuitry comprises: comparing the second workload value against a reference workload value; operating the circuitry at a third clock frequency in response to the determination that the second workload value is less than the reference workload value; and operating the circuitry at a fourth clock frequency lower than the third clock frequency in response to the determining that the second workload value is greater than the reference workload value.

13. The system of claim 12, further determining the second clock frequency by:

18. The control circuitry further comprises: determining a range from a plurality of ranges of workload values ​​to which the second workload value corresponds, where each range of the plurality of ranges of workload values ​​corresponds to a respective clock frequency; and selecting the clock frequency corresponding to the determined range as the second clock frequency.

13. The system of claim 12, wherein the second clock frequency is determined by:

19. 13. The system of claim 12, wherein the control circuitry further couples the circuit to a voltage rail of a plurality of voltage rails selected based on the second clock frequency, thereby causing the circuit to operate at the second clock frequency.

20. 13. The system of claim 12, wherein the control circuitry further causes the circuit to operate at the second clock frequency by modifying a voltage of the circuit using a power management integrated circuit (PMIC) coupled to the circuit.

21. Solid-state drive (SSD) pipeline accelerator; a storage controller communicatively coupled to the SSD pipeline accelerator, the storage controller comprising: determining a first workload value for the circuit operating at the first clock frequency; Detecting a second workload value for the circuit that is less than the first workload value; and In response to detecting the second workload value for the circuit: calculating a second clock frequency for the circuit that is greater than the first clock frequency; operating the circuit at the second clock frequency This is an SSD storage system.

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