Semiconductor substrate, its manufacturing method and image sensor

Abstract

This application discloses a semiconductor substrate, a method for manufacturing the same, and an image sensor. The semiconductor substrate of this application includes a substrate having a first surface; a capture layer located on the side of the substrate away from the first surface and used to capture metal ions from the substrate or metal ions that have passed through the substrate; and a backside sealing layer located on the side of the capture layer away from the substrate. In this application, the capture layer is provided on one side of the base of the semiconductor substrate, thereby improving the external impurity adsorption ability of the semiconductor substrate. Using the semiconductor substrate of this application as the base of an image sensor reduces the dark current and the number of white pixels in the image sensor.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION This application relates to the field of semiconductor technology, and more particularly to substrates, image sensors and methods for manufacturing the same.

[0002] This application claims priority to a Chinese patent application bearing application number 202311114955.5, filed with the China Patent Office on August 30, 2023, and entitled "Semiconductor substrate, manufacturing method thereof, and image sensor," the entire contents of which are incorporated herein by reference. [Background technology]

[0003] Semiconductor substrates are the basic materials used in the manufacture of semiconductor devices. Silicon substrates are commonly used as semiconductor substrate materials due to their excellent electrical properties, thermal stability, and processability, and the quality of silicon substrates is crucial for the performance and manufacture of semiconductor devices. Summary of the Invention [Problem to be solved by the invention]

[0004] The semiconductor substrate has a relatively low ability to adsorb external impurities and is easily contaminated by metal ions, resulting in a relatively low product yield. When the semiconductor substrate is applied to devices, the device's dark current and the number of white pixels are relatively high, which affects the quality of the chip device. [Means for solving the problem]

[0005] An embodiment of the present application provides a semiconductor substrate, the semiconductor substrate comprising: a substrate having a first surface; a capture layer located on a side of the substrate away from the first surface; a backside encapsulation layer located on a side of the capture layer away from the substrate.

[0006] In some embodiments, the capture layer is used to capture metal ions, including metal ions in the substrate and metal ions that have passed through the first surface and entered the substrate.

[0007] In some embodiments, the capture layer has a thickness of between 1000 Å and 8000 Å.

[0008] In some embodiments, the resistivity of the substrate is between 0.010 ohm-cm and 0.020 ohm-cm.

[0009] In accordance with the above, an embodiment of the present application provides a manufacturing method for a semiconductor substrate, the manufacturing method for the semiconductor substrate comprising: providing a substrate having a first surface; forming a capture layer located on a side of the substrate away from the first surface; forming a backside encapsulation layer located on a side of the capture layer away from the substrate.

[0010] In some embodiments, the thickness of the capture layer in the thickness direction of the substrate is between 1000 Å and 8000 Å.

[0011] In some embodiments, forming the capture layer comprises: forming a second polysilicon layer overlying the first surface; forming a first polysilicon layer, the substrate having a second surface opposite the first surface, the second polysilicon layer being located on the second surface; removing the second polysilicon layer and leaving the first polysilicon layer, with the first polysilicon layer being the capture layer.

[0012] In some embodiments, the first polysilicon layer is fabricated by the following method: depositing a polysilicon layer on the surface of the substrate using a silicon-containing gas, and the amount of silicon-containing gas used is 2 L / 1000 Å to 4 L / 1000 Å.

[0013] In some embodiments, the second polysilicon layer is fabricated by the following method: depositing a polysilicon layer on the surface of the substrate using a silicon-containing gas, and the amount of silicon-containing gas used is 2 L / 1000 Å to 4 L / 1000 Å.

[0014] In some embodiments, the substrate is placed in an environment having a temperature range of 600°C to 660°C in the step of forming the first polysilicon layer.

[0015] In some embodiments, the substrate is placed in an environment with a temperature range of 600°C to 660°C in the step of forming the second polysilicon layer.

[0016] In some embodiments, the second polysilicon layer is removed by chemical mechanical polishing, the chemical mechanical polishing including grinding the second polysilicon layer to remove the second polysilicon layer.

[0017] In some embodiments, a first substrate is adsorbed to a polishing head, the polishing head having a cavity, and in a thickness direction of the semiconductor substrate, the cavity has a first thickness H1 μm, the first substrate has a second thickness H2 μm, and

[0018] An embodiment of the present application provides an image sensor, the image sensor including the semiconductor substrate described above, or the image sensor including a semiconductor substrate manufactured by the manufacturing method relating to the semiconductor substrate described above, the semiconductor substrate serving as a substrate of the image sensor.

[0019] In some embodiments, the semiconductor substrate comprises a P-type substrate. [Effects of the Invention]

[0020] ​The present application provides a semiconductor substrate, a manufacturing method thereof, and an image sensor, the semiconductor substrate of the present application including a substrate having a first surface, a capture layer located on a side of the substrate away from the first surface and used to capture metal ions from the substrate or metal ions that have passed through the substrate, and a backside sealing layer located on the side of the capture layer away from the substrate. The present application improves the external impurity adsorption ability of the semiconductor substrate by providing a capture layer on one side of the base of the semiconductor substrate. [Brief explanation of the drawings]

[0021] In the following, in order to more clearly explain the technical solutions in the embodiments of the present application, the accompanying drawings used in the description of the embodiments will be briefly described. However, the accompanying drawings in the following description are only a part of the embodiments of the present application, and it is obvious that a person skilled in the art can obtain other accompanying drawings based on these drawings without exerting creative efforts.

[0022] [Figure 1] 1 is a flow diagram of a manufacturing process for a semiconductor substrate according to an embodiment of the present application. [Figure 2] 1 is a flow diagram of a manufacturing process for a semiconductor substrate according to an embodiment of the present application. [Figure 3] 1 is a flow diagram of a manufacturing process for a semiconductor substrate according to an embodiment of the present application. [Figure 4] 1 is a schematic diagram showing the structure of a semiconductor substrate according to an embodiment of the present application. [Figure 5] 1 is a schematic diagram illustrating a structure of an image sensor according to an embodiment of the present invention; [Figure 6] 1 is a schematic diagram showing the structure of a grinding disk and a semiconductor substrate according to an embodiment of the present invention. [Figure 7] 1 shows geometric flatness test results for semiconductor substrates manufactured in examples of the present application, where Figure A shows the test results for maximum local flatness SFQR, Figure B shows the test results for maximum edge flatness ESFQR, Figure C shows the average results for maximum local flatness, Figure D shows the average results for maximum edge flatness, and Figure E shows the test results for maximum local flatness at 95% distribution. [Figure 8]FIG. 2 is a schematic diagram showing the structure of an image sensor manufactured in an embodiment of the present application. [Figure 9] 1 is a schematic diagram illustrating the structure of a front-illuminated image sensor according to an embodiment of the present application; [Figure 10] 10 shows test results of the semiconductor substrate of the embodiment of the present application applied to dark current in an image sensor. [Figure 11] 10 shows test results in which the semiconductor substrate of the embodiment of the present application is applied to a white pixel in an image sensor. DETAILED DESCRIPTION OF THE INVENTION

[0023] The following provides a clear and complete description of the technical solutions in the embodiments of the present application in conjunction with the examples of the present application. However, it is clear that the described examples are only some of the examples of the present application and do not represent all of the examples. Based on the examples of the present application, all other examples that a person skilled in the art can derive without inventive effort fall within the scope of protection of the present application. Furthermore, in the description of the present application, the term "including" means "including but not limited to." Terms such as "first," "second," and "third" are merely used as markings and do not impose numerical requirements or ordering. Each embodiment of the present application may exist in the form of a range. It should be understood that the description in the form of a range is for convenience and conciseness only and should not be construed as a rigid limitation on the scope of the present application. Therefore, the description of a range is considered to specifically disclose all possible subranges and single numerical values ​​within that range. For example, a description of a range of 1 to 6 specifically discloses subranges, e.g., 1 to 3, 1 to 4, 1 to 5, 2 to 4, 2 to 6, 3 to 6, etc., and single numbers within the numerical range, e.g., 1, 2, 3, 4, 5, and 6, which apply regardless of the range. Furthermore, whenever a numerical range is given herein, it is meant to include any recited number (fractional or integer) within the stated range. In this application, the X direction is the thickness direction, and the Y direction is the extension direction of the semiconductor substrate.

[0024] As shown in Figure 4, an embodiment of the present application provides a semiconductor substrate, which includes a substrate 100 having a first surface 101, a capture layer 200 located on the side of the substrate 100 away from the first surface 101 and used to capture metal ions from the substrate 100 or metal ions that have passed through the substrate 100, and a backside encapsulation layer 300 located on the side of the capture layer 200 away from the substrate 100. By providing the capture layer 200 on one side of the base of the semiconductor substrate 100, the present application improves the external impurity adsorption ability of the semiconductor substrate, effectively reduces contamination by metal ions, and increases product yield.

[0025] In some embodiments, the thickness of the capture layer 200 is between 1000 Å and 8000 Å. For example, the thickness (Å) of the capture layer 200 may be any of 1000, 2000, 3000, 4000, 5000, 6000, 7000, and 8000, or any range consisting of any two of these values. For example, the thickness of the capture layer 200 may be between 1000 Å and 5000 Å or between 1000 Å and 3000 Å. In the present application, the provision of the capture layer 200 deteriorates the geometric flatness of the substrate. Therefore, by setting the thickness of the capture layer 200 within the range of 1000 Å to 8000 Å, the external impurity adsorption capacity of the semiconductor substrate of the present application can be satisfied and the degree of deterioration of the device flatness due to the provision of the capture layer 200 can be improved.

[0026] In some embodiments, the substrate 100 is a silicon substrate, and the resistivity of the substrate 100 is between 0.010 ohm-cm and 0.020 ohm-cm. For example, the resistivity (ohm-cm) of the substrate 100 may be any one of the following values, or a range consisting of any two of the following values: 0.01, 0.011, 0.012, 0.013, 0.014, 0.015, 0.016, 0.017, 0.018, 0.019, and 0.020.

[0027] In some embodiments, the resistivity of the substrate 100 is changed by the following methods: For example, ion doping is performed on the silicon substrate, and the doping method may be ion implantation; or different concentrations of doping elements are added to the silicon material during the manufacturing process of the silicon substrate to change the resistivity of the substrate 100.

[0028] In some embodiments, the trapping layer 200 includes polysilicon, which is used as an impurity adsorbent material to trap metal ions from the outer layer, and when the semiconductor substrate of the present application is applied to a device, it can trap metal ions in the device layer and reduce the dark current and the number of white pixels of the device.

[0029] In some embodiments, backside encapsulation layer 300 is a silicon oxide layer, and the thickness of backside encapsulation layer 300 is 3000 Å to 4000 Å. For example, the thickness (Å) of backside encapsulation layer 300 is any value of 3000, 3100, 3200, 3300, 3400, 3500, 3600, 3700, 3800, 3900, 4000, or a range consisting of any two of these values.

[0030] In some embodiments, the backside encapsulation layer 300 comprises low temperature silicon oxide (LTO).

[0031] In some embodiments, the deposition temperature of the low temperature silicon oxide is 400°C to 800°C, for example, the deposition temperature (°C) is any value or range consisting of any two of the following values: 400, 450, 500, 550, 600, 650, 700, 750, 800. In some embodiments, the fabrication temperature of the backside encapsulation layer 300 is 600 to 650°C.

[0032] In some embodiments, backside encapsulation layer 300 is fabricated by the following method: Chemical vapor deposition is performed on substrate 100 having capture layer 200 to fabricate backside encapsulation layer 300. In some embodiments, the oxygen introduction flow rate (Standard Cubic Centimeters per Minute, sccm) ranges from 495 to 616. In some embodiments, the SiH introduction flow rate (Standard Cubic Centimeters per Minute, sccm) ranges from 45 to 56.

[0033] In some embodiments, the present application provides a manufacturing method for a semiconductor substrate, the manufacturing method for the semiconductor substrate including:

[0034] As shown in FIG. 1, a substrate 100 is provided, the substrate 100 having a first surface 101 .

[0035] A capture layer 200 is formed, and the capture layer 200 is located on the side away from the first surface 101 of the substrate 100. A back surface sealing layer 300 is formed, and the back surface sealing layer 300 is located on the side of the capture layer 200 away from the substrate 100.

[0036] In some embodiments, the thickness of capture layer 200 in the thickness direction X of the substrate is between 1000 Å and 8000 Å.

[0037] As shown in FIG. 2, the steps of forming the trapping layer 200 include:

[0038] A second polysilicon layer 220 is formed, and the second polysilicon layer 220 is located on the first surface 101 .

[0039] A first polysilicon layer 210 is formed, the substrate 100 has a second surface 102 opposite the first surface 101, and a second polysilicon layer 220 is located on the second surface 102.

[0040] 3, the second polysilicon layer 220 is removed, leaving the first polysilicon layer 210. The first polysilicon layer 210 is used as the capture layer 200.

[0041] In some embodiments, the first polysilicon layer 210 is fabricated by the following method: depositing the first polysilicon layer 210 on the surface of the substrate 100 using a silicon-containing gas. The amount of silicon-containing gas used is 2 L / 1000 Å to 4 L / 1000 Å. For example, the amount of silicon-containing gas used (L / 1000 Å) may be any of 2.0, 2.5, 3.0, 3.5, and 4.0, or any range consisting of any two of these values. By controlling the amount of silicon-containing gas used, the present application can control the thickness of the first polysilicon layer 210 and further control the deposition rate of the first polysilicon layer 210 on the surface of the substrate 100, thereby reducing the impact of the fabrication of the polysilicon layer on the flatness of the semiconductor workpiece 1.

[0042] In some embodiments, the second polysilicon layer 220 is fabricated by the following method: depositing the second polysilicon layer 220 on the surface of the substrate 100 using a silicon-containing gas. The amount of silicon-containing gas used is 2 L / 1000 Å to 4 L / 1000 Å. For example, the amount of silicon-containing gas used (L / 1000 Å) may be any of 2.0, 2.5, 3.0, 3.5, and 4.0, or any range consisting of any two of these values. By controlling the amount of silicon-containing gas used, the present application can control the thickness of the second polysilicon layer 220 and further control the deposition rate of the second polysilicon layer 220 on the surface of the substrate 100, thereby improving the quality of the semiconductor substrate produced.

[0043] In some embodiments, the step of forming the first polysilicon layer 210 places the substrate 100 in an environment with a temperature range of 600°C to 660°C.

[0044] In some embodiments, the step of forming the second polysilicon layer 220 places the substrate 100 in an environment with a temperature range of 600°C to 660°C.

[0045] In some embodiments, the temperature (° C.) at which first polysilicon layer 210 is formed is any one of the following values, or a range consisting of any two of the following values: 600, 610, 620, 630, 6405, 650, 660.

[0046] In some embodiments, the temperature (° C.) at which second polysilicon layer 220 is formed is any one of the following values, or a range consisting of any two of the following values: 600, 610, 620, 630, 6405, 650, 660.

[0047] In some embodiments, polysilicon layers are simultaneously formed on both sides of the substrate 100, i.e., the first polysilicon layer 210 and the second polysilicon layer 220 are simultaneously formed on both sides of the substrate 100 to obtain the first base material 110. The temperature range for forming the first polysilicon layer 210 and the second polysilicon layer 220 is 600°C to 620°C, or 640°C to 660°C.

[0048] If the thickness of the polysilicon layer to be manufactured is 4000 Å or less, it may be manufactured by the following method.

[0049] In some embodiments, the first polysilicon layer 210 and the second polysilicon layer 220 are fabricated by the following method: fabricating the polysilicon layer at a first temperature range of 600°C to 620°C and a first flow rate of the silicon-containing gas of 3 L / 1000 Å to 4 L / 1000 Å;

[0050] In some embodiments, a polysilicon layer is produced when the second temperature range is between 640° C. and 660° C. and the second flow rate of the silicon-containing gas is between 2 L / 1000 Å and 3 L / 1000 Å.

[0051] If the thickness of the polysilicon layer to be manufactured is greater than 4000 Å, it may be manufactured by the following method.

[0052] In some embodiments, the first polysilicon layer 210 and the second polysilicon layer 220 are fabricated by the following method: fabricating the polysilicon layer at a first temperature range of 600°C to 620°C and a third flow rate of the silicon-containing gas of 2.8 L / 1000 Å to 3.4 L / 1000 Å.

[0053] In some embodiments, a polysilicon layer is produced when the second temperature range is between 640° C. and 660° C. and the fourth flow rate of the silicon-containing gas is between 2.25 L / 1000 Å and 2.75 L / 1000 Å.

[0054] In some embodiments, the silicon-containing gas comprises SiH4.

[0055] In some embodiments, the second polysilicon layer 220 is removed by chemical mechanical polishing.

[0056] As shown in Figure 6, the chemical mechanical polishing apparatus includes a grinding disk 2 and a polishing head 3, and the polishing head 3 has a cavity 300. When performing chemical mechanical polishing, the surface of the semiconductor substrate is adsorbed by a pressurized air bag in the intermediate gas pipe, i.e., the first substrate 110 is attached to the upper polishing head 3 by vacuum adsorption, a delivery pipe delivers a polishing fluid containing an etchant and abrasive particles, and the polishing head 3 rotates at high speed to remove the second polysilicon layer 220.

[0057] In some embodiments, in the thickness direction (X direction) of the semiconductor body 1, the cavity 300 has a first thickness H1 μm, the substrate has a second thickness H2 μm, and

[0058] ​In some embodiments, the difference between H1 and H2 is S μm, the distance from the bottom surface 301 of the polishing head 3 to the top surface of the first substrate 110. In the present application, the bottom surface and the top surface are descriptions with respect to directions and do not limit the specific structure of the present application.

[0059] In some embodiments, the distance S from the bottom surface 301 of the polishing head 3 to the top surface of the first substrate 110 satisfies 0 < S ≤ 20 μm. For example, the value of S is any one of 5, 10, 15, 20, or a range consisting of any two of them.

[0060] In some embodiments, the value of the first thickness H1 of the cavity 300 is from 780 μm to 790 μm. For example, the value of the first thickness H1 is any one of 780, 785, 790, or a range consisting of any two of them.

[0061] In some embodiments, the value of the second thickness H2 of the first substrate 110 is from 765 μm to 785 μm. For example, the value of the second thickness H2 is any one of 765, 770, 775, 780, 785, or a range consisting of any two of them.

[0062] When H1 - H2 in the present application is greater than 20 μm, for example, when the selected height of the cavity 300 is 800 μm, the thickness of the first substrate 110 is 775 μm, and the thickness of the manufactured polysilicon layer is within the range of 1000 Å to 8000 Å, when a geometric flatness test is performed on the obtained substrate, the geometric flatness of the substrate deteriorates. On the other hand, it has been found that reducing the distance between the lower surface of the cavity 300 and the first substrate 110 can reduce the influence on the deterioration of the geometric flatness of the substrate caused by the polysilicon layer manufactured in the present application. <​​​​​​In some embodiments, the flatness testing device used herein is an optical microscope, a scanning electron microscope (SEM), or an atomic force microscope (AFM).

[0065] As shown in Figures 5 and 7, an embodiment of the present application provides an image sensor (CIS, CMOS Image Sensor), which includes the above-mentioned semiconductor substrate 1, which is the base of the image sensor, and in which an element layer 400 is provided on the outer layer of the semiconductor substrate 1.

[0066] As shown in FIG. 7, in some embodiments, the semiconductor substrate of the present application is a P-type substrate, and the image sensor includes an NMOS transistor structure and a PMOS transistor structure. The image sensor shown in FIG. 7 of the present application is intended only as an enumerated structure. The semiconductor substrate 1 of the present application may also be an N-type substrate. The image sensor may be a front-illuminated image sensor or a back-illuminated image sensor.

[0067] 8 is a schematic diagram illustrating the structure of a front-illuminated image sensor provided herein, in some embodiments. The image sensor includes a sensor body, a color filter 500, and a lens 600. The sensor body includes a substrate and a CMOS device structure, i.e., device layer 400, disposed on the substrate.

[0068] In some embodiments, color filters 500 are used to capture different colored light. Types of color filters such as Bayer filters, X-Trans filters, etc. may be selected.

[0069] In some embodiments, a lens 600 is used to collect light and direct it to the sensor. Lens types such as plano-convex and bi-convex lenses may be selected.

[0070] In some embodiments, when the semiconductor substrate fabricated according to the above embodiments of the present application is applied to an image sensor, leakage due to excess metal ions in the device can be improved to affect the dark current and the number of white pixels generated under different operating temperature conditions.

[0071] In some embodiments, the range of the number of pixels of the average dark current of the image sensor to which the semiconductor substrate 1 of the present application is applied is 16.3 to 16.6.

[0072] In some embodiments, the number of white pixels in the image sensor to which the semiconductor substrate 1 of the present application is applied is in the range of 200-250.

[0073] Example 1 is as follows.

[0074] The semiconductor substrate is a polished P-type single crystal silicon wafer having a diameter of 300 mm as the substrate 100, a resistivity of 0.010 to 0.020 ohm-cm, and an outer layer thickness H2 of 775 μm.

[0075] An LPCVD furnace is selected to process the substrate 100, the purity of the silicon-containing gas SiH4 is 99.9999% or more, and the purity of N2 is 99.9999999% or more, and the LPCVD furnace is used to deposit polysilicon. The same single-crystal silicon raw material is selected and processed to produce the polysilicon layer, and the manufacturing process is shown in Table 1.

[0076] The second polysilicon layer 220 is removed, specifically, in the thickness direction X of the substrate, the polishing head 3 has a grinding cavity 300, and the cavity 300 has a first thickness H1 of 780 μm.

[0077] To manufacture the backside encapsulation layer 300, specifically, an APCVD furnace is selected to process the substrate 100, and the purity of the silicon-containing gas SiH4 is set to 99.9999% or more, the purity of O2 is set to 99.9999999% or more, and the purity of N2 is set to 99.9999999% or more. A low-temperature oxide layer is deposited using the APCVD furnace at a deposition temperature range of 640-650°C. The same single-crystal silicon raw material is selected and processed to manufacture the oxide layer, and the backside encapsulation film has a thickness of 3000 Å. This results in the semiconductor substrate shown in FIG. 4.

[0078] Examples 2 to 12 are as follows.

[0079] The manufacturing method is the same as in Example 1, except for adjusting the manufacturing parameters of the polysilicon layer, as shown in Table 1.

[0080] Comparative Example 1 is as follows.

[0081] The capture layer 200 is not fabricated.

[0082] Manufacturing process parameters for semiconductor substrates [Table 1]

[0083] The geometric flatness of Example 5 (5k), Example 7 (4k), Example 8 (3k), Example 10 (2k), Example 11 (1k), and Comparative Example 1 (BSL) was tested, and the test results are shown in Table 2 and FIG. 7.

[0084] Geometric Flatness Test Results for Semiconductor Substrates [Table 2]

[0085] As can be seen from the results in Table 2 and Figure 2, when the thickness of the trapping layer 200 manufactured in the present application was within the range of 1000 Å to 3000 Å, the deterioration of the geometric flatness of the semiconductor substrate 1 was improved compared to Comparative Example 1, in which the trapping layer 200 was not deposited. Furthermore, in the present application, after improving the CMP method, when the thickness of the trapping layer 200 manufactured in the present application was within the range of 3000 Å to 8000 Å, the deterioration of the geometric flatness was suppressed. The thickness of the trapping layer 200 manufactured in the present application was within the range of 5000 Å to 8000 Å, and the maximum local flatness (nm) was within the range of 130 nm to 250 nm. The thickness of the trapping layer 200 manufactured in the present application was within the range of 4000 Å to 8000 Å, and the maximum edge flatness (μm) was within the range of 130 nm to 250 nm.

[0086] 2 shows the average maximum local flatness (SFQR Mean / nm) and the average maximum edge flatness (ESFQR Mean / nm) of the capture layer 200 of the present invention. The results showing a consistent trend of the maximum local flatness and the maximum edge flatness indicate that the manufacturing of the capture layer 200 of the present invention has improved the deterioration of the flatness of the semiconductor substrate 1.

[0087] Examples of applications are as follows:

[0088] The semiconductor substrates 1 manufactured in Example 2 (Poly+LTO 8k+3k), Example 5 (Poly+LTO 5k+3k), Example 8 (Poly+LTO 3k+3k) and Comparative Example 1 (POR) are applied to image sensors (CMOS).

[0089] The image sensor is manufactured by the following method.

[0090] A circuit structure including an NMOS and a PMOS shown in FIG. 8 is formed on the semiconductor substrate 1 using an ion implantation method.

[0091] Specifically, the gate electrode is manufactured by forming a gate electrode on the semiconductor substrate 1 using polysilicon to control the transmission of current.

[0092] The formation of the oxide layer specifically involves forming silicon dioxide on the semiconductor substrate 1 as an oxide layer for isolating and protecting circuits.

[0093] The metal deposition specifically involves depositing metallic copper on the oxide layer to form electrodes and connecting lines.

[0094] Specifically, the exposure and etching process defines the circuit shapes and structures in the oxide layer through an exposure process, and then removes excess material through etching to form the desired circuit structures.

[0095] Specifically, the formation of the dielectric layer involves forming a dielectric layer between the metal electrodes and the connecting lines to separate and protect the circuits.

[0096] The metal filling specifically fills the dielectric layer with metal to form the tops of the electrodes and connecting lines.

[0097] Specifically, after the manufacturing of the image sensor is completed, packaging and testing are carried out. The sensor body is packaged in a packaging material, and electrical characteristics tests and image quality tests are carried out.

[0098] Specifically, the test method tests dark current using a dark current imaging sensor.

[0099] If the test object is a white pixel, a dark field test method is used.

[0100] Test results of the semiconductor substrate manufactured in this application applied to a front-illuminated image sensor [Table 3]

[0101] As can be seen from Figure 10 (where D-Mean in Figure 10 represents test data related to dark current), Figure 11 (where Peak02 in Figure 11 represents test data related to white pixels), and the data in Table 3, the test results for devices fabricated using semiconductor substrate 1 manufactured according to the present invention show that image sensors with a backside polysilicon layer (green, blue, and orange lines) show significant improvements compared to semiconductor substrates without a backside polysilicon layer (red line), with both dark current and white pixels being significantly lower and tighter. This demonstrates that the use of semiconductor substrates with a backside polysilicon layer manufactured according to the present invention can effectively suppress leakage caused by metal ion contamination during processing. Therefore, according to the present invention, dark current and white pixels can be effectively improved in CIS products, thereby improving the quality of CIS chip devices.

[0102] In the above-described embodiments, the description of each embodiment has its own focus, and for parts of an embodiment that are not described in detail, reference can be made to the descriptions of other embodiments.

[0103] Although the semiconductor substrate, its manufacturing method, and image sensor provided in the examples of the present application have been described in detail above, the present application describes the principles and embodiments using specific examples, and the description of the above examples is intended to facilitate understanding of the technical solutions and core ideas of the present application. Furthermore, those skilled in the art may modify the specific embodiments and application scope according to the technical ideas of the present application, and therefore the contents of the present application should not be construed as limiting the present application. [Explanation of symbols]

[0104] 1: Semiconductor substrate 100: Substrate 101: 1st surface 102:Second surface 110: 1st base material 200: Capture layer 210: First polysilicon layer 220: Second polysilicon layer 300: Back sealing layer 2: Grinding disc 3: Polishing head 300: Cavity 301: Bottom

Claims

1. a substrate (100) having a first surface (101); a capture layer (200) located on a side of the substrate (100) away from the first surface (101); a backside sealing layer (300) located on the side of the capture layer (200) away from the substrate (100); Semiconductor substrate.

2. In the thickness direction (X) of the substrate (100), the thickness of the capture layer (200) is 1000 Å to 8000 Å; The semiconductor substrate of claim 1 .

3. The resistivity of the substrate (100) is 0.010 ohm-cm to 0.020 ohm-cm; The semiconductor substrate of claim 1 .

4. Providing a substrate (100) having a first surface (101); forming a capture layer (200) located on a side of the substrate (100) away from the first surface (101); forming a backside encapsulation layer (300) located on a side of the capture layer (200) away from the substrate (100); Manufacturing methods relating to semiconductor substrates.

5. In the thickness direction (X) of the substrate (100), the thickness of the capture layer (200) is 1000 Å to 8000 Å; A manufacturing method for the semiconductor substrate of claim 4.

6. The step of forming the capture layer (200) comprises: forming a second polysilicon layer (220) located on the first surface (101); forming a first polysilicon layer (210), the substrate (100) having a second surface (102) opposite the first surface (101), the second polysilicon layer (220) being located on the second surface (102), to obtain a first substrate (110); removing the second polysilicon layer (220), leaving the first polysilicon layer (210), and using the first polysilicon layer (210) as the capture layer (200); A manufacturing method for the semiconductor substrate of claim 4.

7. The first polysilicon layer (210) is fabricated by depositing polysilicon on the surface of the substrate (100) using a silicon-containing gas. A manufacturing method for the semiconductor substrate of claim 6.

8. The amount of the silicon-containing gas used is 2 L / 1000 Å to 4 L / 1000 Å. A manufacturing method for the semiconductor substrate of claim 7.

9. The second polysilicon layer (220) is fabricated by depositing polysilicon on the surface of the substrate (100) using a silicon-containing gas. A manufacturing method for the semiconductor substrate of claim 6.

10. The amount of the silicon-containing gas used is 2 L / 1000 Å to 4 L / 1000 Å.

10. A manufacturing method for the semiconductor substrate of claim 9.

11. In the step of forming the first polysilicon layer (210), the substrate (100) is placed in an environment having a temperature range of 600°C to 660°C; A manufacturing method for the semiconductor substrate of claim 6.

12. In the step of forming the second polysilicon layer (220), the substrate (100) is placed in an environment having a temperature range of 600°C to 660°C; A manufacturing method for the semiconductor substrate of claim 6.

13. removing the second polysilicon layer (220) by chemical mechanical polishing; A manufacturing method for the semiconductor substrate of claim 6.

14. The chemical mechanical polishing method includes grinding the second polysilicon layer (220) to remove the second polysilicon layer (220).

14. A manufacturing method for the semiconductor substrate of claim 13.

15. The first substrate (110) is attached to a polishing head (3), and the polishing head (3) has a cavity (300). In the thickness direction (X) of the semiconductor substrate (1), the cavity (300) has a first thickness H １ μm, and the first substrate (110) has a second thickness H ２ μm, and 0<H １ -H ２ Satisfies ≦20 μm, 15. A manufacturing method for the semiconductor substrate of claim 14.

16. An image sensor comprising a semiconductor substrate (1) according to any one of claims 1 to 3 or a semiconductor substrate (1) manufactured by a manufacturing method relating to a semiconductor substrate (1) according to any one of claims 4 to 15, The semiconductor substrate (1) serves as the substrate of the image sensor; Image sensor.

17. The semiconductor substrate (1) comprises a P-type substrate; 17. The image sensor of claim 16.

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