Uniform epitaxial growth on crystalline templates

Abstract

The processing system includes one or more processing chambers and a system controller configured to cause the processing system to perform: (a) a pre-cleaning process on an exposed surface of a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region; (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surface of the semiconductor structure; (c) a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer in the trench; (d) an etching process to remove remaining portions of the amorphous silicon-containing layer; and (e) a second deposition process to epitaxially form source / drain regions on the silicon-containing crystalline layer in the trench.

Description

[Technical Field]

[0001] FIELD OF THE INVENTION

[0001] Embodiments described herein relate generally to semiconductor device manufacturing, and more particularly to systems and methods for uniform epitaxial growth in semiconductor structures. [Background technology]

[0002] Multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), such as double-gate field-effect transistors (FinFETs), silicon-on-insulator (SOI) tri-gate MOSFETs, and gate-all-around (GAA) FETs, incorporate two or more gates into a single device, making them more scalable than conventional planar bulk MOSFETs. However, their three-dimensional (3D) design and small size pose manufacturability challenges. In architectures targeted at technology nodes below 10-15 nm, such as GAA FETs, which place gates on two or all four sides of a silicon-based channel, parasitic or external resistance significantly impacts device performance. In these devices, source / drain regions can be formed within trenches by an epitaxy process. However, because the inner surfaces of the trenches contain different materials (e.g., silicon (Si) and silicon nitride (Si3N4)), significant variations in critical dimensions (e.g., linewidth) have been observed during the epitaxy process. This non-uniformity leads to variations in growth rate on the inner surface of the trench during the epitaxy process, resulting in the formation of defects such as twins, stacking faults, or voids in the source / drain regions. The presence of defects in the source / drain regions can dramatically increase the contact resistance.

[0003] Therefore, what is needed is a method and system that can form uniform epitaxial source / drain regions. Summary of the Invention

[0004] An embodiment of the present disclosure provides a processing system including one or more processing chambers and a system controller configured to cause the processing system to perform, in the one or more processing chambers, (a) a pre-cleaning process on an exposed surface of a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region, (b) a first deposition process to form an amorphous silicon-containing layer on the exposed surface of the semiconductor structure, (c) a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer in the trench, (d) an etching process to remove remaining portions of the amorphous silicon-containing layer, and (e) a second deposition process to epitaxially form source / drain regions on the silicon-containing crystalline layer in the trench.

[0005]

[0005] An embodiment of the present disclosure provides a method for filling a trench in a semiconductor structure, the method including: performing a first deposition process to form an amorphous silicon-containing layer on an exposed surface of the semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region; performing a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer in the trench; performing an etching process to remove remaining portions of the amorphous silicon-containing layer; and performing a second deposition process to epitaxially form source / drain regions on the silicon-containing crystalline layer in the trench.

[0006]

[0006] An embodiment of the present disclosure provides a method for filling a trench in a semiconductor structure, the method including: performing a pre-cleaning process on an exposed surface of the semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region; performing a first deposition process to form an amorphous silicon-containing layer on the exposed surface of the semiconductor structure; performing a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer in the trench; performing an etching process to remove remaining portions of the amorphous silicon-containing layer; and performing a second deposition process to epitaxially form source / drain regions on the silicon-containing crystalline layer in the trench.

[0007]

[0007] In order that the above-described features of the present disclosure may be understood in detail, the above-summarized disclosure will be more particularly described by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings depict only typical embodiments of the present disclosure and therefore should not be considered as limiting the scope of the present disclosure, which may also admit of other equally effective embodiments. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure. [Figure 2A] 1 is a cross-sectional view of a processing chamber according to one or more embodiments. [Figure 2B] 2B is an enlarged view of a portion of the processing chamber of FIG. 2A. [Figure 3] 1 is a cross-sectional view of a processing chamber according to one or more embodiments. [Figure 4] 1 is a cross-sectional view of a processing system according to one or more embodiments. [Figure 5]FIG. 2 is a process flow diagram illustrating a method for forming a contact layer in a semiconductor structure according to a first embodiment of the present disclosure. [Figure 6A] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6B] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6C] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6D] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. [Figure 6E] 6A-6C are cross-sectional views of a portion of a semiconductor structure corresponding to various states of the method of FIG. 5. DETAILED DESCRIPTION OF THE INVENTION

[0009]

[0015] To facilitate understanding, wherever possible, the same reference numerals have been used to designate identical elements common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.

[0010]

[0016] Embodiments described herein provide methods and systems for epitaxial growth to fill trenches in semiconductor structures. The methods and systems may be particularly useful for forming source / drain regions in trenches in gate-all-around (GAA) FETs. Unlike conventional processes that require epitaxial growth of source / drain regions on the roughened surface of the trench, embodiments described herein involve epitaxially growing the source / drain regions on a crystalline template formed on the surface of the trench. Therefore, the formed source / drain regions are uniform and of high quality, free of defects or voids.

[0011]

[0017] 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, substrates within the processing system 100 can be processed in and transferred between various chambers without exposing the substrates to an ambient environment outside the processing system 100 (e.g., an ambient atmospheric environment such as may exist in a semiconductor manufacturing facility). For example, substrates can be processed in and transferred between various chambers maintained in a low-pressure (e.g., about 300 Torr or less) or vacuum environment without breaking the low-pressure or vacuum environment between various processes performed on the substrates in the processing system 100. Thus, the processing system 100 can provide an integrated solution for processing a portion of a substrate.

[0012]

[0018] Examples of processing systems that may be suitably modified in accordance with the teachings provided herein include the Endura®, Producer®, or Centura® integrated processing systems, or other suitable processing systems commercially available from Applied Materials, Inc., Santa Clara, Calif. It is contemplated that other processing systems (including those from other manufacturers) may be adapted to benefit from aspects described herein.

[0013]

[0019] 1 , the factory interface 102 includes a docking station 132 and a factory interface robot 134 to facilitate the transfer of substrates. The docking station 132 is adapted to receive one or more front-opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed at one end of the respective factory interface robot 134 adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0014]

[0020] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 148, 150 coupled to the holding chambers 116, 118 and respective ports 152, 154 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. Ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 may be, for example, slit valve openings with slit valves for passing substrates therethrough by transfer robots 112, 114 and for providing a seal between the respective chambers to prevent gas from passing between the respective chambers. Generally, any port is opened to allow a substrate to pass therethrough; otherwise, the port is closed.

[0015]

[0021] The load lock chambers 104, 106, transfer chambers 108, 110, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130 may be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system may include one or more gas pumps (e.g., turbo pumps, cryopumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. During operation, the factory interface robot 134 transfers a substrate from a FOUP 136 to the load lock chamber 104 or 106 through port 140 or 142. The gas and pressure control system then pumps down the load lock chamber 104 or 106. The gas and pressure control system further maintains an internal low-pressure or vacuum environment (which may include an inert gas) within the transfer chambers 108, 110 and holding chambers 116, 118. Thus, pumping down the load lock chambers 104 or 106 facilitates passing substrates between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108 .

[0016]

[0022] The transfer robot 112 transfers a substrate in a pumped-down load lock chamber 104 or 106 from the load lock chamber 104 or 106 into the transfer chamber 108 through a port 144 or 146. The transfer robot 112 can then transfer the substrate to and / or between any of the processing chambers 120, 122 through respective ports 152, 154 for processing, and can transfer the substrate to any of the holding chambers 116, 118 through respective ports 148, 150 for holding awaiting further transfer. Similarly, the transfer robot 114 can access substrates in the holding chambers 116 or 118 through ports 156 or 158, can transfer substrates to and / or between any of the processing chambers 124, 126, 128, 130 for processing through respective ports 160, 162, 164, 166, and can transfer substrates to either of the holding chambers 116, 118 for holding awaiting further transfer through respective ports 156, 158. Transfer and holding of substrates in and between the various chambers can occur under low pressure or vacuum environments provided by gas and pressure control systems.

[0017]

[0023] Processing chambers 120, 122, 124, 126, 128, and 130 may be any suitable chambers for processing substrates. In some examples, processing chamber 120 may be capable of performing an etch process, processing chamber 122 may be capable of performing a cleaning process, processing chamber 124 may be capable of performing a selective removal process, and processing chambers 126, 128, and 130 may be capable of performing respective epitaxial growth processes. Processing chamber 120 may be a Selectra™ etch chamber available from Applied Materials, Inc. of Santa Clara, California. Processing chamber 122 may be a SiCoNi™ pre-clean chamber available from Applied Materials, Inc. of Santa Clara, California. Processing chambers 126, 128, or 130 may be Centura™ Epi chambers available from Applied Materials, Inc. of Santa Clara, California.

[0018]

[0024] A system controller 168 is coupled to the processing system 100 to control the processing system 100 or its components. For example, the system controller 168 can control operations in the processing system 100 by using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, and 130. During operation, the system controller 168 enables data collection and feedback from each chamber to adjust the performance of the processing system 100.

[0019]

[0025] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuits 174. The CPU 170 may be any type of general-purpose processor available in an industrial environment. The memory 172, or non-transitory computer-readable medium, is accessible by the CPU 170 and may be one or more of memory, such as random access memory (RAM), read-only memory (ROM), a floppy disk, a hard disk, or any other form of local or remote digital storage. The support circuits 174 are coupled to the CPU 170 and may include cache, clock circuits, an input / output subsystem, power supplies, etc. The various methods disclosed herein may generally be performed under the control of the CPU 170 by the CPU 170 executing computer instruction code stored, for example, as software routines, in the memory 172 (or in the memory of a particular processing chamber). When the computer instruction code is executed by the CPU 170, the CPU 170 controls the chamber to perform processes according to various methods.

[0020]

[0026] Other processing systems may have other configurations. For example, more or fewer processing chambers may be coupled to the transfer apparatus. In the illustrated example, the transfer apparatus includes transfer chambers 108, 110 and holding chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer holding chambers (e.g., no holding chambers) may be implemented as the transfer apparatus in a processing system.

[0021]

[0027] Figure 2A is a cross-sectional view of one or more embodiments of a processing chamber 200 adapted to perform a pre-cleaning process, as described in more detail below. Processing chamber 200 may be processing chamber 122 shown in Figure 1. Figure 2B is an enlarged view of a portion of processing chamber 200 of Figure 2A.

[0022]

[0028] The processing chamber 200 may be particularly useful for performing thermal or plasma-based cleaning processes and / or plasma dry etching processes. The processing chamber 200 includes a chamber body 202, a lid assembly 204, and a support assembly 206. The lid assembly 204 is disposed on top of the chamber body 202, and the support assembly 206 is disposed at least partially within the chamber body 202. A vacuum system can be used to remove gases from the processing chamber 200. The vacuum system includes a vacuum pump 208 coupled to a vacuum port 210 disposed in the chamber body 202. The processing chamber 200 also includes a controller 212 for controlling processes within the processing chamber 200.

[0023]

[0029] The lid assembly 204 includes stacked components adapted to supply precursor gases and / or plasma to the processing region 214 within the processing chamber 200. The first plate 216 is coupled to the second plate 218. The third plate 220 is coupled to the second plate 218. The lid assembly 204 may be connected to a power supply (not shown) for supplying plasma to a conical chamber 222 formed in the lid assembly 204. The lid assembly 204 may also be connected to a remote plasma source 224 that generates plasma upstream of the lid stack. The remote plasma cavity (e.g., the processing region 214, the first plate 216, and the second plate 218 of FIGS. 2A-2B) is coupled to a gas source 226 via the remote plasma source 224 (or, in the absence of a remote plasma source 224, the gas source 226 is directly coupled to the lid assembly 204). The gas source 226 may include a gas source adapted to supply helium, argon, or other inert gas. In some configurations, a gas supplied by the gas source 226 can be energized to generate a plasma and supplied to the lid assembly 204 using a remote plasma source. In an alternative embodiment, the gas source 226 can supply a process gas that can be activated by the remote plasma source 224 before being introduced to the surface of a substrate disposed within the processing chamber 200. Referring to FIG. 2B, the conical chamber 222 has an opening 228 that allows the formed plasma to flow from the remote plasma source 224 to a region 230 formed in a fourth plate 232 of the lid assembly 204.

[0024]

[0030] In some configurations of the lid assembly 204, a plasma is generated within the conical chamber 222 by application of energy delivered from a plasma source. In one example, the energy may be provided by biasing the lid assembly 204 to capacitively couple RF, VHF, and / or UHF energy to the gas disposed within the conical chamber 222. In this configuration of the lid assembly 204, a remote plasma source 224 may not be used or may not be located within the lid assembly 204.

[0025]

[0031] A central conduit 234 formed in the fourth plate 232 is adapted to deliver plasma-generated species from the region 230 through the fifth plate 236 to a mixing chamber 238 formed in a sixth plate 240 of the lid assembly 204. The central conduit 234 is connected to the mixing chamber 238 through an opening 242 in the fifth plate 236. The opening 242 may have a smaller, larger, or the same diameter as the central conduit 234. In the embodiment of FIG. 2B, the opening 242 has the same diameter as the central conduit 234.

[0026]

[0032] The fourth plate 232 also includes inlets 244 and 246 adapted to supply gas to the mixing chamber 238. The inlet 244 is coupled to a first gas source 248, and the inlet 246 is coupled to a second gas source 250. The first gas source 248 and the second gas source 250 may contain an inert gas, such as argon and / or helium, utilized as a carrier gas as well as a process gas. The first gas source 248 may include ammonia (NH3) as well as argon (Ar). The second gas source 250 may include a fluorine-containing gas, a hydrogen-containing gas, or a combination thereof. In one example, the second gas source 250 may include hydrogen fluoride (HF) as well as argon (Ar).

[0027]

[0033] As shown in FIG. 2B , in some configurations, the inlet 244 is coupled to the mixing chamber 238 through a cylindrical channel 252 (shown in dotted lines) and holes 254 formed in the fifth plate 236. The inlet 246 is coupled to the mixing chamber 238 through a cylindrical channel 256 (shown in dotted lines) and holes 258 formed in the fifth plate 236. The holes 254, 258 formed in the fifth plate 236 are generally sized to allow for uniform flow of gases supplied from the respective gas sources 248, 250 into the mixing chamber 238. In some configurations, the holes 258 have a diameter smaller than the width of the opening defined by the opposing sidewalls of the cylindrical channel 256 formed in the fourth plate 232. The holes 258 are typically distributed around the centerline of the cylindrical channel 256 to provide uniform fluid flow into the mixing chamber 238. In one configuration, the holes 254 have a diameter smaller than the width of the opening defined by the opposing sidewalls of the cylindrical channel 252 formed in the fourth plate 232. The holes 254 are typically distributed around the centerline of the cylindrical channel 252 to provide uniform fluid flow into the mixing chamber 238.

[0028]

[0034] Inlets 244 and 246 provide respective fluid flow paths that extend laterally through the fourth plate, pivot toward fifth plate 236, and extend through fifth plate 236 to mixing chamber 238. Lid assembly 204 also includes a seventh plate or first gas distributor 260, which may be a gas distribution plate such as a showerhead, through which various gases mixed within lid assembly 204 flow through perforations 262 formed therein. Perforations 262 are in fluid communication with mixing chamber 238 and provide a flow path from mixing chamber 238 through first gas distributor 260. Referring again to FIG. 2A , a blocker plate 264 and a second gas distributor 266, which may be a gas distribution plate such as a showerhead, are disposed below lid assembly 204.

[0029]

[0035] Alternatively, another cleaning process can be utilized to clean the substrate surface. For example, a remote plasma containing helium (He) and ammonia (NH) can be introduced into the processing chamber 200 through the lid assembly 204, and the ammonia (NH) can be injected directly into the processing chamber 200 through a separate gas inlet 268 located on the side of the chamber body 202 and coupled to a gas source (not shown).

[0030]

[0036] The support assembly 206 may include a substrate support 270 for supporting a substrate 272 thereon during processing. The substrate support 270 may be coupled to an actuator 274 by a shaft 276 extending through a centrally located opening formed in the bottom of the chamber body 202. The actuator 274 may be flexibly sealed to the chamber body 202 by a bellows (not shown) that prevents vacuum leakage around the shaft 276. The actuator 274 enables the substrate support 270 to be moved vertically within the chamber body 202 between a processing position and a loading position. The loading position is slightly below the opening of a tunnel (not shown) formed in the sidewall of the chamber body 202.

[0031]

[0037] The substrate support 270 has a flat or substantially flat substrate support surface for supporting a substrate 272 to be processed thereon. The substrate support 270 can be moved vertically within the chamber body 202 by an actuator 274 coupled to the substrate support 270 by a shaft 276. In some process steps, the substrate support 270 can be raised to a position adjacent to the lid assembly 204 to control the temperature of the substrate 272 being processed. In this manner, the substrate 272 can be heated via radiation emitted from the second gas distributor 266 or another radiation source, or by convection or conduction through an intervening gas from the second gas distributor 266. In some process steps, the substrate can be placed on lift pins 278 to perform an additional thermal treatment step, such as an annealing step.

[0032]

[0038] 3 is a cross-sectional view of a processing chamber 300 adapted to perform an epitaxial (Epi) deposition process, described in detail below, according to one or more embodiments. Processing chamber 300 may be processing chamber 126, 128, or 130 shown in FIG. 1.

[0033]

[0039] The processing chamber 300 includes a housing structure 302 made of a process-resistant material such as aluminum or stainless steel, e.g., 316L stainless steel. The housing structure 302 encloses various functional elements of the processing chamber 300, such as a quartz chamber 304 that includes an upper quartz chamber 306, and a lower quartz chamber 308 that includes a processing region 310. Reactive species are supplied to the quartz chamber 304 by a gas distribution assembly 312, and processing by-products are removed from the processing region 310 by an outlet port 314 that is typically connected to a vacuum source (not shown).

[0034]

[0040] The substrate support 316 is adapted to receive a substrate 318 transferred to the processing region 310. The substrate support 316 is disposed along a longitudinal axis 320 of the processing chamber 300. The substrate support 316 may be made of a ceramic or graphite material coated with a silicon material, such as silicon carbide, or other process-resistant material. Reactive species from precursor reactants may be supplied to a surface 322 of the substrate 318, and by-products may then be removed from the surface 322 of the substrate 318. Heating of the substrate 318 and / or the processing region 310 may be accomplished by a radiation source, such as an upper lamp module 324A and a lower lamp module 324B.

[0035]

[0041] In one embodiment, the upper lamp module 324A and the lower lamp module 324B are infrared (IR) lamps. Non-thermal energy or radiation from the lamp modules 324A and 324B passes through an upper quartz window 326 of the upper quartz chamber 306 and through a lower quartz window 328 of the lower quartz chamber 308. Cooling gas for the upper quartz chamber 306, if required, enters through an inlet 330 and exits through an outlet 332. Precursor reactants, as well as diluents, purge gases, and vent gases for the processing chamber 300, enter through the gas distribution assembly 312 and exit through an outlet port 314. While a curved or convex upper quartz window 326 is illustrated, the upper quartz window 326 may also be flat or concave, so that the pressure on both sides of the upper quartz window 326 is substantially the same (i.e., atmospheric pressure).

[0036]

[0042] The low wavelength radiation in the processing region 310 used to energize reactive species and assist in the adsorption of reactants and desorption of process by-products from the surface 322 of the substrate 318 typically ranges from about 0.8 μm to about 1.2 μm, e.g., from about 0.95 μm to about 1.05 μm, with various wavelength combinations provided depending, for example, on the composition of the film being epitaxially grown.

[0037]

[0043] Component gases enter the processing region 310 via a gas distribution assembly 312. The gases flow from the gas distribution assembly 312 and exit through an exit port 314, as generally illustrated by flow path 334. Combinations of component gases used to clean / passivate a substrate surface or to form epitaxially grown silicon- and / or germanium-containing films are typically mixed before entering the processing region 310. The overall pressure within the processing region 310 can be adjusted by a valve (not shown) at the exit port 314. At least a portion of the interior surface of the processing region 310 is covered by a liner 336. In one embodiment, the liner 336 comprises an opaque quartz material. In this manner, the chamber walls are insulated from heat within the processing region 310.

[0038]

[0044] The temperature of surfaces within processing region 310 can be controlled within a temperature range of about 200°C to about 600°C or greater by the flow of cooling gas entering through inlet 330 and exiting through outlet 332 in combination with radiation from upper lamp module 324A positioned above upper quartz window 326. The temperature within lower quartz chamber 308 can be controlled within a temperature range of about 200°C to about 600°C or greater by adjusting the speed of a blower unit (not shown) and by radiation from lower lamp module 324B positioned below lower quartz chamber 308. The pressure within processing region 310 can be between about 0.1 Torr and about 600 Torr, for example, between about 5 Torr and about 30 Torr.

[0039]

[0045] The temperature of the surface 322 of the substrate 318 can be controlled by adjusting the power to the lower lamp module 324B in the lower quartz chamber 308, or by adjusting the power to both the upper lamp module 324A above the upper quartz window 326 and the lower lamp module 324B in the lower quartz chamber 308. The power density in the processing region 310 is about 40 W / cm 2 ~about 400W / cm 2 , for example, about 80 W / cm 2 ~Approx. 120W / cm 2 It may be.

[0040]

[0046] In one aspect, the gas distribution assembly 312 is positioned perpendicular, or radially 338, to the longitudinal axis 320 of the processing chamber 300 or substrate 318. In this orientation, the gas distribution assembly 312 is adapted to flow process gases in the radial direction 338 across or parallel to the surface 322 of the substrate 318. In some processing applications, the process gases are preheated upon introduction into the processing chamber 300, and preheating of the gases is initiated and / or certain bonds in the gases are broken prior to introduction into the processing region 310. In this manner, surface reaction kinetics can be altered independently of the thermal temperature of the substrate 318.

[0041]

[0047] During processing, precursors used to form blanket or selective epitaxial films of silicon (Si) and silicon germanium (SiGe) are supplied to the gas distribution assembly 312 from one or more gas sources 340A and 340B. IR lamps 342 (only one shown in FIG. 3 ) can be used to heat the precursors within the gas distribution assembly 312 and along the flow path 334. The gas sources 340A, 340B can be coupled to the gas distribution assembly 312 in a manner adapted to facilitate introduction zones within the gas distribution assembly 312, such as a radially outer zone and a radially inner zone between the outer zones, when viewed from a top view. The gas sources 340A, 340B can include valves (not shown) to control the introduction rate into the zones.

[0042]

[0048] Gas sources 340A, 340B may contain silicon precursors such as silanes, including silane (SiH), disilane (SiH), dichlorosilane (SiHCl), hexachlorodisilane (SiCl), dibromosilane (SiHBr), higher silanes, derivatives thereof, and combinations thereof. Gas sources 340A, 340B may also contain germanium-containing precursors, such as germane (GeH), digermane (GeH), germanium tetrachloride (GeCl), dichlorogermane (GeHCl), derivatives thereof, and combinations thereof. Silicon and / or germanium-containing precursors may be used in combination with hydrogen chloride (HCl), chlorine gas (Cl), hydrogen bromide (HBr), and combinations thereof. The gas sources 340A, 340B may include one or more of silicon and germanium containing precursors in one or both of the gas sources 340A, 340B.

[0043]

[0049] The precursor material enters the processing region 310 through openings or holes 344 (only one shown in FIG. 3 ) in the excited aperture plate 346, which in one embodiment is a quartz material with the holes 344 formed therethrough. The aperture plate 346 is transparent to IR energy and may be made of a transparent quartz material. In other embodiments, the aperture plate 346 may be any material that is transparent to IR energy and resistant to process and other processing chemistries. Upon application of a voltage, the precursor material flows through the holes 344 in the aperture plate 346 and through channels 348 (only one shown in FIG. 3 ) toward the processing region 310. A portion of the photons and non-thermal energy from the IR lamps 342 are also promoted by reflective materials and / or surfaces disposed on the interior surface of the gas distribution assembly 312 to pass through the holes 344, aperture plate 346, and channels 348, thereby illuminating the precursor material flow path 334. In this way, the vibrational energy of the precursor material can be maintained along the flow path from the point of introduction into the processing region 310 .

[0044]

[0050] 4 is a cross-sectional view of one or more embodiments of a processing system 400 adapted to perform a recrystallization anneal or oxidation process, as described in more detail below. Processing system 400 may be a rapid thermal processing (RTP) apparatus, such as, but not limited to, an RTP CENTURA® available from Applied Materials, Inc. of Santa Clara, California. Other types of thermal reactors, such as an EPI CENTURA® available from Applied Materials, Inc. of Santa Clara, California, may also be used in place of an RTP apparatus. Other suitable plasma reactors may also be utilized, including a remote plasma oxidation (RPO) reactor available from Applied Materials, Inc. of Santa Clara, California.

[0045]

[0051] The processing system 400 includes a thermal treatment chamber 402 and a precursor activator 404 coupled to the thermal treatment chamber 402 and used to remotely supply plasma radicals to a processing region 406 of the thermal treatment chamber 402. The precursor activator 404 can also be used to supply an activated plasma gas mixture, for example, by applying energy to the gas to create a highly radical-rich mixture with only a trace amount of ions. The processing region 406 is surrounded by one or more sidewalls 408 (e.g., four sidewalls) and a base 410. The tops of the sidewalls 408 can be sealed to a window assembly 412 (e.g., using an "O" ring). A radiant energy assembly 414 is positioned above and coupled to the window assembly 412. The radiant energy assembly 414 includes multiple lamps 416, which can be tungsten halogen lamps, each mounted in a receptacle 418 and positioned to emit electromagnetic radiation within the processing region 406. Although the window assembly 412 in FIG. 4 includes a plurality of light pipes 420, the window assembly 412 may include only a flat, solid window without any light pipes. The window assembly 412 has an outer wall 422 (e.g., a cylindrical outer wall) around its periphery that forms a rim surrounding the window assembly 412. The window assembly 412 also has a first window 424 that covers a first end of the plurality of light pipes 420 and a second window 426 that covers a second end of the plurality of light pipes 420 opposite the first ends. The first window 424 and the second window 426 extend to and engage the outer wall 422 of the window assembly 412, enclosing and sealing the interior of the window assembly 412, including the plurality of light pipes 420. In such a case, when the light pipes are used, a vacuum can be generated within the plurality of light pipes 420 by applying a vacuum to one of the plurality of light pipes 420 through a conduit 428 that penetrates the outer wall 422 and is then fluidly connected to the remainder of the light pipe.

[0046]

[0052] The substrate W is supported in the thermal treatment chamber 402 by a support ring 430 within the processing region 406. The support ring 430 is attached to a rotatable cylinder 432. Rotating the rotatable cylinder 432 rotates the support ring 430 and the substrate W during processing. The base 410 of the thermal treatment chamber 402 is provided with a reflective surface 434 for reflecting energy onto the backside of the substrate W during processing. Alternatively, a separate reflector (not shown) can be positioned between the base 410 of the thermal treatment chamber 402 and the support ring 430. The thermal treatment chamber 402 can include multiple temperature probes 436 positioned through the base 410 of the thermal treatment chamber 402 to detect the temperature of the substrate W. As described above, if a separate reflector is used, the temperature probes 436 are also positioned through the separate reflector to optically access electromagnetic radiation coming from the substrate W.

[0047]

[0053] The rotatable cylinder 432 is supported by a magnetic rotor 438, which is a cylindrical member having a ledge 440 on which the rotatable cylinder 432 rests when both members are installed in the thermal treatment chamber 402. The magnetic rotor 438 has a plurality of magnets in a magnet region 442 below the ledge 440. The magnetic rotor 438 is disposed in an annular well 444 located along the base 410 at the peripheral region of the thermal treatment chamber 402. A cover 446 rests on the peripheral portion of the base 410 and extends over the annular well 444 toward the rotatable cylinder 432 and the support ring 430, leaving a tolerance gap between the cover 446 and the rotatable cylinder 432 and / or the support ring 430. The cover 446 generally protects the magnetic rotor 438 from exposure to process conditions in the processing region 406.

[0048]

[0054] The magnetic rotor 438 is rotated by magnetic energy from a magnetic stator 448 disposed about the base 410. The magnetic stator 448 has a plurality of electromagnets 450 that are powered in a rotational pattern to form a rotating magnetic field that provides the magnetic energy to rotate the magnetic rotor 438 during processing of the substrate W. The magnetic stator 448 is coupled to a linear actuator 452 by a support 454. Actuation of the linear actuator 452 moves the magnetic stator 448 along an axis 456 of the thermal treatment chamber 402, thereby moving the magnetic rotor 438, the rotatable cylinder 432, the support ring 430, and the substrate W along the axis 456.

[0049]

[0055] Process gases are supplied to the thermal treatment chamber 402 through a chamber inlet 458 and directed out of the page, and are exhausted through a chamber outlet that is generally coplanar with the chamber inlet 458 and the support ring 430 (not shown in FIG. 4). Substrates enter and exit the thermal treatment chamber 402 through an access port 460 formed in the sidewall 408 and shown at the rear in FIG.

[0050]

[0056] The precursor activation device 404 has a body 462 that encloses an interior space 464 in which a plasma 466 of ions, radicals, and electrons can be formed. A quartz or sapphire liner 468 protects the body 462 from chemical attack by the plasma. The interior space 464 is preferably free of any potential gradient that could attract charged particles, such as ions. A gas inlet 470 is disposed at a first end 472 of the body 462, opposite a gas outlet 474 located at a second end 476 of the body 462. When the precursor activation device 404 is coupled to a thermal treatment chamber 402, the gas outlet 474 is fluidly connected to the thermal treatment chamber 402 through a delivery line 478 to the chamber inlet 458 so that radicals from the plasma 466 generated in the interior space 464 are supplied to the processing region 406 of the thermal treatment chamber 402. The gas outlet 474 may have a larger diameter than the gas inlet 470 so that the excited radicals can be efficiently exhausted at a targeted flow rate and so that contact of the radicals with the liner 468 can be minimized. If targeted, another orifice can be inserted in the liner 468 at the gas outlet 474 to reduce the internal dimension of the interior space 464 of the gas outlet 474. The diameter of the gas outlet 474 (or orifice, if used) can be selected to create a pressure differential between the processing region 406 and the precursor activation device 404. The pressure differential can be selected to flow into the thermal treatment chamber 402 a composition of ions, radicals, and molecules appropriate for the process to be performed therein.

[0051]

[0057] To supply gas for plasma processing, a first gas source 480 is coupled to the gas inlet 470 via a first input of a four-way valve 482 and a valve 484 used to control the flow rate of gas released from the first gas source 480. A second input of the four-way valve 482 may be coupled to a second gas source 486. A third input of the four-way valve may be coupled to a third gas source 488. The first gas source 480, the second gas source 486, and the third gas source 488 may each be or include one or more of a nitrogen-containing gas, an oxygen-containing gas, a silicon-containing gas, a hydrogen-containing gas, or a plasma-forming gas such as argon or helium. A flow controller 490 is connected to the four-way valve 482 and switches the valve between its different positions depending on which process is being performed. The flow controller 490 also controls the switching of the four-way valve 482.

[0052]

[0058] In some implementations, a second hydrogen gas source (not shown) is fluidly coupled to the thermal treatment chamber 402. The second hydrogen gas source delivers hydrogen gas to the processing region 406, where the hydrogen gas is activated by a remote plasma comprising oxygen and argon delivered to the processing region 406 from the precursor activation device 404. In some implementations targeting a high percentage of hydrogen gas, hydrogen gas can be supplied to the processing region 406 through both the third gas source 488 and the second hydrogen gas source.

[0053]

[0059] In some implementations, a second argon gas source (not shown) is coupled to the thermal treatment chamber 402. The second argon gas source delivers argon gas to the processing region 406, where the argon gas is activated by a remote plasma delivered to the processing region 406 from the precursor activator 404. In some implementations targeting a high percentage of argon gas, argon gas can be supplied to the processing region 406 through both the second gas source 486 and the second argon gas source.

[0054]

[0060] FIG. 5 is a process flow diagram illustrating a method 500 of forming source / drain regions in a semiconductor structure 600 according to a first embodiment of the present disclosure. FIGS. 6A, 6B, 6C, 6D, and 6E are cross-sectional views of a portion of the semiconductor structure 600 corresponding to various states of the method 500. It should be understood that FIGS. 6A, 6B, 6C, 6D, and 6E illustrate only partial schematic views of the semiconductor structure 600, and that the semiconductor structure 600 may include any number of transistor sections and additional materials having the aspects shown. It should also be noted that while the method illustrated in FIG. 5 is described sequentially, other process sequences including one or more steps omitted and / or added and / or rearranged in another desired order are within the scope of the embodiments of the present disclosure provided herein.

[0055]

[0061] 6A, 6B, 6C, 6D, and 6E, a semiconductor structure 600 can include a first semiconductor region 602 and a second semiconductor region 604 formed on a substrate 606. The first semiconductor region 602 and the second semiconductor region 604 are separated by a trench 608 in which a source / drain (SD) region is formed.

[0056]

[0062] The term "substrate" as used herein refers to a layer of material that provides the basis for subsequent processing steps and includes a surface to be cleaned. The substrate may be a silicon-based material, or any suitable insulating or conductive material as desired. The substrate may be crystalline silicon (e.g., Si <100> or Si <111> ), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0057]

[0063] As shown in FIG. 6A, the first semiconductor region 602 and the second semiconductor region 604 each include a first semiconductor layer 610 and a second semiconductor layer 612 stacked alternately on a substrate 606. The first semiconductor layer 610 is formed of a first material that has an etch selectivity (i.e., the etch rate of the first material is higher than the etch rate of the second material) relative to the second material from which the second semiconductor layer 612 is formed. The etch selectivity (i.e., the ratio of the etch rate of the first material to the etch rate of the second material) is approximately 10:1 to 200:1. Examples of combinations of the first and second materials include silicon germanium (SiGe) / silicon (Si), silicon germanium (SiGe) / germanium (Ge), and germanium tin (GeSn) / silicon (Si). The first semiconductor layer 610 may be selectively etched to form recesses at the ends of the first semiconductor layer 610 facing the trench 608, in which spacers 614 are respectively formed. These spacers 614 may be formed of a dielectric material such as silicon nitride (Si3N4), silicon oxynitride (SiON), or silicon oxycarbide (SiOCN).

[0058]

[0064] The second semiconductor layer 612 can function as a channel having a width of several nanometers to several tens of nanometers.

[0059]

[0065] The first and second semiconductor layers 610 and 612 can be formed using any suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), and the trench 608 is formed by a patterning technique, such as a lithography and etching process. The first and second semiconductor layers 610 and 612 can each have a thickness of about 3 nm to about 15 nm, for example, about 10 nm. The selective etching of the first semiconductor layer 610 can be performed by any suitable etching process, such as a dry plasma etching process.

[0060]

[0066] The semiconductor structure 600 further includes a dummy gate layer (also referred to as a "dielectric layer") 616 formed over at least a portion of each of the first semiconductor region 602 and the second semiconductor region 604. The dummy gate layer 616 may be formed of a dielectric material such as silicon dioxide (SiO2).

[0061]

[0067] Method 500 begins with a pre-cleaning process at block 510. The pre-cleaning process may be performed in a processing chamber such as processing chamber 122 shown in Figure 1, processing chamber 200 shown in Figure 2, or processing chamber 300 shown in Figure 3. In some embodiments, the pre-cleaning process at block 510 and the first deposition process at block 520 are performed in situ in the same processing chamber to minimize regrowth of an oxide layer.

[0062]

[0068] The pre-cleaning process is configured to remove contaminants such as native oxide layers or patterning residues (e.g., fluorocarbons) formed on the exposed surfaces of the first semiconductor region 602 and the second semiconductor region 604 within the trench 608.

[0063]

[0069] The pre-clean etch process may be a wet etch process using a cleaning solution such as a hydrofluoric acid (HF)-rust type cleaning solution, an ozone water cleaning solution, an HF and hydrogen peroxide (H2O2) solution, and / or other suitable cleaning solution. The cleaning solution may be heated.

[0064]

[0070] The pre-cleaning process can include an isotropic plasma etching process, such as a SiCoNi™ dry chemical etching process, which uses a plasma formed from a gas containing ammonia (NH), nitrogen trifluoride (NF), hydrogen fluoride (HF), or a combination thereof, and a carrier gas such as nitrogen (N), hydrogen (H), or a combination thereof. Because the dry chemical etching process is selective to oxide layers, it does not readily etch silicon, germanium, or nitride layers, regardless of whether the layers are amorphous, crystalline, or polycrystalline. The selectivity of the dry chemical etching process for oxide to silicon or germanium is at least about 3:1, typically 5:1 or greater, and in some cases 10:1. The dry chemical etching process also has a high oxide to nitride selectivity. The selectivity of the dry chemical etching process for nitride is at least about 3:1, typically 5:1 or greater, and in some cases 10:1.

[0065]

[0071] The pre-cleaning process may include an anisotropic remote plasma dry etching process, such as a reactive ion etching (RIE) process, using a plasma formed from a gas including argon (Ar), helium (He), or a combination thereof. The plasma effluents directionally impinge on and remove contaminants on the exposed surfaces of first semiconductor region 602 and second semiconductor region 604 within trench 608.

[0066]

[0072] The pre-cleaning process can include an inductively coupled plasma (ICP) etching process using a plasma formed from a gas containing chlorine (Cl) and hydrogen (H) and a carrier gas containing argon (Ar) and helium (He). The ICP etching process is used to form deep ridges with smooth sidewalls in the silicon.

[0067]

[0073] In block 520, as shown in Figure 6B, a first deposition process is performed to form an amorphous silicon-containing layer 618 on exposed surfaces of semiconductor structure 600 (i.e., exposed surfaces of first semiconductor region 602 and second semiconductor region 604 in trench 608, and dummy gate layer 616). The first deposition process may include any suitable deposition process, such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), an epitaxy process, or the like, in a processing chamber, such as processing chamber 126, 128, or 130 shown in Figure 1 or processing chamber 300 shown in Figure 3.

[0068]

[0074] The amorphous silicon-containing layer 618 may be doped with a silicon-containing material having a thickness of approximately 100 Å, depending on the desired conductivity characteristics of the S / D regions formed in the trenches 608. 19 cm -3 ~Approx. 5×10 21 cm -3 The amorphous silicon-containing layer 618 may be doped with a p-type dopant, such as boron (B) or gallium (Ga), at a concentration of about 1000 .mu.m or less. The p-type amorphous silicon-containing layer 618 may be formed of silicon germanium (SiGe) with a high germanium (Ge) concentration, for example, about 5% to about 60%, to minimize parasitic resistance. The amorphous silicon-containing layer 618 may also contain carbon (C) at a concentration of less than about 1%, which may be used for subsequent dopant diffusion control in the source / drain regions to be formed.

[0069]

[0075] The amorphous silicon-containing layer 618 may be doped with a silicon-containing material having a thickness of approximately 100 Å, depending on the desired conductivity characteristics of the S / D regions formed in the trenches 608. 19 cm -3 ~5×10 21 cm -3 The n-type amorphous silicon-containing layer 618 may be doped with an n-type dopant, such as phosphorus (P), antimony (Sb), or the like, at a concentration of 0.1% or less. The n-type amorphous silicon-containing layer 618 may be formed of silicon germanium (SiGe) having a low germanium (Ge) concentration, for example, less than about 5%, to promote recrystallization of the amorphous silicon-containing layer 618 in a subsequent recrystallization annealing process in block 530.

[0070]

[0076] In the first deposition process, the semiconductor structure 600 is exposed to a silicon-containing deposition gas at a low temperature between about 200° C. and about 500° C. to ensure that the formed layer 618 is amorphous. The deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursors include silane (SiH), disilane (SiH), trisilane (SiH), tetrasilane (SiH), and tetrasilane (SiH). 10 The germanium-containing precursor may include germane (GeH), germanium tetrachloride (GeCl), and digermane (GeH). To form the n-type amorphous silicon layer 618, the dopant source may include an n-type dopant, such as phosphorus (P), antimony (Sb), or arsenic (As). The dopant source may include the precursors phosphine (PH), phosphorus trichloride (PCl), triisobutylphosphine ([(CH)C]P), antimony trichloride (SbCl), Sb(CH), arsine (AsH), arsenic trichloride (AsCl), tertiary butylarsine (AsCH). 11 ) To form the p-type amorphous silicon-containing layer 618, the dopant source may include a p-type dopant, such as boron (B) or gallium (Ga). The dopant source may include the precursor diborane (B2H6) or trimethylgallium Ga(CH3)3. It should be noted that the dopant may facilitate recrystallization of the amorphous silicon-containing layer 618 in a subsequent recrystallization process in block 530.

[0071]

[0077] In block 530, a recrystallization anneal process is performed to recrystallize at least a portion of the amorphous silicon-containing layer 618, as shown in Figure 6C. In some embodiments, the recrystallization anneal process is performed in situ in the same chamber as the subsequent epitaxial deposition process in block 550, such as processing chamber 300 shown in Figure 3. In other embodiments, the recrystallization anneal process is a rapid thermal anneal process and is performed ex situ in a rapid thermal processing (RTP) tool, such as processing system 400 shown in Figure 4. The recrystallization anneal process may be a laser anneal process.

[0072]

[0078] The recrystallization annealing process can be carried out at a temperature between about 400°C and about 700°C for a duration of about 1 minute to about 15 minutes, or at a temperature between about 700°C and about 900°C for a duration of milliseconds. In some embodiments, the temperature is fixed, for example, at about 600°C, for the duration of the thermal anneal. In some embodiments, the temperature is increased, for example, from about 300°C to about 600°C, and then decreased to about 300°C, and this temperature change is repeated for the duration of the thermal anneal.

[0073]

[0079] During the recrystallization annealing process, the amorphous silicon-containing layer 618 crystallizes starting from a surface 612S of the second semiconductor layer 612 (e.g., silicon (Si)) facing the trench 608, continues laterally along the width of the trench 608, and continues vertically along the length of the trench 608 on a surface 614S of the spacer 614 facing the trench 608. A portion of the amorphous silicon-containing layer 618 crystallizes in this manner, forming a silicon-containing crystalline layer 620 in the trench 608 and covering the surface 612S of the second semiconductor layer 612 and the surface 614S of the spacer 614. A portion of the amorphous silicon-containing layer 618 (e.g., silicon dioxide (SiO)) on the dummy gate layer 616 remains amorphous.

[0074]

[0080] In block 540, an etching process is performed to remove remaining portions of the amorphous silicon-containing layer 618, as shown in FIG. 6D. The etching process may include any suitable etching process and may be performed in situ in the same chamber as the subsequent epitaxial deposition process in block 550, such as processing chamber 300 shown in FIG. 3. In some embodiments, the etching process may be performed ex situ in a different processing chamber from the processing chamber in which the subsequent epitaxial deposition process in block 550 occurs, such as processing chamber 122 shown in FIG. 1. In these embodiments, the etching process is followed by a pre-cleaning process, such as in block 510, prior to the subsequent epitaxial deposition process in block 550.

[0075]

[0081] In the etching process, the portion of the amorphous silicon-containing layer 618 (e.g., silicon dioxide (SiO)) over the dummy gate layer 616 and any portion of the amorphous silicon-containing layer 618 that was not crystallized during the recrystallization annealing process in block 530 are removed with an appropriate etching gas. The amorphous silicon-containing layer 618 may etch at a faster rate than the silicon-containing crystalline layer 620 and may therefore be selectively etched relative to the silicon-containing crystalline layer 620. The etching process in block 540 may also remove any polycrystalline or defective material.

[0076]

[0082] In block 550, a second deposition process is performed to epitaxially form S / D regions 622 in trenches 608, as shown in Figure 6E. The second deposition process may include an epitaxial deposition process in a processing chamber such as processing chambers 126, 128, or 130 shown in Figure 1 or processing chamber 300 shown in Figure 3.

[0077]

[0083] The S / D regions 622 are formed of the same material as the silicon-containing crystalline layer 620, and thus the amorphous silicon-containing layer 618. In the second deposition process, the silicon-containing crystalline layer 620 is used as a crystalline template for the epitaxial growth of the S / D regions 622. Thus, the S / D regions 622 formed in block 550 can be uniform and of high quality without twins or stacking faults.

[0078]

[0084] The epitaxial deposition process may be carried out at a temperature between about 400° C. and about 700° C. and a pressure between 5 Torr and 300 Torr.

[0079]

[0085]

[0003] Embodiments described herein provide methods and systems for performing epitaxial growth to fill trenches in semiconductor structures, the interior surfaces of the trenches including silicon-containing and silicon nitride-containing portions. According to the embodiments described herein, epitaxial growth of source / drain regions is performed on a crystalline template formed on the surface of the trench, covering the silicon-containing and silicon nitride-containing portions, resulting in high-quality, uniform source / drain regions free of defects or voids. The crystalline template is formed by recrystallizing an amorphous silicon-containing layer disposed on the interior surfaces of the trenches.

[0080]

[0086] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from the basic scope thereof as determined by the following claims.

Claims

1. 1. A processing system comprising: one or more processing chambers; a system controller for controlling the processing system in the one or more processing chambers; (a) a pre-cleaning process for an exposed surface of a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region; (b) a first deposition process that forms an amorphous silicon-containing layer on the exposed surface of the semiconductor structure; (c) a recrystallization annealing process that recrystallizes at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer in the trench; (d) an etching process to remove remaining portions of the amorphous silicon-containing layer; (e) a second deposition process to epitaxially form source / drain regions on the silicon-containing crystalline layer in the trench; a system controller configured to execute A processing system comprising:

2. the one or more processing chambers include a first processing chamber and a second processing chamber; (a) and (b) are performed in the first processing chamber; (c) through (e) are performed in the second processing chamber; The processing system of claim 1 .

3. the one or more processing chambers include a first processing chamber; (a) through (e) are performed in the first processing chamber; The processing system of claim 1 .

4. 10. The processing system of claim 1, wherein the first deposition process is performed at a temperature between 200°C and 500°C.

5. 10. The processing system of claim 1, wherein said recrystallization annealing process is performed at a temperature between 400°C and 700°C.

6. the first semiconductor region and the second semiconductor region each include a first semiconductor layer and a second semiconductor layer that are alternately and repeatedly stacked; each of the first semiconductor layers includes a spacer at an end of each of the first semiconductor layers facing the trench; the first semiconductor layer includes silicon (Si); the second semiconductor layer includes silicon germanium (SiGe); The spacer is made of silicon nitride (Si ３ N ４ ), silicon oxynitride (SiON), and silicon oxycarbide (SiOCN), The processing system of claim 1 .

7. 1. A method of filling a trench in a semiconductor structure, comprising: performing a first deposition process to form an amorphous silicon-containing layer on an exposed surface of a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region; performing a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer in the trench; performing an etching process to remove remaining portions of the amorphous silicon-containing layer; performing a second deposition process to epitaxially form source / drain regions on the silicon-containing crystalline layer within the trench; A method comprising:

8. The method of claim 7 , wherein the first deposition process is carried out at a temperature between 200° C. and 500° C.

9. 8. The method of claim 7, wherein the recrystallization annealing process is carried out at a temperature between 400°C and 700°C.

10. The method of claim 7 , wherein the amorphous silicon-containing layer, the silicon-containing crystalline layer, and the source / drain regions are doped with an n-type dopant.

11. The method of claim 7 , wherein the amorphous silicon-containing layer, the silicon-containing crystalline layer, and the source / drain regions are doped with a p-type dopant.

12. the first semiconductor region and the second semiconductor region each include a first semiconductor layer and a second semiconductor layer that are alternately and repeatedly stacked; each of the first semiconductor layers includes a spacer at an end of each of the first semiconductor layers facing the trench; The method of claim 7.

13. the first semiconductor layer includes silicon (Si); the second semiconductor layer includes silicon germanium (SiGe); The spacer is made of silicon nitride (Si ３ N ４ ), silicon oxynitride (SiON), and silicon oxycarbide (SiOCN), The method of claim 12.

14. performing a pre-cleaning process on the exposed surface of the semiconductor structure prior to the first deposition process. The method of claim 7 further comprising:

15. 1. A method of filling a trench in a semiconductor structure, comprising: performing a pre-cleaning process on an exposed surface of a semiconductor structure, the semiconductor structure including a first semiconductor region, a second semiconductor region separated from the first semiconductor region by a trench, and a dielectric layer over at least a portion of the first semiconductor region and the second semiconductor region; performing a first deposition process to form an amorphous silicon-containing layer on the exposed surface of the semiconductor structure; performing a recrystallization annealing process to recrystallize at least a portion of the amorphous silicon-containing layer to form a silicon-containing crystalline layer in the trench; performing an etching process to remove remaining portions of the amorphous silicon-containing layer; performing a second deposition process to epitaxially form source / drain regions on the silicon-containing crystalline layer within the trench; A method comprising:

16. 16. The method of claim 15, wherein the first deposition process is carried out at a temperature between 200°C and 500°C.

17. 16. The method of claim 15, wherein the recrystallization annealing process is carried out at a temperature between 400°C and 700°C.

18. 16. The method of claim 15, wherein the amorphous silicon-containing layer, the silicon-containing crystalline layer, and the source / drain regions are doped with an n-type dopant.

19. 16. The method of claim 15, wherein the amorphous silicon-containing layer, the silicon-containing crystalline layer, and the source / drain regions are doped with a p-type dopant.

20. the first semiconductor region and the second semiconductor region each include a first semiconductor layer and a second semiconductor layer that are alternately and repeatedly stacked; each of the first semiconductor layers includes a spacer at an end of each of the first semiconductor layers facing the trench; the first semiconductor layer includes silicon (Si); the second semiconductor layer includes silicon germanium (SiGe); The spacer is made of silicon nitride (Si ３ N ４ ), silicon oxynitride (SiON), and silicon oxycarbide (SiOCN), 16. The method of claim 15.

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