Output-optimized VTFET circuit

Abstract

The semiconductor device comprises: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks above the first via level; a second via level forming a first top jumper above the first set of two or more first metallization tracks; and a second metallization track above the second via level.

Description

[Background technology]

[0001] FIELD OF THE INVENTION The exemplary embodiments described herein relate generally to semiconductor device fabrication methods and resulting structures, and more particularly to fabrication methods and resulting semiconductor device structures such as vertical transport field effect transistors.

[0002] Semiconductor device chip architectures for logic circuits use lateral-transport field-effect transistors (FETs), such as fin field-effect transistors or finFETs, in which the transistors are layered along the surface of a silicon wafer. Typically, transistors are arranged and laid out horizontally on the wafer. The problem with horizontal layouts is that transistor components occupy a significant amount of surface area on the chip, and increasing the number of transistor components while minimizing surface area means increasing transistor density. In existing processes, increasing transistor density focuses on reducing the size of various components. However, it is still required that all basic units of a transistor component (including the isolation elements between transistors) fit within the minimum area required for the transistor to be laid out functionally.

[0003] On the other hand, vertical transport FETs (VTFETs) have transistors layered perpendicular to the wafer, with current flow also directed perpendicular to the wafer surface. This approach addresses barriers to scaling by relaxing physical constraints on transistor gate length, spacer thickness, and contact size, allowing these features to be optimized for either performance or energy consumption, respectively. Layering transistors perpendicular to the wafer allows transistors to be scaled in the Z-axis without increasing the amount of wafer floor space they occupy. This allows manufacturers to reduce the number of components required to make the transistors function (more specifically, eliminate inter-transistor insulators from the design) and place transistors closer together. Current in this configuration naturally flows perpendicular to the supporting wafer, rather than the typical horizontal direction currently employed.

[0004] U.S. Patent Application No. 2020 / 0295134 discusses a vertical field effect transistor (VFET) cell architecture in which a gate connection pattern is formed between four VFETs to connect the gates. A gate contact structure is formed on the gate connection pattern, and a metal pattern is formed on the contact structure. The metal pattern can be connected to the gate contact structure through a via formed between the metal pattern and the gate contact structure. U.S. Patent Application No. 2020 / 0295134 aims to provide an improved cell architecture with reduced dimensions by including a square-top source / drain (S / D) contact structure for internal routing between the VFETs and a supervia for gate connection. However, jumpers are not present in any of the embodiments disclosed in U.S. Patent Application No. 2020 / 0295134. In fact, all of the architectures described in U.S. Patent Application No. 2020 / 0295134 lack jumpers, either above or below the metal pattern. The present invention addresses this lack of jumpers. Summary of the Invention

[0005] In one exemplary embodiment, a semiconductor device comprises: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks above the first via level; a second via level forming a first top jumper above the first set of two or more first metallization tracks; and a second metallization track above the second via level.

[0006] The length of the first via level may not be equal to the length of the second via level. The first set of two or more first metallization tracks may have three or more metallization tracks, and the spacing between three or more of the three or more first metallization tracks may be uneven. The first set of two or more first metallization tracks may be formed by a subtractive process. The first via level, the second via level, and the second metallization tracks may be formed by a damascene process. The second via level may form a second top jumper above the second set of first metallization tracks. The length of the second top jumper may be different from the length of the first top jumper. The second top jumper may be above one metallization track of the second set of first metallization tracks. Circuits employing such a configuration of metallization tracks and jumpers can reduce via resistance due to the use of multiple V0 / M1 / V1 sequences arranged in parallel, improving the overall efficiency and performance of the circuit.

[0007] In another exemplary embodiment, a vertical transport field effect transistor comprises: a bottom jumper formed in a substrate; a first M1 track and a second M1 track each above the bottom jumper; a first top jumper above the first M1 track and the second M1 track; and a first M2 track above the first top jumper.

[0008] The vertical transport field effect transistor may further include a third M1 track above the bottom jumper, and the spacing between the first M1 track, the second M1 track, and the third M1 track may be non-uniform. The vertical transport field effect transistor may further include a second top jumper above at least the third M1 track, and the first M2 track extends to and is above the second top jumper. The lengths of the first top jumper and the second top jumper may be non-uniform. Using multiple jumpers and metallization tracks in parallel can dramatically reduce the output resistance of the vertical transport field effect transistor in scaled-up cells (e.g., by tens of ohms).

[0009] In another exemplary embodiment, a method includes: providing a substrate; forming a recess in the substrate; depositing a first metal in the recess and on a top surface of the substrate such that the deposited first metal protrudes from the recess; patterning the deposited first metal; subtractively etching the first metal down to the top surface of the substrate to form a first jumper in the recess and a first set of two or more first metallization tracks above the first jumper; and depositing a dielectric material overlying the subtractively etched first metal. the dielectric material; patterning the dielectric material; forming openings in the dielectric material down to a top surface of the first set of two or more first metallization tracks; depositing a second metal in the openings in the dielectric material to form a second jumper in the openings spanning at least two of the two or more first metallization tracks; patterning the deposited second metal; and depositing a third metal over the deposited and patterned second metal to form a set of two or more second metallization tracks, at least one of the two or more second metallization tracks extending the length of the second jumper.

[0010] The method may further include forming a device region on the substrate. Forming the openings in the dielectric material down to the top surface of the first set of two or more first metallization tracks may include using a reverse selective barrier process. Depositing the first metal in the recesses on the top surface of the substrate may include using a first damascene process. Forming the second jumper in the opening by depositing the second metal in the opening of the dielectric material may include using a second damascene process. Forming the set of two or more second metallization tracks by depositing the third metal onto the patterned deposited second metal may include using a third damascene process. In any of the foregoing embodiments, a path from a V0 jumper to an M2 metallization track can be made interface-free with the same metal. [Brief explanation of the drawings]

[0011] The foregoing and other aspects of the exemplary embodiments will be more clearly apparent from the following detailed description when read in conjunction with the accompanying drawings.

[0012] [Figure 1] FIG. 1 is a schematic top view of a VTFET with unused M1 metallization tracks.

[0013] [Figure 2A] FIG. 1 is a schematic side view of an exemplary embodiment of a VTFET having a V1 jumper across an M1 metallization track.

[0014] [Figure 2B] FIG. 2B is a schematic top view of the VTFET of FIG. 2A.

[0015] [Figure 3A] FIG. 2B is a schematic side view of one exemplary embodiment of a process flow by which the VTFET of FIG. 2A may be fabricated. [Figure 3B]FIG. 2B is a schematic side view of one exemplary embodiment of a process flow by which the VTFET of FIG. 2A may be fabricated. [Figure 3C] FIG. 2B is a schematic side view of one exemplary embodiment of a process flow by which the VTFET of FIG. 2A may be fabricated. [Figure 3D] FIG. 2B is a schematic side view of one exemplary embodiment of a process flow by which the VTFET of FIG. 2A may be fabricated. [Figure 3E] FIG. 2B is a schematic side view of one exemplary embodiment of a process flow by which the VTFET of FIG. 2A may be fabricated. [Figure 3F] FIG. 2B is a schematic side view of one exemplary embodiment of a process flow by which the VTFET of FIG. 2A may be fabricated.

[0016] [Figure 4A] FIG. 1 is a schematic side view of an exemplary embodiment of a VTFET having a V1 jumper across unevenly spaced M1 metallization tracks.

[0017] [Figure 4B] FIG. 4B is a schematic top view of the VTFET of FIG. 4A.

[0018] [Figure 5A] FIG. 1 is a schematic side view of an exemplary embodiment of a VTFET having multiple V1 jumpers of different sizes.

[0019] [Figure 5B] FIG. 5B is a schematic top view of the VTFET of FIG. 5A.

[0020] [Figure 6A] FIG. 1 is a schematic side view of an exemplary embodiment of a VTFET with jumpers and vias.

[0021] [Figure 6B] FIG. 6B is a schematic top view of the VTFET of FIG. 6A.

[0022] [Figure 7]is a graphical representation of the parallel resistance of the VTFET as a function of the number of V0 / M1 / V1 objects.

[0023] [Figure 8] 1 is a flowchart of an exemplary method of forming a VTFET. DETAILED DESCRIPTION OF THE INVENTION

[0024] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. All embodiments described in this detailed description are example embodiments provided to enable any person skilled in the art to make or use the invention and do not limit the scope of the invention, which is defined by the claims.

[0025] Exemplary embodiments described herein are directed to the placement of metal in interconnect configurations and the use of jumpers and jumper turning to connect the interconnects. The interconnects are comprised of metallization lines used in fabricating VTFETs and optimizing circuit output. In the disclosed embodiments, the jumper turning to connect the interconnects is enabled by a semi-damascene process, which is preferable to a dual-damascene process because it facilitates the formation of vias under the metallization lines. Because "wrong-way" V0 jumper turning is enabled by these semi-damascene processes, vias can be configured to extend outward in areas without metallization lines above them. Specifically, multiple adjacently positioned metallization lines (M1 tracks) are secured together from both the top and bottom by via jumpers. This is typically performed for large-scale VTFET circuits (e.g., NAND or NOR logic circuits) that use backside power and have unused M1 tracks within the cell. These circuits have lower via resistance due to the use of multiple V0 / M1 / V1 sequences in parallel, improving the overall efficiency and performance of the circuit.

[0026] Referring now to the Figures, there are shown VTFET circuits and exemplary methods of their fabrication. The size of the circuit footprint is generally referred to as the "cell gate pitch" or C PP which in this case is characterized by 4C PP 1, a VTFET with a backside power supply is generally designated 100 and hereafter referred to as "VTFET 100." VTFET 100 includes multiple M1 tracks 110, three of which are designated 115 as unused (not connected to metallization M2) when power is transferred to the backside.

[0027] 2A and 2B, one exemplary embodiment of a VTFET with backside power supply is generally designated 200 and hereinafter referred to as "VTFET 200." VTFET 200 includes a via level V0 configured to output a signal, a first metallization layer M1, a V1 layer, and a second metallization layer M2. As shown in FIG. 2A, first metallization layer M1 includes multiple M1 tracks 210 (three of which are designated 215 in FIG. 2A as unused) connected downward by V0 jumpers 220 and upward by V1 jumpers 225. As shown in FIG. 2B, five M1 tracks are designated 210, and M2 tracks 230 may extend to one or more of the M1 tracks 210. The elongated M2 track 235 can extend across and completely cover the top surface of the V1 jumper 225 (the elongated M2 track 235 is shown as spanning three of the M1 tracks 210). The M1 track 210 can be formed using a subtractive process, while the V0 jumper 220, the V1 jumper 225, and the M2 track 230 (and the elongated M2 track 235) can be deposited using a damascene process.

[0028] 3A-3F, one exemplary embodiment of a process flow used to fabricate VTFET 200 is generally designated 300 and hereafter referred to as "method 300." As shown in FIG. 3A, middle-of-line (MOL) formation allows one or more devices to be placed in device region 310 on substrate 315. Substrate 315 can be silicon, silicon oxide, silicon dioxide, or any other substrate material.

[0029] As shown in FIG. 3B, a trench or recess 320 can be formed in the substrate 315 by etching the substrate 315 using any suitable etching process (e.g., reactive ion etching (RIE)).

[0030] 3C, metallization can be performed in which a damascene process (metal deposition and planarization) is used to overfill recess 320 with metal 330 to form V0 jumper 220. Planarization can be by chemical mechanical polishing (CMP). Metals that can be used for metal deposition include, but are not limited to, ruthenium, tungsten, cobalt, iridium, rhodium, molybdenum, niobium, and alloys and combinations thereof.

[0031] As shown in FIG. 3D, a subtractive process is used to form metallization onto the M1 track 210, thereby forming the M1 track 210 integral with the V0 jumper 220.

[0032] As shown in FIG. 3E, a dielectric layer 335 is deposited over the M1 track 210 and the V0 jumper 220.

[0033] As shown in FIG. 3F, a lithography process is used to etch the dielectric layer 335, thereby forming an opening 340 in the dielectric layer 335 down to the top surface of the M1 track 210. Optionally, a reverse selective barrier (RSB) process can be used to remove the dielectric layer 335 down to the M1 track 210 (allowing for direct metal-to-metal contact). The opening 340 can then be filled with metal to form the V1 jumper 225. The metal used to form the V1 jumper 225 may be the same as or different from the metal used for the V0 jumper 220 and the M1 track 210. A damascene process can be used to perform a second metallization to form the M2 track 230, as shown in FIG. 2A.

[0034] 4A and 4B, an alternative exemplary embodiment of a VTFET with a backside power supply is generally designated 400 and hereafter referred to as "VTFET 400." VTFET 400 is similar to VTFET 200 described above and includes multiple M1 tracks 410 (four of which are shown in FIG. 4A) connected downward by V0 jumpers 420. Two or more of the M1 tracks 410 are connected upward by a first V1 jumper 425, and two or more of the M1 tracks 410 are similarly connected upward by a second V1 jumper 426. The spacing of the M1 tracks 410 may be non-uniform. The length of each of the first V1 jumper 425 and the second V1 jumper 426 may be uniform. An M2 track 430 may extend to one or more of the M1 tracks 410. The elongated M2 track 440 may extend over and completely cover the top surfaces of the first V1 jumper 425 and the second V1 jumper 426, thereby connecting the jumpers 425, 426. As with the previous exemplary embodiment, the M1 track 410 may be deposited using a subtractive process, while the V0 jumper 420, the V1 jumpers 425, 426, and the M2 track 430 (and the elongated M2 track 440) may be deposited using a damascene process.

[0035] 5A and 5B, another alternative exemplary embodiment of a VTFET with backside power supply is generally designated 500 and hereafter referred to as “VTFET 500.” VTFET 500 is similar to VTFET 200 and VTFET 400 and includes multiple M1 tracks 510 (five of which are shown in FIG. 5A as being evenly spaced) connected downward by V0 jumpers 520. Multiple V1 jumpers are incorporated. Specifically, a first V1 jumper 525 having a first length L1 can be used to connect three M1 tracks 510, and a second V1 jumper 526 having a second length L2 can be used to connect two M1 tracks 510. L1 may be different from L2. The spacing of the M1 tracks 510 may be uniform, as shown, or may be uneven. M2 tracks 530 may extend to one or more of the M1 tracks 510. The elongated M2 track 540 may extend over and completely cover the top surfaces of the first V1 jumper 525 and the second V1 jumper 526, thereby connecting the jumpers 525, 526. As with the previous exemplary embodiment, the M1 track 510 may be deposited using a subtractive process, while the V0 jumper 520, the V1 jumpers 525, 526, and the M2 track 530 (and the elongated M2 track 530) may be deposited using a damascene process.

[0036] 6A and 6B, another alternative exemplary embodiment of a VTFET with backside power supply is generally designated 600 and hereafter referred to as "VTFET 600." VTFET 600 is similar to the VTFET described above and includes multiple M1 tracks 610 (five of which are shown in FIG. 6A as being evenly spaced apart) connected downward by V0 jumpers 620. M2 tracks 630 may extend to one or more of the M1 tracks 610. V1 jumpers 625 may be used to connect three M1 tracks 610, and V1 vias 626 may be used to connect the M1 tracks 610 to an extended M2 track 640 that extends over and completely covers the top surface of the V1 jumpers 625. As with previous exemplary embodiments, the M1 track 610 can be deposited using a subtractive process, while the V0 jumper 620, the V1 jumper 625, and the M2 track 630 (and the extended M2 track 640) can be deposited using a damascene process.

[0037] Referring now to FIG. 7, a graph showing parallel resistance (in ohms) as a function of the number of vias and jumpers is shown generally at 700. PP Comparisons are made for configurations where the V0 / M1 / V1 jumpers are 5 nm or 2 nm in size. As can be seen, having multiple V0 / M1 / V1 jumpers in parallel can reduce the VTFET output resistance at increased cell scale. Particularly at the 2 nm size, the output resistance can be reduced from approximately 80 ohms as shown at 710 to approximately 15 ohms as shown at 720.

[0038] Referring to FIG. 8 , one exemplary embodiment of a process flow for forming VTFET 200 is generally designated 800 and hereafter referred to as “method 800.” The initial stage of method 800 is metal-on-metal (MOL) formation in the device region of a substrate, as indicated in block 810. The substrate is etched in block 815 to form recesses or trenches for subsequent metal deposition. In block 820, a damascene process is used to deposit a first metal into the recess or trench and protrude above the recess or trench to form V0 jumper 220. Patterning is performed as needed. As indicated in block 825, a subtractive process is used to form an M1 track over the V0 jumper. In block 830, a dielectric layer is deposited over and covering the formed M1 track and V0 jumper. Again, patterning is performed as needed. In block 835, the dielectric layer is etched to form an opening down to the top surface of the M1 track. The opening to the M1 track is metallized using a damascene process to deposit a second metal to form a V1 jumper over the M1 track, as shown in block 840. A damascene process is used to deposit a third metal onto the V1 jumper to form the M2 track, as shown in block 845.

[0039] In one aspect, a semiconductor device comprises: a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks above the first via level; a second via level forming a first top jumper above the first set of two or more first metallization tracks; and a second metallization track above the second via level.

[0040] The length of the first via level may not be equal to the length of the second via level. The first set of two or more first metallization tracks may have three or more metallization tracks, and the spacing between three or more of the three or more first metallization tracks may be uneven. The first set of two or more first metallization tracks may be formed by a subtractive process. The first via level, the second via level, and the second metallization tracks may be formed by a damascene process. The second via level may form a second top jumper above the second set of first metallization tracks. The length of the second top jumper may be different from the length of the first top jumper. The second top jumper may be above one metallization track of the second set of first metallization tracks.

[0041] In another aspect, a vertical transport field effect transistor comprises: a bottom jumper formed in a substrate; a first M1 track and a second M1 track each above the bottom jumper; a first top jumper above the first M1 track and the second M1 track; and a first M2 track above the first top jumper.

[0042] The vertical transport field effect transistor may further include a third M1 track above the bottom jumper, and the spacing between the first M1 track, the second M1 track, and the third M1 track may be non-uniform. The vertical transport field effect transistor may further include a second top jumper above at least the third M1 track, and the first M2 track extends to and is above the second top jumper. The lengths of the first top jumper and the second top jumper may be non-uniform.

[0043] In another aspect, a method includes: providing a substrate; forming a recess in the substrate; depositing a first metal in the recess and on a top surface of the substrate such that the deposited first metal protrudes from the recess; patterning the deposited first metal; subtractively etching the first metal down to the top surface of the substrate to form a first jumper in the recess and a first set of two or more first metallization tracks above the first jumper; and depositing a dielectric material overlying the subtractively etched first metal. The method includes the steps of: forming a first set of two or more first metallization tracks; patterning the dielectric material; forming openings in the dielectric material down to a top surface of the first set of two or more first metallization tracks; depositing a second metal in the openings in the dielectric material to form a second jumper in the openings spanning at least two of the two or more first metallization tracks; patterning the deposited second metal; and depositing a third metal over the deposited and patterned second metal to form a set of two or more second metallization tracks, at least one of the two or more second metallization tracks extending the length of the second jumper.

[0044] The method may further include forming a device region on the substrate. Forming the openings in the dielectric material down to the top surface of the first set of two or more first metallization tracks may include using a reverse selective barrier process. Depositing the first metal in the recesses on the top surface of the substrate may include using a first damascene process. Forming the second jumper in the openings by depositing the second metal in the openings of the dielectric material may include using a second damascene process. Forming the set of two or more second metallization tracks by depositing the third metal onto the patterned deposited second metal may include using a third damascene process.

[0045] In the foregoing description, numerous specific details have been set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, to provide a thorough understanding of the exemplary embodiments disclosed herein. However, it will be understood by those skilled in the art that the exemplary embodiments disclosed herein may be practiced without these specific details. Additionally, details of well-known structures or processing steps may be omitted or not described to avoid obscuring the presented embodiments. When an element, such as a layer, region, or substrate, is referred to as being "on" or "over" another element, it will be understood that it may be directly on the other element, or that intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. When an element is referred to as being "beneath" or "under" another element, it will be understood that the element can be directly below or directly underneath the other element, or that intervening elements may be present. In contrast, when an element is referred to as being "directly beneath" or "directly under" another element, there are no intervening elements present.

[0046] The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the precise form disclosed. Many modifications and variations will become apparent to those skilled in the art that do not depart from the scope of the invention. The embodiments have been chosen and described to best explain the principles of the invention and its practical application and to enable others skilled in the art to understand the invention in various embodiments with various modifications suited to the particular uses contemplated.

Claims

1. a first via level forming a bottom jumper configured to provide an output; a first set of two or more first metallization tracks above the first via level; a second via level forming a first top jumper above the first set of two or more first metallization tracks; and a second metallization track above the second via level; A semiconductor device comprising:

2. The semiconductor device of claim 1 , wherein a length of the first via level is not equal to a length of the second via level.

3. 2. The semiconductor device of claim 1, wherein the first set of two or more first metallization tracks comprises three or more metallization tracks, and wherein the spacing between three or more of the three or more first metallization tracks is non-uniform.

4. 10. The semiconductor device of claim 1, wherein the first set of two or more first metallization tracks is formed by a subtractive process.

5. The semiconductor of claim 1 , wherein the first via level, the second via level, and the second metallization track are formed by a damascene process.

6. The semiconductor of claim 1 , wherein the second via level forms a second top jumper above a second set of first metallization tracks.

7. The semiconductor of claim 6 , wherein the length of the second top jumper is different from the length of the first top jumper.

8. The semiconductor of claim 7 , wherein the second top jumper is above one metallization track of the second set of first metallization tracks.

9. a bottom jumper formed in the substrate; a first M1 track and a second M1 track each above the bottom jumper; a first top jumper above the first M1 track and the second M1 track; and a first M2 track above the first top jumper; A vertical transport field effect transistor comprising:

10. 10. The vertical transport field effect transistor of claim 9, further comprising a third M1 track above the bottom jumper, wherein the spacing between the first M1 track, the second M1 track, and the third M1 track is non-uniform.

11. 10. The vertical transport field effect transistor of claim 9, further comprising a second top jumper above at least a third M1 track, the first M2 track extending up to and above the second top jumper.

12. 12. The vertical transport field effect transistor of claim 11, wherein the first top jumper and the second top jumper have non-uniform lengths.

13. providing a substrate; forming a recess in the substrate; depositing a first metal in the recess and on an upper surface of the substrate, such that the deposited first metal protrudes from the recess; patterning the deposited first metal; subtractively etching the first metal down to the top surface of the substrate to form a first jumper in the recess and a first set of two or more first metallization tracks above the first jumper; depositing a dielectric material overlying the subtractively etched first metal; patterning the dielectric material; forming openings in the dielectric material down to a top surface of the first set of two or more first metallization tracks; depositing a second metal within the opening in the dielectric material to form a second jumper within the opening spanning at least two of the two or more first metallization tracks; patterning the deposited second metal; and forming a set of two or more second metallization tracks by depositing a third metal onto the deposited and patterned second metal; Provided with: At least one of the two or more second metallization tracks extends the length of the second jumper. method.

14. The method of claim 13 further comprising forming a device region on the substrate.

15. 14. The method of claim 13, wherein forming the openings in the dielectric material down to a top surface of the first set of two or more first metallization tracks comprises using a reverse selective barrier process.

16. 14. The method of claim 13, wherein depositing the first metal in the recess and over the top surface of the substrate comprises using a first damascene process.

17. 14. The method of claim 13, wherein forming the second jumper in the opening by depositing the second metal in the opening of the dielectric material comprises using a second damascene process.

18. 14. The method of claim 13, wherein forming the set of two or more second metallization tracks by depositing the third metal onto the patterned deposited second metal comprises using a third damascene process.

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