Transistor amplifier with PCB routing and surface mounted transistor die

Abstract

The transistor amplifier package includes a package substrate having a conductive pattern exposed at a surface of the package substrate by a solder mask pattern, and at least one transistor die having a semiconductor structure attached to the surface of the package substrate by a solder material and aligned by the solder mask pattern, whereby respective gate, drain, and / or source terminals of the at least one transistor die are electrically connected to respective conductive patterns of the conductive patterns. Related transistor amplifiers and fabrication methods are also discussed.

Description

[Technical Field]

[0001] Priority claims

[0001] This application claims priority to U.S. patent application Ser. No. 17 / 934,698, filed Sep. 23, 2022, the disclosure of which is incorporated by reference.

[0002]

[0002] The present disclosure relates generally to transistor devices, and more particularly to radio frequency ("RF") power amplifier devices. [Background technology]

[0003]

[0003] Electrical circuits requiring high power handling capabilities while operating at high frequencies, such as UHF (0.3-1 GHz), L-band (1-2 GHz), R-band (1.7-2.6 GHz), S-band (2-4 GHz), and X-band (8-12 GHz), have become more prevalent in recent years. In particular, there may be high demands for RF power amplifiers used to amplify RF signals at radio (including microwave) frequencies. These RF power amplifiers may be required to exhibit high reliability, good linearity, and handle high output power levels.

[0004]

[0004] RF power amplifiers may be implemented with silicon or using wide-bandgap semiconductor materials (i.e., having a bandgap greater than 1.40 eV), such as silicon carbide ("SiC") and Group III nitride materials. As used herein, the term "Group III nitride" refers to semiconductor compounds formed between nitrogen and elements from Group III of the periodic table, usually aluminum (Al), gallium (Ga), and / or indium (In). Group III elements can combine with nitrogen to form binary (e.g., GaN), ternary (e.g., AlGaN, AlInN), and quaternary (e.g., AlInGaN) compounds. These compounds have empirical formulas in which one mole of nitrogen is combined with one mole of the Group III element.

[0005]

[0005] Silicon-based RF power amplifiers are typically implemented using laterally diffused metal oxide semiconductor ("LDMOS") transistors. Silicon LDMOS RF power amplifiers can exhibit high levels of linearity and can be relatively inexpensive to fabricate. III-nitride-based RF power amplifiers are typically implemented using high electron mobility transistors ("HEMTs") and are primarily used in applications requiring high power and / or high frequency operation where LDMOS RF power amplifiers may have inherent performance limitations.

[0006]

[0006] An RF power amplifier may include one or more amplification stages, with each stage typically implemented as a transistor amplifier. To increase output power and current handling capabilities, RF power amplifiers are typically implemented in a "unit cell" configuration, in which multiple individual "unit cell" transistor structures are arranged electrically in parallel. An RF power amplifier may be implemented as a single integrated circuit chip or "die," or may include multiple dies. A die or chip may refer to a small block of semiconductor material or other substrate on which electronic circuit elements are fabricated. When multiple RF transistor dies are used, the multiple RF transistor dies may be connected in series and / or in parallel.

[0007]

[0007] RF power amplifiers often include matching circuits, such as (i) impedance matching circuits designed to improve the impedance match between active transistor dies (e.g., including MOSFETs, HEMTs, LDMOSs, etc.) and transmission lines connected to the active transistor dies for RF signals at the fundamental operating frequency, and (ii) harmonic termination circuits designed to at least partially terminate harmonics, such as second and third harmonics, that may be generated during device operation. Harmonic termination also affects the generation of intermodulation distortion products.

[0008] The RF transistor die(s) and impedance matching and / or harmonic termination circuitry may be enclosed within an integrated circuit device package. Integrated circuit packaging may refer to sealing one or more dies within a support case or package that protects the die from physical damage and / or corrosion and supports electrical contacts for connection to external circuitry. The input and output impedance matching circuits within the integrated circuit device package typically include inductor-capacitor (LC) networks that provide at least a portion of the impedance matching circuit configured to match the impedance of the active transistor die to a fixed value. The package typically includes a conductive attachment surface or “flange” on which the die is mounted, and an electrically insulating protective material, such as plastic or ceramic, that seals and protects the die from moisture and dust particles. Conductive leads (also referred to herein as package leads or RF leads) may extend from the package and are used to electrically connect the RF transistor amplifier to external circuit elements, such as input and output RF transmission lines and bias voltage sources.

[0009] As mentioned above, III-nitride-based RF power amplifiers are often used in high-power and / or high-frequency applications. Typically, high levels of heat are generated within the III-nitride-based RF transistor die(s) during operation. If the RF transistor die(s) become too hot, the performance (e.g., output power, efficiency, linearity, gain, etc.) of the RF transistor amplifier may be degraded, and / or the RF transistor die(s) may be damaged. Therefore, III-nitride-based RF power amplifiers are typically mounted in packages that may be optimized for heat removal.

[0010] In some package designs, the package flange includes a thermally conductive substrate, also referred to as a "heat slug" or "heat sink." The package-level heat slug is designed to transfer heat away from the integrated circuit toward an external heat sink. Typically, the heat slug is formed from a thermally conductive material (e.g., metal). In some package configurations, the heat slug also serves as an electrical terminal that provides a reference potential (e.g., ground) for a die mounted on the heat slug. For example, the flange may be a CPC (copper, copper-molybdenum, copper laminate structure) or copper flange that provides both an attachment surface for the die and the heat slug.

[0011]

[0011] One semiconductor package design is a molded design (or "overmold" package) in which a plastic or other non-conductive encapsulating material is molded directly over a heat slug (e.g., by injection molding or transfer molding) to form a solid structure that directly contacts and encapsulates the RF transistor die and / or other integrated circuits and associated electrical connections as well as at least a portion of the heat slug.

[0012] Another semiconductor package design is the "open-air cavity" or "open cavity" package, in which a (typically ceramic) lid is placed and attached over a metal heat slug. The ceramic lid seals the open-air cavity containing the RF transistor die and / or other integrated circuits and associated electrical connections.

[0013] 1A is a schematic side view of a conventional open-cavity RF power amplifier package 170 (illustratively shown as a thermally enhanced package) including a transistor die 110 and matching circuitry (illustratively shown as chip capacitors 190, 192) mounted on a conductive attachment surface or flange provided by a package submount 176. The open-cavity package 170 includes a lid member 179 (e.g., a ceramic lid such as alumina) and a sidewall member (e.g., a printed circuit board (PCB) 177) on the submount 176. The lid 179 and sidewalls of the PCB 177 seal an open-air cavity containing the transistor die 110 and / or other integrated circuits and associated electrical connections 125, also referred to herein as the package's component. In the example of FIG. 1A, the PCB 177 provides a "window frame" 175 around the component and supports conductive layers or traces 173 (e.g., copper cladding) that provide input and output leads 172 and 174.

[0014] 1B is a simplified side view of the package 170 of FIG. 1A mounted on an RF circuit board 180. Input and output leads 172 and 174 connect the package 170 to respective conductive layers or traces 183 (e.g., copper cladding) on ​​a structure 187 (e.g., a PCB layer) of the connecting RF circuit board 180, providing RF signal connections to / from the die 110 via matching circuits 190 and 192. The RF circuit board 180 includes an opening 181 sized to receive a flange 176, whereby a lower surface of the flange 176 may contact a heat sink 186, which may be, or may be part of, a layer supporting the RF circuit board 180. Summary of the Invention [Means for solving the problem]

[0015]

[0015] According to some embodiments, a transistor amplifier includes a package substrate having conductive patterns exposed by a solder mask pattern on the surface of the package substrate, and at least one transistor die including a semiconductor structure having respective gate, drain, and / or source terminals attached to and electrically connected by a solder material to each of the conductive patterns exposed by the solder mask pattern on the surface of the package substrate.

[0016]

[0016] According to some embodiments, a transistor amplifier package includes a package substrate having a conductive pattern exposed on a surface of the package substrate by a solder mask pattern, and at least one transistor die including a semiconductor structure attached to the surface of the package substrate by a solder material and aligned by the solder mask pattern, whereby each gate, drain, and / or source terminal of the at least one transistor die is electrically connected to each of the conductive patterns of the conductive pattern.

[0017]

[0017] In some embodiments, at least one transistor die includes a patterned back metal layer on the lower surface of the semiconductor structure, the patterned back metal layer including respective gate, drain, and / or source terminals, and a barrier metal layer between the patterned back metal layer and the solder material on the surface of the substrate.

[0018] In some embodiments, the barrier metal layer comprises at least one of nickel, titanium, and / or alloys thereof.

[0019] In some embodiments, at least one transistor die includes a plurality of conductive pillars on the top surface of the semiconductor structure adjacent to the transistor active area and electrically coupled to respective gate, drain, and / or source terminals, and a solder material is between the conductive pillars and the surface of the substrate.

[0019]

[0020] In some embodiments, one or more discrete passive electrical components are attached to the surface of the package substrate by a solder material and aligned by a solder mask pattern.

[0020]

[0021] In some embodiments, the one or more discrete passive electrical components and / or the at least one transistor die are spaced apart from one another by respective gaps of less than about 0.25 mm or between about 0.25 mm and about 0.1 mm.

[0021]

[0022] In some embodiments, respective terminals of the one or more discrete passive electrical components are electrically connected to respective gate, drain, and / or source terminals of the at least one transistor die by respective conductive patterns of the conductive patterns.

[0022]

[0023] In some embodiments, at least one of the respective gate, drain, and / or source terminals is on the top surface of the semiconductor structure adjacent the transistor active area, and at least one wire bond electrically connects at least one of the respective gate, drain, and / or source terminals on the top surface to a respective terminal of one or more discrete passive electrical components.

[0023]

[0024] In some embodiments, one or more discrete passive electrical components define a portion of an input, interstage, or output impedance matching circuit or harmonic termination circuit.

[0024]

[0025] In some embodiments, the conductive pattern provides respective leads for RF signal connections that are substantially coplanar with a surface of a package substrate having at least one transistor die attached to the package substrate.

[0025]

[0026] In some embodiments, the package substrate comprises an electrically insulating member, and each lead has no electrical connection extending substantially beyond the edge of the electrically insulating member.

[0027] In some embodiments, the conductive pattern comprises an embedded conductive member extending through the electrically insulating member, and a source terminal of the at least one transistor die is attached to the embedded conductive member by a solder material at the surface of the package substrate.

[0026]

[0028] In some embodiments, the package is free of a thermally conductive package submount.

[0029] In some embodiments, the thermally conductive package submount has a package substrate on the thermally conductive package submount, and each lead does not extend substantially beyond the edge of the thermally conductive package submount.

[0027]

[0030] In some embodiments, the environmental protection layer extends conformally over one or more surfaces of the at least one transistor die.

[0031] In some embodiments, the transistor amplifier package is free of an overmold or lid member over the at least one transistor die.

[0028]

[0032] In some embodiments, the transistor amplifier package is wirebond-free.

[0033] According to some embodiments, a transistor amplifier includes: a substrate comprising a conductive pattern on a surface of the substrate; at least one transistor die comprising a semiconductor structure and a patterned backside metal layer on a lower surface of the semiconductor structure, the patterned backside metal layer being attached to the surface of the substrate by a solder material, whereby respective gate, drain, and / or source terminals of the at least one transistor die are electrically connected to respective conductive patterns of the conductive pattern; and a barrier metal layer between the patterned backside metal layer and the solder material.

[0029]

[0034] In some embodiments, the barrier metal layer comprises at least one of nickel, titanium, and / or alloys thereof.

[0035] In some embodiments, the bottom surface is silicon carbide and the backside metal layer comprises gold.

[0030]

[0036] In some embodiments, the conductive pattern is exposed by a solder mask pattern at the surface of the substrate, and the at least one transistor die is aligned by the solder mask pattern.

[0031]

[0037] In some embodiments, the conductive pattern provides respective leads for RF signal connections that are substantially coplanar with a surface of the substrate, the substrate having at least one transistor die attached to the substrate.

[0032]

[0038] In some embodiments, the substrate comprises an electrically insulating member, the conductive pattern includes an embedded conductive member extending through the electrically insulating member, and a source terminal of the at least one transistor die is attached to the embedded conductive member by a solder material at a surface of the substrate.

[0033]

[0039] In some embodiments, the substrate is an RF circuit board, and the RF circuit board is mounted on a conductive heat sink member that is electrically connected to an embedded conductive member opposite the at least one transistor die.

[0034]

[0040] In some embodiments, the substrate is a package substrate of an RF transistor amplifier package, and the leads do not extend beyond the edge of the electrical insulation member.

[0041] In some embodiments, the transistor amplifier further includes an RF circuit board having an opening thereon, and the RF transistor amplifier package is mounted within the opening in the RF circuit board, thereby enclosing the package substrate within the opening.

[0035]

[0042] In some embodiments, one or more conductive surface mount components extend beyond the edge of the electrically insulating member and electrically connect their respective leads to conductive traces on the surface of the RF circuit board outside the opening.

[0036]

[0043] In some embodiments, the surface of the package substrate is substantially coplanar with the surface of the RF circuit board outside the opening.

[0044] In some embodiments, the RF circuit board is mounted on a conductive heat sink member that is exposed by an opening in the RF circuit board.

[0037]

[0045] In some embodiments, the conductive heat sink member includes a substantially planar surface, and the package substrate is mounted on the conductive heat sink member without a thermally conductive package submount between the package substrate and the conductive heat sink member.

[0038]

[0046] In some embodiments, the RF transistor amplifier package includes a thermally conductive package submount having a package substrate on the thermally conductive package submount, and the conductive heat sink member includes a recess in the conductive heat sink member sized to receive the thermally conductive package submount.

[0039]

[0047] In some embodiments, the RF circuit board includes fewer or more conductive layers than one or more conductive layers of the package substrate.

[0048] In some embodiments, one or more discrete passive electrical components are attached to the surface of the substrate by a solder material and aligned by a solder mask pattern.

[0040]

[0049] In some embodiments, the one or more discrete passive electrical components and / or the at least one transistor die are spaced apart from one another by respective gaps of less than about 0.25 mm or between about 0.25 mm and about 0.1 mm.

[0041]

[0050] According to some embodiments, a transistor amplifier includes a substrate having a conductive pattern exposed at a surface of the substrate by a solder mask pattern and providing respective leads for signal connections, at least one transistor die comprising a semiconductor structure attached to the surface of the substrate by a solder material, and one or more discrete passive electrical components attached to the surface of the substrate by the solder material, wherein the one or more discrete passive electrical components and / or the at least one transistor die are spaced from one another on the surface of the substrate by respective gaps of less than about 0.25 mm.

[0042]

[0051] In some embodiments, each gap is between about 0.25 mm and about 0.1 mm, or between about 0.1 mm and about 0.05 mm.

[0052] In some embodiments, one or more discrete passive electrical components define a portion of an input, interstage, or output impedance matching circuit or harmonic termination circuit.

[0043]

[0053] In some embodiments, the conductive pattern provides respective leads for RF signal connections that are substantially coplanar with a surface of the substrate, the substrate having at least one transistor die attached to the substrate.

[0044]

[0054] In some embodiments, the substrate comprises an electrically insulating member, the conductive pattern comprises an embedded conductive member extending through the electrically insulating member, and a terminal of the at least one transistor die is attached to the embedded conductive member by a solder material at a surface of the substrate.

[0045]

[0055] In some embodiments, the substrate is a package substrate of an RF transistor amplifier package, and each lead does not extend beyond the edge of the electrical insulation member.

[0056] In some embodiments, the transistor amplifier includes an RF circuit board having an opening therein, and the RF transistor amplifier package is mounted within the opening in the RF circuit board, thereby enclosing the package substrate within the opening.

[0046]

[0057] In some embodiments, one or more conductive surface mount components extend beyond the edge of the electrically insulating member and electrically connect their respective leads to conductive traces on the surface of the RF circuit board outside the opening.

[0047]

[0058] According to some embodiments, a method of fabricating a transistor amplifier package includes providing a plurality of package substrates, each package substrate having a conductive pattern exposed by a solder mask pattern on a surface of a respective one of the plurality of package substrates; applying solder material to the surface of each of the package substrates using a stencil on the package substrates; providing at least one transistor die having a semiconductor structure on the surface of each of the package substrates; and performing a solder reflow process to attach and align the at least one transistor die on the surface of each of the package substrates, whereby a gate, drain, and / or source terminal of each of the at least one transistor die is electrically connected to the conductive pattern of the respective one of the conductive patterns.

[0048]

[0059] In some embodiments, at least one transistor die includes a patterned backside metal layer providing respective gate, drain, and / or source terminals on a lower surface of the semiconductor structure, and a barrier metal layer on the patterned backside metal layer. At least one transistor die is provided on each surface of the package substrate, whereby the barrier metal layer is between the patterned backside metal layer and the solder material.

[0049]

[0060] In some embodiments, the barrier metal layer comprises at least one of nickel, titanium, and / or alloys thereof.

[0061] In some embodiments, the at least one transistor die includes a plurality of conductive pillars on a top surface of the semiconductor structure adjacent to the transistor active area and electrically coupled to respective gate, drain, and / or source terminals, and the at least one transistor die is disposed such that a solder material is between the conductive pillars and respective surfaces of the package substrate.

[0050]

[0062] In some embodiments, prior to performing the solder reflow process, the method includes providing one or more discrete passive electrical components on each surface of the package substrate, the solder reflow process attaching and aligning the one or more discrete passive electrical components on each surface.

[0051]

[0063] In some embodiments, in response to performing a solder reflow process, the one or more discrete passive electrical components and / or the at least one transistor die are spaced apart from one another on the respective package substrates by respective gaps of less than about 0.25 mm or between about 0.25 mm and about 0.1 mm.

[0052]

[0064] In some embodiments, the package substrates are connected within a panel, and after performing a solder reflow process, the method includes singulating the panel to define RF transistor amplifier packages each comprising a package substrate.

[0053]

[0065] In some embodiments, the conductive pattern provides respective leads for RF signal connections that are substantially coplanar with respective surfaces of the package substrate.

[0066] In some embodiments, each package substrate comprises an electrical insulating member, and after the panel is singulated, each lead has no electrical connections extending substantially beyond the edges of the electrical insulating member.

[0054]

[0067] In some embodiments, the method includes forming an environmental protection layer that conformally extends over one or more surfaces of the at least one transistor die.

[0068] In some embodiments, at least one transistor die may be a gallium nitride-based high electron mobility transistor (HEMT).

[0055]

[0069] In some embodiments, at least one transistor die may be a silicon-based laterally diffused metal oxide semiconductor (LDMOS).

[0056]

[0070] In some embodiments, at least one transistor die may be a radio frequency (“RF”) transistor die.

[0071] In some embodiments, at least one transistor die may be configured to operate in at least a portion of one or more of the 2.5-2.7 GHz, 3.4-4.2 GHz, or 5.1-5.8 GHz frequency bands.

[0057]

[0072] In some embodiments, at least one transistor die may be configured to operate at frequencies greater than 10 GHz.

[0073] Other devices, apparatus, and / or methods according to some embodiments will become apparent to one of ordinary skill in the art upon review of the following figures and detailed description, and all such additional embodiments, in addition to any and all combinations of the above embodiments, are intended to be included within this description, be within the scope of the present invention, and be protected by the accompanying claims. [Brief explanation of the drawings]

[0058] [Figure 1A]

[0074] 1 is a simplified side view of a conventional open cavity transistor amplifier package. [Figure 1B]

[0075] 1 is a simplified side view of a conventional open cavity transistor amplifier package mounted on an RF circuit board. [Figure 2A]

[0076] FIG. 1 is a plan view of an RF transistor die according to various embodiments of the present disclosure. [Figure 2B]

[0077] 2B is a simplified cross-sectional view of a transistor die unit cell according to various embodiments of the present disclosure, the cross-section being taken along line BB' of FIG. 2A. [Figure 3A]

[0078] 1 is a simplified side view of a transistor amplifier package including surface-mounted active and passive components according to various embodiments of the present disclosure. [Figure 3B]

[0079] 3B is a simplified side view of the transistor amplifier package of FIG. 3A mounted on an RF circuit board with conductive shims used for package board connections according to various embodiments of the present disclosure. FIG. [Figure 4A]

[0080] 1 is a simplified side view of a transistor amplifier package including surface-mounted active and passive components according to various embodiments of the present disclosure. [Figure 4B]

[0081] 4B is a simplified side view of the transistor amplifier package of FIG. 4A mounted on an RF circuit board with conductive shims used for package board connections according to various embodiments of the present disclosure. FIG. [Figure 5A]

[0082] 1 is a simplified side view of active and passive components of a transistor amplifier according to various embodiments of the present disclosure. [Figure 5B]

[0083] FIG. 5B is a simplified side view of the transistor amplifier and passive components of FIG. 5A mounted on an external RF circuit board according to various embodiments of the present disclosure. [Figure 6A]

[0084] 1A-1C are simplified side views of a backside mountable RF transistor die, respectively, according to various embodiments of the present disclosure. [Figure 6B]

[0085] FIG. 6B is a plan view of the RF transistor die of FIG. 6A mounted on a PCB. [Figure 6C]

[0086] 1 is a simplified side view of a flip-chip mountable RF transistor die according to various embodiments of the present disclosure. [Figure 7]

[0087] 1 is a simplified side view of a transistor amplifier package including wire bonds between active and passive components according to various embodiments of the present disclosure. [Figure 8]

[0088] 1 is a simplified diagram illustrating a method of making a transistor amplifier package according to various embodiments of the present disclosure. [Figure 9] 1 is a simplified diagram illustrating a method of making a transistor amplifier package according to various embodiments of the present disclosure. [Figure 10] 1 is a simplified diagram illustrating a method of making a transistor amplifier package according to various embodiments of the present disclosure. [Figure 11]

[0089] FIG. 1 is a simplified perspective view showing a package board connection between a transistor amplifier package and an RF circuit board. [Figure 12]

[0090] 12 is an enlarged schematic perspective view showing the package board connection portion of FIG. 11. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0059]

[0091] FIG. 2A is a simplified cross-sectional view of a transistor die 210 according to various embodiments of the present disclosure, the cross-section being taken through a portion of the upper metallization structure of the transistor die 210, for example, along line III-III′ in FIG. 3A . Dielectric layers insulating various conductive elements of the upper metallization structure from one another are not shown in FIG. 2A to simplify the drawing. FIG. 2B is a simplified cross-sectional view of a transistor die unit cell according to various embodiments of the present disclosure, the cross-section being taken along line B-B′ in FIG. 2A . While embodiments will hereinafter be described with reference to examples including an RF transistor die and an RF transistor amplifier package, it will be understood that embodiments of the present invention are not limited to RF devices.

[0060]

[0092] 2A-2B, RF transistor die 210 is illustrated by way of example as a III-nitride-based HEMT RF transistor amplifier having a plurality of unit cell transistors 116, each including a gate finger 152, a drain finger 154, and a source finger 156. However, it will be appreciated that RF transistor die 210 may be implemented in a different technology, such as, for example, a silicon LDMOS RF transistor amplifier. Gate fingers 152 are electrically connected to a common gate bus 146, and drain fingers 154 are electrically connected to a common drain bus 148. The gate bus 146 is electrically connected to a gate terminal (e.g., through a conductive via 162 extending from the gate bus 146), which may be implemented as an input contact pad 362 (see FIG. 6A) or a conductive pillar 222 (see FIG. 6C), and the drain bus 148 is electrically connected to a drain terminal (e.g., through a conductive via 164 extending from the drain bus 148), which may be implemented as an output contact pad 364 (see FIG. 6A) or a conductive pillar 224 (see FIG. 6C). The source finger 156 is electrically connected to a source terminal 126 (e.g., through a conductive via 166), which may be implemented as a ground contact pad 366 (see FIG. 6A) or a conductive pillar 226 (see FIG. 6C). The conductive vias 162, 164, 166 may be metal-plated vias extending through the semiconductor structure 130.

[0061]

[0093] In some embodiments, the patterned backside metal layer 126 may provide one or more of the input 362, output 364, and ground 366 terminals (see FIG. 6A) on the bottom surface of the transistor die 210. In other embodiments, one or more conductive pillar structures may provide the input 222, output 224, and ground 226 terminals (see FIG. 6C) that protrude from the top surface of the transistor die 210.

[0062]

[0094] 2A-2B (and various views of other figures) are highly simplified diagrams, and that an actual RF transistor die may include many more unit cells and various circuit portions and elements not shown in the simplified views herein. More generally, the views herein are intended to show structures for identification and explanation, and are not intended to show structures to physical scale.

[0063]

[0095] Some embodiments of the present disclosure address difficulties that may be presented by existing RF power device package configurations, such as mechanical issues related to mounting the package to an RF circuit board and / or inter-component spacing. For example, manufacturing a flange 176 and / or package PCB 177 with varying thicknesses may lead to mechanical issues, including misalignment between the upper cladding 183 of the RF circuit board 180 and the contact leads 172, 174 of the package 170. Therefore, it may be difficult to achieve simultaneous contact between the bottom of the flange 176 and the heat sink 186 at the bottom of the opening 181 in the RF circuit board 180, and between the upper cladding 183 of the RF circuit board 180 and the package input / output leads 172 / 174. Similarly, component attachment using some conventional epoxy-based attachment techniques may require relatively large inter-component spacing to prevent undesired electrical contact between components, which may impose limitations on package size and / or wire bond length.

[0064]

[0096] Embodiments of the present disclosure provide a packaged RF power device (also referred to herein as an RF transistor amplifier package) that includes a transistor die and / or discrete passive components that are attached to a substrate by a solder material or paste, e.g., using a solder mask / solder / solder reflow method, instead of epoxy or solder bump-based attachment. In contrast, components in conventional RF transistor amplifier packages may typically be attached to a metal flange using epoxy, silver (Ag) sinter, pre-attached gold-tin (AuSn) backside metal, etc.

[0065]

[0097] The transistor die may include a wide bandgap semiconductor-based structure (e.g., GaN and / or SiC), e.g., a GaN HEMT, or a silicon-based semiconductor structure, e.g., a silicon-based LDMOS transistor. The discrete passive components (e.g., capacitors, spiral inductors, transmission lines, etc.) may include integrated passive devices (IPDs) and / or surface mount devices (SMDs), e.g., wide bandgap semiconductor-based components (e.g., SiC components on a SiC substrate) or other components including a semiconductor body with respective conductive terminals configured for surface mount attachment.

[0066]

[0098] The substrate to which the transistor die(s) are attached may be a structure (such as a PCB) including one or more electrically insulating members having a conductive layer defining patterns, traces, routing, and / or leads thereon that are exposed by a patterned solder mask on the surface of the substrate. The substrate may be included in the RF transistor amplifier package (also referred to herein as the package substrate) or may be external to the RF transistor amplifier package (e.g., a customer PCB). The transistor die are electrically connected to the conductive patterns of the substrate by a solder material and aligned by the patterned solder mask. The conductive top cladding or other conductive layer of the package substrate may define respective conductive leads (e.g., input and output leads) configured to provide RF signal connections to the transistor die, also referred to herein as RF leads, that extend along (and, in some embodiments, are coplanar with) the same surface to which the transistor die(s) are attached. The conductive leads are free of electrical connections that extend substantially beyond the edges of the package substrate (its electrically insulating layer).

[0067]

[0099] In some embodiments, the transistor die and / or passive components may have patterned underside metallization (also referred to as a patterned backside metal layer). For example, in a transistor die, gate, source, and / or drain terminals may be routed to the bottom surface of the transistor die by conductive vias. The backside gate and drain terminals may be insulated or separated from the source / ground terminals by isolation gaps in the backside metal layer. In other embodiments, the transistor die may include conductive pillar connections (also referred to herein as conductive pillars) protruding from the top surface of the transistor die (adjacent the transistor active area), which may be connected to the gate, source, and / or drain terminals.

[0068]

[0100] Transistor die and / or passive component attachment using solder / solder mask / solder reflow methods according to embodiments of the present disclosure may provide smaller inter-component spacing with higher placement accuracy with less variability compared to some conventional attachment methods (e.g., epoxy-based (or other dispensed attachment materials)) that may require large dispensing nozzles (and therefore larger dispensing areas and larger components and separation gaps between them). Solder material can be applied using screen printing and stencil methods onto large panels containing multiple package substrates (e.g., PCB arrays), and several wide bandgap semiconductor components may be placed and reflowed simultaneously. That is, multiple components may be attached in parallel (i.e., "in batch") rather than having to sequentially dispense epoxy for each component attachment, thereby reducing assembly time and costs.

[0069]

[0101] The self-aligning nature of the solder reflow method, when combined with a properly designed solder mask pattern on the substrate, can enable more accurate die-attach placement and tighter placement tolerances. That is, as the solder material reflows, the attached components can self-align, correcting for rotations, twists, and the like, and re-center themselves on the boundary defined by the solder mask pattern or the conductive pattern / metallization exposed by the solder mask pattern. Furthermore, smaller components can be attached more precisely (compared to epoxy), and the separation between components can have smaller requirements (e.g., less than about 0.25 mm (10 mils) or between about 0.25 mm and about 0.1 mm (4 mils) or even less than about 0.1 mm, e.g., between about 0.1 mm and about 0.05 mm). In contrast, component spacing for epoxy attachment may typically be greater than about 0.25 mm (10 mils) to ensure adjacent components are sufficiently spaced to avoid shorting.

[0070]

[0102] Furthermore, the lower temperature profile of solder reflow (approximately 260°C or less) may be gentle on the package components, improving the reliability, ruggedness, and assembly costs of the attachment compared to epoxy attachment (which may require curing temperatures of up to 400°C). Furthermore, the input, output, and ground terminals may be provided on the same side of the semiconductor die (compared to epoxy attachment, which typically requires sufficient terminal spacing to avoid shorting between terminals due to the epoxy). Therefore, parasitic inductance and losses due to interconnecting or stitching wire bonds may be eliminated because multiple transistor leads may be directly connected to the substrate (no wire bonds), with routing layers and / or passive components on the substrate providing pre-matching and / or filtering circuitry.

[0071]

[0103] The packaged RF power device may be disposed within an external RF circuit board (e.g., a customer PCB). For example, the package input / output leads may be confined to the edges of the package substrate or may not extend substantially beyond the edges of the package substrate, and the RF transistor amplifier package may be sized or otherwise configured so that the package substrate may be disposed within an opening in the RF circuit board. In some embodiments, the top surface of the package substrate (e.g., the conductive top cladding layer) may be substantially coplanar or “flush” with the surface of the RF circuit board (e.g., the conductive top cladding layer) outside the opening. That is, each lead of the RF transistor amplifier package may be substantially coplanar with (i) the surface of the package to which the transistor die(s) are attached and / or (ii) the conductive traces / routing on the surface of the external RF circuit board. Accordingly, electrically conductive (e.g., copper) shims and / or SMD / IPDs may be used to bridge the gap from the RF transistor amplifier package to the RF circuit board and provide electrical connection therebetween.

[0072]

[0104] In some embodiments, transistor dies (with patterned backside metal layers or surface conductive pillar structures) and / or other discrete passive surface-mountable components (e.g., SMDs and / or IPDs that may provide matching and / or harmonic termination circuits) may be solder attached directly to an external RF circuit board, thus eliminating the need for a package housing. By exposing the passive surface-mountable components (equivalent to components on an RF circuit board) on the top surface, embodiments of the present disclosure provide a package configuration in which components of the matching circuit may be changed (or fine-tuned) even after package assembly is complete. That is, in embodiments of the present disclosure, an RF transistor amplifier package may be modified or tuned for different frequency bands (e.g., in virtual broadband applications) after assembly and / or shipment to a customer.

[0073]

[0105] Transistor dies and other passive components may be protected after solder attachment to the substrate by applying an environmental scratch-coat layer or other conformal (e.g., spray-on) protective layer. Examples of such conformal protective layers may include, but are not limited to, polyimide, benzocyclobutene (BCB), polyolefin resin, siloxane, or erucic acid amide. Embodiments of the present disclosure may provide packaged RF power devices with lower thermal resistance because the package substrate can be placed directly on the heat sink (or heat sink metallization) of an external RF circuit board without intervening vias or copper slats required to reach the heat sink metallization.

[0074]

[0106] Embodiments are described below with reference to exemplary RF transistor amplifier packages 370, 470 or components 570 and variations thereof. Each of the transistor amplifier packages 370, 470 or components 570 may include at least one transistor die 210 (which may include variations 210-1, 210-2 described herein) having a semiconductor structure 130 attached to and electrically connected to a conductive pattern 373 on a surface of a substrate 375, 387 by a solder material 340. In particular, the gate 362, source 366, and / or drain 364 terminals of each of the transistor die 210 are attached to and electrically connected to a respective one of the conductive patterns 373 exposed by a solder mask pattern 330 on a surface of the substrate 375, 387 by the solder material 340 and aligned by the solder mask pattern 330. One or more surface-mountable passive electrical components 378i, 378o (collectively, 378) may be similarly attached to the surface of the substrate 375, 387 by solder material 340 and aligned by solder mask pattern 330, such that respective terminals of the transistor die 210 are electrically connected to respective conductive patterns of the conductive patterns 373. The passive electrical components 378 may include discrete surface-mountable capacitors, inductors, resistors, or other interconnect structures, including IPDs, and may implement predetermined portions of input, interstage, or output impedance matching circuits or harmonic termination circuits for the RF transistor amplifier 370, 470, 570. The substrate may be a substrate 375 (referred to herein as package substrate 375) included in the packaged RF transistor amplifier 370, 470, or may be a substrate 387 (e.g., a customer PCB) included in the external RF circuit board 300, 400.

[0075]

[0107] In some RF transistor amplifier packages 370, 470, or components 570 described herein, the transistor die(s) 210 may include a patterned backside metal layer 126 on the bottom surface of the transistor die 210, as shown, for example, by transistor die 210-1 in FIG. 6A . The patterned backside metal layer 126 may provide input (e.g., gate 362), output (e.g., drain 364), and / or ground (e.g., source 366) terminals for each transistor die(s) 210. The transistor die(s) 210 may be mounted backside down with the patterned backside metal layer 126 attached to the surface of the substrate 375, 387 by solder material 340 (aligned by the solder mask pattern 330 at desired locations on the surface), such that the respective gate 362, source 366, and / or drain 364 terminals of the transistor die(s) 210 are electrically connected to respective conductive patterns of the conductive patterns 373. The barrier metal layer 345 may be provided between the patterned backside metal layer 126 and the solder material 340 on the surface of the substrate 375, 387 and may be a material (e.g., nickel (Ni), titanium (Ti), and / or alloys thereof) configured to prevent migration of metal particles from the solder material 340 into the backside metal layer 126 (e.g., gold (Au)).

[0076]

[0108] In some RF transistor amplifier packages 370, 470 or components 570 described herein, the transistor die(s) 210 may include multiple conductive pillars 222, 224, 226 on a top surface (adjacent the transistor active area 2) of the transistor die 210, as shown, for example, by transistor die 210-2 in FIG. 6C. The conductive pillars 222, 224, 226 may be coupled to input (e.g., gate 310), output (e.g., drain 305), and / or ground (e.g., source 315) terminals for the respective transistors 10. The transistor die(s) 210 may be mounted face-down or front-side down with the conductive pillars 222, 224, 226 attached to the surface of the substrate 375, 387 by the solder material 340 (aligned by the solder mask pattern 330 at desired locations on the surface), such that the respective gate 222, source 226, and / or drain 224 terminals of the transistor die(s) 210 are electrically connected to the respective conductive patterns of the conductive pattern 373. That is, the conductive pillar-based interconnects 222, 224, 226 may enable a “flip-chip” die configuration in which the pads or terminals of the transistor die(s) 210 are mounted on the upper surface or top side of the transistor die 210 (i.e., adjacent to the transistor region area 2), and the die 210 is mounted face-down on the substrate 375, 387 and electrically connected to the conductive patterns 373.

[0077]

[0109] In any of the front or back mount configurations described herein, the transistor die(s) 210 are attached with solder material 340 to conductive patterns 373 exposed by solder mask patterns or strips 330 on the surface of the substrate 375, 387 using a solder / solder mask / solder reflow method in a manner similar to that used with other discrete surface mountable components such as SMDs or IPDs. The self-aligning feature of the solder reflow attach method allows for tighter placement tolerances of the transistor die(s) 210 and passive electrical components 378 onto the surface of the substrate 375, 387. For example, the passive electrical components 378 and / or transistor die(s) 210 may be aligned by the solder mask pattern 330 and spaced apart from one another by respective gaps D1, D2 of less than about 0.25 mm (10 mils), e.g., less than about 0.1 mm (4 mils), or between about 0.1 mm and about 0.05 mm, which may be significantly smaller than inter-component spacing achievable with some existing epoxy-based or conductive bump-based techniques. In some embodiments, no wire bonds are used to electrically connect the terminals 362, 364, and / or 366 of the transistor die(s) 210 to the package substrate 375 or the external RF circuit board substrate 387. Embodiments of the present invention may thereby increase component density and placement accuracy, and reduce costs and time associated with package assembly.

[0078]

[0110] 3A is a simplified side view of an RF power amplifier package 370 including surface-mounted active components 210 and passive components 378 according to various embodiments of the present disclosure. FIG. 4A is a simplified side view of an RF power amplifier package 470 including surface-mounted active components 210 and passive components 378 according to a further embodiment of the present disclosure.

[0079]

[0111] As shown in FIGS. 3A and 4A , packages 370, 470 each include one or more transistor dies (e.g., GaN on SiC transistor dies) 210 and / or one or more passive components 378i, 378o (collectively 378). The transistor dies 210 and passive components 378 are attached to conductive patterns 373 on the surface of a package substrate 375 by solder material 340 and aligned by solder mask patterns 330. The transistor dies 210 each include input, output, and ground terminals, shown as gate 362, drain 364, and source 366 terminals, respectively. In the example of FIGS. 3A and 4A , terminals 362 and 364 are provided on the front or top surface of die(s) 210, while terminal 366 is provided on the back or bottom surface of die(s) 210. However, it will be understood that terminals 362, 364, and 366 may be routed to the top or bottom (or both) surfaces of die(s) 210 in various combinations, for example, as defined by respective portions of patterned backside metal layer 126 shown in Figure 6A or as coupled to respective conductive pillars 222, 224, 226 shown in Figure 6C. Transistor die(s) 210 may, in some embodiments, define a single stage amplifier or a multi-stage amplifier (such as a Doherty amplifier).

[0080]

[0112] The package substrate 375 may be any substrate or laminate (e.g., a PCB) including an electrical insulating member 377 and one or more conductive patterns 373 defined by predetermined portions of a conductive layer (e.g., a copper clad layer or other metallization) exposed by the solder mask pattern 330. Although shown as including two conductive layers (a conductive top cladding and a conductive bottom cladding) on ​​the electrical insulating member 377, the package substrate 375 may include fewer or more layers (e.g., a multilayer circuit board including, e.g., five layers, eight layers, etc.), with conductive vias connecting different conductive layers. The number of layers on the package substrate 375 can differ from the number of layers on an external (e.g., customer) RF circuit board (shown herein as 300, 400). In some embodiments, the package substrate 375 may include an embedded capacitance layer, where the conductive pattern 373 on the surface provides electrical connections to the capacitance layer.

[0081]

[0113] The transistor die 210 and passive components 378 are reflow soldered to the top surface of the package substrate 375. The solder material 340 may be a solder paste containing metal (e.g., tin (Sn)) solder particles suspended in a thick fluid medium or flux. The solder mask pattern 330 may be a thin polymer layer that is patterned to expose predetermined portions of the conductive pattern 373 for electrical connection while covering other portions of the conductive pattern 373 for electrical insulation and protection against oxidation. The solder mask pattern or strip 330 is used to guide the location of the solder 340 on the top surface of the package substrate 375.

[0082]

[0114] The conductive pattern 373 may define input and output leads 372 and 374 of the package 370. The input and output leads 372 and 374 are respective RF leads that provide RF signal connections to the respective terminals 362 and 364 of the transistor die(s) 210. The RF leads 372, 374 may comprise, for example, microstrip transmission lines and may extend along or otherwise be substantially coplanar with the same surface to which the transistor die(s) 210 are attached. The ground terminals of the transistor die(s) 210 (e.g., the source terminals 366 in FIG. 6A and the conductive pillars 226 in FIG. 6C ) are attached to the conductive member or array 380 by the solder material 340. The conductive member 380 may be embedded in or otherwise extend from the package substrate 375 to provide an electrical and / or thermal conduction path from the transistor die(s) 210. For example, the conductive member 380 may be an embedded copper member, a copper slat, or a dense / filled copper via array that extends through the package substrate 375 to provide an electrical ground and thermal heat sink for the transistor die(s) 210.

[0083]

[0115] In the example package 370 of FIG. 3A , the bottom surface of the package substrate 375 is mounted to a thermally conductive package submount or metal flange 376. For example, the flange 376 may be a CPC (copper, copper molybdenum, copper laminate construction) or copper flange that provides a heat dissipation path or structure for the package 370. The package substrate 375 may, in some embodiments, not extend substantially beyond the edge of the thermally conductive package submount 376. An embedded conductive member 380 may electrically and thermally couple the ground terminal 366 of the transistor die(s) to the flange 376, which may be configured to be disposed on a heat sink / ground of an external RF circuit board (e.g., the heat sink 386 of the RF circuit board 300 shown in FIG. 3B ).

[0084]

[0116] 4A does not include a thermally conductive package mount 376 on the bottom surface of the package substrate 375. Rather, the embedded conductive members 380 are exposed at the bottom surface of the package substrate 375, allowing the package substrate 375 to be placed directly on the heat sink / ground of an external RF circuit board (e.g., the heat sink 486 of the RF circuit board 400 shown in FIG. 4B).

[0085]

[0117] 3A and 4B , the transistor die(s) 210 are not directly attached to a conductive submount or flange 376, but rather are attached by solder material 340 and aligned by solder mask pattern 330 on the surface of a package substrate 375. That is, the package substrate 375 does not include an opening therein that exposes the submount 376, but rather provides a substantially planar or continuous surface to which the transistor die(s) 210 and / or other passive components 378 are attached by solder material 340. The high-power RF transistor die(s) 210 can generate a significant amount of heat, which should be effectively conducted to the thermal submount 376 to maintain good RF performance. This may be effectively achieved by an embedded conductive member 380 (which may include, for example, copper slats or embedded copper coins), thus providing a lower thermal resistance for, for example, a sparse via array.

[0086]

[0118] The transistor die(s) 210 and / or other passive components 378 may be protected by an environmental scratch coat (e.g., a spray-on coating) or other environmental protection layer 390 (see FIGS. 6A and 6C). The environmental protection layer 390 may conformally extend over one or more surfaces of the die(s) 210, the passive components 378, and / or the surface of the package substrate 375 therebetween. The environmental protection layer 390 may be a polyimide or benzocyclobutene (BCB) layer or coating and, in some embodiments, may have a thickness of about 3 μm to about 10 μm, e.g., about 5 μm to about 7 μm. Thus, the package 370, 470 may be free of an overmold or lid member covering the transistor die(s) 210. Additionally, the environmental protection layer 390 may be an optically dark or opaque material configured to reduce or block light penetration into the transistor die and prevent undesirable effects of light on transistor performance, as is known to occur with III-nitride devices.

[0087]

[0119] 3B is a schematic side view of the RF power amplifier package 370 of FIG. 3A mounted on an external RF circuit board 300 (e.g., a customer PCB) with a conductive shim 385 used for package board electrical connection according to various embodiments of the present disclosure. FIG. 4B is a schematic side view of an RF power amplifier package 470 mounted on an external RF circuit board 400 (e.g., a customer PCB) with a conductive shim 385 used for package board connection according to a further embodiment of the present disclosure.

[0088]

[0120] As shown in FIGS. 3B and 4B , the RF circuit boards 300, 400 each include a substrate 387 (e.g., a PCB) having one or more conductive layers that define a conductive pattern 373. The substrate 387 is attached to the top surface of a thermally conductive substrate or heat sink 386, 486 (e.g., a copper or aluminum block or base structure). One or more passive components 378′ may be electrically connected to the conductive pattern 373, for example, to implement a predetermined portion of an impedance matching or harmonic termination network. The substrate 387 includes openings 381, 481 that expose the surface of the heat sink 386, 486. The openings 381, 481 are sized to receive the RF amplifier packages 370, 470, so that the packages 370, 470 can be mounted on the heat sink 386, 486. The heat sink 386, 486 provides a thermal path for conducting heat away from the transistor die. The heat sinks 386, 486 also serve as electrical grounds for the RF signals traveling through the RF circuit boards 300, 400.

[0089]

[0121] 3B , opening 381 exposes a recessed portion R of heat sink 386. Recess R may be machined into heat sink 386 such that, after placement of packaged RF device 370 on RF circuit board 300, package submount 376 and package substrate 375 are confined within opening 381. For example, recess R may have a depth corresponding to the combined thickness of package substrate 375 and package submount 376 such that, when placed within opening 381, the top surface of package substrate 375 may be substantially coplanar with the top surface of PCB 387 outside opening 381. Opening 381 may have dimensions sized to receive packaged device 370 with some clearance or gap (e.g., less than about 15 mils, e.g., about 10 mils or less, or about 5 mils or less) between the sidewalls of opening 381 and the perimeter or edge of packaged device 370. In some cases, it may be desirable to justify packaged device 370 to the left or right of the center of opening 381 (e.g., so that it is flush with or in contact with PCB 387 on one side), with a gap of about 30 mils or less (e.g., about 15 mils or less, or about 10 mils or less) between the perimeter or edge of packaged device 370 and input leads 372 or output leads on the other side. In other cases, the packaged device 370 may be substantially centered in the opening 381, for example, with a respective gap of 0.375 mm (15 mils) or less (e.g., about 0.25 mm (10 mils) or less or about 0.125 mm (5 mils) or less) on either side (e.g., on the input side and output side, respectively, for connection to the input lead 372 and the output lead 374).

[0090]

[0122] 4B , package substrate 375 may have the same or substantially similar thickness as PCB 387 of external RF circuit board 400, such that heat sink 486 of RF circuit board 400 may provide a substantially planar or continuous surface (i.e., no recesses R therein) on heat sink 486 that includes the lower surface of package substrate 375 and the lower surface of PCB 387. That is, heat sink 486 may have a continuous surface that has a substantially uniform thickness throughout and is free of any recesses, dips, or embedded conductors (e.g., copper coins) therein. Thus, package 470 may be placed on RF circuit board 300 directly on the substantially planar surface of heat sink 486 with consistent positioning in the vertical dimension and low performance variation as signals pass from the packaged device to a customer circuit board, which may simplify assembly and manufacturing of an RF amplifier that includes RF circuit board 400 and package 470 and may improve the ground return path for RF signals passing from RF circuit board 400 to package 470.

[0091]

[0123] 3B and 4B, the respective surfaces (e.g., conductive upper cladding layer 373) of package substrate 375 and RF circuit board 300, 400 may be substantially coplanar (or "flush") with one another. For example, the upper or top surface of package substrate 375 may be within about 15 mils (e.g., within about 10 mils, within 7 mils, within 5 mils, or less) above or below the top surface of RF circuit board 300, 400 or PCB 387. Conductive surface-mount components 385 are used to bridge connections between RF circuit board 300, 400 and conductive leads 372, 374 of packaged device 370, 470. For example, the conductive surface-mount components may be implemented by discrete conductive shims 385 (e.g., copper shims) or other flexible conductive materials. In some embodiments, the conductive shims 385 may be implemented by copper tape, which may be flexible enough to provide a conductive bridge between the conductive pattern 373 on the top surface of the RF circuit board 300, 400 and the conductive pattern 373 on the top surface of the package substrate 375 that provides the leads 372, 374 of the packaged RF power device 370, 470, with a deflection of as much as about ±15 mils (e.g., about ±10 mils, about ±7 mils, or about ±5 mils) between the substantially coplanar surfaces of the substrates 375 and 387.

[0092]

[0124] In some embodiments, the conductive surface mount components used for package board connections may be mounted by additional passive surface mount components 378. For example, in addition to or in place of the flexible conductive shim 385, other surface mount components 378 (e.g., discrete capacitors, inductors, resistors, or other interconnect structures, including IPDs) may be used to provide a conductive bridge between the conductive traces 373 of the RF circuit board 300, 400 and the conductive traces 373 that provide the leads 372, 374 of the packaged RF power device 370, 470.

[0093]

[0125] Thus, the RF signal connections between the package 370, 470 and the RF circuit board 300, 400 are implemented by conductive (e.g., copper) shims 385 or SMD components 378 (e.g., RF capacitors, zero-ohm resistors, etc.) that extend substantially beyond the edge or perimeter of the package substrate 375 and may be added after assembly and / or sale. Because the conductive shims 385 are flexible, RF transistor amplifier packages 370, 470 according to embodiments of the present disclosure may be more tolerant of misalignment (e.g., non-coplanarity) between the top surface 373 of the RF circuit board 300, 400 and the package 370, 470. That is, the flexible conductive shims 385 can flex to accommodate misalignment between the respective surfaces 373 of the RF circuit boards 300, 400 and the package 370, 470 while still maintaining electrical connection for the RF signal connections.

[0094]

[0126] Figure 5A is a simplified side view of components 570 (including active components 210 and passive components 378i, 378o) of an RF power amplifier according to various embodiments of the present disclosure. Figure 5B is a simplified side view of components 570 of Figure 5A mounted on an external (e.g., customer) RF circuit board 500 according to various embodiments of the present disclosure.

[0095]

[0127] As shown in FIG. 5A , the RF power amplifier component 570 includes one or more transistor dies 210 and one or more surface-mount passive components 378i, 378o (collectively 378). In some embodiments, the passive component(s) 378o coupled to the output leads 374 may be SiC or other wide-bandgap semiconductor IPDs or SMDs that may be configured to handle the power and / or thermal requirements at the output of the transistor die(s) 210 (for which a ceramic SMD may not be sufficient). The passive component(s) 378i coupled to the input leads 372 of the transistor die(s) 210 may include ceramic or SiC SMDs or IPDs. The transistor die(s) 210 and the passive components 378 may be similar to or identical to the components described above with reference to the packages 370, 470 of FIGS. 3A and 4A . The RF amplifier may be implemented by mounting the respective terminals of the components 570 on the surface of the substrate 387 of the external RF circuit board 500, without an intervening package substrate 375. Although shown in FIG. 5A as including components 570 having bottom terminals (gate 362, drain 364, and source 366 terminals on the lower surface of the die 210), it will be understood that one or more of the components 570 may have top terminals (e.g., mounted by conductive pillars 222, 224, 226 on the die 210 that protrude from the top surface of the die 210) and may be mounted in a flip-chip configuration on the surface of the substrate 387.

[0096]

[0128] 5B , RF circuit board 500 includes a substrate 387 (e.g., a PCB) having one or more conductive layers that define a conductive pattern 373. Substrate 387 is attached to the top surface of a thermally conductive substrate or heat sink 486 (e.g., a copper or aluminum block or base structure). Substrate 387 does not include an opening therein that exposes the top surface of heat sink 486; rather, heat sink 486 may provide a substantially planar top surface, with the bottom surface of substrate 387 resting on heat sink 486. Conductive pattern 373 may include embedded conductive members 380 (e.g., embedded copper members, copper slats, or dense / packed copper via arrays) that extend through package substrate 375 to provide electrical ground and thermal heat sinking for transistor die(s) 210. The transistor die(s) 210 and passive components may be reflow soldered to the top surface of the substrate 387 of the external RF circuit board 500, whereby the respective terminals of the components 570 are attached to and electrically connected to the respective conductive patterns 373 exposed by the solder mask pattern 330 on the surface of the substrate 387 (in particular, the terminals 366 of the die 210 are attached to and electrically connected to the embedded conductive members 380). The solder mask pattern or strips 330 are used to guide the location of the solder material 340 and thus align the components 570.

[0097]

[0129] That is, the substrate 387 of the external RF circuit board 500 similarly provides a substrate for attachment of the RF transistor amplifier component 570. Thus, there may be no transition or discontinuity (lateral or vertical) between the customer circuit board 500 and the RF amplifier package substrate. As such, the RF transistor amplifier component 570 is integrated onto the external RF circuit board 500 as a continuous piece, which may reduce interconnect parasitics and reduce performance variation. For example, the RF circuit board 500 may be manufactured by the customer, and the RF transistor amplifier supplier may supply the transistor die(s) 210 and discrete surface-mount passive components 378 that may be reflow soldered to the external RF circuit board 500 simultaneously with the other surface-mount passive components 378′. Such a configuration may provide additional flexibility and / or reduce costs (e.g., assembly costs, packaging costs) for the supplier.

[0098]

[0130] 3A-5B illustrate packages 370, 470 and components 570 that are configured to be attached and electrically connected to external RF circuit boards 300, 400, 500 by solder material 340 and that may enable RF amplifier implementations without wirebonds and with conductive traces 373 that provide routing between RF input terminals 372, transistor die(s) 210, and RF output terminals 374. Passive components on the substrates 375, 387 may implement pre-matching and / or filtering circuits without wirebonds between components, thereby eliminating parasitic inductance and losses associated with wirebonded connections between components.

[0099]

[0131] 6A and 6B are enlarged simplified side and top views, respectively, of a backside-mountable RF power transistor die 210-1 and a top view of the transistor die 210-1 of FIG. 6A mounted on a package substrate 375, according to various embodiments of the present disclosure.

[0100]

[0132] As shown in FIG. 6A , transistor die 210-1 includes a semiconductor structure 130 having a backside metal layer 126 on its bottom surface. The bottom surface of semiconductor structure 130 faces transistor active area 2 and may comprise a semiconductor (e.g., SiC) substrate in some embodiments. Backside metal layer 126 may extend along the bottom surface and may be patterned to provide input (gate) 362, output (drain) 364, and ground (source) 366 terminals for transistor die 210. Additional gate 362′ and drain 364′ terminals are shown on the top surface of die 210 by way of example. A barrier metal layer 345 is provided between terminals 362, 364, 366 defined by patterned backside metal layer 126 and solder material 340 on the surface of substrates 375, 387. Barrier metal layer 345 is configured to reduce or prevent migration of metal particles (e.g., Sn) from solder material 340 into backside metal layer 126. For example, backside metal layer 126 may include gold (Au), and barrier metal layer 345 may include at least one of Ni, Ti, and / or alloys thereof. In some embodiments, barrier metal layer 345 may have a thickness of less than about 2 micrometers (μm), for example, from about 0.5 μm to about 1.5 μm.

[0101]

[0133] As shown in FIG. 6B , transistor die 210-1 is mounted backside down on the front surface of package substrate 375. Package substrate 375 includes solder mask pattern 330 thereon, which exposes conductive pattern 373 on its front surface. Gate 362, source 366, and drain 364 terminals of transistor die 210-1 are attached to and electrically connected to respective conductive patterns of conductive pattern 373 by solder material 340, with predetermined portions of barrier metal layer 345 between terminals 362, 364, 366 and solder material 340. The self-aligning nature of solder mask pattern 330 and the solder reflow process may align the input, output, and ground terminals of die 210-1 with greater precision or accuracy than would be possible using epoxy-based or conductive bump-based attachment. The input 362, output 364, and ground 366 terminals may all be provided on the same (back) surface of die 210-1. The solder-based attachment described herein may thereby enable connection of the transistor die 210-1 with multiple terminals on the same (e.g., bottom) surface of the die 210-1, which may not be possible using some conventional epoxy-based attachment techniques (where the relatively large volume of epoxy material or lack of surface adhesion to the metal surface may short-circuit adjacent terminals on the same surface of the transistor die).

[0102]

[0134] 6C is a simplified side view of a flip-chip mountable RF power amplifier die 210-2 according to various embodiments of the present disclosure. As shown in FIG. 6C, the transistor die 210-2 includes a semiconductor structure 130 having a top surface adjacent to a transistor active area 2 and a plurality of conductive pillars 222, 224, and 226 protruding from the top surface of the transistor die 210-2. The conductive pillars 222, 224, and 226 provide input, output, and ground terminals, respectively, on the surface of the transistor die 210-2 (adjacent to the active area 2) and are configured to be attached to and electrically connected to respective conductive patterns 373 on the surface of the substrates 375, 387 by a solder material 340. The conductive pillars 222, 224, and 226 may be formed from a material (e.g., copper) that is not susceptible to migration of metal particles from the solder material 340, such that the solder material 340 may directly attach the conductive pillars 222, 224, and 226 to the conductive pattern 373 on the surface of the substrate 375, 387 without a barrier metal layer 345 between them.

[0103]

[0135] 6A-6C, environmental protection layer 390 conformally extends over one or more surfaces of transistor die 210-1, 210-2. Environmental protection layer 390 may be an environmental scratch-coat layer or other conformal (e.g., spray-on) protective layer, such as polyimide, benzocyclobutene (BCB), polyolefin resin, siloxane, or erucamide, and may be applied after solder attachment of transistor die 210-1, 210-2 to substrates 375, 387. Environmental protection layer 390 may have a thickness of about 3 μm to about 10 μm, e.g., about 5 μm to about 7 μm, on each surface of transistor die 210-1, 210-2 in some embodiments.

[0104]

[0136] 7 is a simplified side view of an RF power amplifier package 770 including wire bonds between the active component 210 and passive components 378i, 378o according to various embodiments of the present disclosure. As shown in FIG. 7 , the transistor die 210 includes a bottom surface including gate 362, drain 364, and source 366 terminals attached and electrically connected to respective conductive patterns 373 on a surface of a package substrate 375 by solder material 340 and aligned by a solder mask pattern 330 on the package substrate 375. The top surface of the transistor die 210, opposite the bottom surface, includes additional gate 362′ and drain 364′ terminals. Wire bonds 325 are used to electrically connect the gate 362′ and / or drain 364′ terminals on the top surface to passive electrical components 378i, 378o. The passive electrical components 378i, 378o may define predetermined portions of input, interstage, or output impedance matching circuits or harmonic termination circuits for the RF transistor amplifier package 770. Thus, electrical connections to terminals 362, 364, 366 of transistor die 210 may be made from both the top and bottom surfaces for further ease in implementing, for example, impedance matching and / or harmonic termination circuits. Other elements of package 770 of FIG. 7 may be similar to or identical to packages 370, 470 described herein.

[0105]

[0137] 8, 9, and 10 are schematic diagrams illustrating methods of fabricating RF power amplifier packages 370, 470 according to various embodiments of the present disclosure. As shown in the perspective view of FIG. 8, multiple package substrates 375 may be mounted or otherwise mechanically connected to one another in a panel 379. Each package substrate 375 includes an electrically insulating layer 377 and one or more conductive layers thereon. Predetermined portions of the conductive layers are exposed by a solder mask pattern 330 on each surface of the package substrate 375 to define a conductive pattern 373. The conductive pattern 373 may define respective leads for RF signal connections along the surface of the package substrate 375, such that the respective leads do not extend beyond the edges of the electrically insulating member 377. The solder mask pattern 330 may be defined by a screen printing process using conventional methods.

[0106]

[0138] As shown in the side view of FIG. 9 , solder material 340 is applied to the conductive patterns 373 exposed by the solder mask pattern 330 on each surface of the substrate 375. More specifically, a stencil 910 is provided on each surface of the substrate 375 to expose the conductive patterns 373, and a squeegee blade 909 is used to apply the solder material 340 to the conductive patterns 373 exposed by the stencil 910. The solder material 340 may be a paste including metal (e.g., tin (Sn)) solder particles suspended in a thick fluid medium or flux. Excess flux may be cleaned from the surface of the substrate 375. Using such screen printing and stencil methods, the solder material 340 may be applied to a large panel 379 (e.g., a PCB array) including multiple package substrates 375, so that several semiconductor components (i.e., transistor die 210 and / or surface-mount passive components 378) may be positioned and reflowed in the same process step.

[0107]

[0139] 10 illustrates the end of the assembly process for packaged RF power devices 370, 470. As shown in FIG. 10, transistor die 210 and discrete surface-mount passive components 378 (e.g., SiC transistors, SiC IPDs, and other SMD components) are provided on respective surfaces of package substrate 375 and attached to the surface of package substrate 375, which includes solder material 340 thereon. A solder reflow process is performed to attach and align transistor die 210 and passive components 378 to conductive patterns 373 on the respective surfaces of substrate 375, such that respective terminals of transistor die 210 and passive components 378 are electrically connected to respective conductive patterns of conductive patterns 373 by solder material 340 and aligned by solder mask patterns 330. That is, the solder mask pattern 330 (having the solder material 340 deposited thereon using the stencil 910) may extend around or outline each conductive pattern of the conductive pattern 373, so that when the solder material is reflowed at a temperature sufficient to melt the solder material 340, the solder mask pattern 330 may be used to self-align and center the transistor die 210 and the passive component 378 in the desired position, so that their respective terminals are electrically connected to their respective conductive patterns of the conductive pattern 373.

[0108]

[0140] In some embodiments, an environmental protection layer 390 (not visible in FIG. 10 ) may be applied to cover the transistor die 210 and passive components 378 (and the electrical connections therebetween). For example, a spray-on process may be used to conformally deposit the protection layer 390, such as a scratch coat or other protective layer, after performing a solder reflow process to attach the components 210 and 378 to the substrate 375. Each substrate 375 may be singulated from the panel 379 to provide the RF transistor amplifier packages 370, 470.

[0109]

[0141] 11 is a simplified perspective view illustrating a package board connection between an RF power amplifier package 370, 470 and a substrate 387 of an external RF circuit board 300, 400 in an RF amplifier application 1100. As shown in FIG. 11 , the RF circuit board 300, 400 includes a substrate 387 that includes a conductive base structure 386, 486 (e.g., a copper or aluminum heat sink) and a conductive layer 373 thereon. Additional surface-mounted electrical components 378′ (e.g., passive and / or reactive SMD, IPD, or interconnect structures) may be provided on the conductive traces / routing 373.

[0110]

[0142] The packaged RF power device 370, 470 is mounted within an opening in the substrate 387 such that the bottom surface of the package 370, 470 (i.e., the flange 376 in the package 370 or the bottom surface of the package substrate 375 in the package 470) contacts the conductive base structure 386, 486, with the package substrate 375 being confined within the opening in the substrate 387 of the RF circuit board 300, 400. Each lead (i.e., 372, 374) defined by the conductive pattern 373 has no electrical connection extending beyond the edge of the electrically insulating member 377 of the package substrate 375.

[0111]

[0143] Figure 12 is an enlarged, schematic perspective view showing in more detail the package board connection between the RF power amplifier package 370, 470 and the substrate 387 of the external RF circuit board 300, 400 of Figure 11. As shown in Figure 12, conductive surface-mount components 385 (e.g., copper shims or other flexible conductive material) are used to provide a conductive bridge between the conductive trace 373 of the RF circuit board substrate 387 and the respective leads provided by the conductive trace 373 of the packaged RF power device substrate 375. Additionally or alternatively, surface-mount electrical components (e.g., passive and / or reactive SMD or IPD) may be used to provide a conductive bridge between the RF circuit board substrate 387 and the packaged RF power device substrate 375.

[0112]

[0144] Thus, multiple RF amplifier packages 370, 470 may be assembled and built in a panel configuration 379. The surface-mount active components 210 and / or passive components 378 may be placed using an automated chip shooter after the solder material 340 is applied using a common stencil 910 for multiple package substrates 375, and the entire panel 379 may be reflowed with the same solder reflow process to complete the attachment of the active components 210 and / or passive components 378 to the conductive patterns 373 exposed by the solder mask pattern 330 on the surface of each of the package substrates 375. The use of surface-mount active components 210 and passive components 378 using solder-based attachment on the surface of the substrates 375, 387 (without a protective lid or overmold member on the surface) may allow greater flexibility in pre-matching circuit design and / or design topology at the supplier and / or customer level. For example, the passive components 378, 378′ may be reconfigurable to provide desired impedance characteristics (e.g., to implement input / interstage / output impedance matching circuits and / or harmonic termination circuits for the transistor die(s) 210) and / or desired frequency performance.

[0113]

[0145] Embodiments of the present disclosure may be used, for example, in various RF power products, such as for 5G, base stations, or aerospace and defense (A&D) applications. Particular embodiments of the present disclosure may be used in various cellular infrastructure (CIFR) RF power products (including, but not limited to, 5W, 10W, 20W, 40W, 60W, 80W, and different frequency bands), such as for 5G and base station applications, including macro (e.g., 20-80W and different frequency bands) average power applications. Embodiments of the present disclosure may be applied to radar and monolithic microwave integrated circuit (MMIC) type applications or any other application using Si or Si IPD components and / or transistors.

[0114]

[0146] The transistor amplifiers described herein may include transistor die(s) defining a gallium nitride-based high electron mobility transistor (HEMT) and / or defining a silicon-based laterally diffused metal oxide semiconductor (LDMOS) transistor. The transistor die(s) may be configured to operate over at least a portion of one or more of the 2.5-2.7 GHz, 3.4-4.2 GHz, or 5.1-5.8 GHz frequency bands, and / or at frequencies greater than 10 GHz.

[0115]

[0147] Referring again to FIG. 2B , a semiconductor structure 130 that may be used in the transistor amplifier packages described herein, such as a semiconductor structure for a III-nitride semiconductor HEMT, may be formed on a substrate 322, such as a silicon carbide substrate, a silicon substrate, or a sapphire substrate. The substrate 322 may be a semi-insulating silicon carbide substrate, which may be, for example, a 4H polytype of silicon carbide. Other silicon carbide candidate polytypes may include the 3C, 6H, and 15R polytypes. The substrate 322 may be a high purity semi-insulating (HPSI) substrate available from Cree, Inc. The term “semi-insulating” is used descriptively herein and not in an absolute sense.

[0116]

[0148] While silicon carbide may be used as the substrate material, embodiments of the present application may utilize any suitable substrate, such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), and the like. In some embodiments of the present disclosure, the SiC bulk crystal of the substrate 322 has a crystallinity of approximately 1×10 at room temperature. 5 The substrate 322 may have a resistivity of ohm-cm or higher. The substrate 322 may be a SiC wafer, and the HEMT devices may be at least partially formed by wafer-level processing, and the wafer may then be diced to provide a plurality of individual HEMTs.

[0117]

[0149] The channel layer 324 is formed on the upper surface of the substrate 322 (or on optional layers described further herein), and the barrier layer 326 is formed on the upper surface of the channel layer 324. The channel layer 324 and the barrier layer 326 may each be formed by epitaxial growth in some embodiments. Techniques for epitaxial growth of Group III nitrides are described, for example, in U.S. Pat. Nos. 5,210,051, 5,393,993, and 5,523,589, the disclosures of which are likewise incorporated by reference herein in their entireties. The channel layer 324 may have a bandgap smaller than that of the barrier layer 326, and the channel layer 324 may have a greater electron affinity than the barrier layer 326. The channel layer 324 and the barrier layer 326 may include Group III nitride-based materials.

[0118]

[0150] In some embodiments, the channel layer 324 is Al x Ga 1-x The channel layer 324 may be a III-nitride such as GaN (0≦x<1), provided that the conduction band edge energy of the channel layer 324 is less than the conduction band edge energy of the barrier layer 326 at the interface between the channel layer 324 and the barrier layer 326. In certain embodiments of the present disclosure, x=0, indicating that the channel layer 324 is GaN. The channel layer 324 may also be other III-nitrides, such as InGaN, AlInGaN, or the like. The channel layer 324 may be undoped (“unintentionally doped”) and grown to a thickness greater than about 0.002 μm. The channel layer 324 may be a superconducting or multilayer structure, such as a combination of GaN, AlGaN, or the like. The channel layer 324 may be under compressive strain in some embodiments.

[0119]

[0151] For a HEMT device, a 2DEG layer is induced in the channel layer 324 at the junction between the channel layer 324 and the barrier layer 326. The 2DEG layer acts as a highly conductive layer that enables conduction between the source and drain regions of the device, which are located underneath the source and drain contacts 156 and 154, respectively. The channel layer 324 and the barrier layer 326 form the semiconductor structure 130.

[0120]

[0152] Although semiconductor structure 130 is shown with channel layer 324 and barrier layer 326 for illustrative purposes, semiconductor structure 130 may include additional layers / structures / elements, such as buffer and / or nucleation layer(s) between channel layer 324 and substrate 322 and / or a cap layer on barrier layer 326. HEMT structures including substrates, channel layers, barrier layers, and other layers are discussed by way of example in U.S. Pat. Nos. 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, 7,548,112, 7,592,211, 7,615,774, and 7,709,269, the disclosures of which are incorporated herein by reference in their entireties. For example, an AlN buffer layer may be formed on the upper surface of the substrate 322 to provide a suitable crystal structure transition between the silicon carbide substrate 322 and the remainder of the HEMT device. Additionally, strain balancing transition layer(s) may also and / or alternatively be provided, for example, as described in commonly assigned U.S. Patent No. 7,030,428, the disclosure of which is incorporated herein by reference as if fully set forth herein.

[0121]

[0153] The source contact 156 and the drain contact 154 may be formed on the upper surface of the barrier layer 326 and may be laterally spaced apart from one another. The gate contact 152 may be formed on the upper surface of the barrier layer 326 between the source contact 156 and the drain contact 154. The material of the gate contact 152 may be selected based on the composition of the barrier layer 326 and may be a Schottky contact in some embodiments.

[0122]

[0154] The source contact 156 may be coupled to a reference signal, such as a ground voltage. The coupling to the reference signal may be provided by a via 166 extending from the lower surface of the substrate 322, through the substrate 322, and to the upper surface of the barrier layer 326. The via 166 may expose the lower surface of the ohmic portion of the source contact 156. A backside metal layer 126 (also referred to as a back metal layer) may be formed on the lower surface of the substrate 322 and on the sidewalls of the via 166. The back metal layer 126 may be patterned such that an electrically isolated portion of the back metal layer 126 directly contacts the ohmic portions of the source contact 156, the gate bus 146, and / or the drain bus 148.

[0123]

[0155] 2B , the HEMT device 110 may include a first insulating layer 350 and a second insulating layer 355. The first insulating layer 350 may directly contact the upper surface of the semiconductor structure 130 (e.g., it may contact the upper surface of the barrier layer 326). The second insulating layer 355 may be formed on the first insulating layer 350. It will also be appreciated that more than two insulating layers may be included in some embodiments. The first insulating layer 350 and the second insulating layer 355 may serve as passivation layers for the HEMT device.

[0124]

[0156] The source contact 156, the drain contact 154, and the gate contact 152 may be formed in the first insulating layer 350. In some embodiments, at least a portion of the gate contact 152 may be on the first insulating layer. In some embodiments, the gate contact 152 may be formed as a T-gate and / or a gamma gate, the formation of which is discussed by way of example in U.S. Pat. Nos. 8,049,252, 7,045,404, and 8,120,064, the disclosures of which are incorporated herein by reference in their entireties. A second insulating layer 355 may be formed on the first insulating layer 350 and on predetermined portions of the drain contact 154, the gate contact 152, and the source contact 156.

[0125]

[0157] In some embodiments, field plate 360 ​​may be formed on second insulating layer 355. At least a portion of field plate 360 ​​may be on gate contact 152. At least a portion of field plate 360 ​​may be on a portion of second insulating layer 355 that is between gate contact 152 and drain contact 154. Field plates and techniques for forming field plates are discussed by way of example in U.S. Pat. No. 8,120,064, the disclosure of which is incorporated herein by reference in its entirety.

[0126]

[0158] In some embodiments, metal contacts 365 may be deposited within second insulating layer 355. Metal contacts 365 may provide interconnections between drain contact 154, gate contact 152, and source contact 156 and other portions of the HEMT device. Each metal contact of metal contacts 365 may directly contact a respective contact of drain contact 154 and / or source contact 156. Metal contacts 365 may comprise a metal or other highly conductive material, including, for example, copper, cobalt, gold, and / or composite metals.

[0127]

[0159] Various embodiments have been described herein with reference to the accompanying drawings in which exemplary embodiments are shown. However, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Various modifications to the exemplary embodiments, as well as the general principles and features described herein, will be readily apparent. In the drawings, the sizes and relative sizes of layers and regions are not shown to scale and, in some instances, may be exaggerated for clarity.

[0128]

[0160] Although the terms "first," "second," etc. may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be referred to as a second element, and similarly, a second element could be referred to as a first element, without departing from the scope of the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0129]

[0161] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and / or "including," as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0130]

[0162] Unless otherwise specified, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and related technology, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0131]

[0163] When an element, such as a layer, region, or substrate, is referred to as being "on," "attached," or "extending onto" another element, it will be understood that it can be directly on top of other elements or intervening elements, which may be present. In contrast, when an element is referred to as being "directly on," or "directly attached," or extending "directly onto," another element, there are no intervening elements present. When an element is referred to as being "connected" or "coupled" to another element, it will also be understood that it can be directly connected to or coupled to other elements or intervening elements, which may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0132]

[0164] Relative terms such as "below," "above," "upper," "lower," "horizontal," "lateral," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0133]

[0165] Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. Thus, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but should include, for example, deviations in shapes that result from manufacturing. Elements shown in dotted lines may be optional in the illustrated embodiments.

[0134]

[0166] Like numbers refer to like elements throughout. As such, the same or similar numbers may be described with reference to other drawings even if they are not mentioned or described in the corresponding drawings. Likewise, elements not indicated by reference numbers may be described with reference to other drawings.

[0135]

[0167] In the drawings and specification, exemplary embodiments of the invention have been disclosed, and although specific terms are used, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the appended claims.

Claims

1. 1. A transistor amplifier package comprising: a package substrate having a conductive pattern exposed by a solder mask pattern on a surface of the package substrate; and at least one transistor die comprising a semiconductor structure attached to the surface of the package substrate by a solder material and aligned by the solder mask pattern, whereby a respective gate, drain, and / or source terminal of the at least one transistor die is electrically connected to a respective one of the conductive patterns.

2. The at least one transistor die includes: a patterned backside metal layer on a lower surface of the semiconductor structure, the patterned backside metal layer comprising the respective gate, drain, and / or source terminals; 10. The transistor amplifier package of claim 1, further comprising a barrier metal layer between said patterned backside metal layer and said solder material on said front surface of said substrate.

3. The transistor amplifier package of claim 2 , wherein the barrier metal layer comprises at least one of nickel, titanium, and / or alloys thereof.

4. The at least one transistor die includes: a plurality of conductive pillars on a top surface of the semiconductor structure adjacent to transistor active areas and electrically coupled to the respective gate, drain, and / or source terminals; The transistor amplifier package of claim 1 , wherein the solder material is between the conductive pillars and the surface of the substrate.

5. 5. The transistor amplifier package of claim 1, further comprising one or more discrete passive electrical components attached to the surface of the package substrate by the solder material and aligned by the solder mask pattern.

6. 6. The transistor amplifier package of claim 5, wherein the one or more discrete passive electrical components and / or the at least one transistor die are spaced apart from one another by respective gaps of less than about 0.25 mm or between about 0.25 mm and about 0.1 mm.

7. 6. The transistor amplifier package of claim 5, wherein respective terminals of the one or more discrete passive electrical components are electrically connected to the respective gate, drain, and / or source terminals of the at least one transistor die by respective ones of the conductive patterns.

8. at least one of the respective gate, drain, and / or source terminals is on an upper surface of the semiconductor structure adjacent a transistor active area; 6. The transistor amplifier package of claim 5, further comprising at least one wire bond electrically connecting at least one of the respective gate, drain, and / or source terminals on the top surface to a respective terminal of the one or more discrete passive electrical components.

9. The transistor amplifier package of claim 5 , wherein the one or more discrete passive electrical components define a portion of an input, interstage, or output impedance matching circuit or a harmonic termination circuit.

10. 10. The transistor amplifier package of claim 1, wherein the conductive pattern provides respective leads for radio frequency ("RF") signal connections that are substantially coplanar with the surface of the package substrate having the at least one transistor die attached to the package substrate.

11. 11. The transistor amplifier package of claim 10, wherein the package substrate comprises an electrical insulating member, and wherein each of the leads has no electrical connections extending substantially beyond an edge of the electrical insulating member.

12. 11. The transistor amplifier package of claim 10, wherein the conductive pattern comprises an embedded conductive member extending through the electrically insulating member, and a source terminal of the at least one transistor die is attached to the embedded conductive member by the solder material at the surface of the package substrate.

13. The transistor amplifier package of claim 12 wherein the package is free of a thermally conductive package submount.

14. a thermally conductive package submount having the package substrate on the thermally conductive package submount; 13. The transistor amplifier package of claim 12, wherein the respective leads do not extend substantially beyond an edge of the thermally conductive package submount.

15. The transistor amplifier package of any one of claims 1 to 14, further comprising an environmental protection layer conformally extending over one or more surfaces of the at least one transistor die.

16. 16. The transistor amplifier package of claim 15, wherein there is no overmold or lid member over the at least one transistor die.

17. A transistor amplifier package according to any preceding claim, which is wire bond free.

18. 1. A transistor amplifier, comprising: a substrate having a conductive pattern on a surface of the substrate; at least one transistor die comprising a semiconductor structure and a patterned backside metal layer on a lower surface of the semiconductor structure, the patterned backside metal layer being attached to the surface of the substrate by a solder material, whereby respective gate, drain, and / or source terminals of the at least one transistor die are electrically connected to respective ones of the conductive patterns; a barrier metal layer between the patterned backside metal layer and the solder material.

19. 20. The transistor amplifier of claim 18, wherein the barrier metal layer comprises at least one of nickel, titanium, and / or alloys thereof.

20. 20. The transistor amplifier of claim 19, wherein the bottom surface comprises silicon carbide and the backside metal layer comprises gold.

21. The transistor amplifier of any one of claims 18 to 20, wherein the conductive pattern is exposed at the surface of the substrate by a solder mask pattern, and the at least one transistor die is aligned by the solder mask pattern.

22. 22. The transistor amplifier of claim 21, wherein the conductive pattern provides respective leads for radio frequency ("RF") signal connections that are substantially coplanar with the surface of the substrate having the at least one transistor die attached to the substrate.

23. 23. The transistor amplifier of claim 22, wherein the substrate comprises an electrically insulating member, the conductive pattern comprises an embedded conductive member extending through the electrically insulating member, and a source terminal of the at least one transistor die is attached to the embedded conductive member by the solder material at the surface of the substrate.

24. 24. The transistor amplifier of claim 23, wherein the substrate is a radio frequency ("RF") circuit board, the RF circuit board mounted on a conductive heat sink member electrically connected to the embedded conductive member opposite the at least one transistor die.

25. 24. The transistor amplifier of claim 23, wherein the substrate is a package substrate of a radio frequency ("RF") transistor amplifier package, and the leads do not extend beyond an edge of the electrical insulation member.

26. further comprising an RF circuit board having an opening thereon; 26. The transistor amplifier of claim 25, wherein the RF transistor amplifier package is mounted in the opening in the RF circuit board, whereby the package substrate is enclosed within the opening.

27. 27. The transistor amplifier of claim 26, further comprising one or more conductive surface mount components extending beyond the edge of the electrically insulating member and electrically connecting the respective leads to conductive traces on a surface of the RF circuit board outside the opening.

28. 28. The transistor amplifier of claim 27, wherein the surface of the package substrate is substantially coplanar with the surface of the RF circuit board outside the opening.

29. 30. The transistor amplifier of claim 28, wherein the RF circuit board is mounted on a conductive heat sink member exposed by the opening in the RF circuit board.

30. 30. The transistor amplifier of claim 29, wherein the conductive heat sink member comprises a substantially planar surface, and the package substrate is mounted on the conductive heat sink member without a thermally conductive package submount between the package substrate and the conductive heat sink member.

31. 30. The transistor amplifier of claim 29, wherein the RF transistor amplifier package comprises a thermally conductive package submount having the package substrate on the thermally conductive package submount, and the conductive heat sink member comprises a recess in the conductive heat sink member sized to receive the thermally conductive package submount.

32. 27. The transistor amplifier of claim 26, wherein the RF circuit board comprises fewer or more conductive layers than the one or more conductive layers of the package substrate.

33. A transistor amplifier according to any one of claims 21 to 32, further comprising one or more discrete passive electrical components attached to the surface of the substrate by the solder material and aligned by the solder mask pattern.

34. 34. The transistor amplifier of claim 33, wherein the one or more discrete passive electrical components and / or the at least one transistor die are spaced apart from one another by respective gaps of less than about 0.25 mm or between about 0.25 mm and about 0.1 mm.

35. 1. A transistor amplifier, comprising: a substrate having a conductive pattern exposed by a solder mask pattern at a surface of the substrate and providing respective leads for signal connections; at least one transistor die comprising a semiconductor structure attached to the surface of the substrate by a solder material; one or more discrete passive electrical components attached to the surface of the substrate by the solder material; the one or more discrete passive electrical components and / or the at least one transistor die are spaced from one another on the surface of the substrate by respective gaps of less than about 0.25 mm.

36. 36. The transistor amplifier of claim 35, wherein the respective gaps are between about 0.25 mm and about 0.1 mm, or between about 0.1 mm and about 0.05 mm.

37. 36. The transistor amplifier of claim 35, wherein the one or more discrete passive electrical components define a portion of an input, interstage, or output impedance matching circuit or a harmonic termination circuit.

38. 36. The transistor amplifier of claim 35, wherein the conductive pattern provides respective leads for radio frequency ("RF") signal connections that are substantially coplanar with the surface of the substrate having the at least one transistor die attached to the substrate.

39. 39. The transistor amplifier of claim 38, wherein the substrate comprises an electrically insulating member, the conductive pattern comprises an embedded conductive member extending through the electrically insulating member, and terminals of the at least one transistor die are attached to the embedded conductive member by the solder material at the surface of the substrate.

40. 40. The transistor amplifier of claim 39, wherein the substrate is a package substrate of an RF transistor amplifier package, and wherein the respective leads do not extend beyond an edge of the electrically insulating member.

41. further comprising an RF circuit board having an opening thereon; 41. The transistor amplifier of claim 40, wherein the RF transistor amplifier package is mounted in the opening in the RF circuit board, whereby the package substrate is enclosed within the opening.

42. 42. The transistor amplifier of claim 41, further comprising one or more conductive surface mount components extending beyond the edge of the electrically insulating member and electrically connecting the respective leads to conductive traces on a surface of the RF circuit board outside the opening.

43. 1. A method of making a transistor amplifier package, comprising: providing a plurality of package substrates, each package substrate having a conductive pattern exposed by a solder mask pattern on a surface of the respective package substrate; applying solder material to the respective surfaces of the package substrate using a stencil on the package substrate; providing at least one transistor die comprising a semiconductor structure on the respective surface of the package substrate; performing a solder reflow process to attach and align the at least one transistor die on the respective surfaces, whereby a gate, drain, and / or source terminal of each of the at least one transistor die is electrically connected to a respective one of the conductive patterns.

44. The at least one transistor die comprises a patterned backside metal layer on a lower surface of the semiconductor structure, the patterned backside metal layer comprising the respective gate, drain, and / or source terminals, and a barrier metal layer on the patterned backside metal layer, and the step of providing the at least one transistor die comprises:

44. The method of claim 43, comprising providing the at least one transistor die on the respective front surface of the package substrate, whereby the barrier metal layer is between the patterned backside metal layer and the solder material.

45. 45. The method of claim 44, wherein the barrier metal layer comprises at least one of nickel, titanium, and / or alloys thereof.

46. The at least one transistor die comprises a plurality of conductive pillars on a top surface of the semiconductor structure adjacent to a transistor active area and electrically coupled to the respective gate, drain, and / or source terminals, and the step of providing the at least one transistor die comprises:

44. The method of claim 43, comprising providing the at least one transistor die such that the solder material is between the conductive pillars and the respective surface of the package substrate.

47. providing one or more discrete passive electrical components on the respective surfaces of the package substrates prior to performing a solder reflow process; 44. The method of claim 43, wherein the solder reflow process attaches and aligns the one or more discrete passive electrical components on the respective surfaces.

48. 48. The method of claim 47, wherein in response to performing the solder reflow process, the one or more discrete passive electrical components and / or the at least one transistor die are spaced apart from one another on the respective package substrate by respective gaps of less than about 0.25 mm or between about 0.25 mm and about 0.1 mm.

49. The package substrates are connected within a panel; 49. The method of any one of claims 43 to 48, further comprising singulating the panel after performing the solder reflow process to define each of the RF transistor amplifier packages comprising the package substrate.

50. 50. The method of claim 49, wherein the conductive pattern provides respective leads for radio frequency ("RF") signal connections that are substantially coplanar with the respective surfaces of the package substrate.

51. 51. The method of claim 50, wherein each of the package substrates comprises an electrical insulating member, and wherein after singulating the panel, each of the leads has no electrical connections extending substantially beyond an edge of the electrical insulating member.

52. 52. The method of any one of claims 43 to 51, further comprising forming an environmental protection layer that conformally extends over one or more surfaces of the at least one transistor die.

53. 53. The transistor amplifier package, transistor amplifier, or method of any one of claims 43-52, wherein the at least one transistor die comprises a radio frequency ("RF") transistor die.

Images