Carbon supplementation of silicon-containing materials

Abstract

An exemplary method of semiconductor processing may include etching a portion of a silicon-containing material from a substrate disposed in a processing region of a semiconductor processing chamber. The silicon-containing material may extend into one or more recesses defined by alternating layers of material deposited on the substrate. The method may include providing a carbon-containing precursor in the processing region of the semiconductor processing chamber. The method may include contacting the remaining silicon-containing material with the carbon-containing precursor. Contact with the carbon-containing precursor may replenish carbon within the silicon-containing material. The method may include providing a cleaning agent in the processing region of the semiconductor processing chamber. The method may include contacting the substrate with the cleaning agent. Contact with the cleaning agent may remove surface oxides from the substrate.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. patent application entitled "CARBON REPLENISHMENT OF SILICON-CONTAINING MATERIAL," filed October 5, 2022, the entire contents of which are incorporated herein by reference.

[0002] Technical Field

[0002] The present technology relates to methods and systems for semiconductor processing. More particularly, the present technology relates to systems and methods for replenishing carbon within silicon-containing materials after etching processes. [Background technology]

[0003]

[0003] Integrated circuits are made possible by processes that form intricately patterned layers of material on substrate surfaces. Fabricating patterned materials on substrates requires controlled methods for forming and removing material. As devices become increasingly smaller, film properties can have a greater impact on device performance. The materials used to form material layers can affect the operating characteristics of the fabricated devices. As material thicknesses continue to decrease, the as-deposited properties of films can have a greater impact on device performance.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technology addresses these and other needs. Summary of the Invention

[0005] An exemplary method of semiconductor processing may include etching a portion of a silicon-containing material from a substrate disposed in a processing region of a semiconductor processing chamber. The silicon-containing material may extend into one or more recesses defined by alternating layers of material deposited on the substrate. The method may include providing a carbon-containing precursor in the processing region of the semiconductor processing chamber. The method may include contacting the remaining silicon-containing material with the carbon-containing precursor. Contact with the carbon-containing precursor may replenish carbon within the silicon-containing material. The method may include providing a cleaning agent in the processing region of the semiconductor processing chamber. The method may include contacting the substrate with the cleaning agent. Contact with the cleaning agent may remove surface oxides from the substrate.

[0006] In some embodiments, the silicon-containing material may be a material containing silicon and oxygen. The silicon-containing material may be a material containing silicon, oxygen, and carbon. The method may include generating a plasma of a carbon-containing precursor. Contacting the remaining silicon-containing material with the carbon-containing precursor may include contacting the remaining silicon-containing material with plasma effluents of the carbon-containing precursor. The plasma power may be less than or about 3000 W. The carbon-containing precursor can be or include hexamethyldisilazane (HMDS), tetramethyldisilazane (TMDS), trimethylchlorosilane (TMCS), dimethyldichlorosilane (DMDCS), methyltrichlorosilane (MTCS), trimethylmethoxysilane (TMMS) (CH3-O-Si-(CH3)3), dimethyldimethoxysilane (DMDMS) ((CH3)2-Si-(OCH3)2), methyltrimethoxysilane (MTMS) ((CH3-O)3-Si-CH3), phenyltrimethoxysilane (PTMOS) (C6H5-Si-(OCH3)3), phenyldimethylchlorosilane (PDMCS) (C6H5-Si(Cl)-(CH3)2), dimethylaminotrimethylsilane (DMATMS) ((CH3)2-N-Si-(CH3)3), or bis(dimethylamino)dimethylsilane (BDMADMS). The method may include exposing the substrate to ultraviolet (UV) radiation before providing the cleaning agent into the processing region of the semiconductor processing chamber. The contacting of the remaining silicon-containing material with the carbon-containing precursor and the exposing of the substrate to ultraviolet (UV) radiation may occur simultaneously. The UV irradiance output is about 100 W / m 2 and approximately 2000 W / m 2 The UV wavelength may be characterized as being between about 100 nm and about 400 nm. The temperature in the semiconductor processing chamber may be less than or about 500°C.

[0007] Some embodiments of the present technology include a semiconductor processing method. The method may include providing a carbon-containing precursor within a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The silicon-containing material may extend within one or more recesses defined by alternating layers of material deposited on the substrate. An exposed surface of the silicon-containing material may be characterized by a first carbon concentration. The method may include contacting the silicon-containing material with the carbon-containing precursor. The contacting may increase the first carbon concentration to a second carbon concentration. The method may include providing a cleaning agent within the processing region of the semiconductor processing chamber. The method may include contacting the substrate with the cleaning agent. The cleaning agent may remove surface oxides from the substrate.

[0008] In some embodiments, the method may include providing one or more etchant precursors to a processing region of a semiconductor processing chamber, contacting a substrate with the one or more etchant precursors, and etching a portion of the silicon-containing material from the substrate. The cleaning agent may be or may include dilute hydrofluoric acid. The second carbon concentration may be greater than or about 5 at.% higher than the first carbon concentration. The silicon-containing material may be an internal spacer of a gate-all-around structure. The method may include exposing the substrate to ultraviolet (UV) radiation.

[0009] Some embodiments of the present technology include a semiconductor processing method. The method may include providing a carbon-containing precursor within a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region. The silicon-containing material may extend within one or more recesses defined by alternating layers of material deposited on the substrate. An exposed surface of the silicon-containing material may be characterized by a first carbon concentration. The method may include contacting the silicon-containing material with the carbon-containing precursor. The contacting may increase the first carbon concentration to a second carbon concentration. The method may include exposing the substrate to ultraviolet (UV) radiation. The method may include providing a cleaning agent within the processing region of the semiconductor processing chamber. The method may include contacting the substrate with the cleaning agent. The cleaning agent may remove surface oxides from the substrate.

[0010] In some embodiments, contacting the silicon-containing material with the carbon-containing precursor and exposing the substrate to ultraviolet (UV) radiation can occur simultaneously. The second carbon concentration can be greater than or about 20 at.%. The temperature in the semiconductor processing chamber can be greater than or about 200°C.

[0011] Such techniques may provide numerous advantages over conventional systems and techniques. For example, embodiments of the present technique may enhance the carbon concentration of carbon-depleted materials. Additionally, the present technique may enhance resistance to subsequent etching processes. The enhanced resistance may enable subsequent etching processes on the structure that reduce or eliminate removal of carbon-enriched process material. These and other embodiments, along with their numerous advantages and features, are described in further detail below in conjunction with the description and accompanying drawings.

[0012] A further understanding of the nature and advantages of the techniques of the present disclosure may be gained by reference to the remainder of this specification and the following drawings. [Brief explanation of the drawings]

[0013] [Figure 1]1 illustrates a top view of an exemplary processing system in accordance with some embodiments of the present technique. [Figure 2]

[0014] 1 shows a schematic cross-sectional view of an exemplary plasma deposition system in accordance with some embodiments of the present technique; [Figure 3]

[0015] 1 illustrates steps in a semiconductor processing method in accordance with some embodiments of the present technique. [Figure 4A-4B]

[0016] 1 illustrates a cross-sectional view of a substrate during processing according to an embodiment of the present technique; DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0017] Some drawings are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless expressly stated to be to scale. Furthermore, as schematic diagrams, the drawings are provided to aid in understanding and may not include all aspects or information compared to realistic depictions and may include exaggerated material for illustrative purposes.

[0015]

[0018] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numeral, with a letter distinguishing between the similar components. When only a first reference numeral is used herein, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letter.

[0016]

[0019] As semiconductor devices continue to shrink, the constituent films contained within the structures, as well as the fabrication of other materials contained within the devices, can affect device performance. Furthermore, increasing demand places a premium on throughput and latency. This necessitates high-quality materials and structures that can be formed quickly and efficiently. However, in processes for forming conformal, low-k silicon-containing materials, such as for gate-all-around (GAA) applications, high conformality and low dielectric constants can result in low resistance during subsequent etching processes. Carbon depletion in silicon-containing materials during trimming and other removal processes can result in the complete removal of the silicon-containing materials during etching processes, such as cleaning processes using wet etchants.

[0017]

[0020] To further improve conformality and lower the dielectric constant, conventional techniques may modify the deposition precursors and deposit alternative materials, such as silicon-, oxygen-, and carbon-containing materials. While these techniques may be effective in depositing high-quality materials, they may have poor resistance to some etchant materials, resulting in complete removal of the material in subsequent processing.

[0018]

[0021] The present technology overcomes these problems by intermittently processing silicon-containing materials with high conformality and low dielectric constants. After several dry etching processes, such as spacer trimming or dummy gate removal in a GAA process, the remaining silicon-containing material can be treated with a carbon-containing precursor and / or ultraviolet (UV) radiation. These treatments can return depleted carbon to the silicon-containing material and increase the material's resistance to subsequent wet etching processes.

[0019]

[0022] While the remainder of the disclosure routinely identifies particular processes utilizing the disclosed technology, it will be readily understood that the systems and methods are equally applicable to other deposition and etch processes that may occur in the described chambers or any other chambers. Thus, the present technology should not be considered limited to use with these particular deposition processes or chambers alone. This disclosure describes one set of possible chambers that may be used to perform processes in accordance with embodiments of the present technology before describing additional modifications and adaptations of this system in accordance with embodiments of the present technology.

[0020]

[0023] 1 illustrates a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100, according to an embodiment. In the figure, a pair of front-opening unified pods 102 supply substrates of various sizes that are received by a robotic arm 104 and placed in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a-108f positioned in tandem sections 109a-109c. A second robotic arm 110 may be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-108f. Each substrate processing chamber 108a-f may be equipped to perform multiple substrate processing operations, including plasma-enhanced chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, alignment, and the formation of semiconductor material stacks as described herein, in addition to other substrate processes including annealing, ashing, and the like.

[0021]

[0024] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a dielectric or other film on a substrate. In one configuration, two pairs of processing chambers (e.g., 108c-d and 108e-f) may be used to deposit a dielectric material on a substrate, and a third pair of processing chambers (e.g., 108a-b) may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers (e.g., 108a-f) may be configured to deposit an alternating stack of dielectric films on a substrate. Any one or more of the described processes may be performed in chambers separate from the fabrication system shown in various embodiments. It will be understood that additional configurations of deposition chambers, etch chambers, annealing chambers, and curing chambers for dielectric films are contemplated by system 100.

[0022]

[0025] 2 shows a schematic cross-sectional view of an exemplary plasma system 200 in accordance with some embodiments of the present technique. The plasma system 200 may illustrate a pair of processing chambers 108 attached to one or more of the tandem sections 109 described above and may include faceplates or other components or assemblies in accordance with embodiments of the present technique. The plasma system 200 may generally include a chamber body 202 having a sidewall 212, a bottom wall 216, and an interior sidewall 201 that define a pair of processing regions 220A and 220B. Each of the processing regions 220A-220B may be similarly configured and may include identical components.

[0023]

[0026] For example, processing region 220B (components of which may also be included in processing region 220A) may include a pedestal 228 disposed within the processing region through a passage 222 formed in the bottom wall 216 of the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on an exposed surface of the pedestal, such as a body portion. The pedestal 228 may include a heating element 232, e.g., a resistive heating element, which may heat and control the substrate temperature at a desired processing temperature. The pedestal 228 may be heated by a remote heating element, such as a lamp assembly, or other heating device.

[0024]

[0027] The body of the pedestal 228 may be coupled to the stem 226 by a flange 233. The stem 226 may electrically couple the pedestal 228 to a power output or power box 203. The power box 203 may include a driver system that controls the elevation and movement of the pedestal 228 within the processing region 220B. The stem 226 may also include a power interface for supplying power to the pedestal 228. The power box 203 may also include an interface for a power meter and a thermometer, such as a thermocouple interface. The stem 226 may include a base assembly 238 adapted to removably couple to the power box 203. A circumferential ring 235 is shown above the power box 203. In some embodiments, the circumferential ring 235 may be a shoulder adapted as a mechanical stop or land configured to provide a mechanical interface between the base assembly 238 and the top surface of the power box 203.

[0025]

[0028] A rod 230 may be included through a passage 224 formed in the bottom wall 216 of the processing region 220B and may be utilized to position substrate lift pins 261 disposed through the body of the pedestal 228. The substrate lift pins 261 may selectively space the substrate 229 from the pedestal to facilitate exchange of the substrate 229 by a robot utilized to transfer substrates in and out of the processing region 220B through the substrate transfer port 260.

[0026]

[0029] The chamber lid 204 may be coupled to the top of the chamber body 202. The lid 204 may house one or more precursor delivery systems 208 coupled thereto. The precursor delivery system 208 may include a precursor injection passage 240, which may deliver reactants and cleaning agents into the processing region 220B through a gas delivery assembly 218. The gas delivery assembly 218 may include a gas box 248 having a shielding plate 244 disposed intermediate a faceplate 246. A radio frequency (“RF”) source 265 may be coupled to the gas delivery assembly 218, which may provide power to the gas delivery assembly 218 to facilitate generating a plasma region between the faceplate 246 of the gas delivery assembly 218 and a pedestal 228, which may be the processing region of the chamber. In some embodiments, the RF source may be coupled to other parts of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. A dielectric isolator 258 may be disposed between the lid 204 and the gas delivery assembly 218 to prevent conduction of RF power to the lid 204. A shadow ring 206 that engages the pedestal 228 may be disposed on the outer edge of the pedestal 228.

[0027]

[0030] Optional cooling channels 247 may be formed in the gas box 248 of the gas distribution system 208 to cool the gas box 248 during processing. A heat transfer fluid, such as water, ethylene glycol, gas, or the like, may be circulated through the cooling channels 247 so that the gas box 248 may be maintained at a predetermined temperature. A liner assembly 227 may be positioned in the processing region 220B in close proximity to the sidewalls 201, 212 of the chamber body 202 to prevent exposure of the sidewalls 201, 212 to the processing environment in the processing region 220B. The liner assembly 227 may include a circumferential pumping cavity 225 that may be coupled to a pumping system 264 configured to exhaust gases and byproducts from the processing region 220B and to control the pressure within the processing region 220B. A plurality of exhaust ports 231 may be formed in the liner assembly 227. The exhaust outlet 231 can be configured to allow gases to flow from the processing region 220B to the circumferential pumping cavity 225 in a manner that facilitates processing within the system 200.

[0028]

[0031] FIG. 3 illustrates exemplary processes in a semiconductor processing method 300 in accordance with some embodiments of the present technique. The method may be performed in a variety of processing chambers, including the system 200 described above. The method 300 may include one or more processes prior to the initiation of the described method processes, including front-end processes, deposition, etching, polishing, cleaning, or any other processes that may be performed prior to the described processes. The method may include numerous optional processes as illustrated in the figure that may or may not be specifically related to methods in accordance with the present technique. For example, many of the processes are described to provide a broader scope of semiconductor processing, but are not critical to the present technique, or may be implemented by alternative methodologies, as described further below.

[0029]

[0032] Method 300 may include any operations for developing a semiconductor structure into a particular fabrication process. In some embodiments, method 300 may be performed on a base structure, while in some embodiments, the method may be performed subsequent to the formation or removal of other materials. For example, any number of deposition, masking, and removal processes may be performed to fabricate any transistor, memory, or other structural feature on the substrate. The substrate may be disposed on a substrate support, which may be positioned within a processing region of a semiconductor processing chamber. The processes may be performed in the same chamber in which aspects of method 300 may be performed, or one or more processes may also be performed in one or more chambers on the same platform as the chamber in which aspects of method 300 may be performed, or on another platform. Method 300 describes the process shown generally in FIGS. 4A-4B, and that illustration will be described in conjunction with the process of method 300. It should be understood that FIGS. 4A-4B are only partial schematic views, and that a substrate may include any number of transistor sections having the features illustrated in the figures.

[0030]

[0033] As shown in FIG. 4A , the structure 400 may include a substrate 405. The substrate 405 may be made of or may include silicon or other semiconductor substrate materials. One or more layers of materials may be formed on the substrate 405. For example, alternating layers of materials 104 may be deposited on the substrate 405. The alternating layers of materials may include, for example, a silicon layer 410 and a silicon germanium layer 415. The silicon germanium layer 415 may be etched selectively relative to the silicon layer 410 in previous processing to form one or more recesses defined by the alternating layers of materials. A dummy gate 425 (which may be replaced with silicon in subsequent processing) may be deposited on the alternating layers of silicon layer 410 and silicon germanium layer 415. The dummy gate 425 may be a silicon material and may be separated from the alternating layers of materials by a silicon oxide layer 420. Similarly, a silicon oxide layer 430 may be formed on the dummy gate 425. Spacers 435 may be formed on the substrate 405 overlying the aforementioned materials. The spacers 435 may extend into one or more recesses defined by the alternating layers of materials deposited on the substrate.

[0031]

[0034] The spacers 435 may be a silicon-containing material, such as a low-k material. For example, the spacers 435 may be a silicon- and oxygen-containing material or a silicon-, oxygen-, and carbon-containing material. Because silicon-containing conformal materials, such as silicon- and oxygen-containing materials or silicon-, oxygen-, and carbon-containing materials, exhibit lower dielectric constants than other conformal materials, these silicon-containing materials are useful for gate-all-around (GAA) applications. The silicon-containing material of the spacers 435 may have a dielectric constant of less than or about 5.0. Furthermore, the silicon-containing material of the spacers 435 may have a conformality of greater than or about 90%. However, as described below, subsequent GAA processing may utilize wet etchants, and these silicon-containing materials may have poor resistance to these wet etchants or cleaning agents. This poor resistance has made it difficult to use these low-k conformal materials.

[0032]

[0035] In optional step 305, method 300 may include providing one or more etchant precursors to a processing region of the semiconductor processing chamber. The etchant precursors may include, for example, a hydrogen-containing precursor, a nitrogen-containing precursor, an oxygen-containing precursor, or other conventional semiconductor precursors used to remove silicon-containing materials. In one example, the one or more etchant precursors may include diatomic hydrogen and diatomic nitrogen. In another example, the one or more etchant precursors may include diatomic hydrogen and molecular oxygen. In embodiments, method 300 may include forming a plasma of the one or more etchant precursors to increase bombardment and removal of silicon-containing materials of spacers 435.

[0033]

[0036] In step 310, method 300 may include contacting substrate 405 with one or more etchant precursors. Method 300 may include etching portions of silicon-containing material, referred to as spacers 435, from substrate 405. As shown in FIG. 4B , one or more etchant precursors may contact substrate 405 and remove portions of spacers 435, i.e., silicon-containing material, from substrate 405. The etching may leave portions of the silicon-containing material of spacers 435, for example, portions that extend into one or more recesses defined by alternating layers of material. Specifically, the remaining silicon-containing material of spacers 435 may be material from recesses formed in silicon germanium layer 415. In embodiments, step 310 may be an inner spacer trim step in a GAA process. In other embodiments, method 300 may include etching dummy gate 425 so that dummy gate 425 may be replaced with a metal material.

[0034]

[0037] During etching of the silicon-containing material of the spacers 435 or during removal of the dummy gate 425, the spacers 435 may be depleted of carbon. Prior to step 310, the exposed surfaces of the silicon-containing material of the spacers 435 may be characterized by a carbon concentration of greater than or about 15 at.%, e.g., greater than or about 16 at.%, greater than or about 16 at.%, greater than or about 17 at.%, greater than or about 18 at.%, greater than or about 19 at.%, greater than or about 20 at.%, greater than or about 21 at.%, greater than or about 22 at.%, greater than or about 23 at.%, greater than or about 24 at.%, greater than or about 25 at.%, or more. During step 310, carbon may be removed at a faster rate relative to other elements, such as silicon, oxygen, and other elements, contained in the silicon-containing material of spacers 435. Carbon may be generated during etching of the silicon-containing material of spacers 435. After step 310, the silicon-containing material of spacers 435 may be characterized by a carbon concentration of less than or about 15 at.%, less than or about 14 at.%, less than or about 13 at.%, less than or about 12 at.%, less than or about 11 at.%, less than or about 10 at.%, or less.

[0035]

[0038] Conversely, the oxygen concentration in the silicon-containing material of spacers 435 may increase during step 310, which may be due to the interaction of one or more etchant precursors, such as oxygen-containing precursors, with the silicon-containing material of spacers 435.

[0036]

[0039] In step 315, the method 300 may include providing a carbon-containing precursor to a processing region of the semiconductor processing chamber. The carbon-containing precursor may be any precursor containing carbon and may also contain silicon and / or oxygen. In embodiments, the carbon-containing precursor is hexamethyldisilazane (HMDS), tetramethyldisilazane (TMDS), trimethylchlorosilane (TMCS), dimethyldichlorosilane (DMDCS), methyltrichlorosilane (MTCS), trimethylmethoxysilane (TMMS) (CH3-O-Si-(CH3)3), dimethyldimethoxysilane (DMDMS) ((CH3)2-Si-(OCH3)2), methyltrimethoxysilane (MTMS) ((CH3-O )3-Si-CH3), phenyltrimethoxysilane (PTMOS) (C6H5-Si-(OCH3)3), phenyldimethylchlorosilane (PDMCS) (C6H5-Si(Cl)-(CH3)2), dimethylaminotrimethylsilane (DMATMS) ((CH3)2-N-Si-(CH3)3), or bis(dimethylamino)dimethylsilane (BDMADMS), as well as any other carbon-containing precursor that may be used in semiconductor processing. The precursor may or may not include delivery of additional precursors, such as one or more carrier gases to aid the flow of the carbon-containing precursor. Carrier gases may include helium, argon, or diatomic nitrogen.

[0037]

[0040] In embodiments, method 300 may include generating a plasma of the carbon-containing precursor. The carbon-containing precursor plasma effluent may be generated at a plasma power of less than or about 3000 W, less than or about 2750 W, less than or about 2500 W, less than or about 2250 W, less than or about 2000 W, less than or about 1750 W, less than or about 1500 W, less than or about 1250 W, less than or about 1000 W, less than or about 750 W, less than or about 500 W, less than or about 250 W, or less than or about 250 W. While some embodiments may generate a plasma of the carbon-containing precursor, other embodiments may include a thermal process that does not include generating a plasma of the carbon-containing precursor.

[0038]

[0041] In step 320, method 300 may include contacting the remaining silicon-containing material of spacers 435 with a carbon-containing precursor or its plasma effluent. Contacting the remaining silicon-containing material of spacers 435 with the carbon-containing precursor may introduce carbon into the silicon-containing material of spacers 435. The introduction and contacting of carbon in step 320 may replace carbon depleted during etching of the silicon-containing material of the liner in step 310. The carbon-containing compound may be provided in a vapor phase, which may allow the carbon-containing precursor to penetrate deeply into the remaining silicon-containing material of spacers 435. The vaporized carbon-containing precursor may be vaporized before being provided to the processing region in step 315, or may be vaporized in the processing region.

[0039]

[0042] In step 320, the remaining silicon-containing material of spacers 435 can be contacted with a carbon-containing precursor or its plasma effluent to increase the carbon concentration in the silicon-containing material of spacers 435. The carbon concentration may be increased to a concentration previously described, such as the concentration before step 310. For example, after step 320, the exposed surface of the silicon-containing material of spacer 435 may be characterized by a carbon concentration of greater than or about 15 at.%, e.g., greater than or about 16 at.%, greater than or about 16 at.%, greater than or about 17 at.%, greater than or about 18 at.%, greater than or about 18 at.%, greater than or about 19 at.%, greater than or about 20 at.%, greater than or about 21 at.%, greater than or about 22 at.%, greater than or about 23 at.%, greater than or about 24 at.%, greater than or about 25 at.%, or more. In an embodiment, contacting the remaining silicon-containing material of the spacers 435 with a carbon-containing precursor in step 320 can increase the carbon concentration at the exposed surfaces of the remaining silicon-containing material of the spacers 435 by greater than or about 5 at.%, e.g., greater than or about 6 at.%, greater than or about 7 at.%, greater than or about 8 at.%, greater than or about 9 at.%, greater than or about 10 at.%, or more.

[0040]

[0043] In optional step 325, method 300 may include exposing the substrate to ultraviolet (UV) radiation. The UV radiation source may be, for example, a UV lamp. The UV radiation source may be positioned outside the semiconductor processing chamber, which may have a quartz window through which the UV radiation can pass. Structure 400 may be positioned in an inert gas environment, such as helium, argon, or diatomic nitrogen. The processing semiconductor chamber may include a microwave source for heating the silicon-containing material of spacer 435 before or simultaneously with contacting the silicon-containing material with UV radiation. In embodiments, UV radiation exposure may be performed using a plasma that simulates UV radiation wavelengths. The plasma may be formed by combining RF power with a processing gas, such as helium, argon, molecular oxygen, or diatomic oxygen. Exposing the silicon-containing material of spacer 435 to UV radiation can break Si—H and / or Si—OH bonds in the material and form Si—CH—CH—Si(CH) and / or Si—O—Si(CH) bonds, thereby increasing the carbon concentration.

[0041]

[0044] During step 325, the conditions of the UV radiation can be adjusted to treat the silicon-containing material of the spacers 435. For example, the UV irradiance output can be about 100 W / m 2 and approximately 2000 W / m 2 100 W / m 2 At UV irradiance outputs below 2000W / m, the UV radiation may not be sufficient to alter the material. 2 At UV irradiance outputs above 100 nm, UV radiation may damage materials or structures. Furthermore, UV wavelengths may be characterized as being between about 100 nm and about 400 nm. UV wavelengths below 100 nm may require specialized light sources that are not commonly available. UV wavelengths above 400 nm, such as visible light, may not have enough energy to alter the aforementioned bonds.

[0042]

[0045] In some embodiments, contacting the remaining silicon-containing material of spacers 435 with the carbon-containing precursor and exposing the substrate to ultraviolet (UV) radiation may occur simultaneously. Specifically, steps 320 and 325 may be performed simultaneously to treat the remaining silicon-containing material of spacers 435. However, it is contemplated that in some embodiments, the steps may be performed sequentially.

[0043]

[0046] In step 330, the method 300 may include providing a cleaning agent to a processing region of the semiconductor processing chamber. The cleaning agent may be a wet etchant, such as a fluorine-containing cleaning agent. In embodiments, the fluorine-containing cleaning agent may be or include dilute hydrofluoric acid. In step 335, the substrate 405 is contacted with the cleaning agent. The cleaning agent may be provided to clean the structure 400 after trimming the spacers 435 or may be provided to clean the structure 400 after removing the dummy gate 425.

[0044]

[0047] Processing conditions may affect the steps performed in method 300. Each of the steps of method 300 may be performed at a constant temperature in some embodiments, and in some embodiments, the temperature may be adjusted between different steps. In some embodiments of the present technology, method 300 may be performed at substrate, pedestal, and / or chamber temperatures of less than or about 500°C, which may be due to thermal balance issues, or may be performed at temperatures of less than or about 475°C, less than or about 450°C, less than or about 425°C, less than or about 400°C, less than or about 375°C, less than or about 350°C, less than or about 325°C, less than or about 300°C, less than or about 275°C, less than or about 250°C, or lower. The temperature may further be maintained at any temperature within these ranges, narrower ranges contained within these ranges, or between any of these ranges. Forming the material at a higher temperature may increase the amount of carbon incorporated into the silicon-containing material of spacer 435 in step 320, thus improving its resistance to wet etchants. Thus, in some embodiments, the temperature may be maintained at greater than or about 200°C, greater than or about 225°C, greater than or about 250°C, greater than or about 275°C, greater than or about 300°C, greater than or about 325°C, greater than or about 350°C, or greater than or about 359°C.

[0045]

[0048] The pressure within the semiconductor processing chamber may also affect the processes performed. In embodiments, the pressure may be maintained at less than about 40 Torr. Thus, the pressure may be maintained at less than or about 35 Torr, less than or about 30 Torr, less than or about 25 Torr, less than or about 20 Torr, less than or about 18 Torr, less than or about 16 Torr, less than or about 14 Torr, less than or about 12 Torr, less than or about 10 Torr, less than or about 8 Torr, less than or about 6 Torr, less than or about 4 Torr, less than or about 2 Torr, less than or about 1 Torr, or at or below. The pressure may further be maintained at any pressure within these ranges, any narrower range contained within these ranges, or between any of these ranges.

[0046]

[0049] In conventional embodiments, the remaining silicon-containing material of spacers 435 may have a reduced carbon concentration at the exposed surfaces of the silicon-containing material, making it less resistant to the cleaning agents in step 330. In such conventional embodiments, spacers 435 may be completely removed, which may damage or destroy structure 400. Carbon may be replenished in the silicon-containing material by treating the silicon-containing material of spacers 435 with a carbon-containing precursor and / or exposing the silicon-containing material of spacers to UV radiation. Increasing the carbon concentration may make the silicon-containing material of spacers 435 more resistant to the cleaning agents and other wet etchants used in processing. Whereas conventional embodiments may begin to etch the silicon-containing material of spacer 435 immediately upon exposure to cleaning agents and other wet etchants, the present technology may resist any etching during exposure periods of greater than or about 5 seconds, e.g., greater than or about 10 seconds, greater than or about 15 seconds, greater than or about 20 seconds, greater than or about 25 seconds, greater than or about 30 seconds, greater than or about 35 seconds, greater than or about 40 seconds, or longer.

[0047]

[0050] In the above description, for purposes of explanation, numerous details are presented in order to facilitate an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that particular embodiments may be practiced without some of these details, or with additional details.

[0048]

[0051] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Additionally, in order to avoid unnecessarily obscuring the technology, some well-known processes and elements have not been described. Therefore, the above description should not be construed as limiting the scope of the technology.

[0049]

[0052] Where a range of values ​​is given, unless the context clearly dictates otherwise, each intervening value between the upper and lower limit of that range is specifically disclosed, to the smallest unit of the lower limit. Any narrower range between any stated or unstated intervening value in a stated range, and any other stated or intervening value in that stated range, is also included. The upper and lower limits of such narrower ranges may individually be included or excluded within that range. Each range in which either or both limits are included in the narrower range, or neither limit is included in the narrower range, is also encompassed within the technology and covers any specifically excluded limit in the stated range. When a stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included.

[0050]

[0053] As used in this specification and claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a precursor" includes a plurality of such precursors, reference to "the material" includes reference to one or more materials and equivalents known to those skilled in the art, and so forth.

[0051]

[0054] Additionally, the terms "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and claims, are intended to specify the presence of stated features, integers, components, or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.

Claims

1. 1. A semiconductor processing method comprising: Etching a portion of a silicon-containing material from a substrate disposed in a processing region of a semiconductor processing chamber, the silicon-containing material extending into one or more recesses defined by alternating layers of materials deposited on the substrate; providing a carbon-containing precursor to the processing region of the semiconductor processing chamber; contacting the remaining silicon-containing material with the carbon-containing precursor, wherein the contacting with the carbon-containing precursor replenishes carbon within the silicon-containing material; and providing a cleaning agent to the processing region of the semiconductor processing chamber; contacting the substrate with the cleaning agent, wherein the contact with the cleaning agent removes surface oxides from the substrate; A semiconductor processing method comprising:

2. The semiconductor processing method of claim 1 , wherein the silicon-containing material comprises a material containing silicon and oxygen.

3. The semiconductor processing method of claim 1 , wherein the silicon-containing material comprises a material containing silicon, oxygen, and carbon.

4. 10. The semiconductor processing method of claim 1, further comprising generating a plasma of the carbon-containing precursor, wherein the contacting of the remaining silicon-containing material with the carbon-containing precursor comprises contacting the remaining silicon-containing material with plasma effluents of the carbon-containing precursor.

5. 5. The semiconductor processing method of claim 4, wherein the plasma power is less than or about 3000W.

6. The carbon-containing precursor is selected from the group consisting of hexamethyldisilazane (HMDS), tetramethyldisilazane (TMDS), trimethylchlorosilane (TMCS), dimethyldichlorosilane (DMDCS), methyltrichlorosilane (MTCS), trimethylmethoxysilane (TMMS) (CH ３ —O—Si—(CH ３ ) ３ ), dimethyldimethoxysilane (DMDMS) ((CH ３ ) ２ -Si-(OCH ３ ) ２ ), methyltrimethoxysilane (MTMS) ((CH ３ -O) ３ -Si-CH ３ ), phenyltrimethoxysilane (PTMOS) (C ６ H ５ -Si-(OCH ３ ) ３ ), phenyldimethylchlorosilane (PDMCS) (C ６ H ５ -Si(Cl)-(CH ３ ) ２ ), dimethylaminotrimethylsilane (DMATMS) ((CH ３ ) ２ —N—Si—(CH ３ ) ３ ), or bis(dimethylamino)dimethylsilane (BDMADMS).

7. 10. The semiconductor processing method of claim 1, further comprising exposing the substrate to ultraviolet (UV) radiation prior to providing the cleaning material into the processing region of the semiconductor processing chamber.

8. 8. The semiconductor processing method of claim 7, wherein contacting the remaining silicon-containing material with the carbon-containing precursor and exposing the substrate to ultraviolet (UV) radiation are performed simultaneously.

9. UV irradiance output is approximately 100 W / m ２ and about 2000 W / m ２ and characterized in that the UV wavelength is between about 100 nm and about 400 nm; 8. The semiconductor processing method of claim 7.

10. 10. The semiconductor processing method of claim 1, wherein the temperature in the semiconductor processing chamber is less than or about 500°C.

11. 1. A semiconductor processing method comprising: providing a carbon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed in the processing region, a silicon-containing material extends into one or more recesses defined by alternating layers of materials deposited on the substrate, and an exposed surface of the silicon-containing material is characterized by a first carbon concentration; contacting the silicon-containing material with the carbon-containing precursor, wherein the contacting increases the first carbon concentration to a second carbon concentration; providing a cleaning agent to the processing region of the semiconductor processing chamber; contacting the substrate with the cleaning agent, wherein the cleaning agent removes surface oxides from the substrate; A method comprising:

12. providing one or more etchant precursors to the processing region of the semiconductor processing chamber; contacting the substrate with the one or more etchant precursors; Etching a portion of the silicon-containing material from the substrate; 12. The semiconductor processing method of claim 11, further comprising:

13. 12. The semiconductor processing method of claim 11, wherein the cleaning agent comprises dilute hydrofluoric acid.

14. 12. The semiconductor processing method of claim 11, wherein the second carbon concentration is greater than or about 5 at. % higher than the first carbon concentration.

15. 12. The semiconductor processing method of claim 11, wherein said silicon-containing material comprises an internal spacer of a gate-all-around structure.

16. 12. The semiconductor processing method of claim 11, further comprising exposing the substrate to ultraviolet (UV) radiation.

17. 1. A semiconductor processing method comprising: providing a carbon-containing precursor to a processing region of a semiconductor processing chamber, wherein a substrate is disposed in the processing region, a silicon-containing material extends into one or more recesses defined by alternating layers of materials deposited on the substrate, and an exposed surface of the silicon-containing material is characterized by a first carbon concentration; contacting the silicon-containing material with the carbon-containing precursor, wherein the contacting increases the first carbon concentration to a second carbon concentration; exposing the substrate to ultraviolet (UV) radiation; providing a cleaning agent to the processing region of the semiconductor processing chamber; contacting the substrate with the cleaning agent, wherein the cleaning agent removes surface oxides from the substrate; A method comprising:

18. 20. The semiconductor processing method of claim 17, wherein contacting the silicon-containing material with the carbon-containing precursor and exposing the substrate to ultraviolet (UV) radiation are performed simultaneously.

19. 20. The semiconductor processing method of claim 17, wherein the second carbon concentration is greater than or about 20 at. %.

20. 20. The semiconductor processing method of claim 17, wherein the temperature in the semiconductor processing chamber is greater than or about 200°C.

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