Isotropic Silicon Nitride Removal

Abstract

An exemplary method for etching silicon-containing materials may include flowing a first fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The method may include flowing a sulfur-containing precursor into the remote plasma region of the semiconductor processing chamber. The method may include forming a plasma in the remote plasma region to generate plasma effluents of the first fluorine-containing precursor and the sulfur-containing precursor. The method may include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned in the processing region. The substrate may include a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The method may include isotropically etching the silicon nitride layer while substantially preserving the silicon oxide.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of and priority to U.S. Patent Application No. 17 / 963,687, filed October 11, 2022, entitled "ISOTROPIC SILICON NITRIDE REMOVAL," which is incorporated herein by reference in its entirety.

[0002] The present technology relates to semiconductor processes and equipment, and more particularly to isotropically etching materials relative to other materials. [Background technology]

[0003] Integrated circuits are made possible by processes that fabricate intricately patterned layers of material on a substrate surface. Fabricating patterned materials on a substrate requires a controlled method for removing exposed material. Chemical etching is used for a variety of purposes, including transferring a photoresist pattern to an underlying layer, thinning a layer, or thinning the lateral dimensions of features already present on a surface. It is often desirable to have an etching process that etches one material faster than another, for example, to facilitate the pattern transfer process. Such an etching process is said to be selective to the first material. As a result of the diversity of materials, circuits, and processes, etching processes selective to a variety of materials have been developed.

[0004] Etching processes are sometimes referred to as wet or dry based on the materials used in the process. Wet HF etching preferentially removes silicon oxide over other dielectrics and materials. However, wet processes can have difficulty penetrating some confined trenches and can sometimes deform the remaining material. Dry etches, generated within a local plasma formed within the substrate processing region, can penetrate more confined trenches and reduce deformation of delicate remaining structures. However, local plasmas can damage the substrate through the generation of electric arcs when they are discharged.

[0005] Therefore, there is a need for improved systems and methods that can be used to manufacture high quality devices and structures. The present technology addresses these and other needs. Summary of the Invention

[0006] An exemplary method for etching silicon-containing materials may include flowing a first fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The method may include flowing a sulfur-containing precursor into the remote plasma region of the semiconductor processing chamber. The method may include forming a plasma in the remote plasma region to generate plasma effluents of the first fluorine-containing precursor and the sulfur-containing precursor. The method may include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned in the processing region. The substrate may include a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The method may include isotropically etching the silicon nitride layer while substantially preserving the silicon oxide.

[0007] In some embodiments, the method can include flowing a second fluorine-containing precursor into a processing region of a semiconductor processing chamber. The second fluorine-containing precursor can bypass the remote plasma region. The method can include stopping the flow of the first fluorine-containing precursor and the sulfur-containing precursor after a first period of time. The method can include purging the processing region with a purge precursor. The sulfur-containing precursor can be or include hydrogen sulfide or carbon disulfide. The method can include flowing an additive precursor with the first fluorine-containing precursor. The additive precursor can be or include a halogen other than fluorine. The etch selectivity between silicon nitride and silicon oxide can be about 20:1 or greater. The fluorine-containing precursor can include sulfur, phosphorus, arsenic, silicon, carbon, selenium, or tellurium. The method can be performed at a chamber operating pressure between about 10 mTorr and about 5 Torr. The method can be performed at a chamber temperature of about 20° C. or less. The method can include flowing argon, helium, or nitrogen with the fluorine-containing precursor. The flow ratio of the argon, helium, or nitrogen to the fluorine-containing precursor can be about 2:1 or less. The method can include flowing a hydrogen-containing precursor with the fluorine-containing precursor. The method can include forming a passivation layer on the silicon oxide.

[0008] Some embodiments of the present technology may include a method for etching silicon-containing materials. The method may include flowing a first halogen-containing precursor into a remote plasma region of a semiconductor processing chamber. The first halogen-containing precursor may include fluorine. The method may include forming a plasma in the remote plasma region to generate plasma effluents of the first halogen-containing precursor. The method may include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region. The substrate may include a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide. The method may include flowing a second halogen-containing precursor directly into the processing region of the semiconductor processing chamber. The second halogen-containing precursor includes fluorine. The method may include laterally etching the silicon nitride layer. The method may include stopping the flow of the first halogen-containing precursor after a first period of time. The method may include purging the processing region with a purge precursor.

[0009] In some embodiments, the method can include flowing a sulfur-containing precursor into a remote plasma region of a semiconductor processing chamber. The second halogen-containing precursor includes chlorine, bromine, or iodine. The method can include repeating the method at least 10 times. The first period can be about 30 seconds or longer. The method can include flowing argon or nitrogen with the first halogen-containing precursor.

[0010] Some embodiments of the present technology may include a method for etching silicon-containing materials. The method may include flowing a first fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The method may include flowing a sulfur-containing precursor into the remote plasma region of the semiconductor processing chamber. The method may include forming a plasma in the remote plasma region to generate plasma effluents of the first fluorine-containing precursor and the sulfur-containing precursor. The method may include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned in the processing region. The substrate may define a trench through stacked layers including alternating layers of silicon nitride and silicon oxide. The method may include flowing a second fluorine-containing precursor into the processing region of the semiconductor processing chamber. The second fluorine-containing precursor may bypass the remote plasma region. The method may include isotropically etching the silicon nitride layer.

[0011] Such techniques can offer many advantages over conventional systems and techniques. For example, these processes can selectively etch silicon nitride isotropically within semiconductor structures. Additionally, these processes can also protect exposed oxide during the etching process. These and other embodiments, along with their many advantages and features, are described in more detail below in conjunction with the description and accompanying drawings.

[0012] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a top view of an embodiment of an exemplary processing system in accordance with some embodiments of the present technique; [Figure 2A] 1 is a schematic cross-sectional view of an exemplary processing chamber in accordance with some embodiments of the present technique; [Figure 2B] FIG. 2B is a detailed view of a portion of the processing chamber shown in FIG. 2A in accordance with some embodiments of the present technique. [Figure 3] 1 is a bottom view of an exemplary showerhead in accordance with some embodiments of the present technique. [Figure 4] FIG. 1 illustrates exemplary steps of a method according to some embodiments of the present technology. [Figure 5A] 1 is a cross-sectional view of a substrate processed in accordance with some embodiments of the present technique; [Figure 5B] 1 is a cross-sectional view of a substrate processed in accordance with some embodiments of the present technique; [Figure 5C] 1 is a cross-sectional view of a substrate processed in accordance with some embodiments of the present technique; DETAILED DESCRIPTION OF THE INVENTION

[0014] Some figures are included as schematic diagrams. It should be understood that the drawings are for illustrative purposes and should not be considered to scale unless specifically stated to scale. Furthermore, as schematic diagrams, the drawings are provided as schematic diagrams to aid understanding and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

[0015] In the accompanying drawings, similar components and / or features may have the same reference numerals. Furthermore, various components of the same type may be distinguished according to the reference numerals, with a letter distinguishing between the similar components. When only a first reference numeral is used in this specification, the description is applicable to any of the similar components having the same first reference numeral, regardless of the letter.

[0016] In the transition from 2D NAND to 3D NAND, many process steps are changed from vertical to horizontal. Furthermore, as 3D NAND structures grow with the number of cells being formed, the aspect ratios of memory holes and other structures increase, sometimes dramatically. During 3D NAND processing, inter-electrode dielectric or IPD layers may be formed by stacking placeholder layers and dielectric materials. These placeholder layers may have various processes performed to position the structure before the material is completely removed and replaced with metal. Even when metallization is incorporated on one side of a cell structure, the other side of the structure may already have processes performed, such as the formation of floating gates or charge trapping layers. These layers can be formed within memory holes, but they can introduce crosstalk between vertically separated memory cells. One way to reduce this communication may be to etch the placeholder material before forming these layers, allowing the dielectric material to further isolate individual cell material layers from adjacent cells.

[0017] Many conventional techniques utilize wet etching to access each cell placeholder material and laterally etch the placeholder before forming layers such as charge trapping layers. However, wet etching is more robust than other etching techniques, and wet etching can result in unnecessary or undesirable etching of the placeholder material. For example, wet etching can over-etch some features. Additionally, wet etching of small form factor structures can result in pattern collapse or distortion due to the surface tension of the etchant. The use of wet etchants can also require subsequent steps to remove residues formed within trenches or holes. While dry etching techniques can also be performed, many of the dry etchants utilized also etch silicon and silicon oxide, reducing the selectivity of the process.

[0018] The present technology overcomes these problems by implementing a dry etching process that can selectively etch silicon nitride laterally while limiting the etching of oxide. By utilizing a specific precursor combination, the exposed oxide surface can be protected during the etching process. In this manner, the protective material may enable the implementation of an etching step that does not remove, or only minimally removes, the underlying structural material.

[0019] While the remaining disclosure routinely identifies specific etching processes utilizing the techniques of the present disclosure, it will be readily understood that the present systems and methods are equally applicable to deposition and cleaning processes that may occur in the described chambers. Accordingly, the techniques should not be considered limited to use with only etching processes or chambers. Furthermore, while an exemplary chamber is described to provide a foundation for the techniques, it should be understood that the techniques may be applied to any semiconductor processing chamber capable of operating in the single chamber described.

[0020] 1 illustrates a top view of one embodiment of a deposition, etch, bake, and cure chamber processing system 100, according to an embodiment. In this illustration, a pair of front-opening unified pods 102 deliver substrates of various sizes, which are received by a robot arm 104 and placed in a low-pressure holding area 106, and then placed into one of the substrate processing chambers 108a-f located in tandem sections 109a-c. A second robot arm 110 can be used to transfer substrate wafers from the holding area 106 to and from the substrate processing chambers 108a-f. Each substrate processing chamber 108a-f can be equipped to perform many substrate processing steps, including cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and other substrate processes, as well as the dry etch processes described herein.

[0021] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching a dielectric film on a substrate wafer. In one configuration, two pairs of processing chambers, e.g., 108c-d and 108e-f, may be used to deposit a dielectric material on a substrate, and a third pair of processing chambers, e.g., 108a-b, may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to etch a dielectric film on a substrate. Any one or more of the described processes may be performed in one or more chambers separate from the fabrication system shown in various embodiments. It will be appreciated that system 100 also contemplates additional configurations of deposition, etching, annealing, and curing chambers for dielectric films.

[0022] 2A shows a cross-sectional view of an exemplary processing chamber system 200, which includes a partitioned plasma generation region within the processing chamber and can be configured to perform processes described further below. For example, during etching of films such as titanium nitride, tantalum nitride, tungsten, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, and silicon oxycarbide, process gases can flow through a gas inlet assembly 205 into a first plasma region 215. An optional remote plasma system 201 can be included within the system to process a first gas, which then travels through the gas inlet assembly 205. The inlet assembly 205 can include two or more separate gas supply channels, and if included, a second channel can bypass the RPS 201.

[0023] Shown are a cooling plate 203, a faceplate 217, an ion suppressor 223, a showerhead 225, and a substrate support 265 with a substrate 255 disposed thereon, each of which may be included depending on the embodiment. The pedestal 265 may have heat exchange channels through which a heat exchange fluid flows to control the temperature of the substrate and may operate to heat and / or cool the substrate or wafer during processing operations. The wafer support platter of the pedestal 265, which may comprise aluminum, ceramic, or a combination thereof, may also be resistively heated using embedded resistive heating elements to achieve relatively high temperatures, such as from about 100° C. or lower to about 1100° C. or higher.

[0024] The face plate 217 can be pyramidal, conical, or another similar structure that is narrow at the top and widens toward the bottom. The face plate 217 can also be flat, as shown, and can include multiple through channels used to distribute process gases. Depending on the use of the RPS 201, plasma generating gases and / or plasma excited species can pass through multiple holes in the face plate 217, as shown in FIG. 2B, for more uniform delivery to the first plasma region 215.

[0025] An exemplary configuration can include a gas inlet assembly 205 opening into a gas feed region 258 separated from the first plasma region 215 by the faceplate 217 such that gases / species flow through holes in the faceplate 217 into the first plasma region 215. Structural and operational features can be selected to prevent significant backflow of plasma from the first plasma region 215 into the feed region 258, the gas inlet assembly 205, and the fluid delivery system 210. The faceplate 217 or conductive top of the chamber and the showerhead 225 are shown with an insulating ring 220 positioned between the features, which allows an AC potential to be applied to the faceplate 217 relative to the showerhead 225 and / or ion suppressor 223. The insulating ring 220 can be positioned between the faceplate 217 and the showerhead 225 and / or ion suppressor 223, thereby allowing a capacitively coupled plasma (CCP) to form in the first plasma region. Baffles (not shown) may additionally be positioned in the first plasma region 215 or otherwise coupled to the gas inlet assembly 205 to affect the flow of fluid into the region through the gas inlet assembly 205. In some embodiments, additional plasma sources may be utilized, including inductively coupled plasma sources that extend around the periphery of the chamber or are fluidly coupled to the chamber, as well as additional plasma generating systems such as microwave plasma generating systems.

[0026] The ion suppressor 223 may include a plate or other geometric shape defining a plurality of apertures throughout its structure configured to suppress the migration of ionic charged species from the first plasma region 215 while allowing uncharged neutral or radical species to pass through the ion suppressor 223 and into the activated gas supply region between the suppressor and the showerhead. In embodiments, the ion suppressor 223 may include a perforated plate having various aperture configurations. These uncharged species may include highly reactive species that are transported from the apertures with a less reactive carrier gas. As noted above, migration of ionic species through the apertures is reduced and, in some cases, may be completely suppressed. Controlling the amount of ionic species passing through the ion suppressor 223 advantageously provides greater control over the gas mixture that contacts the underlying wafer substrate, thereby providing greater control over the deposition and / or etching characteristics of the gas mixture. For example, adjusting the ion concentration of the gas mixture can significantly change etch selectivities, e.g., SiNx:SiOx etch ratio, Si:SiOx etch ratio, etc. In alternative embodiments where deposition is performed, the balance may be shifted from conformal deposition of dielectric material to flowable deposition.

[0027] The plurality of apertures in the ion suppressor 223 can be configured to control the passage of the activated gas, i.e., ionic, radical, and / or neutral species, through the ion suppressor 223. For example, the aspect ratio of the apertures, or the diameter to length of the apertures, and / or the geometry of the apertures can be controlled to reduce the flow of ionic charged species in the activated gas through the ion suppressor 223. The apertures in the ion suppressor 223 can include a tapered portion facing the plasma excitation region 215 and a cylindrical portion facing the showerhead 225. The cylindrical portion can be shaped and dimensioned to control the flow of ionic species through the showerhead 225. An adjustable electrical bias can also be applied to the ion suppressor 223 as an additional means of controlling the flow of ionic species through the suppressor.

[0028] The ion suppressor 223 can function to reduce or eliminate the amount of ionic charged species that travel from the plasma generation region to the substrate. Uncharged neutral and radical species can still pass through the openings in the ion suppressor and react with the substrate. It should be noted that complete elimination of ionic charged species in the reaction region surrounding the substrate may not be achieved in some embodiments. In certain cases, ionic species are intended to reach the substrate to perform etching and / or deposition processes. In these cases, the ion suppressor can help control the concentration of ionic species in the reaction region at a level that is process-supportive.

[0029] The showerhead 225 in combination with the ion suppressor 223 prevents the plasma present in the first plasma region 215 from directly exciting gases in the substrate processing region 233, while still allowing excited species to migrate from the chamber plasma region 215 into the substrate processing region 233. In this manner, the chamber can be configured to prevent the plasma from contacting the substrate 255 being etched. This can advantageously protect various complex structures and films patterned on the substrate that could be damaged, dislocated, or otherwise warped if the generated plasma were to come into direct contact. Furthermore, the rate at which the plasma contacts or approaches the substrate level can increase the etching rate of oxide species. Therefore, if the exposed area of ​​material is an oxide, this material can be further protected by keeping the plasma away from the substrate.

[0030] The processing system may further include a power supply 240 electrically coupled to the processing chamber to supply power to the faceplate 217, the ion suppressor 233, the showerhead 225, and / or the pedestal 265 to generate a plasma in the first plasma region 215 or processing region 233. The power supply may be configured to supply an adjustable amount of power to the chamber depending on the process being performed. Such a configuration allows for the use of an adjustable plasma in the process being performed. Unlike remote plasma units, which often provide an on or off function, an adjustable plasma may be configured to supply a specific amount of power to the plasma region 215. This allows for the development of specific plasma characteristics that can dissociate precursors in specific ways to enhance the etch profile produced by those precursors.

[0031] A plasma can be ignited either in the chamber plasma region 215 above the showerhead 225 or in the substrate processing region 233 below the showerhead 225. A plasma may exist in the chamber plasma region 215, for example, to generate radical precursors from an inflow of a fluorine-containing precursor or other precursor. An AC voltage, typically in the radio frequency (RF) range, can be applied between a conductive top portion of the processing chamber, such as the faceplate 217, and the showerhead 225 and / or ion suppressor 223 to ignite a plasma in the chamber plasma region 215 during deposition. The RF power source can generate a high RF frequency of 13.56 MHz, although other frequencies can also be generated alone or in combination with the 13.56 MHz frequency.

[0032] 2B shows a detailed view 253 of features that affect the distribution of process gas through face plate 217. As shown in FIGS. 2A and 2B, face plate 217, cooling plate 203, and gas inlet assembly 205 intersect to define a gas delivery region 258 to which process gas can be delivered from gas inlet 205. Gas fills gas delivery region 258 and can flow through apertures 259 in face plate 217 into first plasma region 215. Apertures 259 can be configured to direct flow substantially in one direction so that process gas can flow into processing region 233 but can partially or completely prevent backflow into gas delivery region 258 after traversing face plate 217.

[0033] A gas distribution assembly, such as the showerhead 225, for use in the processing chamber section 200 may be referred to as a dual channel showerhead (DCSH), and is further detailed in the embodiment depicted in Figure 3. A dual channel showerhead can accommodate an etching process that allows for separation of etchants outside the processing region 233, thereby providing limited interaction with chamber components and each other before being delivered into the processing region.

[0034] The showerhead 225 can include an upper plate 214 and a lower plate 216. The plates can be coupled together to define a volume 218 between the plates. The coupling of the plates can provide a first fluid channel 219 through the upper and lower plates and a second fluid channel 221 through the lower plate 216. The formed channels can be configured to provide fluid access from the volume 218 through the lower plate 216 only via the second fluid channel 221, and the first fluid channel 219 can be fluidly isolated from the volume 218 between the plates and the second fluid channel 221. The volume 218 can be fluidly accessible through a side of the gas distribution assembly 225.

[0035] 3 is a bottom view of a showerhead 325 for use with a processing chamber, according to an embodiment. The showerhead 325 may correspond to the showerhead 225 shown in FIG. 2A. The through-holes 365, which show a view of the first fluid channel 219, may have multiple shapes and configurations to control and influence the flow of precursors through the showerhead 225. The small holes 375, which show a view of the second fluid channel 221, may provide a substantially even distribution over the surface of the showerhead, even among the through-holes 365, which may help to provide a more uniform mixing of the precursors as they exit the showerhead than other configurations.

[0036] The chambers described above can be used to perform exemplary methods, including etching methods. Turning to FIG. 4 , exemplary steps in a method 400 according to an embodiment of the present technology are shown. Prior to the first step of the method, a substrate can be processed with one or more methods and then placed in a processing region of a chamber in which the method 400 can be performed. For example, an IPD layer can be formed on the substrate, and then one or more memory holes or trenches can be formed through the stacked layers. The IPD layer can include any number of materials and can include alternating layers of placeholder materials and dielectric materials. In embodiments, the dielectric material can be or include silicon oxide, and the placeholder material can be or include silicon nitride. While the remaining disclosure discusses silicon nitride and silicon oxide, any other known material used for these two layers can be used in place of one or more layers. Some or all of these steps can be performed in a chamber or system tool, as described above, or can be performed in different chambers on the same system tool, which can include the chamber in which the steps of the method 400 are performed.

[0037] The method 400 may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber in step 405. An exemplary chamber may be chamber 200 described above and may include one or both of the RPS unit 201 or first plasma region 215. Either or both of these regions may be the remote plasma region used in step 405. In step 410, a plasma may be generated in the remote plasma region, thereby generating plasma effluents of the fluorine-containing precursor. In step 415, the plasma effluents may be flowed into a processing region of the chamber. In some embodiments, the method 400 may include flowing one or more precursors directly into the processing region, bypassing the remote plasma region, in step 420. In some embodiments, the plasma effluents may interact with a substrate in the processing region and, in optional step 425, passivate or protect portions of the structure. For example, in some embodiments, the plasma effluents may passivate oxide materials. As mentioned, the substrate may include a silicon or silicon-containing substrate or wafer, on which multiple material layers are formed, such as alternating layers of silicon oxide and silicon nitride. A memory hole or trench may be formed through the stacked layers to the substrate level, thereby providing an exposed portion of the substrate at the bottom of the hole or trench. Thus, exposed regions of silicon nitride, silicon oxide, and silicon, or some silicon-containing material, may exist within the memory hole structure.

[0038] The formation of the holes or trenches may be performed in a different chamber or in an earlier process step. If performed in the same chamber as method 400, the exposed portions of the substrate surface may be relatively clean or tidy. However, if the process is performed in a different chamber or in a different environment, native oxide may form on the exposed portions of the substrate through the holes or trenches. The native oxide may be different from the oxide formed in alternating layers of the memory structure. For example, a silicon oxide layer that can be used to separate memory cells may be a relatively high-quality oxide, while the native oxide may be a relatively low-quality oxide and may be relatively porous compared to the silicon oxide layer.

[0039] Etching processes for removing silicon nitride can have relatively high selectivity to silicon oxide, such as selectivity of about 100:1 or greater. However, depending on the structure, the amount of silicon nitride removed can range from a few nanometers up to a fraction of a micrometer or more. For example, in some embodiments, the amount of silicon nitride recessed can be tens of nanometers up to hundreds of nanometers. Etching such amounts of material can require relatively long etching times. The selectivity to oxide in the nitride removal process can be based, in part, on the oxide's resistance to the etchant, which can include multiple fluorine-containing materials. The fluorine can eventually penetrate some of the silicon oxide material, generating volatiles that will also remove the silicon oxide material. However, the process generally includes an incubation period during which the fluorine slowly interacts with the oxide material. The incubation can take two minutes or more, for example, up to five minutes, up to ten minutes, or even longer, depending on the quality of the oxide, the energy of the fluorine, and other processing conditions. As a result, the process can laterally or isotropically etch the silicon nitride in step 430 while the oxide material can be limitedly affected by forming a silicon oxide passivation.

[0040] The radical fluorine emissions may contact the semiconductor structure and penetrate into the formed trenches. The exposed surface of the silicon oxide may be unaffected or only minimally affected by the fluorine plasma emissions, while the silicon nitride may be laterally etched between sections of the silicon oxide. Additionally, as described below, by utilizing certain fluorine-containing precursors, and in some embodiments, additive precursors, a passivation layer may be formed on the exposed surface of the silicon oxide, thereby forming a polymerized protective layer on the material.

[0041] The extent of this damage or interaction can be related to the power of the plasma used to form the fluorine-containing plasma effluents, as well as the distance the formed effluents travel. For example, by utilizing a remote plasma, a relatively low plasma power can be used, such as less than 5 kW, about 3 kW or less, about 1 kW or less, about 500 W or less, which can limit the energy of the plasma effluents and also limit complete dissociation of the precursor material. In addition, forming a remote plasma, which can include ion filtering before delivery to the substrate as described above, can limit the extent to which ionic plasma effluents interact with the silicon nitride structure. For example, a localized plasma can retain sufficient energy at the wafer level through a bombardment process to damage at least the upper silicon oxide or silicon nitride layers included in the stack. Furthermore, the plasma power can be pulsed, which can further reduce the effective plasma power. In addition, ionic effluents are often directional, which can be beneficial for anisotropic etching of surfaces perpendicular to the effluent delivery direction, but may not promote lateral etching. This technique utilizes neutral or radical species generated in the plasma to generate an isotropic etchant capable of laterally etching silicon nitride. As described below, as the total flow rate decreases and / or the pressure increases, the plasma power can be further reduced while the plasma is maintained, for example, to about 400 W or less, about 300 W or less, about 200 W or less, about 100 W or less, or even less. This can further suppress fluorine dissociation and additive precursor dissociation, which can improve both selective etching of nitride, which may occur more readily, and oxide etching, which may occur after an initiation period or saturation. Additionally, the additive precursor has reduced dissociation, which in some embodiments can promote the development of a passivation layer.

[0042] The etching process may continue for a first period of time, in some embodiments. After the first period of time, the flow of the fluorine-containing precursor may be stopped along with the formation of the plasma. A purge may then be performed in optional step 435, which may remove residual etchant material, etch by-products, or other materials from the chamber. The purge may be performed using any number of chemically inert materials, such as nitrogen or a noble gas, that may be used to purge the processing region of the chamber. The purge process may improve etch selectivity by facilitating the removal of by-products and less beneficial plasma effluents, reducing the residence time of these materials within the processing region. This may, for example, facilitate lateral etching of silicon nitride while reducing exposure and impact to silicon oxide.

[0043] The first period of time can be sufficient to produce etching while limiting residence time that may begin to affect the oxide surface. For example, in some embodiments, the first period of time can be about 5 seconds or more, and can be about 10 seconds or more, about 15 seconds or more, about 20 seconds or more, about 25 seconds or more, about 30 seconds or more, about 35 seconds or more, about 40 seconds or more, about 45 seconds or more, about 50 seconds or more, about 55 seconds or more, about 60 seconds or more, about 2 minutes or more, about 3 minutes or more, about 4 minutes or more, about 5 minutes or more, or longer. However, to limit additional effects, in some embodiments, the first period of time can be about 5 minutes or less, about 4 minutes or less, about 3 minutes or less, about 2 minutes or less, or shorter.

[0044] Precursors used in this technique may include fluorine-containing precursors as well as additional precursors described below. An exemplary fluorine-containing precursor may be nitrogen trifluoride (NF), which may be flowed into a remote plasma region that may be separate from but fluidly coupled to the processing region. Other fluorine sources may be used in conjunction with or in place of nitrogen trifluoride. Generally, a fluorine-containing precursor is flowed into the remote plasma region, and the fluorine-containing precursor may include at least one precursor selected from the group consisting of atomic fluorine, diatomic fluorine, nitrogen trifluoride, carbon tetrafluoride, hydrogen fluoride, xenon difluoride, and various other fluorine-containing precursors used or useful in semiconductor processing.

[0045] In some embodiments, the fluorine-containing precursor can be characterized by an increased fluorine content in the molecule of the fluorine-containing precursor. For example, in some embodiments, the fluorine-containing precursor can be XF y The precursors can be characterized by the molecular formula: X = 1F ⁢ ...

[0046] For example, non-limiting examples include any other nonmetal that can bond with a halide, such as sulfur or phosphorus, as well as other base metals, transition metals, or other elements that can chemically bond with a halogen element. Non-limiting examples of fluorine-containing precursors include phosphorus pentafluoride, sulfur hexafluoride, and other fluorine- or halogen-containing materials. These materials can generate many plasma effluent materials that can enhance etching. For example, sulfur hexafluoride can be used to generate a variety of elements that can enhance etching, including S, F, SF, SF, SF, SF, SF, F, and S, among many other radical and neutral species.

[0047] While any number of halogen-containing precursors can be used, such as fluorine-containing precursors, some materials, such as phosphorus and sulfur, may improve selectivity over other materials, such as nitrogen trifluoride, due to additional effects that may be provided by silicon oxide materials. For example, sulfur and phosphorus compounds may create a type of passivation or protective material on the exposed silicon oxide surface. For example, sulfur and phosphorus are sufficiently large elements that some polymerization may occur, forming a type of bridged polymer on the oxide surface. The sulfur may bond with the oxygen surface and be incorporated into the film, while one or more fluorine atoms may be retained, thereby protecting the surface from further fluorination and reaction with the oxygen surface. This may allow etching of nitride structures while maintaining or limiting the impact on the oxide layer. This is because side formation may not occur on the nitride.

[0048] In some embodiments, a sulfur-containing precursor can be co-flowed with a fluorine-containing precursor. An exemplary sulfur-containing precursor can include hydrogen sulfide (HS), which can be co-flowed with a fluorine-containing precursor into the remote plasma region. Other sulfur sources can be used in conjunction with or in place of hydrogen sulfide. Generally, a sulfur-containing precursor can be flowed into the remote plasma region, and the sulfur-containing precursor can include at least one precursor selected from the group consisting of hydrogen sulfide, carbon disulfide, disulfur dichloride, disulfur tetrachloride, and various other sulfur-containing precursors used or useful in semiconductor processing. As discussed above, sulfur forms a passivation or protective material on the exposed surface of the silicon oxide material, thereby improving selectivity to other materials, such as fluorine-containing precursors. Therefore, co-flowing a sulfur-containing precursor with a fluorine-containing precursor can increase the formation of a passivation or protective material to balance etch selectivity.

[0049] In some embodiments, the additive precursor can be flowed with the fluorine-containing precursor and, if present, the sulfur-containing precursor. The additive precursor can be or include a halogen-containing precursor containing a halogen different from fluorine. For example, the additive precursor can include a precursor containing a Group VII element or a halogen in any combination with any Group III, IV, V, or VI element. Exemplary materials include those having the formula X a Y bwhere X comprises any Group III, IV, V, or VI element, Y comprises chlorine, bromine, or iodine, a is 1, 2, or 3, and b is 3, 4, 5, 6, 7, 8, or 9. The additive precursor formula can also include precursors characterized by the formula R1R2R3XY, where X can be any Group IV element, Y can be chlorine, bromine, or iodine, and R1-R3 can be any combination of additional Group IV elements combined with H, methyl, ethyl, or other hydrocarbons, additional halogens, or any other listed chain extending material. For example, without being limited to precursors encompassed by the above formula, exemplary precursors can include any combination of silicon and chlorine, such as carbon tetrachloride and / or disilicon hexachloride, and precursors can also include carbon and chlorine, germanium and chlorine, silicon and fluorine, carbon and fluorine, germanium and fluorine, silicon and bromine, carbon and bromine, germanium and bromine, silicon and iodine, carbon and iodine, germanium and iodine, selenium and fluorine, bromine, chlorine, or iodine, tellurium and fluorine, bromine, chlorine, or iodine, phosphorus and fluorine, bromine, chlorine, or iodine, and arsenic and fluorine, bromine, chlorine, or iodine. Additionally, additive precursors can be characterized by one or more methyl groups, such as trimethylsilane.

[0050] The additive precursor may act as a passivation precursor, as discussed above. For example, while fluorine-containing precursors can etch materials including silicon nitride and silicon oxide after sufficient exposure or without sufficient stabilization treatment, additive precursors can perform the same stabilization step described above without etching the structure. Other halogen-containing precursors can perform the same function as the fluorine precursors described above, thereby not only performing the same steps but also providing additional control over the etching process by limiting the additional fluorine contamination. While any precursor encompassed by the above formula can be used as the additive precursor, in some embodiments, precursors characterized by silicon-silicon, carbon-carbon, germanium-germanium, or similar atomic bonding structures can be used. This is because low-power plasma can more easily break these bonds through the auxiliary moieties of the precursor. The additive precursor can also promote the repair of etched surfaces. For example, the additive precursor can include silicon, as described above. When plasma-enhanced, the silicon-containing precursor can provide silicon back into the silicon oxide when etched. When the structure is removed from the processing environment, the added silicon may be oxidized, and atmospheric water may react with the silicon, causing the oxidized surface to reappear. Thus, this process can limit, prevent, or regenerate silicon oxide, maintaining the silicon oxide layer during the etching process. In some embodiments where the additive precursor contains fluorine, the additive precursor may be replaced with a fluorine-containing precursor.

[0051] In some embodiments of the present technique, additional precursors may be provided along with the fluorine-containing precursor. For example, a hydrogen-containing precursor may be provided, or one or more other precursors may be provided, such as argon, nitrogen, helium, an oxygen-containing precursor, or other precursors. Hydrogen and argon may be more easily ionized than helium, which may facilitate processing in some embodiments. The hydrogen-containing precursor may be or include hydrogen, a hydrocarbon, or any hydrogen-containing precursor. Exemplary oxygen-containing precursors may be or include water vapor, hydrogen peroxide, oxygen, ozone, nitrous oxide, nitric oxide, or an excited oxygen-containing material, although, as noted above, in some embodiments, the oxygen-containing precursor may not be plasma-enhanced to limit interaction with the silicon nitride material through the subsequently etched trench. The present technique may further etch silicon, and providing a certain amount of an oxygen-containing precursor may facilitate the etching.

[0052] Without being bound by theory, providing materials such as or containing hydrogen or argon, among other precursors, can enhance the etching process by providing additional electrons to the process. While fluorine can be a pseudo-scavenger of electrons in the plasma, the additional precursor can donate additional electrons, thereby increasing the electron density in the plasma and improving the etching process and nitride selectivity. Thus, in some embodiments, a flow ratio of the fluorine-containing precursor to the additional precursor can be maintained. For example, the flow ratio of the additive and / or additional precursor, such as hydrogen or argon, to the fluorine-containing precursor can be maintained at least about 1:2, and can be maintained at about 1:1 or greater, about 1.5:1 or greater, about 2.0:1 or greater, about 2.5:1 or greater, about 3.0:1 or greater, about 3.5:1 or greater, about 4.0:1 or greater, or even higher. However, the flow ratio may be maintained to limit dilution. Sufficient dilution can inhibit further etching; therefore, in some embodiments, the flow ratio of the additional precursor to the fluorine-containing precursor may be maintained at about 10.0:1 or less, about 9.0:1 or less, about 8.0:1 or less, about 7.0:1 or less, about 6.0:1 or less, about 5.0:1 or less, about 4.0:1 or less, about 3.0:1 or less, about 2.0:1 or less, about 1.0:1 or less, or lower. For example, to facilitate plasma formation, an additional precursor, such as argon, capable of supplying electrons may be included. However, if the additive precursor is characterized by a lower ionization energy than argon, argon may be excluded from the plasma precursor, thereby improving selectivity.

[0053] In some embodiments, any one or more of the precursors discussed above can be flowed directly into the processing region of a semiconductor processing chamber, bypassing the remote plasma region. By bypassing the remote plasma region, plasma effluents may not be formed for precursors flowing directly into the processing region. However, it is believed that plasma effluents may be formed due to contact with plasma effluents generated in the remote plasma region and flowed into the processing region. For example, a second fluorine-containing precursor can be flowed directly into the processing region, bypassing the remote plasma region. The second fluorine-containing precursor may be any of the fluorine-containing precursors described above, and in embodiments, may be atomic fluorine, diatomic fluorine, or a precursor of Formula X a Y b where X comprises any Group III, IV, V, or VI element; Y is chlorine, bromine, or iodine; a is 1, 2, or 3; and b is 3, 4, 5, 6, 7, 8, or 9. For example, the second fluorine-containing precursor can be or include chlorine trifluoride, chlorine pentafluoride, bromine trifluoride, bromine pentafluoride, iodine trifluoride, iodine pentafluoride, iodine heptafluoride, and various other fluorine-containing precursors used or useful in semiconductor processing. Additionally, a carrier gas or inert gas can be flowed directly into the processing region of the semiconductor processing chamber, bypassing the remote plasma region.

[0054] When bypassing the remote plasma region, precursors provided directly to the process can be flowed into the process chamber separately from the plasma effluents. By flowing precursors directly into the process chamber, the presence of excited plasma effluents and unexcited precursors can be tailored within the process region, potentially enabling tailoring of the etch rate and / or etch selectivity. For example, flowing additional fluorine-containing precursors into the process region can form additional fluorine radicals, which can increase the etch rate and / or decrease the etch selectivity. Conversely, reducing or stopping the flow of additional fluorine-containing precursors into the process region can reduce the fluorine radicals in the process region, which can decrease the etch rate and / or increase the etch selectivity.

[0055] Process conditions can also affect the steps performed in method 400. While each step of method 400 can be performed at a constant temperature in some embodiments, the temperature can be adjusted during different steps in some embodiments. While the temperature can be maintained within any range, at higher temperatures, further dissociation of the fluorine-containing material can occur, potentially generating more fluorine radicals. As the amount of fluorine radicals increases, oxides can begin to etch more easily, reducing selectivity. Thus, in some embodiments, the temperature can be maintained at about 700°C or less, and can be maintained at about 650°C or less, about 600°C or less, about 550°C or less, about 500°C or less, or even lower. In some embodiments, the temperature of the substrate, pedestal, or chamber during nitride or silicon etching may be maintained at a temperature of about 400° C. or less, and in some embodiments, the temperature may be maintained at about 350° C. or less, about 300° C. or less, about 250° C. or less, about 200° C. or less, about 150° C. or less, about 100° C. or less, about 50° C. or less, about 25° C. or less, about 10° C. or less, about 0° C. or less, about −10° C. or less, about −20° C. or less, about −30° C. or less, about −40° C. or less, about −50° C. or less, about −60° C. or less, or lower.

[0056] As process temperatures decrease, precursor selection can be expanded to reduce or limit free hydrogen. For example, methyl groups can still be beneficial for passivating exposed oxide surfaces, but as temperatures decrease below about 20°C, the free hydrogen can generate ammonia or fluoroimides, which can also etch oxides by producing ammonium fluorosilicate as a byproduct. Thus, in some embodiments, the hydrogen concentration can be limited to less than 1:1 with any other element in the precursor, and, based on plasma power, can be limited to methyl groups, which can passivate exposed oxide surfaces during nitride etching.

[0057] In some embodiments, the process can be performed at a variety of pressures, which can facilitate processing in any of a number of processing chambers. For example, the process can be performed in a chamber capable of providing a pressure of about 10 mTorr or less, such as with a turbomolecular pump. Additionally, the pressure in the chamber can be maintained at a higher pressure, which can increase the associated etch rate; the pressure in the processing chamber can be maintained at about 1 Torr or more, about 2 Torr or more, about 5 Torr or more, about 10 Torr or more, about 50 Torr or more, about 100 Torr or more, about 200 Torr or more, or even higher.

[0058] The precursor and total flow rates can also promote improved silicon nitride etching. For example, argon, helium, nitrogen, or other plasma-stabilizing precursors can be supplied or maintained at a flow rate of about 100 sccm or less, and can be maintained at a flow rate of about 90 sccm or less, about 80 sccm or less, about 70 sccm or less, about 60 sccm or less, about 50 sccm or less, about 40 sccm or less, about 30 sccm or less, about 20 sccm or less, about 10 sccm or less, or even less. Reducing the flow rate of the plasma-stabilizing precursor reduces dissociation, allows the plasma to be generated using lower plasma power, and can control the etch to enhance nitride etching, which can be more easily performed compared to oxide etching. The flow rates of the additive precursor, first halogen-containing precursor, second halogen-containing precursor, or total precursor flow rate can be maintained at or below any of the above flow rates or approximately constant, which can further control dissociation and improve selectivity of nitride etching over oxide etching.

[0059] A controlled lateral or isotropic etch of silicon nitride can be achieved by performing a certain amount of etching followed by a certain amount of purging. To further enhance the etching, the technique can be performed in multiple cycles to refresh the silicon oxide, remove etching by-products, and facilitate the delivery of etchant to the lateral recesses of the silicon nitride. In some embodiments, the process, including optional purging, can be performed for about 2 or more, about 3 or more, about 4 or more, about 5 or more, about 10 or more, about 20 or more, about 50 or more, about 100 or more, about 200 or more, or more cycles, depending on factors such as the extent of silicon nitride etching performed or other effects of the process.

[0060] Benefits of performing additional cycles may include the incorporation of hydrogen into the etchant precursor, allowing hydrogen plasma effluents to beneficially interact with the silicon oxide layer of the stack and extract fluorine that may interact with the layer during each cycle. As discussed above, after an incubation period during which fluorine interacts with and begins to diffuse into the oxide structure, the silicon oxide may ultimately react with the silicon nitride removal process. However, even if the hydrogen effluents do not react with the silicon oxide itself or exhibit only minimal interaction, the energy of the effluents may be sufficient to extract fluorine that has begun to interact with the silicon oxide, removing fluorine from the layer when the plasma effluents contact the exposed surface of the silicon oxide layer. Purging, as described above, can evacuate the chamber from the removed fluorine and the hydrogen that has reacted with the removed fluorine. This can, at least to some extent, renew the incubation period and improve the overall selectivity of the silicon nitride etch process relative to silicon oxide by removing residual etchant from the silicon oxide with each cycle. By practicing the above-described process, the etch selectivity of silicon nitride to silicon oxide can be maintained at about 10:1 or greater, and selectivities of about 15:1 or greater, about 20:1 or greater, about 30:1 or greater, about 50:1 or greater, about 70:1 or greater, about 100:1 or greater, or even greater, can be obtained.

[0061] 5A-5C, cross-sectional views of a structure 500 being processed in accordance with some embodiments of the present technology are shown. As shown in FIG. 5A, a substrate 505 can have multiple stacked layers overlying the substrate, which can be silicon, silicon germanium, or other substrate materials. These layers can include an IPD layer including a dielectric material 510, which can be silicon oxide, alternating with a placeholder material 520, which can be silicon nitride. The placeholder material 520 can be or can include a material that will be removed to create individual memory cells in subsequent operations. While only seven layers of material are shown in the figures, it should be understood that the exemplary structure can include any number of the aforementioned layers, and the figures are merely schematic diagrams for purposes of illustrating aspects of the present technology. A trench 530 (which can be a memory hole) can be defined through the stacked structure down to the level of the substrate 505. The trench 530 can be defined by sidewalls 532, which can be composed of alternating layers of dielectric material 510 and placeholder material 520.

[0062] 5B illustrates the structure after the method according to the present technique has begun, as discussed above with respect to FIG. 4. A remote plasma of a fluorine-containing precursor (which may include additional precursors) may be formed to generate plasma effluents. The plasma effluents may be delivered to a substrate processing region where they may interact with the substrate and exposed material. As discussed above, when etching silicon nitride or placeholder material 520, plasma effluents of some precursors according to embodiments of the present technique may passivate silicon oxide or generate a protective layer 540 on the exposed regions.

[0063] 5C shows the structure after further methods or treatments according to the present technique have been performed, such as those discussed above with respect to FIG. 4. For example, as the etching process continues, additional passivation or protective material 540 may spread over the more exposed surfaces of the dielectric material 510, continuing to protect the material from vertical etching as the silicon nitride continues to be recessed during the process cycles. By utilizing the precursors and treatments discussed throughout the present technique, the silicon nitride may be isotropically or laterally etched from between sections of silicon oxide while limiting damage or removal of the silicon oxide.

[0064] In the foregoing description, for purposes of explanation, numerous details have been set forth in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to one skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0065] Although several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents can be used without departing from the spirit of the embodiments. Moreover, some well-known processes and elements have not been described to avoid unnecessarily obscuring the present technology. Therefore, the above description should not be construed as limiting the scope of the present technology. In addition, while a method or process may be described sequentially or stepwise, it should be understood that steps may be performed simultaneously or in an order different from that described.

[0066] Where a range of values ​​is presented, unless the context clearly dictates otherwise, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated value or unstated intervening value in a stated range and any other stated or intervening value within that stated range is also encompassed. The upper and lower limits of these smaller ranges may independently be included or excluded from the range, and each range where either, neither, or both limits are included in the smaller range is also encompassed within the scope, subject to any specifically excluded limits in the stated range. When one or both limits are included in a stated range, ranges excluding either or both of those included limits are also included.

[0067] As used in this specification and the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to "a precursor" includes a plurality of such precursors, a reference to "the layer" includes a reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth.

[0068] Additionally, the words "comprise(s)," "comprising," "contain(s)," "containing," "include(s)," and "including," when used in this specification and the appended claims, are intended to specify the presence of stated features, integers, components, or steps, but do not exclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.

Claims

1. 1. A method of etching a silicon-containing material, comprising: flowing a first fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber; flowing a sulfur-containing precursor into the remote plasma region of the semiconductor processing chamber; forming a plasma in the remote plasma region to produce plasma effluents of the first fluorine-containing precursor and the sulfur-containing precursor; flowing the plasma effluents into a processing region of the semiconductor processing chamber having a substrate positioned within the processing region, the substrate including a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide; and isotropically etching the silicon nitride layer while substantially preserving the silicon oxide layer.

1. A method for etching silicon-containing materials, comprising:

2. flowing a second fluorine-containing precursor into the processing region of the semiconductor processing chamber, wherein the second fluorine-containing precursor bypasses the remote plasma region; 10. The method of claim 1 further comprising:

3. stopping the flow of the first fluorine-containing precursor and the sulfur-containing precursor after a first period of time; and purging the processing area with a purge precursor; 10. The method of claim 1 further comprising:

4. 10. The method of etching silicon-containing materials of claim 1, wherein the sulfur-containing precursor comprises hydrogen sulfide or carbon disulfide.

5. flowing an additive precursor with the first fluorine-containing precursor, wherein the additive precursor comprises a halogen other than fluorine; 10. The method of claim 1 further comprising:

6. 10. The method of processing a silicon-containing substrate of claim 1, wherein the etch selectivity between silicon nitride and silicon oxide is greater than or equal to about 20:

1.

7. 10. The method of etching silicon-containing materials of claim 1, wherein the first fluorine-containing precursor comprises sulfur, phosphorus, arsenic, silicon, carbon, selenium, or tellurium.

8. 10. The method of etching silicon-containing materials of claim 1, wherein the method is performed at a chamber operating pressure between about 10 mTorr and about 5 Torr.

9. 10. The method of etching silicon-containing materials of claim 1, wherein the method is performed at a chamber temperature of about 20[deg.] C. or less.

10. flowing argon, helium, or nitrogen with the first fluorine-containing precursor and the sulfur-containing precursor; 10. The method of claim 1 further comprising:

11. 11. The method of etching silicon-containing materials of claim 10, wherein a flow ratio of the argon, helium, or nitrogen to the first fluorine-containing precursor is about 2:1 or less.

12. flowing a hydrogen-containing precursor with said first fluorine-containing precursor; 10. The method of claim 1 further comprising:

13. forming a passivation layer over said silicon oxide; 10. The method of claim 1 further comprising:

14. 1. A method of etching a silicon-containing material, comprising: flowing a first halogen-containing precursor into a remote plasma region of a semiconductor processing chamber, the first halogen-containing precursor comprising fluorine; forming a plasma in the remote plasma region to produce a plasma effluent of the first halogen-containing precursor; flowing the plasma effluents into a processing region of the semiconductor processing chamber having a substrate positioned within the processing region, the substrate including a trench formed through stacked layers including alternating layers of silicon nitride and silicon oxide; flowing a second halogen-containing precursor directly into a processing region of the semiconductor processing chamber, wherein the second halogen-containing precursor comprises fluorine; laterally etching the layer of silicon nitride; stopping the flow of the first halogen-containing precursor after a first period of time; and purging the processing area with a purge precursor; 4. A method for etching silicon-containing materials, further comprising:

15. flowing a sulfur-containing precursor into the remote plasma region of the semiconductor processing chamber; 15. The method of etching silicon-containing materials of claim 14, further comprising:

16. 15. The method of etching silicon-containing materials of claim 14, wherein the second halogen-containing precursor comprises chlorine, bromine, or iodine.

17. repeating said method for at least 10 cycles.

15. The method of etching silicon-containing materials of claim 14, further comprising:

18. 15. The method of etching silicon-containing materials of claim 14, wherein the first period of time is about 30 seconds or longer.

19. flowing argon or nitrogen with said first halogen-containing precursor; 15. The method of etching silicon-containing materials of claim 14, further comprising:

20. 1. A method of etching a silicon-containing material, comprising: flowing a first fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber; flowing a sulfur-containing precursor into the remote plasma region of the semiconductor processing chamber; forming a plasma in the remote plasma region to produce plasma effluents of the first fluorine-containing precursor and the sulfur-containing precursor; flowing the plasma effluents into a processing region of the semiconductor processing chamber, wherein a substrate is positioned within the processing region, the substrate defining a trench through stacked layers including alternating layers of silicon nitride and silicon oxide; flowing a second fluorine-containing precursor into the processing region of the semiconductor processing chamber, wherein the second fluorine-containing precursor bypasses the remote plasma region; and isotropically etching said silicon nitride layer; 1. A method for etching silicon-containing materials, comprising:

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