Stacked FET with 3-terminal SOT MRAM

Abstract

[0003] Embodiments of a three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device are disclosed. The three-terminal SOT MRAM device includes a first-type field effect transistor (FET) driving an SOT line. Additionally, the first-type FET includes a write gate in electrical contact with a write word line (WWL). Furthermore, the device also includes a second-type FET in electrical contact with a magnetic tunnel junction (MTJ). The second-type FET also includes a read gate in electrical contact with a read word line (RWL). Additionally, the first-type FET is disposed above the second-type FET. Furthermore, the three-terminal SOT MRAM device provides a density of three contact poly pitches (CPPs) per two cells.

Description

[Technical Field]

[0001] The present disclosure relates to stacked field effect transistors (FETs), and more particularly to stacked FETs with three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM).

[0002] Integrated circuits such as microprocessors may have a relatively large number of circuit elements, such as transistors, arranged within a limited chip area. The transistors may be n-type metal-oxide semiconductor field-effect transistor (nFET) or p-type metal-oxide semiconductor FET (pFET) type devices, where the "N" and "P" designations depend on the type of dopant used in creating the source / drain regions of the device. Complementary metal oxide semiconductor (CMOS) technology refers to integrated circuit products that use both n-type and p-type transistor devices.

[0003] Additionally, CMOS devices may include stacked FETs, which may be electrically connected and / or isolated. Furthermore, stacked FET CMOS devices may be useful for many applications, from memory to computer processors. Memory may include, for example, read-only memory (ROM) and random access memory (RAM). More specifically, RAM may include MRAM, such as three-terminal SOT MRAM.

[0004] Three-terminal SOT MRAM can provide separable read and write paths and enable switching in the sub-nanosecond (ns) range using different write mechanisms, such as spin-orbit coupling. However, SOT MRAM may use two transistors (e.g., FETs) per cell for read and write operations, which increases the density penalty compared to other configurations, such as one transistor per resistive RAM (RRAM) magnetic tunnel junction (1T / 1R MTJ), which use one transistor per cell. In SOT MRAM, a cell has a three-transistor gate pitch (also called contacted poly pitch, or CPP) in the X direction and two fins (or two nanosheet devices) with merged epitaxial layers (epi) in the Y direction. Alternatively, SOT MRAM may include relatively wide nanosheets, which may be impractical to implement. Summary of the Invention

[0005] Embodiments of a three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device are disclosed. The three-terminal SOT MRAM device includes a first-type field effect transistor (FET) driving an SOT line. Additionally, the first-type FET includes a write gate in electrical contact with a write wordline (WWL). The device also includes a second-type FET in electrical contact with a magnetic tunnel junction (MTJ). The second-type FET also includes a read gate in electrical contact with a read wordline (RWL). Additionally, the first-type FET is disposed above the second-type FET. Furthermore, the three-terminal SOT MRAM device provides a density of three contact poly pitches (CPP) per two cells. Advantageously, such embodiments improve the density of three-terminal SOT MRAM arrays.

[0006] An embodiment of a three-terminal SOT MRAM device is disclosed. The three-terminal SOT MRAM device includes an NFET driving an SOT line. In addition, the NFET includes a write gate in electrical contact with the WWL. Furthermore, the three-terminal SOT MRAM device includes a PFET in electrical contact with the MTJ. In addition, the PFET includes a read gate in electrical contact with the RWL. Furthermore, the PFET is disposed above the NFET. Advantageously, such an embodiment improves the density of a three-terminal SOT MRAM array.

[0007] An embodiment of a three-terminal SOT MRAM device is disclosed. The three-terminal SOT MRAM device includes a PFET driving an SOT line. In addition, the PFET includes a write gate in electrical contact with the WWL. Furthermore, the three-terminal SOT MRAM device includes an NFET in electrical contact with the MTJ. In addition, the NFET includes a read gate in electrical contact with the RWL. Furthermore, the NFET is disposed above the PFET. Advantageously, such an embodiment improves the density of a three-terminal SOT MRAM array.

[0008] An embodiment of a method for fabricating a three-terminal SOT MRAM device is disclosed. The method includes forming a lower dummy gate on an insulating layer in contact with a substrate. The method also includes forming a lower source / drain epitaxy (S / D epi). In addition, the method includes performing ILD deposition on the dummy gate and the lower S / D epi. The method further includes performing chemical mechanical planarization to remove a gate hard mask of the lower dummy gate and spacers in contact with the gate hard mask. In addition, the method includes forming a lower S / D sacrificial contact in contact with the lower S / D epi. The method also includes forming a junction oxide layer disposed above a bottom layer including the lower dummy gate. The method further includes bonding the junction oxide layer to a nanosheet channel in a top layer. The top layer includes a sacrificial nanosheet layer in contact with the nanosheet channel. In addition, the method includes performing active device patterning on the top layer. The method further includes forming an upper dummy gate in the top layer. The method also includes forming a spacer for the top layer. Additionally, the method includes forming an upper S / D epi for the top layer. Additionally, the method includes depositing an ILD for the top layer. Furthermore, the method includes performing CMP to remove the top-layer hard mask and the top-layer spacer. Additionally, the method includes forming a gate opening mask. Additionally, the method includes removing the upper dummy gate and the lower dummy gate. Additionally, the method includes performing a SiGe release. Additionally, the method includes removing the sacrificial nanosheet layer. Additionally, the method includes forming replacement gates for the top and bottom layers. Additionally, the method includes forming a gate cut to provide access to the top S / D epi and the lower S / D epi. Additionally, the method includes forming a middle-of-line (MOL) contact. Additionally, the method includes removing the lower S / D sacrificial contact. Additionally, the method includes forming contact metallization using the gate cut.Additionally, the method includes forming back end of line (BEOL) connections. Advantageously, such an embodiment improves the density of three-terminal SOT MRAM arrays.

[0009] Disclosed is an embodiment of a computer program product comprising program instructions stored on a computer-readable storage medium. The program instructions are executable by a processor to cause the processor to perform a method for fabricating a three-terminal SOT MRAM device. The method includes forming a lower dummy gate on an insulating layer in contact with a substrate. The method also includes forming a lower source / drain epitaxy (S / D epi). In addition, the method includes performing ILD deposition on the dummy gate and the lower S / D epi. The method further includes performing chemical mechanical planarization to remove a gate hard mask of the lower dummy gate and spacers in contact with the gate hard mask. In addition, the method includes forming a lower S / D sacrificial contact in contact with the lower S / D epi. The method also includes forming a junction oxide layer disposed above a bottom layer including the lower dummy gate. The method further includes bonding the junction oxide layer to a nanosheet channel in a top layer. The top layer includes a sacrificial nanosheet layer in contact with the nanosheet channel. In addition, the method includes performing active device patterning on the top layer. The method further includes forming an upper dummy gate for the top layer. The method also includes forming a spacer for the top layer. The method also includes forming an upper S / D epi for the top layer. The method also includes depositing an ILD for the top layer. The method also includes performing CMP to remove the top-layer hard mask and the top-layer spacer. The method also includes forming a gate opening mask. The method also includes removing the upper dummy gate and the lower dummy gate. The method also includes performing a SiGe release. The method also includes removing a sacrificial nanosheet layer. The method also includes forming replacement gates for the top and bottom layers. The method also includes forming a gate cut to provide access to the upper S / D epi and the lower S / D epi. The method also includes forming a middle-of-line (MOL) contact. The method also includes removing the lower S / D sacrificial contact.Furthermore, the method includes forming contact metallization using a gate cut. Additionally, the method includes forming back-end-of-line (BEOL) connections. Advantageously, such embodiments improve the density of three-terminal SOT MRAM arrays. [Brief explanation of the drawings]

[0010] The drawings included herein are incorporated into and form a part of this specification. They illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure. The drawings are merely illustrative of particular embodiments and are not intended to limit the disclosure.

[0011] [Figure 1] 1 is a block diagram of an example stacked field effect transistor (FET) with a three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) fabrication manager, according to some embodiments of the present disclosure.

[0012] [Figure 2A] FIG. 1 is a side view of a stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure.

[0013] [Figure 2B] FIG. 1 is a top view of a stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure.

[0014] [Figure 2C] FIG. 1 is a schematic diagram of a stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure.

[0015] [Figure 3A] 1 is a process flow diagram of a method for fabricating a stacked FET device with a three-terminal SOT MRAM according to some embodiments of the present disclosure. [Figure 3B]1 is a process flow diagram of a method for fabricating a stacked FET device with a three-terminal SOT MRAM according to some embodiments of the present disclosure.

[0016] [Figure 4A] 1A-1C illustrate exemplary fabrication states of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. [Figure 4B] 1A-1C illustrate exemplary fabrication states of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. [Figure 4C] 1A-1C illustrate exemplary fabrication states of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. [Figure 4D] 1A-1C illustrate exemplary fabrication states of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. [Figure 4E] 1A-1C illustrate exemplary fabrication states of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. [Figure 4F] 1A-1C illustrate exemplary fabrication states of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. [Figure 4G] 1A-1C illustrate exemplary fabrication states of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. [Figure 4H] 1A-1C illustrate exemplary fabrication states of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. [Figure 4I] 1A-1C illustrate exemplary fabrication states of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. [Figure 4J] 1A-1C illustrate exemplary fabrication states of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. [Figure 4K] 1A-1C illustrate exemplary fabrication states of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. [Figure 4L]1A-1C illustrate exemplary fabrication states of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure.

[0017] While the present disclosure is susceptible to various modifications and alternative forms, specific features thereof have been shown by way of example in the drawings and will be described in detail. It is to be understood, however, that there is no intention to limit the disclosure to the described embodiments. Rather, the intention is to cover all modifications, equivalents, and alternatives falling within the scope of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0018] As mentioned above, three-terminal SOT MRAM can provide separable read and write paths and enable switching in the sub-nanosecond (ns) range using different write mechanisms, such as spin-orbit coupling. However, SOT MRAM may use two transistors, e.g., FETs, per cell for read and write operations, which increases the density penalty compared to other configurations, such as resistive random access memory (RRAM) with one transistor per cell (1T / 1R MTJ). In SOT MRAM, a cell has a three-transistor gate pitch, also referred to as contact poly pitch (CPP), in the X direction and two fins (or two nanosheet devices) with merged epitaxial layers (epi) in the Y direction. Alternatively, SOT MRAM may include relatively wide nanosheets, which may be impractical to implement.

[0019] Thus, some embodiments of the present disclosure may provide a relatively high-density three-terminal SOT MRAM integrated with stacked nanosheet technology, and a method for fabricating such an embodiment, thereby providing a stacked FET SOT MRAM with 3 CPP per two cells, i.e., 1.5 CPP per cell. More specifically, such an embodiment may include a three-terminal spin-orbit torque MRAM array having an nFET transistor driving an SOT line, the gate of which is connected to a write word line. In addition, such an embodiment may include a PFET transistor connected to an MTJ, the gate of which is connected to a read word line. Furthermore, at least one type of FET (i.e., n-type) is stacked on top of a different type of FET (i.e., p-type). The method for fabricating such an embodiment may be performed using stacked nanosheet technology by wafer bonding and contacting the bottom FET through an insulating oxide layer.

[0020] In this manner, some embodiments of the present disclosure may provide memory devices that represent improvements over existing memory devices. Specifically, such embodiments may double the areal density achieved by current SOT schemes. In addition, such embodiments may be compatible with technologies including, but not limited to, nanosheet, FinFET, and monolithic transistor integration. Furthermore, in such embodiments, robust pFETs (e.g., pFETs with enhanced current drive) may be used for read operations using orientation engineering for the top layer or high-mobility channel materials (e.g., silicon germanium and / or germanium [SiGe / Ge]). Additionally, in such embodiments, PFET current may be adjusted by increasing the number of pFET sheet layers.

[0021] FIG. 1 is a block diagram of an example stacked field effect transistor (FET) 150 with a three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) fabrication manager according to some embodiments of the present disclosure.

[0022] In various embodiments, the exemplary stacked FET with three-terminal SOT MRAM fabrication manager 150 may perform the method described in FIG. 3 and / or cause one or more machines to design, fabricate, and / or utilize components as discussed in FIGS. 2A, 2B, 4A-4L, 5A, and 5B. In some embodiments, the exemplary stacked FET with three-terminal SOT MRAM fabrication manager 150 provides instructions for the above-described methods and / or functions to a client machine, such that the client machine performs the method, or portions of the method, based on the instructions provided by the exemplary stacked FET with three-terminal SOT MRAM fabrication manager 150. In some embodiments, the exemplary stacked FET with three-terminal SOT MRAM fabrication manager 150 includes software running on hardware embedded in multiple devices.

[0023] Various aspects of the present disclosure are described through text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. For any flowchart, depending on the technology involved, operations may be performed in an order different from that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in successive flowchart blocks may be performed in the reverse order, as a single integrated step, simultaneously, or in an at least partially overlapping manner.

[0024] A computer program product embodiment ("CPP embodiment" or "CPP") is a term used in this disclosure to describe any set of one or more storage media (also referred to as "media") collectively contained in one or more storage devices that collectively contain machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A "storage device" is any tangible device that can hold and store instructions for use by a computer processor. The computer-readable storage medium may be, but is not limited to, an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disc read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded device (such as pits / lands formed on a major surface of a punch card or disk), or any suitable combination of the foregoing. Computer-readable storage media, as the term is used in this disclosure, is not to be construed as storage in the form of a transitory signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through fiber optic cables, electrical signals transmitted through wires, and / or other transmission media. As will be appreciated by those skilled in the art, data is typically moved at some infrequent time during the normal operation of a storage device, such as during access, defragmentation, or garbage collection, but this does not make the storage device temporary because the data is not temporary while it is stored.

[0025] The computing environment 100 includes an example of an environment for execution of at least a portion of computer code involved in performing the methodology of the present invention, such as a stacked FET three-terminal SOT MRAM fabrication manager 150. Additionally, the computing environment 100 includes, for example, a computer 101, a wide area network (WAN) 102, an end user device (EUD) 103, a remote server 104, a public cloud 105, and a private cloud 106. In this embodiment, the computer 101 includes a processor set 110 (including processing circuitry 120 and cache 121), a communication fabric 111, volatile memory 112, persistent storage 113 (including an operating system 122 and block 150, as identified above), a peripheral device set 114 (including a user interface (UI), a device set 123, storage 124, and an Internet of Things (IoT) sensor set 125), and a network module 115. The remote server 104 includes a remote database 130. The public cloud 105 includes a gateway 140, a cloud orchestration module 141, a set of host physical machines 142, a set of virtual machines 143, and a set of containers 144.

[0026] Computer 101 may take the form of a desktop computer, a laptop computer, a tablet computer, a smartphone, a smartwatch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device now known or later developed that is capable of executing programs, accessing a network, or querying a database, such as remote database 130. As is well understood in the field of computer technology, and depending on the technology, execution of a computer-implemented method may be distributed among multiple computers and / or multiple locations. However, in this presentation of computing environment 100, to keep the presentation as concise as possible, the detailed discussion focuses on a single computer, specifically computer 101. Although computer 101 is not shown in FIG. 1 within a cloud, it may be located within a cloud. However, computer 101 is not required to reside within a cloud except to any extent that may be expressly indicated.

[0027] Processor set 110 includes one or more computer processors of any type now known or to be developed in the future. Processing circuitry 120 may be distributed across multiple packages, e.g., multiple tailored integrated circuit chips. Processing circuitry 120 may implement multiple processor threads and / or multiple processor cores. Cache 121 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by threads or cores executing on processor set 110. Cache memory is typically organized into multiple levels depending on relative proximity to the processing circuitry. Alternatively, some or all caches for a processor set may be located “off-chip.” In some computing environments, processor set 110 may be designed to operate with qubits and perform quantum computing.

[0028] Computer-readable program instructions are typically loaded onto computer 101 and cause processor set 110 of computer 101 to execute a series of operational steps, thereby enabling a computer-implemented method, such that the instructions so executed instantiate the methods specified in the computer-implemented method flowcharts and / or descriptions contained herein (collectively referred to as the "methods of the present invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 121 and other storage media discussed below. The program instructions and associated data are accessed by processor set 110 to control and direct the execution of the methods of the present invention. In computing environment 100, at least some of the instructions for executing the methods of the present invention may be stored in block 150 within persistent storage 113.

[0029] Communications fabric 111 is the signal-conducting pathway that allows various components of computer 101 to communicate with one another. Typically, this fabric is made up of switches and conductive pathways, such as switches and conductive pathways that make up buses, bridges, physical input / output ports, and the like. Other types of signal communication pathways may be used, such as fiber optic communication pathways and / or wireless communication pathways.

[0030] Volatile memory 112 may be any type of volatile memory now known or later developed. Examples include dynamic random access memory (RAM) or static RAM. Typically, volatile memory 112 is characterized by random access, although this is not required unless expressly indicated. In computer 101, volatile memory 112 is located in a single package and is internal to computer 101; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located external to computer 101.

[0031] Persistent storage 113 is any form of non-volatile storage for a computer, now known or later developed. The non-volatility of this storage means that stored data is maintained regardless of whether power is supplied to computer 101 and / or to persistent storage 113 directly. Persistent storage 113 can be read-only memory (ROM), but typically at least a portion of persistent storage allows data to be written, data to be deleted, and data to be rewritten. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 122 can take several forms, including various known proprietary operating systems or open-source Portable Operating System Interface-type operating systems that employ a kernel. The code contained in block 150 typically includes at least some of the computer code involved in performing the methods of the present invention.

[0032] The peripheral device set 114 includes a set of peripheral devices of the computer 101. Data communication connections between the peripheral devices and other components of the computer 101 may be implemented in various ways, such as Bluetooth connections, Near-Field Communication (NFC) connections, connections made by cable (such as a Universal Serial Bus (USB)-type cable), pluggable connections (e.g., a Secure Digital (SD) card), connections made through a local area communication network, and even connections made through a wide area network such as the Internet. In various embodiments, the UI device set 123 may include components such as a display screen, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. The storage 124 may be external storage, such as an external hard drive, or insertable storage, such as an SD card. The storage 124 may be persistent and / or volatile. In some embodiments, the storage 124 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 101 is required to have a large amount of storage (e.g., where computer 101 stores and manages large databases locally), this storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple, geographically distributed computers. IoT sensor set 125 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another sensor may be a motion detector.

[0033] Network module 115 is a collection of computer software, hardware, and firmware that enables computer 101 to communicate with other computers over WAN 102. Network module 115 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of network module 115 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing Software-Defined Networking (SDN)), the control and forwarding functions of network module 115 are performed on physically separate devices, such that the control function manages multiple different network hardware devices. Computer-readable program instructions for implementing the methods of the present invention may be downloaded to computer 101 from an external computer or external storage device, typically through a network adapter card or network interface included in network module 115.

[0034] WAN 102 is any wide area network (e.g., the Internet) capable of communicating computer data over non-local distances using any technology for communicating computer data now known or later developed. In some embodiments, WAN 102 may be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include copper transmission cables, optical fiber transmissions, wireless transmissions, and computer hardware such as routers, firewalls, switches, gateway computers, and edge servers.

[0035] End-user device (EUD) 103 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 101) and may take any of the forms discussed above in connection with computer 101. EUD 103 typically receives useful and useful data from the operation of computer 101. For example, in a hypothetical case where computer 101 is designed to provide recommendations to the end user, the recommendations would typically be communicated from computer 101's network module 115 over WAN 102 to EUD 103. In this manner, EUD 103 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 103 may be a client device, such as a thin client, a heavy client, a mainframe computer, a desktop computer, and the like.

[0036] Remote server 104 is any computer system that provides at least some data and / or functionality to computer 101. Remote server 104 may be controlled and used by the same entity that operates computer 101. Remote server 104 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 101. For example, in the hypothetical case where computer 101 is designed and programmed to provide recommendations based on past data, this past data may be provided to computer 101 from remote database 130 of remote server 104.

[0037] A public cloud 105 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer capabilities, particularly data storage (cloud storage) and computing power, without direct active management by users. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct active management of public cloud 105 computing resources is performed by computer hardware and / or software in cloud orchestration module 141. The computing resources provided by public cloud 105 are typically implemented by virtual computing environments running on various computers comprising host physical machine set 142, which is the universe of physical computers within and / or available in public cloud 105. Virtual computing environments (VCEs) typically take the form of virtual machines from virtual machine set 143 and / or containers from container set 144. It is understood that these VCEs may be stored as images and may be transferred among and between various physical machine hosts, either as images or after instantiation of the VCEs. Cloud orchestration module 141 manages the transfer and storage of images, deploys new instantiations of VCE, and manages active instantiations of VCE deployments. Gateway 140 is a collection of computer software, hardware, and firmware that enables public cloud 105 to communicate over WAN 102.

[0038] Some further discussion of virtualized computing environments (VCEs) is now provided. A VCE can be stored as an "image." A new, active instance of a VCE can be instantiated from an image. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to a feature of an operating system in which the kernel allows the existence of multiple isolated user space instances, called containers. These isolated user space instances typically behave as actual computers from the perspective of programs running within them. A computer program running on a typical operating system can utilize all of the computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and of the devices assigned to the container; this feature is known as containerization.

[0039] Private cloud 106 is similar to public cloud 105, except that its computing resources are available only for use by a single enterprise. While private cloud 106 is shown in communication with WAN 102, in other embodiments, the private cloud may be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private, community, or public cloud types), often each implemented by a different vendor. While each of the multiple clouds remains a separate, discrete entity, the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the constituent clouds. In this embodiment, both public cloud 105 and private cloud 106 are part of a larger hybrid cloud.

[0040] 2A is a side view of a stacked FET 200 having a three-terminal SOT MRAM according to some embodiments of the present disclosure. The stacked FET 200 includes a substrate 202, an insulating layer 204, a source / drain epitaxy (S / D epi) 205, a nanosheet channel 210, a spacer (Sp) 216, an interlayer dielectric (ILD) 218, a high-K metal gate (HK / MG) 222, a metal layer (M1) 228, a bit line (BL) 230, an SOT channel 232, and a magnetic tunnel junction (MTJ) 234. The SOT channel 232 can be a heavy metal with a high spin Hall effect (SHE). The spin Hall effect is the conversion of charge current into spin-polarized current due to spin-orbit interaction. The SOT channel 232 can be a heavy metal.

[0041] Substrate 202 may represent a layer of silicon (Si). Furthermore, insulating layer 204 may be composed of doped Si, epitaxially doped Si, buried oxide (BOX) such as silicon dioxide (SiO2), and the like. Furthermore, S / D epi 205 may represent a single crystal lattice structure across the interface. Nanosheet channel 210 may include nanosheets that may be conductive in the "on" state within a transistor or semiconducting, which may be highly resistive in the "off" state within a transistor. The conductivity may be controlled by HK / MG 222. Spacer 216 may be a layer of material deposited and etched back to provide spacing between HK / MG 222 and contacts (CA). Additionally, ILD 218 may be a dielectric material with a relatively low k constant (e.g., k = 3.9 or less). HK / MG 222 may provide a conductive gate electrode for the transistor. The HK / MG materials may differ based on the type of device being built (e.g., N-type or P-type). Metal layer 222 may provide power or ground for MRAM 200. Bit lines 230 may be a set of memory cells used to generate a memory address in conjunction with a read or write WL.

[0042] According to some embodiments of the present disclosure, the three-terminal SOT MRAM 200 may represent a structure having a three-terminal spin-orbit torque MRAM array in which an NFET transistor drives a SOT line (SL) whose gate is connected to a write word line (WW). In addition, a PFET transistor is connected to a magnetic tunnel junction (MTJ) and whose gate is connected to a read word line, and at least one type of FET (i.e., N-type) is stacked on another type of FET (i.e., P-type). This stacked NFET and PFET configuration may provide higher memory density compared to conventional three-terminal SOT MRAM.

[0043] 2B is a top view of a stacked FET 200 having a three-terminal SOT MRAM according to some embodiments of the present disclosure. The three-terminal SOT MRAM 200 includes a read word line (RWL) and a write word line (WWL) in the horizontal direction, and a SOT line (SL) and a bit line (BL) in the vertical direction. By providing current along a specific RWL or WWL and BL, the three-terminal SOT MRAM 200 can identify the specific HK / MG being written to or read from.

[0044] 2C is a schematic diagram of a stacked FET having a three-terminal SOT MRAM 200 according to some embodiments of the present disclosure. The three-terminal SOT MRAM 200 includes a RWL and a WWL in the horizontal direction and a SL and a BL in the vertical direction. Furthermore, the three-terminal SOT MRAM 200 includes an SOT channel made of a heavy metal (HM) and a magnetic tunnel junction (MTJ). An MTJ can be a magnetic storage device in which two magnetic layers are separated by an insulating barrier that, when subjected to a small electrical bias, allows an electron current, whose magnitude depends on the orientation of both magnetic layers, to tunnel through the barrier.

[0045] According to some embodiments of the present disclosure, the three-terminal SOT MRAM 200 can read data from and write data to the MTJ through the SOT channel by providing current to the S / D epi 205. The particular S / D epi 205 can be determined by the WL and BL carrier currents flowing through the contacts (CA) to the S / D epi 205. More specifically, current flowing through the read WL can cause a read operation. Similarly, current flowing through the write WL can cause a write operation. In this manner, the three-terminal SOT MRAM 200 can store and retrieve data.

[0046] More specifically, the three-terminal SOT MRAM 200 can perform read and write operations by setting values ​​for WWL, RWL, BL, and SL to either provide current (e.g., value = 1) or not provide current (e.g., value = 0). Thus, for a write operation, the three-terminal SOT MRAM 200 can set values ​​for WWL = RWL = 1. Furthermore, the three-terminal SOT MRAM 200 can set values ​​for BL / SL = Vw / GND or GND / Vw depending on the stored values. In contrast, for a read operation, the three-terminal SOT MRAM 200 can set values ​​for WWL = RWL = 0 and values ​​for BL / SL = Vr / VDD. Here, Vw and Vr refer to write and read voltages, respectively, which depend on the SOT and MTJ characteristics.

[0047] FIG. 3 (including FIGS. 3A and 3B) is a process flowchart of a method for fabricating a stacked FET device with a three-terminal SOT MRAM according to some embodiments of the present disclosure. In some embodiments, an exemplary stacked FET with a three-terminal SOT MRAM fabrication manager, such as the exemplary stacked FET with a three-terminal SOT MRAM fabrication manager 150 described with reference to FIG. 1, can perform method 300. In this method, the three-terminal SOT MRAM fabrication manager 150 can fabricate the above-described three-terminal spin-orbit torque MRAM structure using stacked nanosheet technology with wafer bonding and contact with the lower FET through an insulating oxide layer. By fabricating the three-terminal SOT MRAM 200 in this manner, some embodiments of the present disclosure can improve the areal density of current SOT MRAM devices. Furthermore, such embodiments can tune pFET current without a penalty for area using stacked nanosheets with stronger stacked FinFETs (e.g., fin height, channel orientation, or channel SiGe) or increased number of vertical stacks. In some embodiments of the present disclosure, the three-terminal SOT MRAM 200 may provide stacked FET SOT MRAM with 3 CPP for two cells (i.e., 1.5 CPP per cell). In contrast, current three-terminal SOT MRAM may provide only 3 CPP per cell. For clarity, the method 300 will be described with reference to FIGS. 4A-4L.

[0048] 4A, 4B, 4C, 4D, 4E, 4F, 4G, 4H, 4I, 4J, 4K, and 4L illustrate exemplary fabrication stages of an exemplary stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The exemplary fabrication stages 4A-4L include a top view 400-T and multiple side views (e.g., X, Y1, Y2, Y3) of the fabricated cell. Accordingly, the top view illustrates the active area 403 and three pillars 401 of the transistor. The active area 403 includes a channel region under the gate, a channel region under the spacer, and source / drain regions. The pillars 401 may represent the location of the gate of the three-terminal SOT MRAM 200.

[0049] Additionally, the side views are represented as cross sections of the cell from the perspective of the corresponding cut line in top view 400-T. For example, in FIG. 4A, view X shows a cross section of the cell along cut line X. Similarly, views Y1, Y2, and Y3 show cross sections of the cell along cut lines Y1, Y2, and Y3. In this manner, exemplary fabrication state 4A may represent the cell after operation 302 of method 300. Similarly, views X, Y1, Y2, and Y3 of exemplary fabrication states 4B-4L may represent the cell after operations 304-320, respectively.

[0050] Referring again to FIG. 3A , in operation 302, stacked FET 150 with a three-terminal SOT MRAM fabrication manager can instruct a fabrication tool to form a dummy gate and S / D epi. Forming the dummy gate can involve depositing a sacrificial layer to serve as a placeholder for the gate. More specifically, stacked FET 150 with a three-terminal SOT MRAM fabrication manager can instruct a fabrication tool to form a patterned nanosheet stack on insulating layer 404. The patterned nanosheet stack includes a sacrificial nanosheet layer 412, which can be composed of, for example, SiGe. Additionally, channel nanosheet layer 410 can be composed of, for example, Si. Furthermore, stacked FET 150 with a three-terminal SOT MRAM fabrication manager can instruct a fabrication tool to deposit dummy gate 408 and gate hard mask layer 406 on the patterned nanosheet stack and perform dummy gate patterning. Additionally, the stacked FET 150 with the three-terminal SOT MRAM fabrication manager can instruct the fabrication tool to form spacers 414 on the sidewalls of the dummy gate 408 and the gate hard mask 406. Furthermore, the stacked FET 150 with the three-terminal SOT MRAM fabrication manager can instruct the fabrication tool to etch the nanosheet stack that is not protected by the gate hard mask 406 and the spacers 414. Additionally, the stacked FET 150 with the three-terminal SOT MRAM fabrication manager can instruct the fabrication tool to perform SiGe indentation and form inner spacers. Furthermore, the stacked FET 150 with the three-terminal SOT MRAM fabrication manager can instruct the fabrication tool to grow S / D epi 405 on the exposed channel nanosheet layer 410.

[0051] 4A is an example fabrication state 400A of a stacked FET with three-terminal SOT MRAM according to some embodiments of the present disclosure. The example fabrication state 400A may represent the state of a cell of the stacked FET with three-terminal SOT MRAM after operation 302.

[0052] Field of view X includes a substrate 402, an insulating layer 404, a sacrificial nanosheet layer 412, a hard mask cap 406, and a source-drain epitaxy (S / D epi) 405. More specifically, the substrate 402 is a Si substrate. Furthermore, the insulating layer 404 may represent an insulating layer and may be composed of silicon dioxide (SiO2). In addition, the sacrificial nanosheet layer 412 may be a layer of SiGe that serves as a placeholder for a gate to be fabricated. Thus, the sacrificial nanosheet layer 412, like the gate, surrounds the channel nanosheet layer 410 of the cell 402-L. The hard mask cap 406 may provide a cap to protect the sacrificial nanosheet layer 412.

[0053] Views Y1 and Y2 include the substrate 402, the insulating layer 404, and the S / D epi 405. According to some embodiments of the present disclosure, the S / D epi 405 can be n-type epitaxy or p-type epitaxy. View Y3 includes the substrate 402, the insulating layer 404, the channel nanosheet layer 410, the sacrificial nanosheet layer 412, the hard mask cap 406, and the dummy gate 408. In this manner, exemplary fabrication state 400A can represent the result of operation 302.

[0054] 3, in operation 304, the three-terminal SOT MRAM fabrication manager 150 may perform inter-layer dielectric (ILD) deposition and chemical-mechanical planarization. Performing ILD deposition may involve depositing ILD material (e.g., ILD 418). Additionally, performing CMP may involve removing the hard mask cap 406 and surrounding spacers 414 using chemical and mechanical processes.

[0055] In operation 306, the three-terminal SOT MRAM fabrication manager 150 may form the bottom S / D sacrificial contact. Forming the bottom S / D sacrificial contact may involve depositing a sacrificial material in the ILD 418.

[0056] 4B is a block diagram of an example fabrication stage 400B of a stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure, which may represent the three-terminal SOT MRAM after operations 304 and 306.

[0057] View X includes a substrate 402, an insulating layer 404, an S / D epi 405, a dummy gate 408, a channel nanosheet layer 410, a sacrificial nanosheet layer 412, a spacer 414, and an ILD 418. The ILD 418 may be a dielectric material with a relatively low k constant (e.g., k=3.9 or less) that electrically isolates relatively close interconnect lines (e.g., channel nanosheet layers 410) arranged in multiple levels. The low-k dielectric material may reduce capacitive coupling between adjacent channel nanosheet layers 410. Compared to the exemplary fabrication state 400A, View X shows the result of operation 304, i.e., the hard mask cap 406 from the exemplary fabrication state 400A has been removed through a CMP process, and the ILD 418 has been deposited on the S / D epi 205.

[0058] The Y1 view includes the substrate 402, the insulating layer 404, the S / D epi 405, the ILD 418, and the bottom S / D sacrificial contact 420. The bottom S / D sacrificial contact 420 may be a placeholder for a contact to the S / D epi 205. The Y2 view includes the substrate 402, the insulating layer 404, the S / D epi, and the ILD 418. Compared to the exemplary fabrication state 400A, the views Y1 and Y2 show the results of operation 304, i.e., the ILD 418 has been deposited on the S / D epi 205.

[0059] View Y3 includes the substrate 402, the insulating layer 404, the dummy gate 408, the channel nanosheet layer 410, and the sacrificial nanosheet layer 412. Compared to the exemplary fabrication state 400A, view Y3 shows the result of operation 304, i.e., the hard mask cap 406 from the exemplary fabrication state 400A has been removed through a CMP process.

[0060] 3 , in operation 308, the three-terminal SOT MRAM fabrication manager 150 may form a junction oxide and a junction to the channel. Forming the junction oxide may involve creating an insulating layer of the three-terminal SOT MRAM that insulates the bottom layer from the top layer to be fabricated. In addition, bonding to the channel may involve depositing an additional sacrificial nanosheet layer 412 and a channel nanosheet layer 410.

[0061] 4C is a block diagram of an exemplary fabrication state 400C of a stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The exemplary fabrication state 400C may represent the three-terminal SOT MRAM after operation 308. Compared to the exemplary fabrication state 400B, the exemplary fabrication state 400C includes additional elements of a sacrificial nanosheet layer 412 and a channel nanosheet layer 410. More specifically, the fields of view X, Y1, Y2, and Y3 include the sacrificial nanosheet layer 412 and the channel nanosheet layer 410 on the bottom layer of the three-terminal SOT MRAM.

[0062] 3A , in operation 310, the stacked FET with three-terminal SOT MRAM fabrication manager 150 may instruct a fabrication tool to perform top active area patterning, dummy gate formation, spacer and s / d epi formation, ILD deposition, and CMP. Operation 310 may be similar to operations 302 and 304, except that operation 310 may be performed on the top layer of the stacked FET with three-terminal SOT MRAM.

[0063] 4D is a block diagram of an example fabrication state 400D of an example stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. Example fabrication state 400D may represent the three-terminal SOT MRAM after operation 310. As previously mentioned, operation 310 is similar to operations 302 and 304 described above. Accordingly, fields of view X, Y1, Y2, and Y3 include a top layer similar to the bottom layer described with respect to FIG. 4A.

[0064] Compared to exemplary fabrication state 400C, views X, Y1, Y2, and Y3 of exemplary fabrication state 400D show the result of operation 310, i.e., a top layer similar to the bottom layer below junction oxide 416. However, view Y1 does not include sacrificial bottom S / D epi contact 420 in the top layer.

[0065] 3 , in operation 312, the stacked FET 150 with three-terminal SOT MRAM fabrication manager can instruct a fabrication tool to run a gate opening mask, which can involve etching openings 421 to the top and bottom dummy gates 408 of the three-terminal SOT MRAM.

[0066] 4E is a block diagram of an example fabrication state 400E of an example stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example fabrication state 400E may represent the three-terminal SOT MRAM after operation 312.

[0067] Compared to example fabrication state 400D, example fabrication state 400E is similar with respect to fields of view X, Y1, and Y2. However, field of view Y3 includes opening 421. Thus, example fabrication state 400E represents the result of operation 312.

[0068] 3 , in operation 314, the stacked FET 150 with the three-terminal SOT MRAM fabrication manager can instruct the fabrication tool to perform dummy gate removal and SiGe release, and sacrificial gate extension removal. Removing the dummy gate can involve an etching process that removes the dummy gate 408. Furthermore, the SiGe release can involve a chemical process that removes the sacrificial nanosheet layer 412 selectively with respect to the channel nanosheet layer 410.

[0069] 4F is a block diagram of an example fabrication state 400F of an example stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. Example fabrication state 400F may represent the three-terminal SOT MRAM after operation 314.

[0070] As shown, compared to exemplary fabrication state 400E, exemplary fabrication state 400F no longer includes the elements removed by operation 314. Specifically, field of view X no longer includes dummy gate 408 and sacrificial nanosheet layer 412. Similarly, field of view Y3 no longer includes dummy gate 408 and sacrificial nanosheet layer 412. However, fields of view Y1 and Y2 remain unchanged compared to exemplary fabrication state 400E. In this manner, exemplary fabrication state 400F represents the result of operation 314.

[0071] 3 , in operation 316, stacked FET 150 with three-terminal SOT MRAM fabrication manager can instruct a fabrication tool to form a replacement gate. Forming the replacement gate can involve depositing a high-k metal gate material using opening 421 in the space created by removing dummy gate 408 and sacrificial nanosheet layer 412.

[0072] 4G is a block diagram of an example fabrication state 400G of an example stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. Example fabrication state 400G may represent the three-terminal SOT MRAM after operation 316.

[0073] In comparison to exemplary fabrication state 400F, exemplary fabrication state 400G illustrates the space vacated by operation 314 and filled with high-k metal gate material 422. Specifically, views X and Y3 include deposited high-k metal gate material 422. In contrast, views Y1 and Y2 are unchanged from exemplary fabrication state 400F. As such, exemplary fabrication state 400G represents the results of operation 316.

[0074] 3 , in operation 318, the stacked FET 150 with three-terminal SOT MRAM fabrication manager may instruct the fabrication tool to form a gate cut. Forming the gate cut may involve removing the high-k gate material 422.

[0075] 4H is a block diagram of an example fabrication state 400H of an example stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure, which may represent the three-terminal SOT MRAM after operation 318.

[0076] Compared to exemplary fabrication state 400G, views X, Y1, and Y2 are unchanged, except view Y3, which shows gate cut 424 formed by removal of high-k metal gate material 422. Thus, exemplary fabrication state 400H represents the result of operation 318.

[0077] Referring again to Figure 3A, operation 318 indicates flow to placeholder A. Placeholder A does not represent a method operation, but serves to connect the operation described in Figure 3A with other operations of method 300, which are described in more detail with respect to Figure 3B.

[0078] 3B is a process flowchart of operations 320-326 of method 300 according to some embodiments of the present disclosure. For clarity, these operations are described with respect to FIGS. 4I-4L.

[0079] The process flowchart of Figure 3B shows the flow from placeholder A to operation 320. As previously mentioned, placeholder A does not represent an operation of method 300, but serves to connect operations 302-318 described in Figure 3A with operations 320-326 described below.

[0080] In operation 320, stacked FET 150 with a three-terminal SOT MRAM fabrication manager can instruct a fabrication tool to form middle-of-line (MOL) contacts. Forming the middle-of-line contacts can involve removing ILD 418 to provide access to S / D epi 405 and bottom S / D sacrificial contact 420.

[0081] 4I is a block diagram of an example fabrication state 400I of a stacked FET with three-terminal SOT MRAM according to some embodiments of the present disclosure. The example fabrication state 400I can result from operation 320.

[0082] In comparison to example fabrication state 400H, example fabrication state 400I illustrates contact openings 423 created by removal of ILD 418 in operation 320. Specifically, views X, Y1, Y2, and Y3 include openings 423 that provide access to S / D epi 405 and bottom S / D sacrificial contact 420. In this manner, example fabrication state 400I represents the result of operation 320.

[0083] 3B , in operation 322, stacked FET 150 with three-terminal SOT MRAM fabrication manager can instruct a fabrication tool to remove the sacrificial contacts. Removing the sacrificial contacts can involve an etching process that removes bottom S / D sacrificial contacts 420.

[0084] 4J is a block diagram of an example fabrication state 400J of a stacked FET with three-terminal SOT MRAM according to some embodiments of the present disclosure. Example fabrication state 400J may result from operation 322. Compared to example fabrication state 400I, views X, Y2, and Y3 are unchanged, except view Y1 shows an opening in place of bottom S / D sacrificial contact 420. In this manner, example fabrication state 400J represents the result of operation 322.

[0085] 3B, in operation 324, stacked FET 150 with three-terminal SOT MRAM fabrication manager may instruct a fabrication tool to form contact metallization. Forming contact metallization may involve depositing a metal material to make conductive contact with S / D epi 205.

[0086] 4K is a block diagram of an example fabrication state 400K of a stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example fabrication state 400K may result from operation 324. As shown in top view 400-T, the three-terminal SOT MRAM includes contacts 426 along cut lines Y1, Y3, and Y2. Additionally, contact 426 along cut line Y2 is represented as a bit line (BL) contact.

[0087] Further, views X, Y1, and Y2 show contacts 426, 426-BL in contact with S / D epi 405 in the top and bottom layers. Additionally, view Y3 shows contact 426-BL in contact with S / D epi 405 in the top layer. Thus, exemplary fabrication state 400K represents the result of operation 324.

[0088] 3B, in operation 326, the stacked FET 150 with the three-terminal SOT MRAM fabrication manager can instruct the fabrication tool to form back-end-of-line (BEOL) connections. Forming the BEOL connections can involve depositing ILD 418 and connecting wordlines (e.g., WWL, RWL), bitlines (BL), and SOT lines (SL) to contacts 426 for S / D epi 405.

[0089] 4L is a block diagram of an example fabrication state 400L of a stacked FET with a three-terminal SOT MRAM according to some embodiments of the present disclosure. The example fabrication state 400L may result from operation 326. As shown in top view 400-T, the three-terminal SOT MRAM includes a WWL, a RWL, a BL, and a SL.

[0090] Additionally, compared to exemplary fabrication state 400K, exemplary fabrication state 400L illustrates BEOL connections. Specifically, views X, Y1, Y2, and Y3 illustrate deposited ILD 418, metal line M1 428, bit line 430, SOT line 432, WWL 434, RWL 436, MTJ 438, and heavy metal layer 440. Heavy metal layer 440 may have a relatively high SHE. As such, exemplary fabrication state 400L illustrates the results of operation 326.

[0091] A non-limiting list of examples is provided below to demonstrate some aspects of the present disclosure.

[0092] Example 1 is a three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device comprising: a first-type field effect transistor (FET) driving an SOT line, where the first-type FET has a write gate in electrical contact with a write word line (WWL); and a second-type FET in electrical contact with a magnetic tunnel junction (MTJ), where the second-type FET has a read gate in electrical contact with a read word line (RWL), the first-type FET being disposed above the second-type FET, and the three-terminal SOT MRAM device provides a density of three contact poly pitches (CPP) per two cells.

[0093] Example 2 includes the device of Example 1, including or excluding optional features. In this example, the first type FET comprises an n-type FET (NFET). Optionally, the second type FET comprises a p-type FET (PFET).

[0094] Example 3 includes the device of any one of Examples 1-2, including or excluding optional features. In this example, the first type FET comprises a PFET. Optionally, the second type FET comprises an NFET.

[0095] Example 4 includes the device of any one of Examples 1-3, including or excluding optional features. In this example, the device includes a substrate; and an insulating layer disposed between the second type FET and the substrate. Optionally, the insulating layer comprises a material selected from the group consisting of doped silicon (Si); epitaxially doped Si; and buried oxide.

[0096] Example 5 includes the device of any one of Examples 1 to 4, including or excluding optional features. In this example, the device includes: the SOT line having a heavy metal; and the MTJ.

[0097] Example 6 is a three-terminal SOT MRAM device comprising: an NFET driving an SOT line, the NFET having a write gate in electrical contact with a WWL; and a PFET in electrical contact with an MTJ, the PFET having a read gate in electrical contact with a RWL, the PFET being disposed above the NFET.

[0098] Example 7 includes the device of Example 6, including or excluding optional features. In this example, the three-terminal SOT MRAM device provides a density of 1.5 CPP per cell.

[0099] Example 8 includes the device of any one of Examples 6-7, including or excluding optional features. In this example, the device includes a substrate; and an insulating layer disposed between the second type FET and the substrate. Optionally, the insulating layer comprises a material selected from the group consisting of doped silicon (Si); epitaxially doped Si; and buried oxide.

[0100] Example 9 is a three-terminal SOT MRAM device. The device comprises a PFET driving an SOT line, the PFET having a write gate in electrical contact with a WWL; and an NFET in electrical contact with an MTJ, the NFET having a read gate in electrical contact with a RWL, the NFET being disposed above the PFET. Optionally, the three-terminal SOT MRAM device provides a density of 1.5 CPP per cell. Optionally, the device comprises a substrate; and an insulating layer disposed between the second type FET and the substrate. Optionally, the insulating layer comprises a material selected from the group consisting of doped silicon (Si); epitaxially doped Si; and buried oxide.

[0101] Example 10 is a method for fabricating a three-terminal SOT MRAM device. The method includes: forming a lower dummy gate on an insulating layer in contact with a substrate; forming a lower source / drain epitaxy (S / D epi); performing interlayer dielectric (ILD) deposition on the dummy gate and lower S / D epi; performing chemical mechanical planarization to remove a gate hard mask for the lower dummy gate and a plurality of spacers in contact with the gate hard mask; forming a lower S / D sacrificial contact in contact with the lower S / D epi; forming a junction oxide layer disposed above a bottom layer including the lower dummy gate; bonding the junction oxide layer to a plurality of nanosheet channels in a top layer, the top layer including a plurality of sacrificial nanosheet layers in contact with the plurality of nanosheet channels; performing active device patterning on the top layer; forming an upper dummy gate for the top layer; and forming a plurality of spacers for the top layer. forming a spacer; forming an upper S / D epi for the top layer; depositing an ILD for the top layer; performing CMP to remove a hard mask for the top layer and the spacers for the top layer; forming a gate opening mask; removing the upper dummy gate and the lower dummy gate; performing a SiGe release; removing the sacrificial nanosheet layers; forming replacement gates for the top and bottom layers; forming a plurality of gate cuts providing access to the upper S / D epi and the lower S / D epi; forming a plurality of middle-of-line (MOL) contacts; removing the lower S / D sacrificial contacts; forming contact metallization using the plurality of gate cuts; and forming a plurality of back-end-of-line (BEOL) connections. Optionally, the three-terminal SOT MRAM device provides a density of three contact poly pitches (CPPs) per two cells.

[0102] Example 11 includes the method of any one of Examples 10-11, including or excluding optional features. In this example, forming the replacement gates for the top and bottom layers includes: forming a lower replacement gate for the removed lower dummy gate; and forming an upper replacement gate for the removed upper dummy gate. Optionally, the lower S / D epi includes an n-type field effect transistor (NFET) and the upper S / D epi includes a p-type field effect transistor (PFET). Optionally, the lower S / D epi includes a PFET and the upper S / D epi includes an NFET.

[0103] Example 12 is a computer program product comprising program instructions stored on a computer-readable storage medium. The computer-readable medium can direct a processor to: form a lower dummy gate on an insulating layer in contact with a substrate; form a lower source / drain epitaxy (S / D epi); perform interlayer dielectric (ILD) deposition on the dummy gate and the lower S / D epi; perform chemical mechanical planarization to remove a gate hard mask of the lower dummy gate and a plurality of spacers in contact with the gate hard mask; form a lower S / D sacrificial contact in contact with the lower S / D epi; form a junction oxide layer disposed above a bottom layer including the lower dummy gate; bond the junction oxide layer to a plurality of nanosheet channels in a top layer, the top layer including a plurality of sacrificial nanosheet layers in contact with the plurality of nanosheet channels; perform active device patterning on the top layer; form an upper dummy gate in the top layer; and the instructions direct: forming a plurality of spacers for the top layer; forming a top S / D epi for the top layer; depositing an ILD for the top layer; performing CMP to remove a hard mask for the top layer and the spacers for the top layer; forming a gate opening mask; removing the upper dummy gate and the lower dummy gate; performing a SiGe release; removing the plurality of sacrificial nanosheet layers; forming replacement gates for the top and bottom layers; forming a plurality of gate cuts providing access to the top S / D epi and the lower S / D epi; forming a plurality of middle-of-line (MOL) contacts; removing the lower S / D sacrificial contacts; forming contact metallization using the plurality of gate cuts; and forming a plurality of back-end-of-line (BEOL) connections. Optionally, the three-terminal SOT MRAM device provides a density of three contact poly pitches (CPP) per two cells.

[0104] Example 13 includes the computer-readable medium of any one of Examples 12-12, including or excluding optional features. In this example, forming the replacement gates for the top and bottom layers includes: forming a lower replacement gate for the removed lower dummy gate; and forming an upper replacement gate for the removed upper dummy gate. Optionally, the lower S / D epi includes an n-type field effect transistor (NFET) and the upper S / D epi includes a p-type field effect transistor (PFET). Optionally, the lower S / D epi includes a PFET and the upper S / D epi includes an NFET.

Claims

1. 1. A three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device comprising: a first type field effect transistor (FET) driving a SOT line, the first type FET having a write gate in electrical contact with a write word line (WWL); and a second-type FET in electrical contact with a magnetic tunnel junction (MTJ), wherein the second-type FET has a read gate in electrical contact with a read word line (RWL), and the first-type FET is disposed above the second-type FET, and the three-terminal SOT MRAM device provides a density of three contact poly pitches (CPPs) per two cells.

1. A three-terminal spin-orbit torque (SOT) magnetoresistive random access memory (MRAM) device comprising:

2. The three-terminal SOT MRAM device of claim 1 , wherein the first type FET comprises an n-type FET (NFET).

3. The three-terminal SOT MRAM device of claim 2 , wherein the second type FET comprises a p-type FET (PFET).

4. The three-terminal SOT MRAM device of claim 1 , wherein the first type FET comprises a PFET.

5. The three-terminal SOT MRAM device of claim 4 , wherein the second type FET comprises an NFET.

6. a substrate; and an insulating layer disposed between the second type FET and the substrate; The three-terminal SOT MRAM device of claim 1 further comprising:

7. The insulating layer comprises: doped silicon (Si); epitaxially doped Si; and buried oxide film 7. The three-terminal SOT MRAM device of claim 6, comprising a material selected from the group consisting of:

8. the SOT wire having a heavy metal; and Said MTJ The three-terminal SOT MRAM device of claim 1 further comprising:

9. an NFET driving the SOT line, the NFET having a write gate in electrical contact with the WWL; and a PFET in electrical contact with the MTJ, the PFET having a read gate in electrical contact with the RWL, the PFET being disposed above the NFET; 1. A three-terminal SOT MRAM device comprising:

10. The three-terminal SOT MRAM device of claim 9 , wherein the three-terminal SOT MRAM device provides a density of 1.5 CPP per cell.

11. a substrate; and an insulating layer disposed between the NFET and the substrate; The three-terminal SOT MRAM device of claim 9 further comprising:

12. The insulating layer comprises: doped silicon (Si); epitaxially doped Si; and buried oxide film 12. The three-terminal SOT MRAM device of claim 11, comprising a material selected from the group consisting of:

13. a PFET driving the SOT line, the PFET having a write gate in electrical contact with the WWL; and an NFET in electrical contact with the MTJ, wherein the NFET has a read gate in electrical contact with the RWL, the NFET being disposed above the PFET, and the three-terminal SOT MRAM device provides a density of 1.5 CPP per cell.

1. A three-terminal SOT MRAM device comprising:

14. a substrate; and an insulating layer disposed between the PFET and the substrate; 14. The three-terminal SOT MRAM device of claim 13, further comprising:

15. The insulating layer comprises: doped silicon (Si); epitaxially doped Si; and buried oxide film 15. The three-terminal SOT MRAM device of claim 14, comprising a material selected from the group consisting of:

16. 1. A method for fabricating a three-terminal SOT MRAM device, comprising: forming a lower dummy gate on the insulating layer in contact with the substrate; forming a lower source / drain epitaxy (S / D epi); performing interlayer dielectric (ILD) deposition on the dummy gate and lower S / D epi; a gate hard mask for the lower dummy gate; and a plurality of spacers in contact with the gate hard mask; performing chemical mechanical planarization to remove forming a lower S / D sacrificial contact in contact with the lower S / D epi; forming a junction oxide layer disposed above a lowermost layer including the lower dummy gate; bonding the bonding oxide film to a plurality of nanosheet channels in a top layer, wherein the top layer includes a plurality of sacrificial nanosheet layers in contact with the plurality of nanosheet channels; performing active device patterning on said top layer; forming an upper dummy gate on the top layer; forming a plurality of spacers for the top layer; forming a top S / D epi for the top layer; depositing an ILD for the top layer; the top hard mask; and the plurality of spacers for the top layer performing CMP to remove forming a gate opening mask; removing the upper dummy gate and the lower dummy gate; performing a SiGe release; removing the plurality of sacrificial nanosheet layers; forming replacement gates for the top and bottom layers; forming a plurality of gate cuts providing access to the upper S / D epi and the lower S / D epi; forming a plurality of middle-of-line (MOL) contacts; removing the lower S / D sacrificial contact; forming contact metallization using the plurality of gate cuts; and Forming a plurality of back-end-of-line (BEOL) connections A method for providing the above.

17. 17. The method of claim 16, wherein the three-terminal SOT MRAM device provides a density of three contact poly pitches (CPP) per two cells.

18. Forming the replacement gates for the top and bottom layers comprises: forming a lower replacement gate for the removed lower dummy gate; and forming an upper replacement gate for the removed upper dummy gate; 18. The method of claim 17, comprising:

19. 20. The method of claim 18, wherein the bottom S / D epi comprises an n-type field effect transistor (NFET) and the top S / D epi comprises a p-type field effect transistor (PFET).

20. 20. The method of claim 18, wherein the bottom S / D epi comprises a PFET and the top S / D epi comprises an NFET.

21. 1. A computer program product comprising program instructions stored on a computer-readable storage medium, the program instructions causing a processor to: forming a lower dummy gate on the insulating layer in contact with the substrate; forming a lower source / drain epitaxy (S / D epi); performing inter-layer dielectric (ILD) deposition on the dummy gate and lower S / D epi; a gate hard mask for the lower dummy gate; and a plurality of spacers in contact with the gate hard mask; performing chemical mechanical planarization to remove forming a lower S / D sacrificial contact in contact with said lower S / D epi; forming a junction oxide film disposed above a bottom layer including the lower dummy gate; bonding the bonding oxide film to a plurality of nanosheet channels in a top layer, wherein the top layer includes a plurality of sacrificial nanosheet layers in contact with the plurality of nanosheet channels; performing active device patterning on said top layer; forming an upper dummy gate on the top layer; forming a plurality of spacers for the top layer; forming a top S / D epi for said top layer; depositing an ILD for the top layer; the top hard mask; and the plurality of spacers for the top layer performing CMP to remove forming a gate opening mask; removing the upper dummy gate and the lower dummy gate; Procedure for performing SiGe release; removing the plurality of sacrificial nanosheet layers; forming replacement gates for said top and bottom layers; forming a plurality of gate cuts providing access to the top S / D epi and the bottom S / D epi; forming a plurality of middle-of-line (MOL) contacts; removing said lower S / D sacrificial contact; forming contact metallization using the plurality of gate cuts; and Procedure for forming multiple back-end-of-line (BEOL) connections a computer program product executable by the processor to cause a method having the steps of:

22. 22. The computer program product of claim 21, wherein the three-terminal SOT MRAM device provides a density of three contact poly pitches (CPPs) per two cells.

23. The steps for forming the replacement gates for the top and bottom layers include: forming a lower replacement gate for the removed lower dummy gate; and forming an upper replacement gate for said removed upper dummy gate; 23. The computer program product of claim 22, comprising:

24. 24. The computer program product of claim 23, wherein the bottom S / D epi comprises an n-type field effect transistor (NFET) and the top S / D epi comprises a p-type field effect transistor (PFET).

25. 24. The computer program product of claim 23, wherein the bottom S / D epi comprises a PFET and the top S / D epi comprises an NFET.

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