Command placement method, unit, display processing device and electronic device

Abstract

This application provides a command placement method, a unit, a display processing device, and an electronic device, which relate to the field of data transfer. The command placement unit includes a read data module including a buffer and a selector, in which a plurality of buffer areas are provided in the buffer, and a plurality of command interfaces configured to correspond to different buffer areas and connected to the image processing modules, respectively. The selector is configured to receive the read data and store the read data in the corresponding buffer area based on the identification information. Each command interface is configured to retrieve the read data from the corresponding buffer area and assign it to the image processing module based on a placement command in the read data. The command placement unit can improve bus bandwidth utilization and increase the efficiency of command placement for each module of the display processing device.

Description

[Technical Field]

[0001] The present application relates to the field of data transfer, and in particular to a command configuration method (also called a command setting method or command installation method), a unit, a display processing device and an electronic device. [Background technology]

[0002] A DPU (Display Processor Unit) processes image data and sends it to a display device by configuring (also called setting or installation) parameters for each image processing module within the DPU in response to control commands from a CPU (Central Processing Unit).

[0003] Currently, the DPU transfers control commands using DMA (Direct Memory Access). The DPU uses DMA technology to read control commands from DRAM (Dynamic Random Access Memory) and send them to the DPU. The DPU then analyzes the control commands to obtain configuration parameters, and allocates each image processing module within the DPU based on the configuration parameters, allowing the DPU to perform the corresponding function.

[0004] With DMA technology, the bandwidth of the transfer bus for reading control commands from DRAM can reach 128 bits or 256 bits, but the bandwidth of the interface bus for the DPU to receive control commands is only 32 bits. Therefore, when transferring control commands to the DPU using DMA technology, only a bus with a bandwidth of 32 bits can be used, and the bandwidth of the transfer bus cannot be fully utilized.

[0005] Furthermore, as requirements for image dynamic range, frame rate, resolution, etc. increase, the number of image processing modules required in the DPU increases, placing a greater burden on the CPU for DPU allocation. Furthermore, since the DPU shares a command allocation system with other modules or circuits within the device, all of which read commands from DRAM based on DMA, if the DPU cannot fully utilize its own transfer bandwidth or bus bandwidth, the overall performance of the device in which it resides will be affected. Summary of the Invention [Problem to be solved by the invention]

[0006] In view of this, the present application aims to provide a command placement method, unit, display processing device, and electronic device to improve bandwidth utilization by the display processing device and improve the efficiency of command placement for each module of the display processing device. [Means for solving the problem]

[0007] In a first aspect, an embodiment of the present application provides a command placement unit, the command placement unit including: a buffer; a selector connected to the buffer; the buffer being provided with a plurality of buffer areas; the selector being connected to a memory that outputs read data; the read data including a placement command and identification information, the placement command including parameters for placing each image processing module in a display processing device, the identification information indicating a buffer area corresponding to the read data; and a plurality of command interfaces respectively connected to the buffer, each configured to correspond to a different buffer area and connected to each of the image processing modules; the selector being configured to receive the read data and store the read data in a corresponding buffer area based on the identification information; and each of the command interfaces being configured to retrieve the read data from the corresponding buffer area and place the image processing module based on the placement command in the read data.

[0008] In an embodiment of the present application, the command interface acquires a placement command from the read data and places the image processing module, so that when transferring the read data and read request, the read data does not need to be transferred according to the bandwidth of the interface of the image processing module, but can be transferred according to the bandwidth of the transfer bus which is larger than the bit width of the interface of the image processing module, thereby improving the utilization rate of the transfer bandwidth and improving the placement efficiency of the display processing device. In addition, the command placement unit can request or analyze multiple placement commands in parallel, further improving the placement efficiency of the display processing device.

[0009] In one embodiment, the command placement unit further includes a read request module having a plurality of read request generators each corresponding to a different command interface, wherein each of the read request generators is configured to send a read request to the memory, and the memory is configured to send the read data to the buffer in response to the read request.

[0010] In an embodiment of the present application, a read request module is provided with multiple read request generators, and different read request generators correspond to different command interfaces, so that each read request module can generate read requests corresponding to different command interfaces. This allows multiple read requests to be generated and issued in parallel, which effectively improves the efficiency of read request generation compared to a method in which read requests are generated and issued one by one. This improves the efficiency of obtaining placement commands for each image processing module, and improves the placement efficiency for the image processing modules.

[0011] In one embodiment, the read request module further includes a read request arbiter connected to each of the read request generators and connected to the memory, the read request arbiter configured to control the output order of each of the read requests based on a preset output priority rule.

[0012] Some image processing modules have high requirements for real-time performance, requiring the memory to receive read requests one by one. In response to this, in an embodiment of the present application, a read request arbiter is provided in the read request module, so that read requests corresponding to command interfaces with higher priority are given priority and output to the memory, and read data is read, thereby satisfying the real-time requirement for obtaining placement commands for each image processing module.

[0013] In one embodiment, the read data module further includes an address cache memory respectively connected to the buffer and each of the command interfaces, the address cache memory being configured to store a write address of the read data in the buffer area and a read address of the read data read from the buffer area, the command interface being configured to read the read data from the buffer area according to the write address, and the selector being configured to store the read data in the corresponding buffer area based on the read address and the identification information.

[0014] In an embodiment of the present application, by using an address cache memory to record read addresses and write addresses, the command interface can accurately obtain read data from the buffer, thereby improving the accuracy of the placement of the image processing module.

[0015] In one embodiment, the read data module further includes a base address memory group having a plurality of base address memories, the address cache memory is respectively connected to each of the command interfaces via each of the base address memories, and the base address memory provides the write address to the command interface connected to this base address memory after the read data is stored in the buffer area.

[0016] In one embodiment of the present application, by recording the write address based on the base address memory group, the command interface only needs to receive the write address stored in the corresponding base address memory, and there is no need to set up additional judgment logic, thereby improving the layout efficiency of the command interface. In one embodiment, the read data module further includes a buffer read arbiter connected to the buffer and each of the command interfaces, and the buffer read arbiter instructs each of the command interfaces to obtain the read data from the buffer.

[0017] In the embodiments of the present application, since normally only one command interface can read the buffer at the same time, a buffer read arbiter is provided to instruct each command interface to obtain read data from the buffer in order, thereby reducing the possibility of data loss and reading errors and improving the accuracy of the display processing device placement.

[0018] In one embodiment, each of the command interfaces includes a command cache memory 121 connected to the buffer and a command parser, the command cache memory 121 is connected to the command parser, the command parser is connected to the image processing module, the command cache memory 121 stores the read data obtained from the buffer, and the command parser outputs the read data to the image processing module in a predetermined format for configuring the image processing module.

[0019] In an embodiment of the present application, the command cache memory 121 temporarily stores data output to the display processing device module, allowing the command parser to read and output read data from the command cache memory 121 in a predetermined format. The command cache memory 121 and the command parser enable the command interface to perform data conversion, converting placement commands into data usable by the image processing module. This allows the bandwidth of the read data before being transferred to the image processing module to be greater than the bandwidth of the image processing module, making full use of the bandwidth of the transfer bus and improving the placement efficiency of the image processing module.

[0020] In one embodiment, the command parser includes a first parser or a second parser, the placement command includes a coefficient command for placing an image processing module having a 3D lookup table, and the second parser is configured to output the read data to the image processing module according to the size of the output band of the second parser, and the output band of the second parser in each of the command interfaces respectively matches the band of each of the image processing modules having the 3D lookup table in the display processing device.

[0021] In an embodiment of the present application, an image processing module having a 3DLUT (3D Look Up Table) receives coefficient commands for configuring the 3D lookup table. However, different coefficient commands have different bandwidths, and transmitting the coefficient commands over the same bandwidth may result in insufficient bandwidth utilization. Therefore, a second parser is provided in the command interface, and the output bandwidth of each second parser is matched to the bandwidth of each image processing module having a 3D lookup table within the display processing device. Image processing modules with different bandwidths can be analyzed by the corresponding second parser, and the output coefficient commands can be matched to each image processing module. This allows system command configuration to be completed in one go, eliminating the need to perform configuration multiple times or introduce invalid data, and enabling full bandwidth utilization.

[0022] In one embodiment, the buffer areas corresponding to each of the command interfaces share the memory space of the buffer, and the memory space corresponding to each of the buffer areas is allocated according to the number of read data corresponding to each of the command interfaces in the buffer.

[0023] In this embodiment, the size of the storage space corresponding to the cache area is dynamically allocated according to the number of read data, so that sufficient storage space can be allocated for the read data in different read data transfers, thereby satisfying the demands for different read data transfers and expanding the application range of the command placement unit.

[0024] An embodiment of the present application further provides a command placement method, which is applied to a command placement unit including a buffer and a selector connected to the buffer, wherein the buffer is provided with a plurality of buffer areas, the selector is connected to a memory that outputs read data, the read data including a placement command and identification information, the placement command including parameters for placing a display processing device, the identification information indicating a buffer area corresponding to the read data, and a plurality of command interfaces respectively connected to the buffer, each configured to correspond to a different buffer area, and each connected to the display processing device, the command placement method including the steps of: receiving the read data by the selector; storing the read data in a corresponding buffer area based on the identification information of the read data received by the selector; obtaining the read data from the buffer area corresponding to the command interface by the command interface; and placing the display processing device based on the placement command in the read data by the command interface.

[0025] In a third aspect, an embodiment of the present application provides a display processing device, the display processing device including: a command placement unit according to any one of the first aspects; and a plurality of image processing modules each connected to the command placement unit.

[0026] In a fourth aspect, an embodiment of the present application provides an electronic device, the electronic device including the display processing device according to the third aspect, a controller, and a memory connected to the controller and the display processing device, respectively, the controller configured to generate the read data and store the read data in the memory, and the memory responding to a read request from the display processing device and outputting the read data to the display processing device.

[0027] In one embodiment, the memory is provided with a plurality of storage areas, each of which corresponds to a different command interface and is configured to store read data corresponding to each of the command interfaces.

[0028] In a fifth aspect, an embodiment of the present application provides an image display system, including the electronic device according to any one of the fourth aspects, and a display device communicatively connected to the electronic device for displaying image data output from the display processing device.

[0029] In order to more clearly explain the technical solutions of the embodiments of the present application, the following will briefly explain the drawings necessary for explaining the embodiments. The following drawings only illustrate some embodiments of the present application and are not intended to limit the scope. Those skilled in the art can obtain other related drawings based on these drawings without using inventive abilities. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 2 is a schematic diagram of a command placement unit according to an embodiment of the present application; [Figure 2] FIG. 2 is a schematic diagram of a buffer storage space according to an embodiment of the present application; [Figure 3] FIG. 2 is another schematic diagram of a command placement unit according to an embodiment of the present application; [Figure 4] FIG. 10 is a schematic diagram of a read by a buffer read arbiter according to an embodiment of the present application. [Figure 5] FIG. 10 is an operational schematic diagram of a read request module according to an embodiment of the present application; [Figure 6] FIG. 2 is a schematic diagram of receiving and analyzing read data according to an embodiment of the present application. [Figure 7] 1 is a flowchart of a command placement method according to an embodiment of the present application. [Figure 8] 1 is a schematic diagram of a display processing device according to an embodiment of the present application; [Figure 9]1 is a schematic diagram of an electronic device according to an embodiment of the present application; [Figure 10] 1 is a schematic diagram of an image display system according to an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0031] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be described in more detail below with reference to the drawings using examples, It should be noted that the specific examples described herein are only for the purpose of illustrating the present application and are not intended to limit the present application.

[0032] 1 is a schematic diagram of a command placement unit 100 according to an embodiment of the present application. The command placement unit 100 includes a read data module 110 and a plurality of command interfaces 120.

[0033] The read data module 110 includes a buffer 112 and a selector 111 connected to the buffer 112. The buffer 112 is provided with a plurality of buffer areas, and the selector 111 is connected to a memory that outputs the read data.

[0034] The buffer 112 may be various types of memory, such as a static random-access memory (SRAM), a dynamic random-access memory (DRAM), or a pseudo static random-access memory (PSRAM).

[0035] After generating the placement commands, the DPU stores the placement commands in memory for retrieval from the memory. The image processor DPU includes multiple image processing modules, and the placement commands are for placing different image processing modules.

[0036] 2 is a schematic diagram of the storage space of a buffer according to one embodiment of the present application. In this embodiment of the present application, since multiple command interfaces 120 are included, the storage space of the buffer 112 is divided into multiple buffer areas, and one command interface 120 is assigned to each buffer area, so that read data corresponding to each command interface 120 is stored in each buffer area. The size of the buffer area can be set as needed; for example, the size of one buffer area may be 256 bytes, 512 bytes, etc.

[0037] In some embodiments, buffer areas corresponding to each command interface share the buffer space, and the storage space corresponding to each buffer area is dynamically allocated according to the number of read data corresponding to each command interface of the buffer. For example, if there are 10 command interfaces, there are 10 corresponding buffer areas, and the 10 buffer areas share the storage space of one buffer. If 10 read data are stored in one buffer, when the storage space is equally divided, each of the 10 buffer areas is allocated space for storing one read data. In contrast, in this embodiment, storage space is allocated to each buffer area according to the number of read data input to the cache memory and the command interface corresponding to each read data. The storage space allocated to one buffer area can be as much as the buffer's storage space or as little as 0. For example, if 9 input read data are data corresponding to command interface 1 and 1 read data are data corresponding to command interface 2, the buffer area corresponding to command interface 1 is allocated storage space for storing 9 read data, the buffer area corresponding to command interface 2 is allocated storage space for storing 1 read data, and the other buffer areas are allocated no storage space, i.e., 0. The above are examples only and are not intended to limit the present application.

[0038] In this embodiment, the read data includes a placement command and identification information, and the placement command includes parameters for placing each image processing module of the display processing device. The specific content of these can be found in the prior art and will not be described here. The identification information represents a buffer area corresponding to the read data, and may be information representing the buffer area, such as an address or number. Furthermore, since the buffer area corresponds to a command interface, the identification information can also represent the command interface.

[0039] In addition, in order to store each read data in a corresponding buffer area, a selector 111 is installed between the buffer 112 and a memory external to the command placement unit 100. The selector 111 can store each read data in a corresponding buffer area based on the identification information.

[0040] A plurality of command interfaces 120 are respectively connected to the buffer 112 and configured to respectively correspond to different buffer areas, and are also respectively connected to the image processing modules.

[0041] In an embodiment of the present application, the selector 111 is configured to receive read data and store the read data in a corresponding buffer area based on the identification information. Each command interface 120 is configured to obtain the read data from the corresponding buffer area and allocate the read data to an image processing module based on an allocation command of the read data. Thus, before outputting the allocation command to each image processing module of the display processing device, the read data is transferred between the memory and the buffer 112 in accordance with the bandwidth (e.g., 128 bits, 256 bits, etc.) of the transfer bus and stored in the buffer 112. Each command interface 120 is connected to an image processing module and converts the read data into data (e.g., 32 bits) that is compatible with the bandwidth of the image processing module. Furthermore, multiple command interfaces 120 operate in parallel, allowing the transferred read data to be processed in a timely manner. The buffer 112 allows the transfer of read data to better utilize the bandwidth of the transfer bus. The command interface 120 allows the transferred read data to be used. The parallel operation of multiple command interfaces 120 improves the allocation efficiency for multiple image processing modules. This allows the command placement unit 100 to improve bandwidth utilization and placement efficiency of image processing modules.

[0042] In some embodiments, the command placement unit 100 is provided with a control unit (not shown). The control unit may be a single control circuit or a combination of multiple control circuits. The control unit includes various control logics for controlling the cooperative operation of each part of the command placement unit 100. In some embodiments, the control unit may be a controller of a display processing device.

[0043] FIG. 3 is another schematic diagram of a command placement unit 100 according to an embodiment of the present application.

[0044] In one embodiment, the command placement unit 100 may further include a read request module 130 having a plurality of read request generators 131, each corresponding to a different command interface 120. Each read request generator 131 is configured to send a read request to the memory, and the memory is configured to send read data to the buffer 112 in response to the read request.

[0045] The display processing device obtains a placement command by sending a read request to an external memory. However, in the embodiment of the present application, because there are multiple command interfaces 120, if the display processing device continues to generate read requests one by one, the efficiency of read request generation is low and the bandwidth utilization of the transfer bus remains low. Therefore, in this embodiment, one read request generator 131 is provided for each different command interface 120, which generates multiple read requests in parallel and sends the read requests to the memory to obtain the read data. This reduces the waiting time when generating read requests, improves the efficiency of read request generation, and improves the placement efficiency of image processing modules.

[0046] In the above embodiment, the number of read request generators 131, command interfaces 120 and buffer areas may be the same as the number of image processing modules in the display processing device.

[0047] In one embodiment, the read request module 130 may further include a read request arbiter 132 connected to each read request generator 131 and connected to the memory. The read request arbiter 132 is configured to control the output order of each read request based on a preset output priority rule.

[0048] Memory reads by a display processing device are typically performed one at a time, meaning that read requests are typically output one at a time. For example, when an AXI (Advanced eXtensible Interface, a bus protocol) bus is used as a transfer bus, the AXI interface can only issue one read request at a time. However, some image processing modules within a display processing device have high requirements for real-time performance. If multiple read requests are generated simultaneously and the requests of these image processing modules are controlled to wait for output, there is a risk that the read data obtained subsequently will not meet the needs of these image processing modules.

[0049] Therefore, for such an image processing module, a read request arbiter 132 connected to the output terminal of each read request generator 131 may be provided, and the read requests may be output to memory after being arbitrated by the read request arbiter 132. An output priority rule is provided in the read request arbiter 132, and the output order of each read request is controlled based on the output priority rule.

[0050] The priority rules may be set according to the needs of the image processing module in the display processing device. The read request arbiter 132 may be an arbitration circuit for realizing round robin arbitration, weighted round robin arbitration, etc. The arbitration circuit may refer to the prior art, and will not be described here.

[0051] In one embodiment, the read data module 110 further includes an address cache memory 113. The address cache memory 113 is respectively connected to the buffer 112 and each command interface 120, and configured to store a write address of the read data in the buffer area and a read address of the read data read from the buffer area.

[0052] In this embodiment, read data is stored in a buffer area of ​​the buffer 112, but when multiple pieces of read data are stored in the same buffer area, it is necessary to distinguish between readable read data and overwritable read data within this buffer area. For this reason, an address cache memory is provided, connected to each of the buffer 112 and each command interface 120. This address cache memory records the write address of the read data within the buffer area and the read address of the read data that has been read. Based on the write address and read address, the command interface 120 determines whether there is unread read data in the buffer 112, and if there is unread read data, obtains the read data from the buffer 112.

[0053] Furthermore, after the selector 111 determines the corresponding buffer area based on the identification information, it further acquires the read address corresponding to this buffer area and determines the overwritable storage space in this buffer area.

[0054] In the above embodiment, the address cache memory 113 may be realized by a conventional cache memory, which will not be described here.

[0055] In some embodiments, the read data module 110 further includes a base address memory group 114 having a plurality of base address memories, and the address cache memory 113 is connected to each command interface 120 via each base address memory.

[0056] In this embodiment, when the command interface 120 does not have the function of determining the read address and the write address, a base address memory is provided. The base address memory acquires a readable write address in the corresponding buffer area of ​​the address cache memory 113 from the corresponding buffer area and provides it to the corresponding command interface 120.

[0057] The base address memory can be a device having a conventional storage function, and may be, for example, a FIFO (First Input First Output) memory, a register, or the like.

[0058] In one embodiment, the read data module 110 further includes a buffer read arbiter 115. The buffer read arbiter 115 is connected to the buffer 112 and each command interface 120. The buffer read arbiter 115 instructs each command interface 120 to obtain read data from the buffer 112.

[0059] Similar to the principle of the read request arbiter 132, when a command interface 120 reads the buffer 112 at the same time, normally only one command interface 120 can read the buffer 112. In this embodiment, when multiple command interfaces 120 need to read the buffer 112 at the same time, the buffer read arbiter 115 instructs each command interface 120 to read in turn, thereby reducing the possibility of data loss and read errors.

[0060] Next, the command interface 120 currently permitted to receive read data is configured to acquire the read data with priority, and the read request arbiter 132 instructs the command interface with the highest priority to acquire the read data with priority. For example, as shown in Figure 4, after the buffer read arbiter determines the command interface that will acquire the read data, it returns this command interface and the write address of the read data to the buffer, so that the command interface can acquire the read data from the buffer area of ​​the buffer according to the write address.

[0061] In the embodiment of the present application, the format of the read data is a data format compatible with the bandwidth of the transfer bus, and may not be directly usable by the image processing module, so the command interface 120 must convert it into a data format usable by the image processing module. Because the conversion process takes time, in this case, the command interface 120 may not be able to receive the read data or may not be permitted to receive it. In response to this, in the present embodiment, the command interface 120 permitted to receive the read data is given priority in obtaining the read data.

[0062] In some embodiments, the preset read priority rule may be set according to, but is not limited to, the real-time read data requirement of the image processing module corresponding to each command interface 120. The buffer read arbiter 115 may refer to a conventional arbitration circuit and will not be described here.

[0063] In one embodiment, each command interface 120 includes a command cache memory 121 and a command parser connected to the buffer 112. The command cache memory 121 is connected to the command parser, which is connected to the image processing module.

[0064] Since the bandwidth of the transfer bus may not match the interface bandwidth of the display processing device, the command interface 120 needs to convert the bandwidth of the read data so that the placement commands in the read data can be used to place the image processing modules within the display processing device.

[0065] In this embodiment, the command cache memory 121 stores read data obtained from the buffer 112. The command parser outputs the read data to the image processing module in a predetermined format in order to allocate the image processing module. Here, the predetermined format may be, for example, a data size of 4 bytes, 32 bytes, or the like. The data size corresponding to the predetermined format is the same as the interface bandwidth of the image processing module.

[0066] The command cache memory 121 can temporarily store read data. On the one hand, storing multiple read data can reduce the storage load on the buffer 112. On the other hand, since the data size corresponding to a predetermined format is usually smaller than the size of a single read data, and the command parser cannot convert the read data all at once, temporarily storing the read data in the command cache memory 121 can reduce the possibility of data loss. This makes it possible for the command cache memory 121 and the command parser to transfer read data without relying on the interface bandwidth of the display processing device before outputting it to the display processing device. Since the transfer bandwidth is usually larger than the interface bandwidth of the display processing device, the utilization rate of the transfer bandwidth when transferring read data can be improved.

[0067] In one embodiment, the command parser includes a first parser 122 or a second parser 123 .

[0068] In the display processing device, the placement commands include normal commands and coefficient commands. A first parser 122 converts the normal commands into a predetermined format, and a second parser 123 converts the coefficient commands. Here, the image processing modules placed based on the normal commands usually have the same corresponding interface bandwidth. Therefore, the output bandwidth of each first parser 122 is the same, which is the bandwidth of the display processing device module.

[0069] On the other hand, the coefficient command is used to configure an image processing module with a 3DLUT within the display processing device. The interface bandwidth of such modules in the display processing device may vary. For example, if some display processing device modules have a bandwidth of 36 bits and others have a bandwidth of 48 bits, but the command parser's output bandwidth is all 32 bits, the command parser must issue the same configuration command twice, which may result in insufficient bandwidth utilization during the second transmission.

[0070] The second parser 123 is configured to output the read data to the image processing module according to the size of the output bandwidth of the second parser 123, and the output bandwidth of the second parser 123 in each command interface 120 respectively matches the bandwidth of each image processing module having a 3D lookup table in the display processing device.

[0071] In an embodiment of the present application, for an image processing module having a different 3DLUT, a second parser 123 is provided as a command parser in the corresponding command interface 120, and the output bandwidth of the second parser 123 can be set to match the bandwidth of this image processing module. This eliminates the need to transfer a single placement command multiple times to an image processing module having such a 3DLUT, making effective use of the interface bandwidth and improving the efficiency of allocation of placement commands to the image processing module.

[0072] The command placement unit 100 can convert the bit width of the read data into a bit width that can be received by the interface of the image processing module. When transferring read data and read requests, they can be transferred according to the bandwidth of the transfer bus which is larger than the bit width of the interface of the image processing module, thereby improving the utilization rate of the transfer bandwidth and improving the placement efficiency of the display processing device. At the same time, the command placement unit 100 can request or analyze multiple placement commands in parallel, further improving the placement efficiency of the display processing device.

[0073] For ease of understanding, an example is provided, but this example is not intended to limit the present application. Figure 5 is a schematic diagram of the operation of a read request module according to an embodiment of the present application. Figure 6 is a schematic diagram of receiving and analyzing read data according to an embodiment of the present application.

[0074] In this example, there are 20 command interfaces 120, 20 corresponding read request generators 131, and 20 buffer areas. The read request arbiter 132 uses a circuit that supports weighted round robin arbitration, and the buffer area can store 256 bytes of data. The interface bandwidth between the command interface 120 and the image processing module is 4 bytes, and the transfer bus between the memory and the command placement unit 100 is 32 bytes.

[0075] 5, each read request generator 131 generates a read request corresponding to each image processing module under the control of the display processing device controller. The read request includes a flag and / or an address corresponding to the read data in the storage area of ​​the memory, and is sent to the memory via the read request arbiter 132.

[0076] 6, the selector 111 determines the corresponding buffer area for the read data obtained from the memory based on the identification information, assigns a write address, and stores the read data in the corresponding buffer area. For example, the size of each buffer area is 256 bytes, and the read / write unit is 64 bytes.

[0077] Then, the write address and read address are provided to the base address memory, the write address of the readable read data is determined by the base address memory, and this write address is provided to the corresponding command interface 120. Here, if the read / write unit is 64 bytes, 64 bytes of read data can be written at one time.

[0078] The buffer read arbiter 115 controls each command interface 120 to acquire read data from the buffer area of ​​the buffer 112 according to a preset read priority rule. When the read data stored in the buffer area is read, the address cache memory 113 records the corresponding read address.

[0079] The read data acquired by each command interface 120 is stored in the command cache memory 121, and then converted into a predetermined format by a command parser and output to the image processing module for allocation. Here, the command cache memory 121 reads the buffer 112 at a bandwidth of 64 bytes, and each command interface can output the converted read data at 4 bytes. Here, the command interface with the second parser parses the read data including coefficient commands, and the command interface with the first parser parses the read data including normal commands.

[0080] Based on the same technical idea, the embodiment of the present application further provides a command placement method, which can be applied to the command placement unit 100 according to the above embodiment.

[0081] 7 is a flowchart of a command placement method according to an embodiment of the present application. The command placement method includes the following steps:

[0082] S210: The selector receives the read data.

[0083] S220: Based on the identification information of the read data received by the selector, the read data is stored in the corresponding buffer area.

[0084] S230: Read data is obtained from the buffer area corresponding to the command interface by the command interface.

[0085] S240: The display processing device is configured based on the configuration command in the read data through the command interface.

[0086] In one embodiment, before the read data is received by the selector, a read request is sent to the memory via each read request generator 131. The memory then sends the read data to the buffer in response to the read request.

[0087] In one embodiment, after each read request generator 131 sends a read request to the memory, the output order of each read request is controlled by a read request arbiter 132. Here, the read request arbiter 132 is configured to control the output order of each read request based on a preset output priority rule.

[0088] In one embodiment, after storing the read data in the corresponding buffer area according to the identification information of the read data received by the selector, the address cache memory 113 stores the write address of the read data in the buffer area and the read address of the read data read from the buffer area. Accordingly, S230 includes the step of obtaining the read data from the buffer area corresponding to this command interface according to the command interface and the write address.

[0089] In one embodiment, after the address cache memory 113 stores the write address of the read data in the buffer area and the read address of the read data read from the buffer area, the base address memory provides the write address to the command interface connected to the base address memory.

[0090] In one embodiment, the step of obtaining read data from the buffer area corresponding to the command interface by the command interface further includes the step of obtaining read data from the buffer according to a preset read priority rule in the buffer read arbiter 115.

[0091] In one embodiment, the step of configuring the display processing device based on the configuration commands in the read data by the command interface includes the steps of storing the read data obtained from the buffer by the command cache memory 121, and outputting the read data in a predetermined format to the image processing module by the command parser to configure the image processing module.

[0092] In one embodiment, the step of outputting the read data in a predetermined format to the image processing module by the command parser includes parsing a configuration command including a coefficient command by the second parser 123. The coefficient command is for configuring the image processing module having a 3D lookup table. The second parser 123 is configured to output the read data to the image processing module according to the size of the output bandwidth of the second parser 123. The output bandwidth of the second parser 123 in each command interface respectively matches the bandwidth of each image processing module having a 3D lookup table in the display processing device.

[0093] Based on the same technical idea, an embodiment of the present application further provides a display processing device. Figure 8 is a schematic diagram of a display processing device according to an embodiment of the present application. The display processing device includes a command placement unit 100 and a plurality of image processing modules 210.

[0094] The image processing modules 210 are respectively connected to the command interfaces of the command placement unit 100. Please refer to the command placement unit 100 according to the above embodiment. The image processing modules 210 may refer to image processing modules in a conventional display processing device, and will not be described here.

[0095] Based on a similar technical idea, an embodiment of the present application further provides an electronic device. Figure 9 is a schematic diagram of an electronic device 300 according to an embodiment of the present application. The electronic device 300 includes a display processing device 200, a controller 310, and a memory 320.

[0096] The display processing device 200 is the display processing device 200 according to the above embodiment, and the specific contents thereof can be referred to the above description, and will not be described here.

[0097] The controller and memory may be conventional components. For example, the controller 310 may be a CPU, and the memory 320 may be a DRAM. The controller, memory, and display processing device 200 are communicatively connected via a bus.

[0098] In the embodiment of the present application, the controller 310 is configured to generate read data and store the read data in the memory. The memory 320 is configured to respond to a read request from the display processing device and output the read data to the display processing device 200. The functions of the controller 310 and the memory 320 in the electronic device can be referred to in the prior art and will not be described here.

[0099] In one embodiment, memory 320 is provided with a plurality of storage areas, each corresponding to a different command interface and configured to store read data corresponding to each command interface.

[0100] By providing a plurality of storage areas in the memory 320, it is possible to acquire read data from the corresponding storage area based on the identification information corresponding to the command interface in the read request, and to arrange the display processing device.

[0101] Based on a similar technical idea, an embodiment of the present application further provides an image display system. Fig. 10 is a schematic diagram of an image display system according to an embodiment of the present application. The image display system 400 includes an electronic device 300 and a display device 410. The electronic device 300 is the electronic device according to the above embodiment.

[0102] The display device 410 is communicatively connected to the electronic device 300, and receives and displays image data output from the display processing device of the electronic device 300.

[0103] In some embodiments, the display device may be provided within the electronic device as part of the electronic device's structure.

[0104] The above description is merely a specific embodiment of the present application and does not limit the scope of protection of the present application. Those skilled in the art may modify or replace the technical solutions within the technical scope disclosed in the present application, and these modifications or replacements are also included in the scope of protection of the present application. Therefore, the scope of protection of the present application is subject to the content set forth in the claims.

[0105] It should be noted that, as used herein, the terms "comprise" and "include" and any variations thereof are intended to cover a non-exclusive inclusion. Thus, a process, method, article, or apparatus that includes a set of elements is not necessarily limited to those elements and may include other elements not expressly stated or inherent to the process, method, article, or apparatus. Unless otherwise specified, an element limited by the expression "comprises" does not exclude the situation in which the process, method, article, or apparatus that includes the element also includes other similar elements. [Explanation of symbols]

[0106] 100 Command Placement Units 110 Read Data Module 111 Selector 112 buffers 113 Address Cache Memory 114 Base Address Memory Group 115 Buffer Read Arbiter 120 Command Interface 121 Command cache memory 122 First Parser 123 Second Parser 130 Lead Request Module 131 Lead Request Generator 132 Read Request Arbiter 200 Display processing device 210 Image Processing Module 300 Electronic equipment 310 Controller 320 memory 400 Display System 410 indicates machine

Claims

1. a read data module including a buffer and a selector connected to the buffer, wherein the buffer is provided with a plurality of buffer areas, the selector is connected to a memory that outputs read data, the read data including a placement command and identification information, the placement command including parameters for placing each image processing module of the display processing device, and the identification information indicating a buffer area corresponding to the read data; a plurality of command interfaces each connected to the buffer and configured to correspond to a different one of the buffer areas, each connected to the image processing module; the selector is configured to receive the read data and store the read data in a corresponding buffer area based on the identification information; Each of the command interfaces is configured to obtain the read data from the corresponding buffer area and configure the image processing module based on a configuration command in the read data. A command placement unit characterized by:

2. a read request module having a plurality of read request generators each corresponding to a different one of the command interfaces; Each of the read request generators is configured to send a read request to the memory, and the memory is configured to send the read data to the buffer in response to the read request.

2. The command placement unit of claim 1.

3. the read request module further includes a read request arbiter coupled to each of the read request generators and coupled to the memory; The read request arbiter is configured to control the output order of the read requests based on a preset output priority rule.

3. A command placement unit according to claim 2.

4. the read data module further includes an address cache memory connected to the buffer and each of the command interfaces; the address cache memory is configured to store a write address of the read data in the buffer area and a read address of the read data read from the buffer area; the command interface is configured to read the read data from the buffer area in accordance with the write address; The selector is configured to store the read data in a corresponding buffer area based on the read address and the identification information.

2. The command placement unit of claim 1.

5. the read data module further includes a base address memory group having a plurality of base address memories; the address cache memories are connected to the command interfaces via the base address memories, respectively; After the read data is stored in the buffer area, the base address memory provides the write address to a command interface connected to the base address memory.

5. A command placement unit according to claim 4.

6. the read data module further includes a buffer read arbiter connected to the buffer and each of the command interfaces; The buffer read arbiter instructs each of the command interfaces to obtain the read data from the buffer.

5. A command placement unit according to claim 4.

7. The buffer areas corresponding to the respective command interfaces share the storage space of the buffer, and the storage space corresponding to each of the buffer areas is allocated according to the number of read data corresponding to each of the command interfaces in the buffer.

2. The command placement unit of claim 1.

8. each of the command interfaces includes a command cache memory connected to the buffer and a command parser, the command cache memory is connected to the command parser, and the command parser is connected to the image processing module; the command cache memory stores the read data obtained from the buffer; The command parser outputs the read data to the image processing module in a predetermined format in order to configure the image processing module. Command placement unit according to any one of claims 1 to 7.

9. the command parser includes a first parser or a second parser; the placement commands include coefficient commands for placing an image processing module having a 3D lookup table; the second parser is configured to output the read data to the image processing module according to a size of an output bandwidth of the second parser; The output bandwidth of the second parser in each of the command interfaces is matched to the bandwidth of each of the image processing modules having the 3D lookup table in the display processing device.

9. A command placement unit according to claim 8.

10. A command placement unit according to any one of claims 1 to 9; a plurality of image processing modules each connected to the command placement unit; A display processing device characterized by:

11. A display processing device according to claim 10, a controller, and memories connected to the controller and the display processing device, the controller is configured to generate the read data and store the read data in the memory; The memory outputs the read data to the display processing device in response to a read request from the display processing device. An electronic device characterized by:

12. a read data module including a buffer and a selector connected to the buffer, the buffer being provided with a plurality of buffer areas, the selector being connected to a memory that outputs read data, the read data including a placement command and identification information, the placement command including a parameter for placing a display processing device, the identification information representing a buffer area corresponding to the read data; and a plurality of command interfaces each connected to the buffer, each configured to correspond to a different buffer area, and each connected to the display processing device; receiving the read data by the selector; storing the read data in a corresponding buffer area based on identification information of the read data received by the selector; obtaining the read data from the buffer area corresponding to the command interface through the command interface; and configuring the display processing device based on a configuration command in the read data by the command interface. A command placement method comprising:

Images