Interface disconnection protocol

Abstract

A method, system, and apparatus, including a computer program encoded on a computer storage medium, for managing an interface between a pair of processing cores of a device configured to exchange data. The device is configured to enable or disable one or more of the pair of processing cores. One method includes configuring a connect / disconnect interface, implemented as a logic circuit between the pair of processing cores, to be in a connected state in which the pair of processing cores can exchange data, and configuring the connect / disconnect interface between the pair of processing cores to be in a disconnected state in which one or more of the processing cores cannot receive data.

Description

[Background technology]

[0001] For example, mobile computing devices such as smartphones, personal digital assistants, electronic tablets, and laptops typically use power provided by one or more rechargeable batteries. The rechargeable batteries supply only a limited amount of power to the device before the battery must be recharged, for example, by applying an electric current to the battery. Recharging the battery of a mobile computing device generally requires the mobile computing device to be connected to a power grid, which reduces or eliminates its mobility.

[0002] Mobile computing devices typically include a system-on-chip (SOC) that provides much of the device's required functionality. Because mobile computing devices often operate from a limited power source (e.g., a battery), energy conservation is an important design consideration for the device. Therefore, it is desirable to frequently power down at least some components of the SOC to eliminate leakage current losses, which are a significant contributor to energy consumption in modern integrated circuit technology.

[0003] However, more reliable communication protocols for determining the state of data interfaces between different components required by the SOC often result in irrecoverable data loss as traffic (i.e., data transmission) between active components and standby components of the SOC that cannot receive data, which hinders device performance and user experience. Summary of the Invention

[0004] This specification describes techniques for implementing and managing a connect / disconnect interface between a pair of processing cores of a system-on-chip (SOC) of a computing device. The connect / disconnect interface implements a reliable communication protocol for computing devices that must cope with frequent power-downs of various components of the SOC.

[0005] In general, one innovative aspect of the subject matter described in this specification can be embodied in a device that includes a pair of processing cores configured to exchange data, the device configured to enable or disable one or more of the pair of processing cores, the device including logic circuitry that implements a connect / disconnect interface between the pair of processing cores, the connect / disconnect interface between the pair of processing cores configured to exhibit a connected state in which the pair of processing cores can exchange data, and a disconnected state in which one or more of the processing cores cannot receive data.

[0006] Other embodiments of this aspect include devices, computer systems, and corresponding methods that include operations performed by computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0007] These and other embodiments may each include one or more of the following features, either alone or in combination. Specifically, one embodiment includes all of the following features in combination:

[0008] Pairs of processing cores that share a connect / disconnect interface may be controlled by respective power controllers.

[0009] When in the disconnected state, the interface may assume a disconnected with wakeup mode during which new traffic causes the interface to assume a connected state.

[0010] When in the disconnected state, the interface may assume a disconnected with termination mode during which all traffic is terminated by one of the pair of processing cores.

[0011] Each processing core may be configured to send output signals to other processing devices, including: i) sending a connection request; ii) sending a disconnection request; and iii) sending a disconnection rejection request.

[0012] Each processing core may be configured to receive input signals from other processing devices, including: i) receiving a connection request; ii) receiving a disconnection request; and iii) receiving a disconnection refusal request.

[0013] The output and input signals may be implemented using six separate wires between the processing cores. Particular embodiments of the subject matter described herein can be implemented to achieve one or more of the following advantages: A system-on-chip (SOC) can more reliably exchange data between multiple processing cores of the SOC by utilizing a connect / disconnect interface implemented in addition to a data interface for transmitting data between the processing cores. The connect / disconnect interface allows a processing core to initiate traffic only to other processing cores that can receive traffic, and not to any processing cores in standby mode or other low-power mode that cannot have the clocks or power required to capture ongoing traffic. This approach allows a processing core to avoid irrecoverable data loss that would occur if it were to initiate traffic to another processing core that may already be in standby mode or that may be transitioning to or from standby mode, and further eliminates the need to reboot the system as a result of such data loss. This approach improves the user experience of a device implementing the SOC while reducing the device's power consumption.

[0014] The details of one or more embodiments of the subject matter herein are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a diagram of an exemplary system. [Figure 2] FIG. 2 is an exemplary illustration of a data interface and a connect / disconnect interface. [Figure 3] 1 is a flowchart of an exemplary process for managing an interface between a pair of processing cores. [Figure 4] 1 is an illustration of an exemplary state diagram of different states of an interface between a pair of processing cores. DETAILED DESCRIPTION OF THE INVENTION

[0016] Like reference numbers and designations in the various drawings indicate like elements. 1 is a diagram of an exemplary system 100. The system includes multiple independent processing cores, e.g., processing cores 110a and 110b. The multiple processing cores may generally provide data processing capabilities, but may be implemented in different ways and for different purposes. For example, implementations of such cores may include: 1) a general-purpose programmable processing core including registers, control circuitry, and an arithmetic logic unit (ALU) intended for general-purpose computing; and 2) a special-purpose processing core with dedicated hardware intended primarily for graphics computing, signal processing computing, cryptographic computing, etc.

[0017] The system also includes a power controller, such as power controllers 130a and 130b, corresponding to each of the multiple processing cores. Each power controller may generally include the logic and components necessary to adjust the power state of the multiple processing cores. In some implementations, the power controllers operate independently of each other to turn off or adjust the voltage independently for each processing core, while in other implementations, they may both be managed by a common power manager that controls which components of system 100 receive power and how much power each component receives.

[0018] Multiple independent processing cores and their corresponding power controllers may be integrated onto a single system-on-chip (SOC) 102. SoC 102 may be an integrated circuit that includes the aforementioned components, and possibly other components of the system, on a single silicon substrate or on multiple dies interconnected using, for example, a silicon interposer, stacked dies, or interconnect bridges.

[0019] SOC 102 is an example of a device that can be installed on or integrated into any suitable computing device, sometimes referred to as a host device. Because the techniques described herein are particularly suited to reducing power consumption and improving performance of host devices, SOC 102 can be particularly beneficial when installed in a mobile host device that relies on battery power, such as a smartphone, a smartwatch or another wearable computing device, a tablet computer, or a laptop computer, to name a few.

[0020] It should be noted that the number of components of SOC 102 may vary depending on the implementation. For example, there may be more processing cores than shown in FIG. 1, either contained in the same processor or in separate processors.

[0021] SOC 102 includes logic circuitry implementing interface blocks corresponding to each of multiple processing cores, which serve as a communication interface between multiple processing cores 110a-b and other components within SOC 102, including power controllers 130a-b. A power controller for each of the multiple processing cores, such as power controller 130a, may be connected to a corresponding processing core, such as processing core 110a, and to the corresponding processing core's interface block, such as interface block 120a. As shown in FIG. 1, control interfaces between the power controllers and the processing cores and interface blocks, such as control interfaces 132a-134a and 132b-134b, may communicate control signals, such as voltage control signals, to the processing cores and interface blocks. The control interface protocol exchanged between the power controllers, processing cores, and interface blocks is used to support a handshake protocol between the interface blocks by providing the ability to continuously monitor the status of the interfaces provided by interface blocks 120a-b.

[0022] An interface block of each processing core, e.g., interface block 120a of processing core 110a, may be coupled to another interface block of another processing core, e.g., interface block 120b of processing core 110b, via a programmable interconnect of SOC 102. A programmable interconnect may be coupled to multiple interface blocks to form connections such that one or more links or channels are formed for transmitting data packets or other signals between paired processing cores. The programmable interconnect may, for example, be an asynchronous or combinatorial interconnect.

[0023] 1, each pair of interface blocks 120a-b provides an interface including: 1) a point-to-point data interface 122 for communication between the corresponding pair of processing cores, where data packets are either transmitted and received over a pair of unidirectional links or simultaneously over a bidirectional link; and 2) a connect / disconnect interface 124 that allows the corresponding pair of processing cores to access the state of the interface between them, i.e., connected or disconnected. This connect / disconnect interface 124 allows one processing core to initiate traffic over point-to-point data interface 122 only to another processing core that can receive traffic, by allowing the pair of processing cores to monitor and change whether the interface between them is in a connected or disconnected state without any race conditions. For example, when the interface is in a connected state, a data packet initiated by processing core 110a can enter through interface block 120a, traverse the programmable interconnect, and reach processing core 110b via interface block 120b.

[0024] 2 is an exemplary illustration of an interface 200 including a data interface 122 and a connect / disconnect interface 124 between processing cores 110a-b of FIG. 1. Data interface 122 may include a pair of point-to-point links as shown, where processing core 110a may be connected to a first link 123a for receiving data transmitted by processing core 110b and to a second link 123b for transmitting data to processing core 110b. In other words, links 123a and 123b may be said to form a data interface between processing core 110a and processing core 110b. Accordingly, processing cores 110a-b may each include a transceiver capable of transmitting and receiving data packets on the corresponding link 123a-b.

[0025] 2, the connect / disconnect interface 124 is implemented as a six-wire handshake protocol with two mode bits that operate in concert with the control interface protocol. The six separate wires include a request wire (u0req), an acknowledge wire (u0ack), and a not-acknowledge wire (u0nak) that flow in one direction, and a request wire (u1req), an acknowledge wire (u1ack), and a not-acknowledge wire (u1nak) that flow in the other direction.

[0026] Each processing core sends three signals (idoreq, idoack, idonak) and receives three signals (idireq, idiack, idinak) for a total of six signals for the handshake protocol. This handshake protocol provides each processing core with the ability to 1) send a connection request, 2) send a disconnection request, and 3) send a disconnection rejection request. Similarly, this handshake protocol also provides each processing core with the ability to 1) receive a connection request, 2) receive a disconnection request, and 3) receive a disconnection rejection request.

[0027] With respect to the handshake protocol, the connect / disconnect interface 124 includes two three-signal sub-handshake protocols that coordinate with each other to achieve connection and disconnection of the interface 200. Specifically, the three signals idooreq, idiack, and idinak are used to manage the outgoing links of a processing core, i.e., to connect or disconnect, and the remaining three signals idooreq, idoack, and idonak are used to manage the incoming links of a processing core.

[0028] Each processing core also transmits a 1-bit idomode signal (received by other processing cores as idimode) that indicates which disconnect mode is requested, e.g., a low idomode signal indicates disconnect with termination mode, and a high idomode signal indicates disconnect with wakeup mode.

[0029] These mode signals may not be considered part of the handshake protocol, but are used to determine the operational mode of the handshake. Merging the incoming and outgoing mode signals allows both processing cores to reach the same disconnect state. The mode signal requirements are: 1) if either or both processing cores intend to disconnect with termination, interface 200 must reach the disconnect with termination mode; and 2) if both processing cores intend to disconnect with wakeup, interface 200 must reach the disconnect with wakeup mode. The mode signals must be stable before performing a connect or disconnect handshake. This eliminates a possible race condition between two processing cores perceiving interface 200 in different states.

[0030] As used herein, the term wake up (or enable) is used to mean providing an increased amount of power to a particular processing core or other electronic circuit. SOC 102 may or may not be providing power to the processing component or other circuit being awakened. In other words, the processing core being awakened may or may not have previously been completely powered down. Waking a processing core may cause the processing core to perform a boot process and load instructions and data for the processing core into random access memory. Alternatively or additionally, awakening a processing core may include resuming from a previously suspended state. As used herein, the term terminate (or disable) is used to mean providing a reduced amount of power to a particular processing core or other electronic circuit that may not have been previously active. Terminating a processing core may cause the processing core to perform a shutdown process and erase instructions and data for the processing core from random access memory.

[0031] 3 is a flowchart of an example process 300 for managing an interface between a pair of processing cores. The example process 300 may be performed by a pair of processing cores, which may be any two processing cores of a SOC having respective interface blocks that provide an interface, including a data interface and a connect / disconnect interface, therebetween. The example process 300 is described as being performed by a pair of processing cores having respective interface blocks on a SOC of a device, appropriately programmed in accordance with this specification.

[0032] A pair of processing cores generally provides data processing capabilities and can exchange data between them, and one or more of the pair of processing cores can be enabled or disabled by the device using a power controller that adjusts the power state of the processing cores.

[0033] The connect / disconnect interface between the pair of processing cores assumes a connected state of the interface, allowing the pair of processing cores to exchange data (310). Thus, step 310 is sometimes referred to as a connection handshake protocol. The connected state refers to the state of the interface, allowing the pair of processing cores to initiate and / or receive traffic over the data interface. An interface in the connected state is always ready to transmit traffic.

[0034] To transition to the connected state, one processing core generates a connection request to another processing core by sending a high iDoReq signal (received at the processing core as a high iDiReq signal) over the connect / disconnect interface, to which the other processing core can send back a reply acknowledgment (i.e., a high iDiAck signal) that is received at the processing core as a high iDiAck signal.

[0035] The connected / disconnected interface between the pair of processing cores assumes a disconnected state for the interface in which one or more of the processing cores cannot receive data (320). Thus, step 320 is sometimes referred to as a disconnection handshake protocol. The disconnected state refers to an interface state in which a processing core must not initiate traffic over the data interface during this mode because the other processing core may not be enabled to receive such traffic. An interface in the disconnected state must not send traffic over the data interface.

[0036] To transition to the disconnected state, one processing core generates a disconnection request to another processing core by sending a low iDoReq signal (received at the processing core as a low iDiReq signal) over the connect / disconnect interface, to which the other processing core can send back a reply acknowledgment (i.e., a low iDiAck signal) that is received at the processing core as a low iDiAck signal.

[0037] Unlike a connection request from one processing core to another, which cannot be rejected because an interface connection is a planned event, a disconnection request can be rejected by the other processing core. That is, following receipt of a low idireq signal, the other processing core can send back a negative acknowledgement (i.e., a high idonak signal), which is received by the processing core as a high idinak signal. In such a case, the interface returns to a connected state.

[0038] The disconnected state has two modes: 1) disconnected with wakeup (DSCWK) mode, during which any new traffic causes the interface to enter the connected state, and 2) disconnected with termination (DSCGT) mode, during which any traffic is terminated by one of the pair of processing cores, e.g., by the initiating processing core. That is, the disconnected with wakeup (DSCWK) mode allows connection requests to be generated based on new traffic targeted to the interface, while the disconnected with termination (DSCGT) mode prevents any traffic from causing the interface to leave the disconnected state and enter the connected state. To indicate which disconnected mode is requested, one processing core may further send an idomode signal over the connect / disconnect interface (received as idimode by the other processing core).

[0039] 4 is an illustration of an exemplary state diagram 400 of different states of an interface between a pair of processing cores. State diagram 400 illustrates the states associated with the interface as well as the possible state transitions between the states.

[0040] The interface may be in disconnected with termination (DSCGT) mode 410. A mode transition from DSCGT mode 410 to disconnected with wakeup (DSCWK) mode 420 may occur when both processing cores have power, clocks, and are not reset, indicating that each processing core is ready to participate in a connection handshake.

[0041] During DSCWK mode 420, if either processing core detects that there is new traffic intended for the data interface between the pair of processing cores, that processing core then utilizes the connection handshake protocol described above to generate a connection request to the other processing core, which, if accepted by the other processing core, transitions the interface to connected state 430. The pair of processing cores may then begin exchanging data.

[0042] Thereafter, when the power controller of any processing core detects that the interface has been inactive for a predetermined period of time, e.g., has zero traffic, the power controller can generate an opportunistic disconnection request utilizing the disconnection handshake protocol described above. If the other processing core accepts the disconnection request, the interface transitions from the connected state 430 to the DSCWK state 420.

[0043] Alternatively, if the other processing core sends a denial (negative response) of the disconnection request, the interface remains in the connected state 430.

[0044] Alternatively, when either power controller detects that the interface has been inactive for a predetermined amount of time, or when the power controller receives a command for a scheduled low power state, the power controller may generate a scheduled disconnection request utilizing the disconnection handshake protocol as described above. If the other processing core accepts the disconnection request, the interface transitions from the connected state 430 to the DSCGT state 410.

[0045] Embodiments of the subject matter and functional operations described herein can be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, or computer hardware, including the structures disclosed herein and their structural equivalents, or one or more combinations thereof. Embodiments of the subject matter described herein can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory storage medium for execution by or to control the operation of a data processing apparatus. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or one or more combinations thereof. Alternatively, or in addition, the program instructions can be encoded into an artificially generated transmitted signal, such as a machine-generated electrical, optical, or electromagnetic signal generated to encode information for transmission to a suitable receiver apparatus for execution by a data processing apparatus.

[0046] The term "data processing apparatus" refers to data processing hardware and encompasses all kinds of apparatus, devices, and machines for processing data, including, by way of example, a programmable processor, a computer, or multiple processors or multiple computers. An apparatus may also be or further include special-purpose logic circuitry, such as an FPGA (field-programmable gate array) or an ASIC (application-specific integrated circuit). In addition to hardware, an apparatus may optionally include code that creates an execution environment for a computer program, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or one or more combinations thereof.

[0047] A computer program, which may also be referred to or described as a program, software, software application, app, module, software module, script, or code, can be written in any form of programming language, including compiled or interpreted, declarative or procedural, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data, e.g., one or more scripts stored in a markup language document, in a single file dedicated to the program, or in multiple cooperating files, e.g., files that store one or more modules, subprograms, or portions of code. A computer program can be deployed to run on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a data communications network.

[0048] To say that one or more computer systems are configured to perform particular operations or actions means that the systems have installed thereon software, firmware, hardware, or a combination thereof that causes the operating system to perform the operations or actions. To say that one or more computer programs are configured to perform particular operations or actions means that one or more programs contain instructions that, when executed by a data processing device, cause the device to perform the operations or actions.

[0049] As used herein, "engine" or "software engine" refers to a hardware- or software-implemented input / output system that provides an output distinct from its input. An engine may be implemented in dedicated digital circuitry or as computer-readable instructions executed by a computing device. Each engine may be implemented in any suitable type of computing device, such as a server, mobile phone, tablet computer, notebook computer, music player, e-book reader, laptop or desktop computer, PDA, smartphone, or other fixed or portable device, that includes one or more processing modules and computer-readable media. In addition, two or more of the engines may be implemented in the same computing device or in different computing devices.

[0050] The processes and logic flows described herein may be performed by one or more programmable computers executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows may also be performed by special purpose logic circuitry, such as an FPGA or an ASIC, or a combination of special purpose logic circuitry and one or more programmed computers.

[0051] A computer suitable for executing a computer program can be based on a general-purpose or special-purpose microprocessor, or both, or any other type of central processing unit. Typically, the central processing unit receives instructions and data from a read-only memory, a random-access memory, or both. The basic elements of a computer are a central processing unit for implementing and executing instructions and one or more memory devices for storing instructions and data. The central processing unit and memory may be supplemented by, or incorporated in, special-purpose logic circuitry. Typically, a computer also includes, or is operatively coupled to, one or more mass storage devices for storing data, such as, for example, magnetic, magneto-optical, or optical disks. However, such devices are not required for a computer. Furthermore, a computer can be embedded in other devices, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device, such as a universal serial bus (USB) flash drive, to name a few.

[0052] Computer-readable media suitable for storing computer program instructions and data include, by way of example, all types of non-volatile memory, media, and memory devices, such as semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices, magnetic disks, e.g., internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM disks.

[0053] To interact with a user, embodiments of the subject matter described herein can be implemented in a host device having a display device, such as a CRT (cathode ray tube) or LCD (liquid crystal display) monitor, for displaying information to the user, and a keyboard and pointing device, such as a mouse, trackball, or display or other surface, by which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user. For example, feedback provided to the user can be any form of sensory feedback, such as visual feedback, auditory feedback, or tactile feedback, and input from the user can be received in any form, such as acoustic input, voice input, or tactile input. Furthermore, a computer may interact with a user by sending documents to and receiving documents from a device used by the user, for example, by sending a web page to a web browser on the user's device in response to a request received from the web browser. A computer may also interact with a user by sending text messages or other types of messages to a personal device, such as a smartphone running a messaging application, and then receiving a reply message from the user.

[0054] While the specification contains many specific implementation details, these should not be construed as limiting the scope of any invention or the scope of patentable subject matter, but rather as descriptions of features that may be unique to particular embodiments of a particular invention. Certain features described herein in the context of separate embodiments may also be implemented in combination in a single embodiment. Conversely, various features of the invention that are described in the context of a single embodiment may also be implemented in multiple embodiments separately or in any suitable subcombination. Furthermore, even if features may be described above as functioning in a particular combination and originally claimed as such, one or more features from a claimed combination may, in some cases, be deleted from the combination, and the claimed combination may be directed to subcombinations or variations of the subcombination.

[0055] Similarly, while acts are shown in a particular order in the figures, this should not be understood as requiring that such acts be performed in the particular order or sequential order shown, or that all of the acts shown be performed, to achieve desirable results. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated into a single software product or packaged into multiple software products.

[0056] Specific embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve desirable results. As an example, the processes depicted in the accompanying figures do not necessarily require the particular order shown or sequential order to achieve desirable results. In certain cases, multitasking and parallel processing may be advantageous.

Claims

1. a device including a pair of processing cores configured to exchange data, the device configured to enable or disable one or more of the pair of processing cores, the device including logic circuitry that implements a connect / disconnect interface between the pair of processing cores; the connect / disconnect interface between the pair of processing cores is configured to be in a connected state in which the pair of processing cores can exchange data, and in a disconnected state in which one or more of the processing cores cannot receive data. device.

2. The method of claim 1 , wherein the pair of processing cores that share the connect / disconnect interface are controlled by respective power controllers.

3. The device of any one of claims 1 to 2, wherein when in the disconnected state, the interface is capable of entering a disconnected with wake-up mode in which new traffic comes into the connected state on the interface.

4. The device of claim 3 , wherein when in the disconnected state, the device is capable of entering a disconnected with termination mode in which all traffic is terminated by one of the pair of processing cores.

5. 5. The device of claim 1, wherein each processing core is configured to send output signals to other processing devices, including: i) sending a connection request; ii) sending a disconnection request; and iii) sending a disconnection rejection request.

6. 6. The device of claim 5, wherein each processing core is configured to receive input signals from other processing devices, including: i) receiving a connection request; ii) receiving a disconnection request; and iii) receiving a disconnection rejection request.

7. The device of any one of claims 5 to 6, wherein the output signals and the input signals are implemented using six separate wires between the processing cores.

8. 1. A method performed by a device including a pair of processing cores configured to exchange data, the device configured to enable or disable one or more of the pair of processing cores, the device including logic circuitry implementing a connect / disconnect interface between the pair of processing cores, the method comprising: configuring the connect / disconnect interface between the pair of processing cores such that the pair of processing cores are connected to exchange data; configuring the connect / disconnect interface between the pair of processing cores to be in a disconnected state in which one or more of the processing cores is unable to receive data; A method comprising:

9. The method of claim 8 , wherein the pair of processing cores that share the connect / disconnect interface are peer processing cores that are both controlled by a power manager.

10. The method of any one of claims 8 to 9, wherein when in the disconnected state, the interface is capable of going into a disconnected with wake-up mode in which new traffic comes into the connected state on the interface.

11. 11. The method of claim 10, wherein when in the disconnected state, the interface is capable of entering a disconnected with termination mode in which all traffic is terminated by one of the pair of processing cores.

12. 12. The method of claim 8, wherein each processing core is configured to send output signals to other processing devices, including: i) sending a connection request; ii) sending a disconnection request; and iii) sending a disconnection rejection request.

13. 13. The method of claim 12, wherein each processing core is configured to receive input signals from other processing devices, including: i) receiving a connection request; ii) receiving a disconnection request; and iii) receiving a disconnection refusal request.

14. The method of any one of claims 12 to 13, wherein the output signals and the input signals are implemented using six separate wires between the processing cores.

Images