Computer-implemented method for defect recognition in wafer imaging data sets, corresponding computer-readable medium, computer program product, and system using such method

Abstract

The present invention relates to a computer-implemented method for defect recognition in an imaging dataset of a wafer in a charged particle beam system (78) having an embedded system (50), the method including: (i) acquiring the imaging dataset of the wafer; (ii) acquiring model data (44, 44', 44'') for a model architecture (42) of a machine learning model (40, 40', 40'') for defect recognition in the imaging dataset of the wafer, where the model architecture (42) is implemented in the embedded system (50); (iii) transferring the model data to a programmable memory (48, 48', 48'') of the embedded system; and (iv) running the embedded system-implemented model architecture (46) using the transferred model data to apply the machine learning model to the imaging dataset of the wafer to recognize defects.

Description

[Technical Field]

[0001] Related Applications This application claims the benefit of German Patent Application No. 102022124580.2, filed September 23, 2022, which is incorporated herein by reference in its entirety.

[0002] The present invention relates to systems and methods for quality control and quality assurance of semiconductor structures, and more particularly to a computer-implemented method, computer-readable medium, and corresponding system for defect recognition in wafer imaging datasets with increased throughput. The method, computer-readable medium, and system are based on the implementation of a generic machine learning model in an embedded system. The method may be used for quantitative metrology, defect recognition, defect detection, defect classification, defect localization, or defect review of integrated circuits within semiconductor wafers, or for process monitoring, process improvement, quality control, or quality assurance during the manufacture of semiconductor wafers. [Background technology]

[0003] Semiconductor manufacturing involves precise manipulation, e.g., etching, of materials such as silicon or oxide on a very fine scale, in the nm range. Therefore, to ensure high quality standards of the manufactured wafers, a quality control process, which includes quality assurance and quality control, is important. Quality assurance refers to a set of activities to ensure high-quality products by preventing defects that may occur during the development process. Quality control refers to a system that inspects the final quality of the product. Quality control is a part of the quality assurance process.

[0004] Wafers, made from thin slices of silicon, serve as the substrate for microelectronic devices, which contain semiconductor structures built within and on the wafer. The semiconductor structures are built layer by layer using repeated processing steps, including repeated chemical, mechanical, thermal, and optical processes. The dimensions, shape, and placement of semiconductor structures and patterns are subject to multiple influences. For example, etching and deposition are currently key processes during the fabrication of 3D memory devices. Other involved process steps, such as lithographic exposure or implantation, can also affect the characteristics of integrated circuit elements. Therefore, fabricated semiconductor structures are adversely affected by rare and diverse imperfections. Quantitative metrology, defect detection, or defect review devices search for these imperfections. These devices are not only needed during wafer fabrication. Because this process is complex and highly nonlinear, optimizing the manufacturing process parameters is challenging. As a solution, an iterative method called process window qualification (PWQ) can be applied. In each iteration, different dies on the wafer are exposed to different manufacturing conditions, and a test wafer is fabricated based on the current best process parameters. By detecting and analyzing defects in various dies based on the quality assurance process, the best manufacturing process parameters can be selected. In this way, the manufacturing process parameters can be fine-tuned toward optimality. Then, high-precision quality control processes and devices are required for metrology semiconductor structures within the wafer.

[0005] The identified defects are then used in root cause analysis. The identified defects can serve as feedback during quality assurance to improve process parameters of the manufacturing process, such as exposure time, focus variation, etc., or during quality control to ensure the quality of the manufactured wafers. For example, bridge defects may indicate insufficient etching, open defects may indicate over-etching, consistently occurring defects may indicate a faulty mask, missing structures may suggest non-ideal material deposition, etc.

[0006] The semiconductor structures to be fabricated are based on prior knowledge. They are fabricated from a series of layers parallel to the substrate. For example, in logic-type samples, metal lines run parallel within the metal layers or HAR (high aspect ratio) structures, while metal vias run perpendicular to the metal layers. The angles between metal lines in different layers are either 0° or 90°. On the other hand, in the case of VNAND-type structures, their cross sections are known to be circular on average. Furthermore, semiconductor wafers have a diameter of 300 mm and are composed of multiple parts, so-called dies, each of which contains at least one integrated circuit pattern, such as a memory chip or a processor chip. During fabrication, semiconductor wafers undergo approximately 1,000 process steps, resulting in the formation of approximately 100 or more parallel layers within the semiconductor wafer, including transistor layers, intermediate layers of lines, and interconnect layers, and in memory devices, multiple 3D arrays of memory cells.

[0007] The aspect ratio and number of layers in integrated circuits are constantly increasing, with structures growing in the third (vertical) dimension. The current height of memory stacks exceeds 12 microns. In contrast, feature sizes are shrinking. Minimum feature sizes, or critical dimensions, are less than 10 nm, e.g., 7 nm or 5 nm, and are approaching feature sizes of less than 3 nm in the near future. While the complexity and dimensions of semiconductor structures are growing in the third dimension, the lateral dimensions of integrated semiconductor structures are shrinking. Therefore, it becomes difficult to measure the shape, size, and orientation of features and patterns in 3D, as well as their overlay, with high accuracy. The lateral measurement resolution of charged particle systems is typically limited by the sampling raster of individual image points, or the dwell time per pixel on the sample, and the diameter of the charged particle beam. The sampling raster resolution can be set within the imaging system and adapted to the diameter of the charged particle beam on the sample. While typical raster resolution is 2 nm or less, the raster resolution limit can be reduced without physical limitations. The diameter of a charged particle beam has a limited dimension that depends on the operating conditions of the charged particle beam and the lens. The beam resolution is limited to approximately half the diameter of the beam. The lateral resolution can be less than 2 nm, for example, even less than 1 nm.

[0008] One important task in semiconductor inspection is to determine a set of specific parameters of semiconductor objects, such as high aspect ratio (HAR) structures, within an inspection volume. Such parameters may be, for example, dimensions, area, shape, or other measurement parameters. Typically, prior art measurement tasks involve multiple computational steps, such as object detection, feature extraction, and any type of metrology operation, e.g., calculating distance, radius, or area from extracted features. Each of these many steps requires significant computational effort.

[0009] Semiconductors typically contain many repetitive three-dimensional structures. During manufacturing processes or process development, selected physical or geometric parameters of a portion of a representative plurality of three-dimensional structures need to be measured with high accuracy and high throughput. To monitor manufacturing, a test volume containing a representative plurality of three-dimensional structures is defined. This test volume is then analyzed, for example, by a slice-and-image technique, leading to a high-resolution 3D volumetric image of the test volume obtained by slicing and imaging multiple cross-sectional surfaces within the test volume.

[0010] The number of repetitive three-dimensional structures within the examination volume can exceed hundreds or thousands of individual structures, resulting in a huge number of cross-sectional images being generated, e.g., at least 100 three-dimensional structures are interrogated by 100 cross-sectional image slices, and thus the number of measurements performed can easily reach 10,000 or more.

[0011] In addition, current techniques such as multibeam scanning electron microscopy (multibeam SEM) can be used to image large areas of a wafer surface in a short time with high resolution. For this purpose, multibeam SEM uses multiple single beams in parallel, each covering a different part of the surface, with pixel sizes down to 2 nm. The resulting data sets are huge and cannot be analyzed manually.

[0012] Machine learning methods can be used to analyze large amounts of data where a large number of measurements need to be made. Machine learning methods are well suited to analyzing large amounts of data with minimal user interaction.

[0013] Machine learning is a branch of artificial intelligence. Machine learning methods generally build parametric machine learning models based on training data consisting of a large number of samples. After training, the method is able to generalize the knowledge gained from the training data to new samples that it has not encountered before, thereby making predictions for new data. There are many machine learning methods, for example, linear regression, k-means, neural networks, or deep learning techniques.

[0014] Deep learning is a type of machine learning that uses artificial neural networks that contain many hidden layers between input and output layers, modeled after the human brain. This vast internal structure allows these networks to progressively extract high-level features from raw input data. Each level learns to transform the input data into slightly more abstract and complex representations, thus deriving low- and high-level knowledge from the training data. Hidden layers can have different sizes and tasks, such as convolutional, pooling, or fully connected layers.

[0015] During quality control and quality assurance, the speed of the algorithms is a key factor to achieve high throughput of wafers. To obtain fast algorithms, embedded systems can be used to implement machine learning models for quality assurance and quality control of the acquired imaging datasets of wafers.

[0016] For example, US2021 / 0097673A1 and US2021 / 0158498A1 both disclose machine learning models for defect recognition in wafer imaging datasets that can be implemented using embedded systems such as FPGAs.

[0017] For software running on conventional processors, numerous pre-programmed libraries are available to minimize programming effort and time. This is not the case for embedded systems. Additionally, each software update requires reprogramming of the embedded system. Therefore, programming an embedded system requires significant programming effort and time. Summary of the Invention [Problem to be solved by the invention]

[0018] It is therefore an object of the present invention to provide a method for obtaining a machine learning model on an embedded system that is reusable and versatile for different use cases or different imaging datasets. Another object of the present invention is to reduce the effort, time, and resources required to program a machine learning model on an embedded system for defect recognition in wafer imaging datasets. Another object of the present invention is to reduce the computation time of a machine learning model. Another object of the present invention is to adapt a machine learning model on an embedded system to a wafer quality control or quality assurance process. A further object of the present invention is to improve throughput during a wafer quality control or quality assurance process. Another object of the present invention is to minimize the execution time of a wafer quality control or quality assurance process. Generally, it is an object of the present invention to provide a wafer inspection method for measurement of semiconductor structures within an inspection volume with high throughput and high accuracy. It is an object of the present invention to provide a generalized wafer inspection method for measurement of semiconductor structures within an inspection volume that can be quickly adapted to changes in measurement tasks, measurement systems, or semiconductor objects of interest. It is a further object of the present invention to provide a fast, robust, and reliable method for measurement of a set of parameters representative of semiconductor structures within an inspection volume with high accuracy and reduced measurement artifacts. Finally, it is an object of the present invention to enable new business models for selling systems that include machine learning algorithms.

[0019] These objects are achieved by the invention as specified in the independent claims. Advantageous embodiments and further developments of the invention are specified in the dependent claims. [Means for solving the problem]

[0020] Embodiments of the present invention relate to a computer-implemented method, computer-readable medium, and system for implementing machine learning models on an embedded system for defect recognition in wafer imaging datasets.

[0021] A first embodiment includes a computer-implemented method for defect recognition in an imaging dataset of a wafer in a charged particle beam system with an embedded system, the method including: (i) acquiring an imaging dataset of the wafer; (ii) acquiring model data of a model architecture of a machine learning model for defect recognition in the imaging dataset of the wafer, where the model architecture is implemented in the embedded system; (iii) transferring the model data to a programmable memory of the embedded system; and (iv) applying the machine learning model to the imaging dataset of the wafer to recognize defects, including executing the embedded system implemented model architecture using the transferred model data. The recognized defects can be used, for example, in a quality assurance system and / or a quality control system, particularly for wafers, but also for other manufactured objects.

[0022] A machine learning model is the result of a machine learning method run on training data. The model represents what the machine learning method has learned. The model includes the model architecture, model data, and prediction methods.

[0023] The model architecture includes so-called hyperparameters that define the design or structure of the machine learning model, which are typically not learned from training data. Hyperparameters can be, for example, user-defined or obtained using AutoML methods. Hyperparameters of neural networks include, for example, the number of layers, layer size, filter type, optimizer, upsampling scheme, etc. Hyperparameters of decision trees include, for example, the number of tree levels and the number of decision nodes at each tree level. Hyperparameters of support vector machines include, for example, the number and format of hyperplanes. Hyperparameters of clustering methods include, for example, the number of clusters.

[0024] Model data includes data structures specific to the rules, values, or any other method needed to make predictions for new data samples. Model data is learned from training data. Model data for neural networks includes, for example, weights learned from training data. Model data for decision trees includes, for example, specific decisions to be made at each node learned from training data. Model data for support vector machines includes, for example, matrices and vectors defining specific hyperplanes learned from training data. Model data for clustering methods includes, for example, specific cluster locations learned from training data.

[0025] A prediction method is a procedure that describes how to make predictions on new data using model data. The application of a machine learning method or model to an imaging dataset refers to the application of a prediction method to an imaging dataset that is based on a trained model that includes a model architecture and model data.

[0026] By separating the model architecture from the trained model data, the model architecture can be implemented on an embedded system to achieve short execution times and high throughput. Meanwhile, the trained model data in the programmable memory of the embedded system can be dynamically updated. In this way, the machine learning model on the embedded system can be adapted to different use cases or retrained for, for example, different imaging datasets. Different imaging datasets may occur, for example, when image acquisition conditions change or the imaging dataset is modified. Furthermore, the implementation effort for the user is reduced.

[0027] A second embodiment of the present invention relates to a computer-implemented method for defect recognition in an imaging dataset of a wafer in a charged particle beam system having at least one embedded system, the method including: (i) acquiring an imaging dataset of the wafer; (ii) defining an embedded system-implemented model architecture of a machine learning model for defect recognition in the imaging dataset of the wafer by specifying a flow of data through some logic block circuits of a plurality of logic block circuits in one of the at least one embedded system, wherein the plurality of logic block circuits include one or more modules of the at least one model architecture of the at least one machine learning model for defect recognition; (iii) acquiring model data for the embedded system-implemented model architecture; (iv) transferring the model data to a programmable memory of the embedded system; and (v) applying the machine learning model to the imaging dataset of the wafer to recognize defects, the method including executing the embedded system-implemented model architecture using the transferred model data.

[0028] The recognized defects can be used, for example, in quality assurance and / or quality control systems, particularly for wafers, but also for other manufactured objects. The modularity of the model architecture makes the implementation of machine learning models on embedded systems even more flexible and versatile, since different modules can be combined to form new model architectures and previously implemented modules can be reused for different model architectures. In this way, not only the model data but also the model architecture can be dynamically changed or adapted to different use cases without requiring significant implementation efforts.

[0029] Throughout this document, the term "some" elements may refer to a single element, multiple elements, or all elements.

[0030] In an example of the first or second embodiment, the machine learning model for defect recognition in the wafer imaging dataset is from a group including a defect detection model, a defect classification model, a defect localization model, a defect segmentation model, an anomaly detection model, an anomaly classification model, an anomaly localization model, and an anomaly segmentation model.

[0031] An anomaly refers to a deviation of a semiconductor structure from a priori defined norm. Generally, a defect is also an anomaly, but not all anomalies are defects. For example, an anomaly may arise due to noise or rare structures in an imaging data set.

[0032] Charged particle beam systems include, but are not limited to, scanning electron microscopes (SEMs), focused ion beam microscopes such as helium ion microscopes, etc. A further example of a charged particle beam system is a corrected scanning electron microscope, which includes correction means for correction of chromatic and spherical aberrations.

[0033] In various embodiments of the present invention, the embedded system can be a field programmable gate array (FPGA), a digital signal processor (DSP), an arithmetic logic unit (ALU), an application-specific integrated circuit (ASIC), or the like.

[0034] In various embodiments of the present invention, the machine learning model for defect recognition in the acquired imaging dataset of the wafer can be from a group including a defect detection model, a defect classification model, a defect localization model, a defect segmentation model, an anomaly detection model, an anomaly classification model, an anomaly localization model, an anomaly segmentation model.

[0035] In an example of the second embodiment, the at least one model architecture of the at least one machine learning model for defect recognition includes a neural network model architecture.

[0036] According to an example aspect of the second embodiment, the one or more modules are head modules, the head module being a module including an output layer of a neural network.

[0037] For example, one or more head modules may include a fully connected output layer of a neural network and / or a convolutional output layer of a neural network.

[0038] Additionally, one or more of the modules can be tail modules, which are modules that include some hidden layers of a neural network.

[0039] In one embodiment, at least one tail module, and in particular each tail module, includes all hidden layers of the neural network.

[0040] In another embodiment, at least one tail module, and in particular each tail module, includes several hidden layers that form semantic entities. The term "semantic entities" refers to several hidden layers that form functional units in the sense that they complement each other and together perform a specific function within the neural network.

[0041] The subdivision of the model architecture into a head module and a tail module significantly reduces the programming and application effort for users. The head module includes the output layer of the neural network and is therefore a task-specific module. By replacing the head module with another module, the task of the neural network can be changed. For example, a defect detection model architecture including a convolutional output layer can become a defect classification model architecture including a fully connected output layer.

[0042] The tail modules include several hidden layers of the neural network. By swapping the tail modules, the size of the feature maps of the hidden layers can be easily adapted between small and large problems that require fewer or more features to produce satisfactory results. Thus, according to a further aspect of an example of the second embodiment, at least two of the tail modules include the same number of hidden layers, and the sizes of the feature maps of the corresponding hidden layers differ by the same factor.

[0043] According to a further aspect of an example of the second embodiment, each module of the one or more modules is either a head module including an output layer of the neural network or a tail module including several hidden layers of the neural network.

[0044] The head and tail modules can be generated from a neural network by dividing the neural network into an output layer and one or more sets of hidden layers. One or more modules can be generated from at least one model architecture of a neural network by dividing each model architecture into a head module that includes the output layer of the neural network and at least one tail module that includes several hidden layers of the neural network. In particular, each model architecture of a neural network can be divided into a task-specific head module and a single tail module, allowing for particularly low effort to specify the flow of data through this number of modules.

[0045] In an example of the second embodiment, the method may further include, before specifying the flow of data through some of the logic block circuits, determining whether the model architecture of the machine learning model can be realized by the plurality of logic block circuits in one of the at least one embedded system, and in response to determining that the model architecture cannot be realized, generating one or more modules of the model architecture of the machine learning model and implementing the one or more modules in one of the at least one embedded system. In this way, the number of modules and embedded system-implemented model architectures increases with the number of use cases, making the system increasingly flexible and versatile.

[0046] In an example of the first or second embodiment, the model data of the embedded system implementation model architecture is obtained by training a machine learning model that includes the model architecture. Additionally or alternatively, the model data of the embedded system implementation model architecture can be loaded from a database. Additionally or alternatively, the model data of the embedded system implementation model architecture can be provided by an external service, creating a new business model that offers a one-time sale of a system having the embedded system implementation model architecture and periodic updates of the model data as a service, for example, to improve defect recognition results or to adapt the system to different use cases.

[0047] In examples of the first and second embodiments, the model data is transferred to the programmable memory of the embedded system by copying. Alternatively, the model data can be transferred to the programmable memory of the embedded system by replacing the hardware block containing the programmable memory of the embedded system with a new hardware block containing the model data to be transferred.

[0048] In any of the examples or aspects of the first and second embodiments, the recognized defects may be monitored, for example, in real time or buffered, for quality assurance or quality control purposes. To this end, the recognized defects may be directed to a display device or dashboard. Additionally or alternatively, the recognized defects may be stored in long-term memory. Additionally or alternatively, the recognized defects may be cached in memory. The recognized defects may also be analyzed to update the embedded system implementation model architecture in step (ii).

[0049] A third embodiment of the present invention includes a computer-implemented method according to any one of aspects or examples of the first or second embodiment of the present invention, the computer-implemented method including: before acquiring an imaging dataset of the wafer in step (i), repeating the steps of selecting at least one image acquisition parameter according to an imaging sampling strategy and acquiring an imaging dataset of the wafer based on the at least one image acquisition parameter, generating training data from the acquired imaging dataset of the wafer, selecting a model architecture and training an associated machine learning model based on the generated training data, and determining quality of the model architecture and the at least one image acquisition parameter by calculating an associated objective function value of an objective function that evaluates the quality of the trained machine learning model; after these iterations, selecting one of the model architectures and the corresponding at least one image acquisition parameter based on the objective function value, wherein the imaging dataset of the wafer in step (i) is acquired based on the selected at least one image acquisition parameter; and the embedded system-implemented model architecture in step (ii) includes the model architecture of the selected machine learning model. In this way, the image acquisition process is optimized with respect to a criterion defined by an objective function, for example the throughput of the system, the execution time of the defect recognition method, or the power consumption of the system.

[0050] A fourth embodiment of the present invention relates to a computer-implemented method for defect recognition in an imaging dataset of a wafer, the method including: iterating the steps of selecting at least one image acquisition parameter according to an imaging sampling strategy and acquiring an imaging dataset of the wafer based on the at least one image acquisition parameter; generating training data from the acquired imaging dataset of the wafer; selecting a model architecture and training an associated machine learning model based on the generated training data; and evaluating quality of the trained machine learning model by calculating an associated objective function value of an objective function, after the final iteration, selecting one of the trained machine learning models based on the objective function value; and applying the selected trained machine learning model to the imaging dataset of the wafer acquired based on the corresponding at least one image acquisition parameter to recognize defects.

[0051] According to the third or fourth embodiment, the at least one image acquisition parameter is for example from the group comprising imaging time, image resolution, pixel size, landing energy and dwell time of the electron wave.

[0052] In an example of the third or fourth embodiment, selecting the model architecture includes selecting at least one hyperparameter that defines the model architecture of the machine learning model according to an architecture sampling strategy, for example using automated machine learning (AutoML) techniques. This procedure is advantageous because the image acquisition process is optimized together with the hyperparameters of the machine learning model with respect to the objective function.

[0053] In an example of the third or fourth embodiment, the objective function includes a measure of the complexity of the model architecture. In a further example, the objective function includes a measure of execution time, and / or a measure of throughput and / or data rate, and / or a measure of power consumption. In a further example, the objective function includes a measure of the quality of defect recognition. In a further example, the objective function includes a measure of the amount of bits of input data for the machine learning model. Selecting one or more of these measures in the objective function allows for a reduction in architectural complexity and, therefore, a reduction in execution time or an increase in throughput of the system.

[0054] Any example of the aspect or any example of the embodiment may further include determining one or more measurements of defects recognized in the imaging dataset of the wafer, such as size, area, dimensions, shape parameters, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of defects, the presence of any defects (i.e., whether defects are detected), etc. Based on one or more of these measurements, the example may further include assessing the quality of the wafer based on the one or more measurements and at least one quality assessment rule. Based on the one or more measurements, the example may include controlling at least one wafer manufacturing process parameter based on the one or more measurements of defects recognized in the imaging dataset of the wafer. Wafer manufacturing process parameters include, but are not limited to, exposure time, etching, deposition, implantation, thermal treatment, and parameters of other processes involved during manufacturing. Other defects may result from imperfections or contamination from various sources, such as lithography mask modifications or particle contamination.

[0055] The present invention also includes a computer readable medium having stored thereon a computer program executable by a computing device, the computer program including code for carrying out a method according to any of the aspects or examples of the embodiments.

[0056] The present invention also relates to a computer program product comprising instructions which, when executed by a computer, cause the computer to carry out a method according to any of the aspects or examples of the embodiments.

[0057] The present invention also relates to a system for managing the quality of wafers manufactured in a semiconductor fabrication factory, the system comprising: an imaging device adapted to provide an imaging dataset of the wafer; one or more processing devices; optionally, at least one embedded system; and one or more machine-readable hardware storage devices containing instructions executable by the one or more processing devices to perform operations comprising a method for assessing the quality of the wafer.

[0058] The present invention also includes a system for controlling the production of wafers in a semiconductor fabrication factory, the system comprising: means for producing wafers controlled by at least one manufacturing process parameter; an imaging device adapted to provide an imaging dataset of the wafers; one or more processing devices; optionally, an embedded system or modules thereof implementing a model architecture of a machine learning model for defect recognition in said imaging dataset of the wafers, the embedded system comprising a programmable memory for transferring model data to the embedded system; and one or more machine-readable hardware storage devices containing instructions executable by the one or more processing devices to perform operations comprising the method for controlling at least one wafer manufacturing process parameter.

[0059] Any of the above systems may include a database, a display device, and / or a user interface.

[0060] Although examples and embodiments of the present invention are described with reference to semiconductor wafers, it will be understood that the present invention is not limited to semiconductor wafers, but may also be applied, for example, to reticles or masks for semiconductor manufacturing or other manufactured objects.

[0061] The present invention described by examples and embodiments is not limited to those embodiments and examples, and can be implemented by those skilled in the art through various combinations or modifications thereof. [Brief explanation of the drawings]

[0062] [Figure 1] FIG. 1 shows a schematic cell structure of an imaging data set of three defective wafers. [Figure 2] FIG. 2 illustrates a flowchart of steps in an exemplary computer-implemented method for defect recognition, according to a first embodiment of the present invention. [Figure 3] FIG. 1 illustrates the use of model architecture and model data separation for flexible implementation of machine learning models into embedded systems. [Figure 4] FIG. 6 illustrates a flowchart of steps in an exemplary computer-implemented method for defect recognition, according to a second embodiment of the present invention. [Figure 5] FIG. 1 illustrates a particularly flexible and versatile method for implementing machine learning models in a system comprising at least one embedded system. [Figure 6] 1 illustrates the use of embedded systems in the form of FPGAs in various use cases based on the separation of hardware-related and software-related parts. [Figure 7] FIG. 1 illustrates a schematic embedded system implementation of a first module and a second module of a neural network model architecture. [Figure 8] FIG. 1 illustrates the subdivision of a model architecture in the form of a neural network into head and tail modules. [Figure 9] 1A-1C illustrate different head and tail modules of various model architectures. [Figure 10] FIG. 1 illustrates a process for implementing a new use case in a system by a computer-implemented method according to various embodiments of the present invention. [Figure 11] FIG. 10 illustrates a flowchart of steps in an exemplary computer-implemented method for defect recognition, according to a third embodiment of the present invention. [Figure 12] FIG. 10 illustrates a flowchart of steps in an exemplary computer-implemented method for defect recognition, according to a third embodiment of the present invention. [Figure 13] FIG. 10 illustrates a flowchart of steps in an exemplary computer-implemented method for defect recognition, according to a third embodiment of the present invention. [Figure 14] FIG. 10 shows a flowchart of steps in an exemplary computer-implemented method for defect recognition, according to a fourth embodiment of the present invention. [Figure 15] FIG. 1 illustrates a system that may be used to control the quality of wafers produced in a semiconductor fabrication factory. [Figure 16] FIG. 1 illustrates a system that may be used to control the production of wafers in a semiconductor foundry. [Figure 17] FIG. 1 illustrates a system that may be used to control the quality of wafers produced in a semiconductor fabrication factory. [Figure 18] FIG. 1 illustrates a system that may be used to control the production of wafers in a semiconductor foundry. DETAILED DESCRIPTION OF THE INVENTION

[0063] In the following, preferred exemplary embodiments of the present invention will be described and illustrated schematically in the drawings. Throughout the drawings and description, the same reference numerals will be used to refer to the same features or components.

[0064] FIG. 1 shows a schematic cell structure 10, 10', 10'' of the imaging data sets 12, 12', 12'' of three defect measurement sites on a wafer 226. In this schematic view, the cells 14, 14', 14'' are identical and regularly distributed throughout each of the imaging data sets 12, 12', 12''. The cell structures 10, 10', 10'' contain defects 16, such as "open," "shrinkage," or "merge," i.e., deviations of semiconductor structures from a priori defined standards. Recognizing defects 16 in the imaging data sets 12, 12', 12'' of the wafer 226 is important for quality control and quality assurance processes. Quality assurance ensures that techniques, methods, and processes for wafer fabrication are performed according to requirements. Quality assurance aims to improve the parameters or conditions of wafer fabrication processes in a fab, such as deposition, exposure, and etching processes. For this purpose, known and unknown defects must be recognized and analyzed. In contrast, quality control aims to ensure the quality of the final manufactured product in an in-line manufacturing process. To this end, known defects must be recognized and analyzed.

[0065] Machine learning models can be used to process vast amounts of data containing a variety of known and unknown defects with limited user interaction.

[0066] A machine learning model is the result of a machine learning method run on training data. A machine learning model represents what has been learned by the machine learning method. A machine learning model includes a model architecture, model data, and a prediction method. The model architecture includes a generalized structure or design of a machine learning model defined by hyperparameters, e.g., neurons of a neural network and the connections between them. The model data includes values, numbers, or any other method-specific data structure that embodies the generalized structure to solve a specific machine learning problem and to make predictions for new data samples, e.g., neural network weights. The prediction method is a procedure, e.g., a forward pass algorithm for a neural network, that describes how to make predictions on new data using the model data. Applying a machine learning method or model to data refers to applying a prediction method based on a trained model to the data.

[0067] In various embodiments of the present invention, the machine learning model can be any type of machine learning model, including, but not limited to, a decision tree-based model, a linear regression-based model, a neural network-based model, a Bayesian network-based model, a support vector machine-based model, and a nearest neighbor-based model, to name a few. The provided machine learning model can also be a combination of various types of models. Furthermore, the model can be provided in any type of format. For example, a neural network model can be provided using representative models such as AlexNet, GoogleNet, ResNet, DenseNet, or another type of neural network format. However, in various embodiments, the type and format of the model are not limited to the aforementioned model types and formats. In some embodiments, the model can be preprocessed and trained, while in other embodiments, preprocessing is not required. The trained model can also be loaded from one or more files.

[0068] For example, a decision tree is a machine learning model that includes a model architecture in the form of a tree of if-then statements. The hyperparameters of a decision tree's model architecture define the structure of the tree, including, for example, the number of levels in the tree and the number of decision nodes. The decision tree includes model data in the form of specific values ​​for the if-then statements and a prediction method that defines the application of the if-then statements to input data.

[0069] Support vector machines (SVMs) are machine learning models that include a model architecture in the form of at least one hyperplane. The hyperparameters of an SVM's model architecture define the at least one hyperplane, including, for example, the number and type of the hyperplanes. An SVM includes model data in the form of a matrix, vector, or value that defines a particular hyperplane, and a prediction method that defines the assignment of output values ​​to input data based on the at least one hyperplane.

[0070] A neural network is a machine learning model that includes a model architecture in the form of a graph structure. The hyperparameters of a neural network's model architecture define the generalized structure or structure of the neural network, including, for example, the topology and size of the neural network, such as: - Loss function type and / or parameters - Bottleneck size - bottleneck filter size (number of features at the bottleneck), - initial filter size (the number of filters in the first layer of the network; other network features are scaled proportionally to the first layer), - initial learning rate, - learning rate decay factor, - Use of momentum, - number of epochs, - regularization scale, - the size and content of the training set (number of images), - the type of convolution used, - upsampling method, - connections between layers, - the number of layers in the model, - a sample representing the dataset, - the size of the layers in the model, - the type of layers in the model, - filter size, - dropout rate, - kernel size of convolutional layers, - Use of Nesterov accelerated gradients, - type of optimization algorithm, - etc.

[0071] The model data of a neural network includes the model weights, which comprise vectors or matrices containing specific values ​​that define the transfer functions of neurons in the hidden layer. A neuron's transfer function converts the neuron's input data into the neuron's output data, which is then passed to one or more other neurons in the neural network. Transfer functions include, for example, sigmoid functions, step functions (thresholds), piecewise linear functions, Gaussian functions, or combinations thereof. The neural network's prediction method defines the forward pass of input data through the network to obtain a result.

[0072] The hyperparameters of the model architecture of a machine learning model are usually not learned from data. Instead, these hyperparameters can be selected by, for example, an expert, or can be automatically optimized using AutoML techniques, for example, in the case of neural networks, particularly by Neural Architecture Search (NAS) techniques. These techniques automatically search for optimal hyperparameter values ​​of the model architecture of a machine learning model. Based on an objective function that evaluates the quality of a set of hyperparameter values, AutoML techniques are usually based on the iterative principle of predicting at least one hyperparameter value based on previously selected hyperparameter values ​​and associated values ​​of the objective function, setting the model architecture of the machine learning model according to the selected hyperparameter values, training the machine learning model based on training data, evaluating the objective function for the predicted at least one hyperparameter based on the trained machine learning model, and selecting at least one hyperparameter value that produces the best objective function value after the final iteration.

[0073] In contrast, model data, e.g., the weights of a neural network, are learned from training data.

[0074] The hyperparameters of a machine learning model's learning algorithm, in principle, do not affect the performance of the model architecture, but they do affect the speed and quality of the learning process. Examples of algorithm hyperparameters are the learning rate and the mini-batch size.

[0075] Both quality assurance and quality control processes require defects to be recognized as accurately and quickly as possible to achieve high throughput or short algorithm execution times. The throughput of a system can be measured, for example, by the area of ​​a wafer inspected in a specific time at a specific resolution, or by the time required to inspect a specific area of ​​a wafer, e.g., 1 cm, at a resolution of 1 nm. 2 wafers can be processed within 24 hours.

[0076] To meet high requirements in terms of execution time, embedded systems are often chosen for digital data processing. However, using embedded systems involves a large design and configuration effort, since pre-programmed libraries common to conventional processors are not available for programming embedded systems.

[0077] In view of such limitations, various embodiments of the present invention are directed to a new method for implementing a machine learning model in an embedded system. The method utilizes the specific structure of the machine learning model defined above, which includes a generalized model architecture and use-case-specific model data. By implementing only the model architecture of the machine learning model on the embedded system and dynamically loading the trained model data into the programmable memory of the embedded system, the implemented machine learning model architecture can be reused for another use case or retrained for different imaging datasets, thereby saving resources, user effort, and computation time.

[0078] The overall method of the first embodiment of the present invention is illustrated in Figure 2. Figure 2 shows a flowchart of steps in an exemplary computer-implemented method 22 for defect recognition in an imaging dataset 12, 12', 12" of a wafer 226 in a charged particle beam system 78 having an embedded system 50, 50', the method including, in an imaging step 26, acquiring the imaging dataset 12, 12', 12" of the wafer 226, and, in a model data step 28, acquiring model data 44, 44', 44" of a model architecture 42 of a machine learning model 40, 40', 40" for defect recognition in the imaging dataset 12, 12', 12" of the wafer 226. The method includes: obtaining, where the model architecture 42 is implemented in an embedded system 50, 50′; transferring, in a model data transfer step 30, the model data 44, 44′, 44″ to a programmable memory 48, 48′, 48″ of the embedded system 50, 50′; and applying, in a step 32, executing the embedded system-implemented model architecture 46 using the transferred model data 44, 44′, 44″; applying the machine learning model 40, 40′, 40″ to the imaging dataset 12, 12′, 12″ of the wafer 226 to recognize defects 16. The recognized defects 16 can be used, for example, in quality assurance systems 228, 234 and / or quality control systems 212, 232, specifically for the wafer 226, but may also be used for other manufactured objects. These steps may be repeated if a new use case 34 is defined or the model architecture or model data is updated.

[0079] FIG. 3 illustrates the use of a separation of model architecture 42 and model data 44, 44′, 44″ for flexible implementation of machine learning models 40, 40′, 40″ in an embedded system 50. Three machine learning models 40, 40′, 40″ including the same model architecture 42 but including different model data 44, 44′, 44″, e.g., neural networks including three different sets of weights for three different use cases, can be implemented in the embedded system 50 by implementing the model architecture 42 in the embedded system 50 to produce an embedded-system-implemented model architecture 46 and transferring the respective model data 44, 44′, 44″ to the programmable memory 48 of the embedded system 50. In this manner, different use cases can be easily implemented in the embedded system 50. Also, adaptation or refinement of the model data 44 of the machine learning models 40 is easily possible. If improved model data 44', 44'' becomes available, for example, by retraining the machine learning model 40, or if the requirements of the machine learning model 40 change, for example, if an unknown defect occurs in the imaging dataset 12, 12', 12'' and the machine learning model 40 needs to be retrained, the new model data 44', 44'' can be easily transferred to the programmable memory 48 of the embedded system 50, and the embedded system implementation of the machine learning model 40 can save implementation effort and time while increasing throughput and reducing execution time.

[0080] In one example, the wafer 226 includes various measurement sites containing various semiconductor structures to be investigated. Using the method according to the first embodiment, during inspection of the wafer 226, it is possible to quickly switch from a first defect inspection task of a first imaging data set 12 acquired at the first measurement site to a second defect inspection task of a second imaging data set 12′ acquired at a second measurement site on the wafer 226. During inspection of the wafer 226, first predefined model data 44 is retrieved from the memory of the charged particle beam system 78 and transferred to the programmable memory 48 of the embedded system 50 for execution of the first defect inspection task. During inspection of the wafer 226, second predefined model data 44′ is retrieved from the memory of the charged particle beam system 78 and transferred to the programmable memory 48 of the embedded system 50 for execution of the second defect inspection task. In one example, a third defect inspection task for a third imaging data set 12" acquired at a third measurement location on the wafer 226 is added to the inspection of the wafer 226. For the third defect inspection task, third model data 44" is determined for the model architecture 42 implemented in the embedded system 50. An example of determining the third model data 44" for the new defect inspection task is further described below in the third embodiment. The newly determined third model data 44" is stored in the memory of the charged particle beam system 78 and transferred to the programmable memory 48 of the embedded system 50 for execution of the third defect inspection task. The model data 44, 44', 44" are stored in the memory of the charged particle beam system 78 and associated with different defect inspection tasks corresponding to different imaging data sets 12, 12', 12" acquired by the charged particle beam system 78 at different measurement locations on the wafer 226.

[0081] The flexibility and modularity of this method can be further improved by subdividing the model architecture into several FPGA-implemented modules that can be combined to form different kinds of machine learning architectures.

[0082] The overall method of the second embodiment of the present invention is illustrated in Figure 4. Figure 4 shows a flowchart of steps in an exemplary computer-implemented method 52 for defect recognition in an imaging dataset 12, 12', 12" of a wafer 226 in a charged particle beam system 78 having at least one embedded system 50, 50', the method including, in an imaging step 56, acquiring the imaging dataset 12, 12', 12" of the wafer 226, and, in a data flow specification step 58, defining an embedded system-implemented model architecture 46 of a machine learning model 40, 40', 40" for defect recognition in an imaging dataset 12, 12', 12" of the wafer 226 by specifying a flow of data 74 through some of a plurality of logic block circuits 72', 72'" of a plurality of logic block circuits 72, 72', 72", 72'", 74, 74', 74", 74'" in one of the at least one embedded system 50, 50', the logic block circuits 72, 72′, 72″, 72′″, 74, 74′, 74″, 74′′ of the at least one model architecture 42 of the at least one machine learning model 40, 40′, 40″ for defect recognition, including one or more modules 102, 104 of the at least one model architecture 42 of the at least one machine learning model 40, 40′, 40″ for defect recognition; acquiring model data 44, 44′, 44″ of the embedded system-implemented model architecture 46 in a model data step 60; transferring the model data 44, 44′, 44″ to a programmable memory 48, 48′, 48″ of the embedded system 50, 50′ in a model data transfer step 62; and executing the embedded system-implemented model architecture 46 using the transferred model data 44, 44′, 44″ in an application step 64; and applying the machine learning model 40, 40′, 40″ to the imaging dataset 12, 12′, 12″ of the wafer 226 to recognize defects 16. The recognized defects 16 can be used, for example, in a quality assurance system 115 and / or in a quality control system 117, particularly for wafers 226, but also for other manufactured objects.These steps can be repeated if new use cases 66 are defined or the model architecture or model data is updated.

[0083] FIG. 5 illustrates a particularly flexible and versatile approach to implementing a machine learning model 40 in a charged particle beam system 78 comprising two embedded systems 50, 50′. The embedded systems 50, 50′ comprise modules of different model architectures, each implemented by a plurality of logic block circuits 72, 72′, 72″, 72′″, 74, 74′, 74″, 74′″. To implement a particular model architecture 42 in the charged particle beam system 78, several logic block circuits 72′, 72′″ are selected in one of the embedded systems 50, and a data flow 74 is specified by interconnecting a selected number of logic block circuits 72′, 72′″ within the embedded system 50. The model data 44 can be transferred to a programmable memory 48′ of the embedded system 50, as previously described. In this way, by interconnecting a number of logic block circuits 72′, 72″ corresponding to the modules of the model architecture 42, not only different model data 44, 44′, 44″ but also different model architectures 42 including various modules can be easily implemented, thereby reducing the effort of implementing machine learning models in the charged particle beam system 78 equipped with the embedded system 50, 50′. The modularity of the machine learning models combined with the dynamic reconfiguration possibilities offered by the embedded system can achieve the aforementioned objectives.

[0084] Each time a new use case 34, 66 arises, the machine learning model 40 can be retrained, and new model data 44′, 44″ can be transferred to the programmable memory 48, 48′, 48″ of the embedded system 50, 50′ without changing the embedded system implementation model architecture 46. The separation of the model architecture 42 from the embedded system implementation, and the generation and transfer of model data 40, 40′, 40″ to the programmable memory 48, 48′, 48″ of the embedded system 50, 50′, significantly reduces the time and effort required to implement the machine learning model 40 on the embedded system 50, 50′, because the model data 44, 44′, 44″ can be easily swapped for new use cases 34, 66. In this way, embedded system programs for machine learning become more flexible, reusable, and versatile. At the same time, a new business model is enabled in which a charged particle beam system including at least one embedded system 50, 50′ each having a plurality of logic block circuits 72, 72′, 72″, 72′″, 74, 74′, 74″, 74′″ of the implemented model architecture 46 implementing modules of the machine learning architecture is sold to a customer only once, while the model data 44, 44′, 44″ can be updated periodically, for example using a service contract, or whenever use cases or requirements change.

[0085] Figure 6 illustrates the use of embedded systems 50, 50' in the form of FPGAs 51 for various use cases. FPGAs are integrated circuits designed to be configured by customers or designers after manufacture. The configuration of an FPGA is typically specified using a hardware description language. FPGAs contain an array of programmable logic blocks and a hierarchy of reconfigurable interconnects that allow the blocks to be wired together. Logic blocks can be configured to perform complex combinatorial functions or function as simple logic gates such as AND and XOR. In most FPGAs, logic blocks also contain memory elements, which can be simple flip-flops or more complete blocks of memory. Many FPGAs can be reprogrammed to perform different logic functions, enabling flexible and reconfigurable computing. FPGA 51 includes an adaptive logic module 80, an M512 block 82, an M4K block 84, a high-speed I / O channel 86 with dynamic phase alignment (DPA), an I / O channel 88 with external memory interface circuitry, a digital signal processing block 90, an M-RAM block 92, and a phase-locked loop 94. By simply exchanging the model data 44 , 44 ′, 44 ″ in the programmable memory 48 of the FPGA 51 , new use cases can be realized in the same charged particle beam system 78 without the additional effort of reprogramming the FPGA 51 .

[0086] The model data 44, 44′, 44″ of the FPGA-implemented model architecture 46 can be obtained in various ways. For example, the model data 44, 44′, 44″ of the FPGA-implemented model architecture 46 can be read from the database 225. The model data 44, 44′, 44″ of the FPGA-implemented model architecture 46 can also be obtained by training a machine learning model 40, 40′, 40″ that includes the aforementioned model architecture 46. After training, the obtained model data 44, 44′, 44″ can be stored in the database 225 to make it available for further applications. Furthermore, the model data 44, 44′, 44″ can be provided by an external service that allows dynamic updating of the model data 44, 44′, 44″, for example, to improve or adapt the model data 44, 44′, 44″ to changed requirements. Such services can be used as a new business model that separates the hardware comprising an embedded system including each module of the implemented model architecture, which is sold only once, from the model data, which may be updated periodically. In this way, the use of embedded systems 50, 50' for implementing machine learning models 40, 40', 40'' can save time and effort, achieve high system flexibility, and optimize the quality of the defect recognition method while maximizing throughput and reducing execution time.

[0087] In examples of the first and second embodiments of the present invention, the model data 44, 44', 44'' may be transferred to the programmable memory 48, 48', 48'' of the embedded system 50, 50' by copying. Alternatively, the model data 44, 44', 44'' may be transferred to the programmable memory 48, 48', 48'' of the embedded system 50, 50' by replacing the hardware block containing the programmable memory 48, 48', 48'' of the embedded system 50, 50' with a new hardware block containing the transferred model data 44, 44', 44''.

[0088] To provide a user with defect recognition results for quality assessment or quality control, the recognized defects 16 can be directed to, for example, a display device 227 or a dashboard, enabling real-time monitoring of the detected defects 16. In another implementation of the first or second embodiment, the recognized defects 16 can be stored in long-term memory for further analysis, for example, to generate statistics about the defects 16. In a further implementation, the recognized defects can be cached in memory for a specified time, for example, 48 hours, to enable further analysis of the detected defects 16, but without requiring a large amount of memory. In another implementation, the recognized defects are analyzed in step (ii) to update the embedded system implementation model architecture 46, for example, the defect recognition results are used to receive feedback from downstream applications, followed by updating each module of the embedded system implementation model architecture, for example, to address data drift.

[0089] The charged particle beam system 78 in the second embodiment of the present invention includes at least one embedded system 50, 50′ to enable implementation of various machine learning models 40, 40′, 40″ based on various model architectures 42 in the same charged particle beam system 78. Each model architecture may be implemented in a separate embedded system 50, 50′ in the charged particle beam system 78. The various model architectures 42 may also be implemented in the same embedded system 50, 50′. To make the system even more flexible and versatile, the model architecture 42 of the machine learning models 40, 40′, 40″ may be divided into one or more modules and implemented in multiple logic block circuits 72, 72′, 72″, 72′″, 74, 74′, 74″, 74′′ in one or more of the at least one embedded system 50, 50′. In this manner, the new model architecture 42 of the machine learning models 40, 40', 40'' can be easily implemented in the charged particle beam system 78 by specifying the flow 74 of data through the required number of logic block circuits 72', 72''' during application of the defect recognition method and interconnecting the aforementioned logic block circuits 72', 72''' as shown and described with respect to Figure 7.

[0090] FIG. 7 shows a schematic embedded system implementation of a first module 102 and a second module 104 of the neural network model architecture. Input data for both modules 102, 104 is available via an input data bus 98. Model data in the form of weights 100 for each module 102, 104 is available via a programmable memory 48 on the embedded system 50. The first module 102 has one convolutional layer including a single 2×2 filter based on multiplication 110 of the input data on the input data bus 98 with the weights 100 corresponding to the first module 102. The second module 104 has two convolutional 2×2 filters based on multiplication 110 of the input data on the input data bus 98 with the weights 100 corresponding to the second module 104. When defining the flow of data 74, the modules 102, 104 can be selected using a multiplexer 108, which is configured, for example, by a user via a programmable configuration memory 106.

[0091] A module of a model architecture can include a part of the model architecture, such as one or more layers of a neural network, a subtree of a decision tree, one or more hyperplanes of an SVM, or a set of one or more nodes of a graph structure, e.g., in a Hidden Markov Model.

[0092] According to an example of the second embodiment, the at least one model architecture of the at least one machine learning model for defect recognition comprises a model architecture of a neural network, e.g., for deep learning, whereby neural networks, due to their subdivision into layers, are particularly suited to subdivision into logic block circuits, offering the advantage of reducing the effort of programming the embedded system and specifying the flow of data through the logic block circuits.

[0093] According to an example aspect of the second embodiment, one or more modules can be head modules, which include an output layer of a neural network. The output layer generates a result of the neural network when presented with input data, such as a classification into one of several classes, a binary output, or one or more specific return values. The output layer can be task-specific, i.e., used only for a specific task. For example, one or more head modules can include a fully connected output layer of a neural network and / or a convolutional output layer of a neural network. The fully connected output layer of a neural network is specifically designed for tasks such as classification because the output layer does not have spatial context limitations. The convolutional layer of a neural network is specifically designed for tasks such as defect detection, anomaly detection, or defect segmentation due to consideration of spatial context.

[0094] According to an example aspect of the second embodiment, one or more modules are tail modules, which are modules that include several hidden layers of a neural network, thereby enabling the combination of multiple hidden layers into a single tail module, thereby reducing programming effort and effort in specifying data flows.

[0095] The separation of the head and / or tail modules offers the advantage of flexibility and versatility, since the tasks imposed on the neural network can be easily changed by swapping the head module to change the flow of data, and since the tail module can be used in many different model architectures without additional effort.

[0096] Additionally, the subdivision of the model architecture into head and tail modules allows for the semantic combination of hidden layers that perform specific tasks within the model architecture into a single tail module, thus further simplifying the modular structure of the model architecture and reducing the programming effort and the effort required to specify the flow of data.

[0097] For example, FIG. 8 illustrates a subdivision of the model architecture 42 in the form of a neural network 114 into a head module 116 and a tail module 118. FIG. 8 illustrates the neural network 114 including hidden layers 122, 123 and an output layer 120 obtained using filters of the indicated spatial and feature sizes. The neural network 114 includes a head module 116 including the output layer 120 of the neural network 114 and a single tail module 118. The head module 116 includes the output layer 120 of the neural network 114, while the tail module 118 includes several hidden layers 122, 123 of the neural network 114, in particular all of the hidden layers 122, 123. The output layer is a 1×1×32 filter pooling layer and is therefore adapted to solve defect detection, anomaly detection, or segmentation tasks based on a feature map including 32 features generated by the last hidden layer 123. The separation of the task-specific head module 116 from the rest of the model architecture is beneficial because in this way the head module 116 can be easily swapped out for a different head module 116 to impose different tasks on the model architecture in different applications. For example, the head module 116 can be adapted for a classification task.

[0098] 9 illustrates different head modules 124, 126 and tail modules 128, 130, 132, 134, 136, and 138 for various model architectures. This modular structure allows a family of model architectures to be realized on the embedded system 50, 50′ by combining one or more different tail modules 128, 130, 132, 134, 136, and 138 with one of the head modules 124, 126. The head modules 124, 126 can be task-specific. For example, the head module 124 with a filter size of 1×1×D (where D indicates the number of features) is suitable for anomaly detection, defect detection, or segmentation tasks, while the head module 126 with a filter size of 1×1×CS (where S indicates softmax and C indicates the number of classes) is suitable for classification tasks. The advantage of this modularity is that the task of the neural network can be easily changed by simply exchanging the head modules 124, 126, e.g., the output layer of the neural network, without changing the tail modules 128, 130, 132, 134, 136, 138, e.g., the hidden layers of the neural network, that define the data flow 74 in order to realize the model architecture on the embedded system 50, 50'.

[0099] According to another aspect of an example of the second embodiment, at least one tail module, and in particular each tail module, can include all hidden layers 122, 123 of a neural network 114, as shown in Figure 8. This is advantageous because each neural network 114 consists of only a single head module 116 and a single tail module 118. This allows for a particularly simple embedded system implementation of the neural network, and a particularly simple specification of the flow of data through the logic block circuitry of the embedded system, since fewer blocks need to be interconnected.

[0100] According to a further aspect of the second embodiment, at least one tail module, and in particular each tail module, may include several hidden layers of a neural network that form semantic entities. The term "semantic entities" refers to several hidden layers 122, 123 that form functional units, in the sense that they complement each other and together perform a specific function within the neural network 114. For example, the hidden layer of tail module 128 is a semantic entity because it forms a functional unit for reducing input data. The same applies to the hidden layer of tail module 132. The hidden layer of tail module 136 forms a functional entity because it forms a bottleneck for reducing the dimensionality of data, for example, a bottleneck for representing an autoencoder. The same applies to the hidden layer of tail module 138. The hidden layer of tail module 130 is a semantic entity because it forms a functional unit for expanding data. The same applies to the hidden layer of tail module 134. By defining tail modules that form semantic entities, the effort to implement the model architecture on one or more embedded systems is reduced, since only a small number of functional entities that perform specific functions in the model architecture need to be interconnected to specify the flow of data.

[0101] According to a further aspect of an example of the second embodiment, at least two of the tail modules include the same number of hidden layers, and the sizes of the feature maps of corresponding hidden layers differ by the same factor. The hidden layers of two modules correspond to each other in terms of their rank in the order of the modules' hidden layers, e.g., the second hidden layer of one module corresponds to the second hidden layer of another module. This enables the implementation of neural networks that consider various numbers of features, for example, using small, medium, or large modules for the same task. In a further aspect of an example of the second embodiment, for each tail module, there is at least one other tail module that includes the same number of hidden layers, and the sizes of the feature maps of corresponding hidden layers differ by the same factor. For example, FIG. 9 shows two tail modules 128 and 132 that include the same number of hidden layers, i.e., three. The feature map sizes of the corresponding first layers 129 and 129′ are 32 and 16, respectively, which differ by a factor of two. The feature map sizes of the corresponding second layers 131 and 131′ are 16 and 8, respectively, which differ by a factor of two. The feature map sizes of the corresponding third layers 133, 133' are 8 and 4, respectively, also differing by a factor of two. Thus, modules 128 and 132 perform the same task and differ only in the complexity of their feature maps. For example, tail modules 136 and 138 include only a single corresponding hidden layer, with feature map sizes differing by a factor of 10. In this way, model architectures that consider various amounts of features—for example, small, medium, or large model architectures—can be implemented in the same embedded system, enabling adaptation of the model architecture size to the difficulty of the machine learning task. By replacing the corresponding logic block circuit of the small tail module 138 with the logic block circuit of the large tail module 136, model architectures that include more or fewer features can be easily implemented on the embedded system. In this way, the embedded system implementation of the model architecture becomes particularly flexible and adaptable to the requirements of the machine learning task being solved.

[0102] In FIG. 9 , for example, by specifying a data flow interconnecting tail modules 128, 136, and 130 with head module 124, anomaly or defect detection based on a larger U-net model architecture that considers more features can be performed. Here, tail module 128 reduces the input data, tail module 136 represents a bottleneck used to obtain a very low-dimensional representation of the input data, and tail module 130 expands the data. Therefore, the combination of these tail modules 128, 136, and 130 represents an autoencoder structure. Head module 124 represents a convolutional layer for calculating the results of the defect or anomaly detection task. Such a large model architecture is useful for more complex defect or anomaly detection tasks that require more features to be considered. To perform anomaly or defect detection based on a smaller U-net model architecture that considers only a few features, tail modules 132, 138, and 134 can be interconnected with head module 124. The combination of tail modules 132, 138, and 134 also represents an autoencoder, but with fewer features and a smaller bottleneck. The head module 124 represents a convolutional layer for computing the results of the defect or anomaly detection task. Such a compact model architecture is useful for less complex defect or anomaly detection tasks that require fewer features to be considered.

[0103] The modular structure shown in FIG. 9 can also be used for segmentation tasks. Here, a large U-net model architecture can be implemented on an embedded system by interconnecting the tail module 128 with the head module 124. To obtain a compact U-net model architecture on an embedded system, the tail module 132 can be interconnected with the head module 124. The head module 124 is a convolutional layer used to calculate the result of the segmentation task, i.e., the assignment of each pixel of the imaging dataset to a particular class. Depending on the difficulty of the segmentation task, more or fewer features should be considered, and therefore, a large model architecture or a compact architecture, respectively, is useful.

[0104] The module structure shown in FIG. 9 can also be used for classification tasks. By specifying the data flow interconnecting the tail modules 128, 136, and 130 with the head module 126, classification based on a larger U-net model architecture that considers more features can be performed. Again, the combination of these tail modules 128, 136, and 130 represents the structure of an autoencoder. The head module 126 represents a fully connected softmax layer for calculating the classification task result. Such a large model architecture is useful for more complex classification tasks that require more features to be considered. To perform classification based on a smaller U-net model architecture that considers only a few features, the tail modules 132, 138, and 134 can be interconnected with the head module 126. The combination of the tail modules 132, 138, and 134 also represents an autoencoder, but with fewer features and a smaller bottleneck. The head module 126 represents a fully connected layer for calculating the classification task result. Such a small model architecture is useful for less complex classification tasks that require fewer features to be considered.

[0105] In this way, large, medium, or small model architectures can be easily implemented on the embedded system, making the system highly flexible for different requirements of different tasks. Additionally, the modular implementation of model architectures with different feature map sizes on the embedded system simplifies testing different model architectures during quality assurance to find the best model architecture in terms of quality and execution time.

[0106] According to an example aspect of the second embodiment, each module of the one or more modules is either a head module including an output layer of a neural network or a tail module including several hidden layers of the neural network. In addition, the one or more modules may include at least one head module and at least one tail module.

[0107] According to an example aspect of the second embodiment, one or more modules are generated from at least one model architecture of a neural network by dividing each model architecture into a head module including an output layer of the neural network and at least one, in particular a single, tail module including several hidden layers of the neural network. In this way, these neural networks can be easily implemented on at least one embedded system in the charged particle beam system, since the modules implemented on the system directly correspond to the model architecture including all hidden layers of the neural network.

[0108] According to a second embodiment of the present invention, before specifying the flow of data through some of the logic block circuits, it is advantageous to determine whether the model architecture of the trained machine learning model can be realized by the logic block circuits in one of the at least one embedded system, and in response to determining that the model architecture cannot be realized, generate one or more modules of the model architecture of the trained machine learning model and implement the one or more modules in one of the at least one embedded system. In this way, for a specific machine learning task and a corresponding machine learning model, it can be checked whether the model architecture of the machine learning model can be realized by various modules already implemented in the embedded system of the charged particle beam system. If not, missing modules can be determined and implemented in one of the embedded systems of the charged particle beam system to make the model architecture representable by the logic block circuits of the embedded system in the charged particle beam system. This process is shown in FIG. 10.

[0109] FIG. 10 illustrates a process for implementing a new use case 34, 66 in a charged particle beam system 78 by a computer-implemented method according to one or more embodiments or examples of the present invention. After start 142, a group of machine learning models needed to solve the new use case 34, 66 is determined in group determination step 144. The group may include, for example, defect detection models, segmentation models, or classification models. If the use case belongs to a new group not yet implemented in the system (“Yes” 170), the expert collects information about possible use cases in this group in use case collection step 154. The expert defines a generic model architecture for this group that includes the determined possible use cases in model architecture definition step 156. Next, the expert determines whether the defined model architecture is feasible on an existing embedded system in the charged particle beam system 78 in feasibility step 158. If not (“No” 180), the defined model is generalized on a new embedded system in the charged particle beam system 78 in model implementation step 160. If feasible (“Yes” 178), then in a data acquisition and training step 150, training data and ground truth data are acquired, and a machine learning model for the new use case 34, 66 is trained. In a model data storage step 152, the expert stores the generated model data, e.g., neural network weights, in a database. To execute the machine learning model on the embedded system within the charged particle beam system 78, in a model data retrieval step 162, the trained model data is read from the database. In a model data transfer step 164, the determined model data is downloaded from the database and transferred to the programmable memory of the embedded system, allowing the model architecture of the machine learning model for the new use case 34, 66 to be realized in the charged particle beam system 78. Finally, in a data processing step 166, the machine learning model implemented in the embedded system is run in real time on the input data, after which the process stops (168).Otherwise, if the use case belongs to a new family that is already implemented in the system (“No” 172), it is determined whether the use case is a new use case 34, 66 that has not yet been implemented in the system (“Yes” 174) or not (“No” 176). If the use case is a new use case 34, 66, the model architecture for this family is already implemented in the system, but model data needs to be generated for the new use case 34, 66. Thus, in problem injection step 148, the machine learning problem is injected into the pre-defined model architecture for this family that is already implemented in the system. Next, in data acquisition and training step 150, model data is obtained as described above, and the process continues as described above. On the other hand, if the use case is already implemented in the system (“No” 176), the model architecture and model data are already available, and the process continues with model data retrieval step 162, as described above.

[0110] As shown above, the implementation of a model architecture of a machine learning model on an embedded system based on tail modules and task-specific head modules that can be interconnected to form a flow of data through multiple logic block circuits on the embedded system, combined with easily exchangeable model data in the programmable memory of the embedded system, results in a highly flexible, adaptable and versatile implementation of the machine learning model on the embedded system.

[0111] A third embodiment of the present invention will now be described with reference to Figure 11. Figure 11 shows a flowchart of steps in an exemplary computer-implemented method 182 for defect recognition. This method includes a computer-implemented method 22, 52 according to the first or second embodiment of the present invention or any example or aspect thereof, and further includes repeating 194 of the following steps: in an image acquisition parameter step 184, selecting at least one image acquisition parameter according to an imaging sampling strategy and acquiring an imaging dataset of the wafer based on the at least one image acquisition parameter, until a convergence criterion, for example a maximum number of steps, is met before acquiring an imaging dataset of the wafer in step (i); in a training data generation step 186, generating training data from the acquired imaging dataset of the wafer; in a machine learning model training step 188, selecting a model architecture and training an associated machine learning model based on the generated training data; in a quality assessment step 190, determining the quality of the model architecture and the at least one image acquisition parameter by calculating an associated objective function value of an objective function that evaluates the quality of the trained machine learning model; and after the final iteration 194, in a selection step 192, selecting one of the model architectures and the corresponding at least one image acquisition parameter based on the objective function value. The imaging dataset of the wafer in step (i) 26, 56 of the computer-implemented method according to the first or second embodiment of the present invention or any example or aspect thereof is acquired based on at least one selected image acquisition parameter, and the embedded system-implemented model architecture in step (ii) 28, 58 of the computer-implemented method according to the first or second embodiment of the present invention or any example or aspect thereof includes the model architecture of the selected machine learning model. This aspect is illustrated in Figures 12 and 13, where the model architecture selected in selection step 192 and the corresponding at least one image acquisition parameter are used in steps 26, 28, 56, 58 of the computer-implemented method 22, 52.

[0112] A fourth embodiment of the present invention will be described below with reference to Figure 14. The fourth embodiment of the present invention is a computer-implemented method 196 for defect recognition in an imaging dataset of a wafer, the method including: selecting at least one image acquisition parameter according to an imaging sampling strategy in an image acquisition parameter step 198 and acquiring an imaging dataset of the wafer based on the at least one image acquisition parameter; generating training data from the acquired imaging dataset of the wafer in a training data generation step 200; selecting a model architecture and training an associated machine learning model based on the generated training data in a machine learning model training step 202; and evaluating the quality of the trained machine learning model by calculating an associated objective function value of an objective function in a quality assessment step 204, until a convergence criterion, e.g., a maximum number of steps, is met; after the final iteration 210, selecting one of the trained machine learning models based on the objective function value in a selection step 206; and applying the selected trained machine learning model to the imaging dataset of the wafer acquired based on the corresponding at least one image acquisition parameter in an application step 208 to recognize defects. The identified defects may be used in wafer quality assurance and / or quality control systems.

[0113] The method according to the third or fourth embodiment of the present invention has the advantage that at least one image acquisition parameter used to generate the imaging data set of the wafer, and therefore the training data, and the model architecture of the machine learning model can be jointly optimized before implementing the model architecture in one of the embedded systems in the charged particle beam system. In this process, the model architecture can be optimized with respect to various criteria, for example, to reduce execution time, to further increase the throughput of the charged particle beam system, to reduce the complexity of the model architecture, or to improve the quality of the predictions of the machine learning model.

[0114] The at least one image acquisition parameter may be from the group including, for example, imaging time, image resolution, pixel size, landing energy and dwell time of the electron wave.

[0115] In an example of the third or fourth embodiment of the present invention, the step of selecting the model architecture 42 includes selecting at least one hyperparameter that defines the model architecture 42 of the machine learning model 40, 40′, 40″ according to an architecture sampling strategy. The architecture sampling strategy may include some hyperparameters selected by a user, or hyperparameters that are automatically sampled according to, for example, AutoML techniques and sampling strategies for hyperparameters known to those skilled in the art, such as a tree-structured Parzen estimator or an asynchronous successive halving strategy. This is advantageous because the hyperparameters of the machine learning model may be automatically optimized together with at least one image acquisition parameter.

[0116] In an example of the third or fourth embodiment of the present invention, the objective function may include a complexity measure of the model architecture 42. The complexity measure may include, for example, the size of the model architecture 42, such as the number of layers and / or neurons of the neural network 114, the number of hyperplanes of an SVM, the number of levels and / or nodes of a decision tree, or the number of nodes and connections in a graph structure. The complexity measure provides the advantage that a smaller size model architecture 42 can be used to solve a machine learning task, thereby reducing the execution time of the machine learning model 40, 40′, 40″, increasing the throughput of the charged particle beam system 78, and requiring less space on the embedded system 50, 50′, such that more model architectures 42 can be implemented in the embedded system 50, 50′ within the charged particle beam system 78.

[0117] In another implementation of the third or fourth embodiment of the present invention, the objective function may include an execution time measure, and / or a throughput and / or data rate measure, and / or a power consumption measure.

[0118] In another example of the third or fourth embodiment of the present invention, the objective function may include a measure of the quality of defect recognition, such as a loss function of the neural network 114 applied to the training data, or any other measure known to those skilled in the art for measuring the prediction error of the machine learning model 40, 40′, 40″ against the training data generated using at least one image acquisition parameter.

[0119] In a further example of the third or fourth embodiment of the present invention, the objective function may include a measure of the amount of bits of input data for the machine learning model 40, 40′, 40″, e.g., the number of input bits for the input layer of the machine learning model 40, 40′, 40″. In this way, the complexity of the model architecture 42 may be reduced. This provides the advantage of faster execution times for the machine learning model 40, 40′, 40″ due to less data needing to be processed. Furthermore, a model architecture 42 with a reduced amount of input bits may be more easily implemented on the embedded system 50, 50′ due to reduced space requirements. In this way, a greater variety of model architectures 42 may be implemented on the embedded system 50, 50′ of the charged particle beam system 78. If a very large model architecture 42 is incompatible with implementation on the embedded system 50, 50′, the size of the model architecture 42 may be reduced by reducing the amount of input bits, thereby increasing the likelihood of implementing the machine learning model 40, 40′, 40″ on the embedded system 50, 50′.

[0120] In one example of an embodiment of the present invention, the computer-implemented method further includes determining one or more measurements of the defects recognized in the imaging data set of the wafer, in particular, size, area, dimension, shape parameter, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of the defects. The aforementioned measurements may be calculated for a specific region, such as a user-defined mask, die boundary, or die core, or for the entire imaging data set.

[0121] The quality of the wafer can be assessed based on one or more measurements and at least one quality assessment rule, e.g., according to DIN-ISO quality specifications that define the upper limit of tolerance for non-ideal wafers. For example, the density of a particular defect type in a die core can be less than 1 nm. 2 There should be less than 10 per

[0122] According to any one of the embodiments of the present invention, at least one wafer manufacturing process parameter may be controlled based on one or more measurements of defects recognized in an imaging data set of the wafer.

[0123] The present invention also relates to a computer readable medium having stored thereon a computer program executable by a computing device, the computer program including code for performing a method according to any of the embodiments of the present invention, the computer program including a data I / O driver for low latency hardware, a program for configuring the low latency hardware to perform image processing functions, a program for performing error checking, etc.

[0124] FIG. 15 schematically illustrates a system 212 that can be used to control the quality of wafers 226 manufactured in a semiconductor fabrication facility. The system 212 includes an imaging device 214 and a processing device 216. The imaging device 214 is coupled to the processing device 216. The imaging device 214 is configured to acquire an imaging dataset 12 of the wafer 226. The wafer 226 may include semiconductor structures, such as transistors, field-effect transistors, memory cells, and the like. An exemplary implementation of the imaging device 214 is an SEM or multi-beam SEM, a helium ion microscope (HIM), or a cross-beam device including a FIB and an SEM, or any charged particle beam imaging device. The processing device 216 is coupled to at least one embedded system 50 that includes a programmable memory 48.

[0125] The imaging device 214 can provide the imaging dataset 12 to a processing device 216. The processing device 216 includes a processor, for example, embodied as a CPU 218 or a GPU. The processor can receive the imaging dataset 12 via an interface 220. The processor can read program code from a memory 222. The processor can execute the program code. When executing the program code, the processor performs techniques such as those described herein, such as assessing wafer quality based on one or more measurements and at least one quality assessment rule, defect recognition, transferring model data to the programmable memory 48 of the embedded system 50, training the machine learning model 40, 40′, 40″, specifying the flow 74 of data through several local block circuits 72, 72′, 72″, 72′′, 76, 76′, 76″, 76′′ of the embedded system 50, 50′, applying the machine learning model 42 implemented on the embedded system 50, 50′ to the data, measuring the recognized defects 16, optimizing at least one image acquisition parameter, etc. For example, the processor can load program code from the memory 222 to execute the computer-implemented methods illustrated in Figures 2, 4, 10, 11, 12, and 13, respectively. The processing device 216 can optionally include a user interface 224 for receiving user input, such as defect measurement types, quality assessment rules, machine learning model parameters, etc. The processing device 216 can optionally include a display device 227 for displaying defect recognition results to a user, for example, in real time or buffered. The processing device 216 can also optionally include a database 225 for storing, for example, a set of machine learning models 40, 40', 40'', 40'', 40''', model architectures 42, or model data 44, 44', 44'', etc., of different trained machine learning models 40, 40', 40'', etc.

[0126] FIG. 16 schematically illustrates a system 228 that may be used to control the fabrication of wafers 226 in a semiconductor foundry. System 228 includes the same components as those illustrated in FIG. 15 , and the above description also applies to the respective components in this figure. Additionally, system 228 includes a means 230 for fabricating wafers 226 controlled by at least one wafer fabrication process parameter. To this end, imaging data set 12 is provided to processing device 216 using imaging device 214. A processor of processing device 216 is configured to perform one of the disclosed methods according to the first, second, or third embodiments of the present invention, which method includes controlling at least one wafer fabrication process parameter based on one or more measured characteristics of defects 16 recognized in imaging data set 12 of wafer 226. For example, a detected bridge defect 16 indicates insufficient etching so the amount of etching is increased, a detected open defect 16 indicates excessive etching so the amount of etching is decreased, consistently occurring anomalies or defects 16 indicate a faulty mask so the mask should be checked, and anomalies or defects 16 due to missing structures suggest non-ideal material deposition so the material deposition is altered.

[0127] 17 schematically illustrates a system 232 that may be used to control the quality of wafers 226 manufactured in a semiconductor fabrication facility. The system 232 includes an imaging device 214 and a processing device 216. The imaging device 214 is coupled to the processing device 216. The imaging device 214 is configured to acquire an imaging dataset 12 of the wafer 226. The wafer 226 may include semiconductor structures, e.g., transistors such as field-effect transistors, memory cells, etc. Exemplary implementations of the imaging device 214 are an SEM or multi-beam SEM, a helium ion microscope (HIM), or a cross-beam device including a FIB and an SEM, or any charged particle imaging device.

[0128] The imaging device 214 can provide the imaging dataset 12 to the processing device 216. The processing device 216 includes a processor, for example, embodied as a CPU 218 or a GPU. The processor can receive the imaging dataset 12 via an interface 220. The processor can load program code from a memory 222. The processor can execute the program code. When executing the program code, the processor performs techniques as described herein, such as defect recognition, measuring the recognized defects, and optimizing at least one image acquisition parameter together with a model architecture of a machine learning model, according to a fourth embodiment of the present invention. For example, upon loading the program code from the memory 222, the processor can execute the computer-implemented method illustrated in FIG. 14. The processing device 216 can optionally include a user interface 224 for receiving user input, such as the type of defect measurement, quality assessment rules, parameters of the machine learning model, etc. The processing device 216 can optionally include a display device 227 for displaying defect recognition results to a user, for example, in real time or buffered.

[0129] FIG. 18 schematically illustrates a system 234 that may be used to control the fabrication of wafers 226 in a semiconductor foundry. System 228 includes the same components as those illustrated in FIG. 17 , and the above description also applies to the respective components in this figure. Additionally, system 234 includes a means 230 for fabricating wafers 226 controlled by at least one wafer fabrication process parameter. To this end, imaging data set 12 is provided to processing device 216 using imaging device 214. A processor of processing device 216 is configured to perform one of the disclosed methods, including controlling at least one wafer fabrication process parameter based on one or more measured characteristics of defects 16 recognized in imaging data set 12 of wafer 226. For example, a detected bridge defect 16 indicates insufficient etching so the amount of etching is increased, a detected open defect 16 indicates excessive etching so the amount of etching is decreased, consistently occurring anomalies or defects 16 indicate a faulty mask so the mask should be checked, and anomalies or defects 16 due to missing structures suggest non-ideal material deposition so the material deposition is altered.

[0130] Embodiments, examples, and aspects of the present invention can be described by the following clauses.

[0131] 1. A computer-implemented method 22 for defect recognition in an imaging data set 12, 12', 12'' of a wafer 226 in a charged particle beam system 78 having an embedded system 50, 50', the method comprising: i. acquiring imaging data sets 12, 12', 12'' of a wafer 226; ii. acquiring model data 44, 44′, 44″ for a model architecture 42 of a machine learning model 40, 40′, 40″ for defect recognition in an imaging dataset 12, 12′, 12″ of a wafer 226, wherein the model architecture 42 is implemented in an embedded system 50, 50′; iii. transferring the model data 44, 44', 44'' to the programmable memory 48, 48', 48'' of the embedded system 50, 50'; iv. applying the machine learning model 40, 40', 40'' to the imaging data set 12, 12', 12'' of the wafer 226 to recognize the defects 16, including executing the embedded system-implemented model architecture 46 using the transferred model data 44, 44', 44''. 22. A computer-implemented method comprising:

[0132] 2. A computer-implemented method 52 for defect recognition in an imaging data set 12, 12', 12'' of a wafer 226 in a charged particle beam system 78 comprising at least one embedded system 50, 50', the method comprising: i. acquiring imaging data sets 12, 12', 12'' of a wafer 226; ii. defining an embedded system implementation model architecture 46 of a machine learning model 40, 40′, 40″ for defect recognition in an imaging dataset 12, 12′, 12″ of a plurality of logic block circuits 72, 72′, 72″, 72′′′, 74, 74′, 74″, 74′″ in one of the at least one embedded system 50, 50′, wherein the plurality of logic block circuits 72, 72′, 72″, 72′′′, 74, 74′, 74″, 74′″ includes one or more modules 102, 104 of the at least one model architecture 42 of the at least one machine learning model 40, 40′, 40″ for defect recognition; iii. Obtaining model data 44, 44', 44'' of the embedded system implementation model architecture 46; iv. transferring the model data 44, 44', 44'' to the programmable memory 48, 48', 48'' of the embedded system 50, 50'; v. applying the machine learning model 40, 40', 40'' to the imaging dataset 12, 12', 12'' of the wafer 226 to recognize the defects 16, including executing the embedded system-implemented model architecture 46 using the transferred model data 44, 44', 44''. 52. A computer-implemented method comprising:

[0133] 3. The computer-implemented method of claim 2, wherein at least one model architecture 42 of at least one machine learning model 40, 40', 40'' for defect recognition includes a model architecture 42 of a neural network 114.

[0134] 4. The computer-implemented method of claim 3, wherein one or more of the modules 102, 104 are head modules 116, 124, 126, and the head modules 116, 124, 126 are modules that include the output layer 120 of the neural network 114.

[0135] 5. The computer-implemented method of claim 4, wherein one or more head modules 116, 124, 126 include a fully connected output layer of the neural network 114 and / or a convolutional output layer of the neural network 114.

[0136] 6. The computer-implemented method of any one of paragraphs 3 to 5, wherein one or more modules 102, 104 are tail modules 118, 128, 130, 132, 134, 136, 138, and wherein the tail modules 118, 128, 130, 132, 134, 136, 138 are modules that include several hidden layers 122 of the neural network 114.

[0137] 7. The computer-implemented method of claim 6, wherein at least one tail module 118, 128, 130, 132, 134, 136, 138, and in particular each tail module 118, 128, 130, 132, 134, 136, 138, includes all hidden layers 122 of the neural network 114.

[0138] 8. The computer-implemented method of claim 6 or 7, wherein at least one tail module 118, 128, 130, 132, 134, 136, 138, in particular each tail module 118, 128, 130, 132, 134, 136, 138, includes several hidden layers 122 that form semantic entities.

[0139] 9. The computer-implemented method of any one of paragraphs 6 to 8, wherein at least two of the tail modules 118, 128, 130, 132, 134, 136, 138 include the same number of hidden layers 122, 123, and the feature map sizes of corresponding layers 129, 129', 131, 131', 133, 133' differ by the same multiple.

[0140] 10. The computer-implemented method of any one of paragraphs 3 to 9, wherein each module 102, 104 of the one or more modules 102, 104 is either a head module 116, 124, 126 including the output layer 120 of the neural network 114, or a tail module 118, 128, 130, 132, 134, 136, 138 including several hidden layers 122 of the neural network 114.

[0141] 11. The computer-implemented method of any one of paragraphs 3 to 10, wherein one or more modules 102, 104 are generated from at least one model architecture 42 of a neural network 114 by dividing each model architecture 42 into a head module 116, 124, 126 including the output layer 120 of the neural network 114 and at least one tail module 118, 128, 130, 132, 134, 136, 138 including several hidden layers 122 of the neural network 114.

[0142] 12. The computer-implemented method of claim 11, wherein each model architecture 42 of the neural network 114 is divided into a task-specific head module 116, 124, 126 and a single tail module 118, 128, 130, 132, 134, 136, 138.

[0143] 13. The computer-implemented method of any one of clauses 2 to 12, further comprising: before specifying the flow 74 of data through some of the logic block circuits 72', 72''' of the plurality of logic block circuits 72, 72', 72'', 72''', 74, 74', 74'', 74''', determining whether the model architecture 42 of the machine learning model 40, 40', 40'' can be realized by the plurality of logic block circuits 72, 72', 72'', 72''', 74, 74', 74'', 74''' in one of the at least one embedded system 50, 50'; and in response to determining that the model architecture 42 cannot be realized, generating one or more modules 102, 104 of the model architecture 42 of the machine learning model 40, 40', 40'', and implementing the one or more modules 102, 104 in one of the at least one embedded system 50, 50'.

[0144] 14. The computer-implemented method of any one of paragraphs 1 to 13, wherein the machine learning model 40, 40', 40'' for defect recognition is from the group including a defect detection model, a defect classification model, a defect localization model, a defect segmentation model, an anomaly detection model, an anomaly classification model, an anomaly localization model, an anomaly segmentation model.

[0145] 15. The computer-implemented method of any of paragraphs 1 to 14, wherein the model data 44, 44', 44'' of the embedded system-implemented model architecture 46 is obtained by training a machine learning model 40, 40', 40'' that includes the aforementioned model architecture.

[0146] 16. The computer-implemented method of any one of paragraphs 1 to 15, wherein the model data 44, 44', 44'' of the embedded system implementation model architecture 46 is read from a database 225.

[0147] 17. The computer-implemented method of any one of paragraphs 1 to 16, wherein the model data 44, 44', 44'' of the embedded system implementation model architecture 46 is provided by an external service.

[0148] 18. The computer-implemented method of any one of paragraphs 1 to 17, wherein the model data 44, 44', 44'' is transferred by copying to the programmable memory 48, 48', 48'' of the embedded system 50, 50'.

[0149] 19. The computer-implemented method of any one of paragraphs 1 to 18, wherein the model data 44, 44', 44'' is transferred to the programmable memory 48, 48', 48'' of the embedded system 50, 50' by replacing the hardware block containing the programmable memory 48, 48', 48'' of the embedded system 50, 50' with a new hardware block containing the transferred model data 44, 44', 44''.

[0150] 20. The computer-implemented method 22, 52 of any one of paragraphs 1 to 19, wherein the recognized defects 16 are directed to a display device 227 or dashboard.

[0151] 21. The computer-implemented method of any one of paragraphs 1 to 20, wherein the recognized defects 16 are stored in long-term memory.

[0152] 22. The computer-implemented method of any one of paragraphs 1 to 21, wherein the recognized defects 16 are cached in memory.

[0153] 23. The computer-implemented method of any one of paragraphs 1 to 22, wherein the recognized defects 16 are analyzed to update the embedded system implementation model architecture 46 in step ii.

[0154] 24. The computer-implemented method of any one of paragraphs 1 to 23, wherein the embedded system 50, 50' is a field programmable gate array 51.

[0155] 25. Before acquiring the wafer imaging data sets 12, 12', 12'' in step i, - Until the convergence criterion is met, selecting at least one image acquisition parameter according to an imaging sampling strategy and acquiring an imaging data set 12, 12′, 12″ of the wafer 226 based on said at least one image acquisition parameter; generating training data from the acquired imaging data set 12, 12′, 12″ of the wafer 226; selecting a model architecture 42 and training an associated machine learning model 40, 40', 40'' based on the generated training data; determining the quality of the model architecture 42 and at least one image acquisition parameter by calculating an associated objective function value of an objective function that evaluates the quality of the trained machine learning model 40, 40′, 40″; repeating the steps of: - selecting one of the model architectures 42 and corresponding at least one image acquisition parameter based on the objective function value. further comprising The computer-implemented method 182 described in any one of paragraphs 1 to 24, wherein the imaging dataset 12, 12', 12'' of the wafer 226 in step i is acquired based on at least one selected image acquisition parameter, and the embedded system-implemented model architecture 46 in step ii includes the model architecture 42 of the selected machine learning model 40, 40', 40''.

[0156] 26. The computer-implemented method of paragraph 25, wherein the step of selecting a model architecture 42 includes selecting at least one hyperparameter that defines the model architecture 42 of the machine learning model 40, 40', 40'' according to an architecture sampling strategy.

[0157] 27. The computer-implemented method of claim 26, wherein the objective function includes a measure of the complexity of the model architecture 42.

[0158] 28. The computer-implemented method of any one of clauses 25 to 27, wherein the objective function includes an execution time measure, and / or a throughput and / or data rate measure, and / or a power consumption measure.

[0159] 29. The computer-implemented method of any one of paragraphs 25 to 28, wherein the objective function includes a measure of quality of defect recognition.

[0160] 30. The computer-implemented method of any one of paragraphs 25 to 29, wherein at least one image acquisition parameter is from the group including imaging time, image resolution, pixel size, electron wave landing energy and dwell time.

[0161] 31. The computer-implemented method of any one of paragraphs 25 to 30, wherein the objective function includes a measure of the amount of bits of input data for the machine learning model 40, 40', 40''.

[0162] 32. A computer-implemented method 196 for defect recognition in an imaging data set 12, 12', 12'' of a wafer 226, the method comprising: - Until the convergence criterion is met, selecting at least one image acquisition parameter according to an imaging sampling strategy and acquiring an imaging data set 12, 12′, 12″ of the wafer 226 based on said at least one image acquisition parameter; generating training data from the acquired imaging data set 12, 12′, 12″ of the wafer 226; selecting a model architecture 42 and training an associated machine learning model 40, 40', 40'' based on the generated training data; ·Evaluating the quality of the trained machine learning model 40, 40′, 40″ by calculating the associated objective function value of the objective function; Repeating the steps, - selecting one of the trained machine learning models 40, 40', and 40'' based on an objective function value; applying the selected trained machine learning model 40, 40', 40'' to the imaging data set 12, 12', 12'' of the wafer 226 acquired based on the corresponding at least one image acquisition parameter to recognize the defect 16. 196. A computer-implemented method comprising:

[0163] 33. The computer-implemented method of paragraph 32, wherein the step of selecting a model architecture 42 includes selecting at least one hyperparameter that defines the model architecture 42 of the machine learning model 40, 40', 40'' according to an architecture sampling strategy.

[0164] 34. The computer-implemented method of paragraph 33, wherein the objective function includes a measure of the complexity of the model architecture 42.

[0165] 35. The computer-implemented method of any one of paragraphs 32 to 34, wherein the objective function includes a measure of execution time, and / or a measure of throughput and / or data rate, and / or a measure of power consumption during defect recognition.

[0166] 36. The computer-implemented method of any one of paragraphs 32 to 35, wherein the objective function includes a measure of quality of defect recognition.

[0167] 37. The computer-implemented method of any one of paragraphs 32 to 36, wherein at least one image acquisition parameter is from the group including imaging time, image resolution, pixel size, electron wave landing energy and dwell time.

[0168] 38. The computer-implemented method of any one of paragraphs 32 to 37, wherein the objective function includes a measure of the amount of bits of the input to the machine learning model 40, 40', 40''.

[0169] 39. The computer-implemented method of any one of paragraphs 1 to 31, further comprising determining one or more measurements of defects 16 recognized in the imaging data set 12, 12', 12'' of the wafer 226, in particular the size, area, dimensions, shape parameters, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of defects, etc.

[0170] 40. The computer-implemented method of clause 39, further comprising assessing the quality of the wafer 226 based on the one or more measurements and at least one quality assessment rule.

[0171] 41. The computer-implemented method of claim 39, further comprising controlling at least one wafer manufacturing process parameter based on one or more measurements of defects recognized in the imaging data set of the wafer.

[0172] 42. The computer-implemented method of any one of paragraphs 32 to 38, further comprising determining one or more measurements of defects 16 recognized in the imaging data set 12, 12', 12'' of the wafer 226, in particular the size, area, dimensions, shape parameters, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of defects, presence of defects, etc.

[0173] 43. The computer-implemented method of clause 42, further comprising assessing the quality of the wafer 226 based on the one or more measurements and at least one quality assessment rule.

[0174] 44. The computer-implemented method of claim 42, further comprising controlling at least one wafer manufacturing process parameter based on one or more measurements of defects 16 recognized in the imaging data set 12, 12', 12'' of the wafer 226.

[0175] 45. A computer-readable medium storing a computer program executable by a computing device, the computer program comprising code for performing the method of any one of clauses 1 to 44.

[0176] 46. ​​A computer program product containing instructions that, when executed by a computer, cause the computer to perform the method of any one of paragraphs 1 to 44.

[0177] 47. A system 212 for controlling the quality of wafers 226 manufactured in a semiconductor manufacturing facility, comprising: an imaging device 214 adapted to provide imaging data sets 12, 12', 12'' of a wafer 226; one or more processing devices 216; at least one embedded system 50, 50', - one or more machine-readable hardware storage devices containing instructions executable by one or more processing devices 216 to perform operations including the method of clause 40; The system 212 includes:

[0178] 48. A system 228 for controlling the production of wafers 226 in a semiconductor fabrication factory, comprising: - means 230 for manufacturing wafers 226 controlled by at least one manufacturing process parameter; an imaging device 214 adapted to provide imaging data sets 12, 12', 12'' of a wafer 226; one or more processing devices 216; at least one embedded system 50, 50', - one or more machine-readable hardware storage devices containing instructions executable by one or more processing devices 216 to perform operations including the method of clause 41; The system 228 includes:

[0179] 49. The system 212, 228 of paragraph 47 or 48, further comprising a database 225.

[0180] 50. A system 232 for controlling the quality of wafers 226 manufactured in a semiconductor manufacturing facility, comprising: an imaging device 214 adapted to provide imaging data sets 12, 12', 12'' of a wafer 226; one or more processing devices 216; - one or more machine-readable hardware storage devices containing instructions executable by one or more processing devices 216 to perform operations including the method of paragraph 43; The system 232 includes:

[0181] 51. A system 234 for controlling the production of wafers 226 in a semiconductor fabrication factory, comprising: - means 230 for manufacturing wafers 226 controlled by at least one manufacturing process parameter; an imaging device 214 adapted to provide imaging data sets 12, 12', 12'' of a wafer 226; one or more processing devices 216; - one or more machine-readable hardware storage devices containing instructions executable by one or more processing devices 216 to perform operations including the method of clause 44; The system 234 includes:

[0182] 52. The system 212, 228, 232, 234 described in any one of paragraphs 47 to 51, further comprising a display device 227.

[0183] 53. The system 212, 228, 232, 234 described in any one of paragraphs 47 to 52, further comprising a user interface 224. [Explanation of symbols]

[0184] 10, 10', 10'' cell structure 12, 12', 12'' imaging dataset 14, 14', 14'' cells 16 Defects 22 Computer-Implemented Methods 26 Imaging Steps 28 Model Data Step 30 Model Data Transfer Steps 32 Application Steps 34 New Use Cases 40, 40', 40'' machine learning model 42 Model Architecture 44, 44', 44'' model data 46 Embedded Systems Implementation Model Architecture 48, 48', 48'' programmable memory 50, 50' Embedded Systems 51 Field Programmable Gate Array 52 Computer-Implemented Methods 56 Imaging Steps 58 Data flow specification step 60 Model Data Steps 62 Model Data Transfer Step 64 Application Steps 66 New Use Cases 72, 72', 72'', 72'''' Logic block circuit 74 Data Flow 76, 76', 76'', 76'''' Logic block circuit 78 Charged Particle Beam System 80 Adaptive Logic Module 82 M512 Block 84 M4K blocks 86 high-speed I / O channels including Dynamic Phase Alignment (DPA) 88 I / O channels including external memory interface circuitry 90 Digital Signal Processing Blocks 92 M-RAM blocks 94 Phase Locked Loop 96 Programmable Memory 98 input data bus 100 weight 102 First Module 104 Second Module 106 Configuration Memory 108 Multiplexer 110 Multiplication 112 Addition 114 Neural Networks 116 Head Module 118 Tail Module 120 output layer 122 Hidden Layer 123 Last Hidden Layer 124 Head Module 126 Head Module 128 Tail Module 129, 129' corresponding first layer 130 Tail Module 131, 131' corresponding second layer 132 Tail Module 133, 133' corresponding third layer 134 Tail Module 136 Tail Module 138 Tail Module 142 Start 144 Group Determination 146 Determine Use Cases 148 Problem Input Steps 150 data acquisition and training steps 152 Model data saving step 154 Use Case Collection Steps 156 Model Architecture Definition Steps 158 Feasibility Steps 160 Model Implementation Steps 162 Model Data Search Step 164 Model Data Transfer Step 166 Data Processing System 168 Stop 170 Yes 172 No 174 Yes 176 No 178 Yes 180 No 182 Computer-Implemented Methods 184 Image Acquisition Parameter Steps 186 Training data generation step 188 Machine Learning Model Training Steps 190 Quality Evaluation Steps 192 Selection Steps 194 repetitions 196 Computer-Implemented Methods 198 Image Acquisition Parameter Steps 200 training data generation steps 202 Machine Learning Model Training Steps 204 Quality Evaluation Steps 206 Selection Step 208 Application Steps 210 iterations 212 System 214 Imaging Devices 216 Processing Device 218 CPU 220 Interface 222 memory 224 User Interface 225 databases 226 wafers 227 Display Devices 228 System 230 means 232 System 234 System

Claims

1. 1. A computer-implemented method (22) for defect recognition in an imaging dataset (12, 12', 12'') of a wafer (226) in a charged particle beam system (78) having an embedded system (50, 50'), the method comprising: i. acquiring an imaging data set (12, 12', 12'') of the wafer (226); ii. acquiring model data (44, 44', 44'') for a model architecture (42) of a machine learning model (40, 40', 40'') for defect recognition in the imaging dataset (12, 12', 12'') of the wafer (226), wherein the model architecture (42) is implemented in the embedded system (50, 50'); iii. Transferring the model data (44, 44', 44'') to a programmable memory (48, 48', 48'') of the embedded system (50, 50'); iv. applying the machine learning model (40, 40', 40'') to the imaging data set (12, 12', 12'') of the wafer (226) to recognize defects (16), including executing the embedded system-implemented model architecture (46) using the transferred model data (44, 44', 44''). A computer-implemented method (22) comprising:

2. 1. A computer-implemented method (52) for defect recognition in an imaging dataset (12, 12', 12'') of a wafer (226) in a charged particle beam system (78) comprising at least one embedded system (50, 50'), the method comprising: i. acquiring an imaging data set (12, 12', 12'') of the wafer (226); ii. defining an embedded system implementation model architecture (46) of a machine learning model (40, 40', 40") for defect recognition in the imaging dataset (12, 12', 12") of the wafer (226) by specifying a data flow (74) through some logic block circuits (72', 72'") of a plurality of logic block circuits (72, 72', 72", 72'", 74, 74', 74", 74'") in one of the at least one embedded system (50, 50'), wherein the plurality of logic block circuits (72, 72', 72", 72'", 74, 74', 74", 74'") includes one or more modules (102, 104) of at least one model architecture (42) of the at least one machine learning model (40, 40', 40") for defect recognition; iii. Obtaining model data (44, 44', 44'') of the embedded system implementation model architecture (46); iv. transferring said model data (44, 44', 44'') to a programmable memory (48, 48', 48'') of said embedded system (50, 50'); v. applying the machine learning model (40, 40', 40'') to the imaging data set (12, 12', 12'') of the wafer (226) to recognize defects (16), including executing the embedded system-implemented model architecture (46) using the transferred model data (44, 44', 44''). A computer-implemented method (52) comprising:

3. 3. The computer-implemented method of claim 2, wherein the at least one model architecture (42) of the at least one machine learning model (40, 40', 40'') for defect recognition comprises a model architecture (42) of a neural network (114).

4. 4. The computer-implemented method of claim 3, wherein one or more of the modules (102, 104) is a head module (116, 124, 126), the head module (116, 124, 126) being a module that includes an output layer (120) of the neural network (114).

5. 5. The computer-implemented method of claim 4, wherein the one or more head modules (116, 124, 126) comprise a fully connected output layer of a neural network (114) and / or a convolutional output layer of a neural network (114).

6. 6. The computer-implemented method of claim 3, wherein one or more of the modules (102, 104) are tail modules (118, 128, 130, 132, 134, 136, 138), and the tail modules (118, 128, 130, 132, 134, 136, 138) are modules that include several hidden layers (122) of the neural network (114).

7. 7. The computer-implemented method of claim 6, wherein at least one tail module (118, 128, 130, 132, 134, 136, 138), in particular each tail module (118, 128, 130, 132, 134, 136, 138), comprises all hidden layers (122) of the neural network (114).

8. 8. The computer-implemented method of claim 6 or 7, wherein at least one tail module (118, 128, 130, 132, 134, 136, 138), in particular each tail module (118, 128, 130, 132, 134, 136, 138), comprises several hidden layers (122) forming semantic entities.

9. 9. The computer-implemented method of claim 6, wherein at least two of the tail modules (118, 128, 130, 132, 134, 136, 138) include the same number of hidden layers (122, 123), and the sizes of the feature maps of corresponding layers (129, 129', 131, 131', 133, 133') differ by the same multiple.

10. 10. The computer-implemented method of claim 3, wherein each module (102, 104) of the one or more modules (102, 104) is either a head module (116, 124, 126) including an output layer (120) of a neural network (114) or a tail module (118, 128, 130, 132, 134, 136, 138) including several hidden layers (122) of the neural network (114).

11. 11. The computer-implemented method of claim 3, wherein the one or more modules (102, 104) are generated from at least one model architecture (42) of the neural network (114) by dividing each model architecture (42) into a head module (116, 124, 126) containing an output layer (120) of the neural network (114) and at least one tail module (118, 128, 130, 132, 134, 136, 138) containing several hidden layers (122) of the neural network (114).

12. 12. The computer-implemented method of claim 11, wherein each model architecture (42) of the neural network (114) is divided into a task-specific head module (116, 124, 126) and a single tail module (118, 128, 130, 132, 134, 136, 138).

13. Before specifying the flow of data (74) through the some of the logic block circuits (72', 72'") among the plurality of logic block circuits (72, 72', 72'', 72''', 74, 74', 74'', 74''', the model architecture (42) of the machine learning model (40, 40', 40'') is configured to be executed by the plurality of logic block circuits (72, 72', 72'', 72''', 74, 74', 74'', 74''') in one of the at least one embedded system (50, 50'). and, in response to determining that the model architecture (42) cannot be realized, generating one or more modules (102, 104) of the model architecture (42) of the machine learning model (40, 40′, 40″) and implementing the one or more modules (102, 104) on one of the at least one embedded system (50, 50′).

14. The computer-implemented method of any one of claims 1 to 13, wherein the machine learning model (40, 40', 40'') for defect recognition is from the group comprising: a defect detection model, a defect classification model, a defect localization model, a defect segmentation model, an anomaly detection model, an anomaly classification model, an anomaly localization model, an anomaly segmentation model.

15. 15. The computer-implemented method of claim 1, wherein the model data (44, 44', 44'') of the embedded system-implemented model architecture (46) is obtained by training a machine learning model (40, 40', 40'') that includes the model architecture.

16. The computer-implemented method of any one of claims 1 to 15, wherein the model data (44, 44', 44'') of the embedded system implementation model architecture (46) is read from a database (225).

17. The computer-implemented method of any one of claims 1 to 16, wherein the model data (44, 44', 44'') of the embedded system implementation model architecture (46) is provided by an external service.

18. The computer-implemented method of any one of claims 1 to 17, wherein the model data (44, 44', 44'') is transferred to the programmable memory (48, 48', 48'') of the embedded system (50, 50') by copying.

19. 19. The computer-implemented method of claim 1, wherein the model data is transferred to the programmable memory of the embedded system by replacing the hardware block containing the programmable memory of the embedded system with a new hardware block containing the model data to be transferred.

20. The computer-implemented method (22, 52) of any one of claims 1 to 19, wherein the recognized defects (16) are directed to a display device (227) or a dashboard.

21. The computer-implemented method of any one of claims 1 to 20, wherein the recognized defects (16) are stored in a long-term memory.

22. The computer-implemented method of any one of claims 1 to 21, wherein the recognized defects (16) are cached in a memory.

23. The computer-implemented method of any one of claims 1 to 22, wherein in step (ii) the identified defects (16) are analyzed to update the embedded system implementation model architecture (46).

24. The computer-implemented method of any one of claims 1 to 23, wherein the embedded system (50, 50') is a field programmable gate array (51).

25. Before acquiring the imaging data sets (12, 12', 12'') of the wafer in step (i), - until the convergence criterion is met, selecting at least one image acquisition parameter according to an imaging sampling strategy and acquiring an imaging data set (12, 12', 12'') of the wafer (226) based on said at least one image acquisition parameter; generating training data from the acquired imaging data sets (12, 12', 12'') of the wafer (226); Selecting a model architecture (42) and training an associated machine learning model (40, 40', 40'') based on the generated training data; determining the quality of the model architecture (42) and the at least one image acquisition parameter by calculating an associated objective function value of an objective function that assesses the quality of the trained machine learning model (40, 40', 40''); repeating the steps of: - selecting one of said model architectures (42) and said corresponding at least one image acquisition parameter based on said objective function value. further comprising 25. The computer-implemented method of claim 1, wherein the imaging dataset of the wafer in step (i) is acquired based on the selected at least one image acquisition parameter, and the embedded system-implemented model architecture in step (ii) includes the model architecture of the selected machine learning model.

26. 26. The computer-implemented method of claim 25, wherein selecting a model architecture (42) comprises selecting at least one hyperparameter that defines the model architecture (42) of the machine learning model (40, 40', 40'') according to an architecture sampling strategy.

27. 27. The computer-implemented method of claim 26, wherein the objective function comprises a measure of complexity of the model architecture (42).

28. A computer-implemented method according to any one of claims 25 to 27, wherein the objective function comprises an execution time measure, and / or a throughput and / or data rate measure, and / or a power consumption measure.

29. The computer-implemented method of any one of claims 25 to 28, wherein the objective function comprises a measure of the quality of the defect recognition.

30. 30. The computer-implemented method of any one of claims 25 to 29, wherein the at least one image acquisition parameter is from the group comprising imaging time, image resolution, pixel size, electron wave landing energy and dwell time.

31. The computer-implemented method of any one of claims 25 to 30, wherein the objective function comprises a measure of the amount of bits of the input data of the machine learning model (40, 40', 40'').

32. 1. A computer-implemented method (196) for defect recognition in an imaging dataset (12, 12', 12'') of a wafer (226), the method comprising: - until the convergence criterion is met, selecting at least one image acquisition parameter according to an imaging sampling strategy and acquiring an imaging data set (12, 12', 12'') of the wafer (226) based on said at least one image acquisition parameter; generating training data from the acquired imaging data sets (12, 12', 12'') of the wafer (226); Selecting a model architecture (42) and training an associated machine learning model (40, 40', 40'') based on the generated training data; assessing the quality of the trained machine learning model (40, 40', 40'') by calculating an associated objective function value of an objective function; Repeating the steps, - selecting one of said trained machine learning models (40, 40', 40'') based on said objective function value; applying the selected trained machine learning model (40, 40', 40'') to an imaging dataset (12, 12', 12'') of the wafer (226) acquired based on the corresponding at least one image acquisition parameter to recognize defects (16). A computer-implemented method (196) comprising:

33. 33. The computer-implemented method of claim 32, wherein the step of selecting a model architecture (42) comprises selecting at least one hyperparameter that defines the model architecture (42) of the machine learning model (40, 40', 40'') according to an architecture sampling strategy.

34. 34. The computer-implemented method of claim 33, wherein the objective function comprises a measure of complexity of the model architecture (42).

35. The computer-implemented method of any one of claims 32 to 34, wherein the objective function comprises a measure of execution time, and / or a measure of throughput and / or data rate, and / or a measure of power consumption during defect recognition.

36. The computer-implemented method of any one of claims 32 to 35, wherein the objective function comprises a measure of the quality of the defect recognition.

37. 37. The computer-implemented method of any one of claims 32 to 36, wherein the at least one image acquisition parameter is from the group comprising imaging time, image resolution, pixel size, electron wave landing energy and dwell time.

38. The computer-implemented method of any one of claims 32 to 37, wherein the objective function comprises a measure of the bit amount of the input to the machine learning model (40, 40', 40'').

39. 32. The computer-implemented method of claim 1, further comprising determining one or more measurements of the recognized defects (16) in the imaging data set (12, 12', 12'') of the wafer (226), in particular size, area, dimensions, shape parameters, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of defects, etc.

40. 40. The computer-implemented method of claim 39, further comprising assessing the quality of the wafer (226) based on the one or more measurements and at least one quality assessment rule.

41. 40. The computer-implemented method of claim 39, further comprising controlling at least one wafer manufacturing process parameter based on one or more measurements of the recognized defects in the imaging data set of the wafer.

42. 39. The computer-implemented method of any one of claims 32 to 38, further comprising determining one or more measurements of the recognized defects (16) in the imaging data set (12, 12', 12'') of the wafer (226), in particular size, area, dimensions, shape parameters, distance, radius, aspect ratio, type, number of defects, density, spatial distribution of defects, presence of defects, etc.

43. 43. The computer-implemented method of claim 42, further comprising assessing the quality of the wafer (226) based on the one or more measurements and at least one quality assessment rule.

44. 43. The computer-implemented method of claim 42, further comprising controlling at least one wafer manufacturing process parameter based on one or more measurements of the recognized defects (16) in the imaging data set (12, 12', 12'') of the wafer (226).

45. A computer readable medium storing a computer program executable by a computing device, said computer program comprising code for performing the method of any one of claims 1 to 44.

46. A computer program product comprising instructions which, when the program is executed by a computer, cause the computer to perform the method of any one of claims 1 to 44.

47. A system (212) for controlling the quality of wafers (226) manufactured in a semiconductor manufacturing facility, comprising: an imaging device (214) adapted to provide an imaging data set (12, 12', 12'') of the wafer (226); one or more processing devices (216); at least one embedded system (50, 50'), - one or more machine-readable hardware storage devices containing instructions executable by one or more processing devices (216) to perform operations including the method of claim 40; A system (212) comprising:

48. 1. A system (228) for controlling the fabrication of wafers (226) in a semiconductor fabrication factory, comprising: means (230) for manufacturing wafers (226) controlled by at least one manufacturing process parameter; an imaging device (214) adapted to provide an imaging data set (12, 12', 12'') of the wafer (226); one or more processing devices (216); at least one embedded system (50, 50'), - one or more machine-readable hardware storage devices containing instructions executable by one or more processing devices (216) to perform operations including the method of claim 41; A system (228) comprising:

49. 49. The system (212, 228) of claim 47 or 48, further comprising a database (225).

50. A system (232) for controlling the quality of wafers (226) manufactured in a semiconductor manufacturing facility, comprising: an imaging device (214) adapted to provide an imaging data set (12, 12', 12'') of the wafer (226); one or more processing devices (216); - one or more machine-readable hardware storage devices containing instructions executable by one or more processing devices (216) to perform operations including the method of claim 43; A system (232) comprising:

51. 1. A system (234) for controlling the fabrication of wafers (226) in a semiconductor fabrication factory, comprising: means (230) for manufacturing wafers (226) controlled by at least one manufacturing process parameter; an imaging device (214) adapted to provide an imaging data set (12, 12', 12'') of the wafer (226); one or more processing devices (216); - one or more machine-readable hardware storage devices containing instructions executable by one or more processing devices (216) to perform operations including the method of claim 44; A system (234) comprising:

52. The system (212, 228, 232, 234) of any one of claims 47 to 51, further comprising a display device (227).

53. The system (212, 228, 232, 234) of any one of claims 47 to 52, further comprising a user interface (224).

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