Dielectric-on-dielectric selective deposition using aniline passivation

Abstract

The method includes forming a conductive material on a first dielectric layer, exposing the conductive material to aniline to create a passivated surface of the conductive material, and, after exposing the conductive material to aniline, forming a second dielectric layer on the first dielectric layer using a deposition process, wherein the deposition process is a waterless, plasmaless deposition process, and the second dielectric layer is not formed on the passivated surface of the conductive material.

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate generally to the fabrication of electronic devices. In particular, embodiments of the present disclosure relate to selective dielectric-on-dielectric (DoD) deposition using aniline passivation. [Background technology]

[0002] An electronic device manufacturing apparatus may include multiple chambers, such as process chambers and load lock chambers. Such an electronic device manufacturing apparatus may employ a robotic device in a transfer chamber configured to transfer substrates between the multiple chambers. In some cases, multiple substrates are transferred together. In an electronic device manufacturing apparatus, a process chamber may be used to perform one or more processes on a substrate, such as a deposition process and an etching process. Many processes involve flowing gases through the process chamber. Summary of the Invention [Problem to be solved by the invention]

[0003] Electronic devices, such as semiconductor devices, are fabricated by performing a series of operations, which may include deposition, oxidation, photolithography, ion implantation, etching, etc., to form multiple patterned layers. It is often beneficial to align features between layers. Misalignment of features (e.g., due to limitations in lithography and / or patterning) can sometimes lead to short circuits and / or capacitive coupling, for example, between vias and underlying metal lines. Such short circuits and / or capacitive coupling can impair the functionality of the fabricated electronic device. [Means for solving the problem]

[0004] According to one embodiment, a method is provided that includes forming a conductive material on a first dielectric layer, exposing the conductive material to aniline to create a passivated surface of the conductive material, and, after exposing the conductive material to aniline, forming a second dielectric layer on the first dielectric layer using a deposition process, wherein the deposition process is a water-free, plasma-free deposition process, and the second dielectric layer is not formed on the passivated surface of the conductive material.

[0005] According to one embodiment, a system is provided. The system includes a passivation chamber for exposing a conductive material to aniline to generate a passivated surface of the conductive material. The conductive material is formed on a first dielectric layer disposed on a substrate. The system further includes a deposition chamber for forming a second dielectric layer on the first dielectric layer using a deposition process after exposing the conductive material to aniline. The deposition process is a water-free, plasma-free deposition process, and the second dielectric layer is not formed on the passivated surface of the conductive material.

[0006] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to like elements. It should be noted that different references to "an" or "one" embodiment in this disclosure are not necessarily to the same embodiment, and such references mean at least one. [Brief explanation of the drawings]

[0007] [Figure 1A] 1A-1C are cross-sectional views illustrating an exemplary method of forming a device using aniline passivation to perform dielectric-on-dielectric (DoD) selective deposition, according to some embodiments. [Figure 1B] 1A-1C are cross-sectional views illustrating an exemplary method of forming a device using aniline passivation to perform dielectric-on-dielectric (DoD) selective deposition, according to some embodiments. [Figure 1C]1A-1C are cross-sectional views illustrating an exemplary method of forming a device using aniline passivation to perform dielectric-on-dielectric (DoD) selective deposition, according to some embodiments. [Figure 1D] 1A-1C are cross-sectional views illustrating an exemplary method of forming a device using aniline passivation to perform dielectric-on-dielectric (DoD) selective deposition, according to some embodiments. [Figure 2A] 1 is a flow diagram of an exemplary method for performing dielectric-on-dielectric (DoD) selective deposition using aniline passivation, according to some embodiments. [Figure 2B] 1 is a flow diagram of an exemplary method for performing dielectric-on-dielectric (DoD) selective deposition using aniline passivation, according to some embodiments. [Figure 3] FIG. 1 is a block diagram of an exemplary electronic device processing system that can be used to perform dielectric-on-dielectric (DoD) selective deposition using aniline passivation, according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0008] The embodiments described herein relate to dielectric-on-dielectric (DoD) selective deposition using aniline passivation. An electronic device may include a dielectric material and a conductive material. For example, the electronic device may include a dielectric layer and several conductive lines disposed within the dielectric layer. More specifically, the electronic device may include several metallization levels, each including a respective set of conductive lines, and each pair of metallization levels separated by a respective dielectric layer (e.g., an interlevel dielectric (ILD) layer). Each conductive line may be formed within a respective trench.

[0009] The electronic device may further include several vias. A via refers to an electrical connection or contact between conductive lines within an electronic device. Each via may serve as a respective interconnection between at least two metallization levels. For example, a through via is a via that is exposed at both ends of the device (i.e., a through via is formed through each metallization level from the top of the device to the bottom of the device). As another example, a buried via is a via that is not exposed at either end of the device (i.e., a buried via serves as an interconnection between internal metallization levels). As yet another example, a blind via is a via that is exposed at one end of the device.

[0010] Electronic device processing techniques can include performing patterning (e.g., photolithography). For example, patterning can include multiple iterative processes of deposition and etching, such as wet etching or dry etching (e.g., plasma etching), using a photomask ("mask") and a resist film. Illustratively, conductive lines and vias can be formed using an appropriate patterning process. For example, conductive lines and vias can be formed using a single damascene process in which the conductive lines and vias are formed sequentially. As another example, conductive lines and vias can be formed using a dual damascene process in which the conductive lines and vias can be formed simultaneously (e.g., by simultaneously filling both the via hole and the trench with a conductive material). The conductive lines and vias can be formed from any suitable conductive material (e.g., a metal). Examples of suitable conductive materials that can be used to form the conductive lines and vias include copper (Cu), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), etc.

[0011] As electronic device sizes shrink (e.g., as transistor sizes shrink), process variations can occur during lithography / patterning (e.g., nanoscale patterning). One example of a process variation is mask misalignment between the mask and the patterned substrate. During exposure, mask misalignment can result in edge placement error, which is equal to the distance between the target location of a feature's edge and the actual location of the feature's edge. Edge placement error can cause detrimental effects such as shorts, increased resistance, and capacitive coupling that can lead to reduced device performance.

[0012] Illustratively, mask misalignment can lead to via misalignment during via patterning, resulting in at least one via being patterned out of alignment with respect to the conductive lines. For example, an aligned via is one whose edge is substantially correctly positioned on the corresponding conductive line (e.g., the via is centered with respect to the conductive line). However, mask misalignment during via patterning can result in edge placement errors for the via edges (e.g., the via edge can be formed in a portion of the dielectric layer in the area between its corresponding conductive line and another adjacent conductive line).

[0013] Via misalignment can lead to shorts or capacitive coupling between the via and adjacent conductive lines, which can be a function of the horizontal spacing between the via and adjacent conductive lines (e.g., the distance between the bottom surface of the via and the top surface of the adjacent conductive line). The effects of via misalignment can become more pronounced as transistor sizes become smaller (e.g., on the nanometer (nm) scale). Therefore, as transistor sizes shrink further, it becomes important to maintain a minimum amount of spacing to prevent shorts or capacitive coupling due to process variations that result in via misalignment.

[0014] One example of a method that can be used to address via misalignment is the conductive line recess method. During the conductive line recess method, trenches in a dielectric layer are filled with a conductive material (e.g., metal) to form conductive lines, and then an etching process can be used to recess the conductive lines to a specific depth within each trench. Vias can then be formed such that the top surface of each conductive line is located below the top surface of the dielectric layer. Therefore, if a via formed on a conductive line is a misaligned via, the edge of the misaligned via can be formed on the dielectric layer and located a certain distance above the top surface of the adjacent conductive line. This allows the misaligned via and the adjacent conductive line (e.g., the bottom surface of the misaligned via and the top surface of the adjacent conductive line) to be separated by a diagonal spacing. The diagonal spacing is a function of the horizontal spacing and the vertical distance between the misaligned via and the adjacent conductive line. That is, the diagonal spacing is longer than the horizontal spacing, which may help prevent short circuits or capacitive coupling. However, the conductive line recess method has several drawbacks. For example, conductive line recessing methods can exhibit poor uniformity across the wafer and across different pitch sizes, high surface roughness of the conductive lines, and material degradation.

[0015] Another example of a method that can be used to address process variations such as via misalignment is the dielectric-on-dielectric (DoD) method. The DoD method utilizes a selective dielectric material deposition approach that can, for example, increase the spacing between a misaligned via and an adjacent conductive line. More specifically, after a trench in a first dielectric layer (e.g., a first ILD) is filled with a conductive material (e.g., a metal) to form a conductive line, a second dielectric layer can be selectively deposited on the exposed surface of the first dielectric layer. The second dielectric layer can be formed to a height comparable to the depth achieved during the recess method described above. Similar to the recess method, if a via formed on a conductive line is a misaligned via, the edge of the misaligned via can be formed on the second dielectric layer and positioned a distance above the adjacent conductive line. Similar to the recess method, the DoD method can separate the misaligned via and the adjacent conductive line by a diagonal spacing that is longer than the horizontal spacing, thus helping to prevent shorting or capacitive coupling.

[0016] The first dielectric layer can comprise any suitable dielectric material. In some embodiments, the first dielectric layer can comprise an oxide. In some embodiments, the first dielectric layer can comprise a nitride. Examples of suitable dielectric materials that can be used to form the first dielectric layer include silicon dioxide (SiO), carbon-doped silicon oxide (e.g., SiOC, SiCOH), silicon nitride (SiN), etc. The second dielectric layer can comprise any suitable dielectric material. In some embodiments, the second dielectric layer can comprise an oxide. Examples of suitable dielectric materials that can be used to form the second dielectric layer include hafnium dioxide (HfO), titanium dioxide (TiO), aluminum oxide (AlO), SiO, etc.

[0017] To implement the dielectric layer formation method, a second dielectric layer can be selectively deposited on a first dielectric layer in preference to a conductive material (e.g., Cu, W, Co, Mo, or Ru). Selectivity can be defined, for example, as the ratio of the film thickness (e.g., the second dielectric layer thickness) on a target surface (e.g., the first dielectric layer) to the film thickness on a non-target surface (e.g., the conductive material). Other definitions of selectivity can be used.

[0018] Some selective deposition processes can use atomic layer deposition (ALD) processes. Some ALD processes can use water (HO) as an oxidant. However, ALD processes using water as an oxidant may not be compatible with embodiments in which the first dielectric layer comprises a porous hydrophobic dielectric material (e.g., SiCOH). Furthermore, some ALD processes use plasma during film deposition (i.e., plasma-enhanced ALD processes). However, like water, ALD processes using plasma may not be compatible with embodiments in which the first dielectric layer comprises a porous hydrophobic dielectric material (e.g., SiCOH).

[0019] To address these and other shortcomings, embodiments described herein can enable dielectric-on-dielectric (DoD) selective deposition using aniline passivation. More specifically, embodiments described herein can achieve selective deposition of a dielectric layer over another dielectric layer in preference to a conductive material. For example, the conductive material can form multiple conductive lines within a first dielectric layer (e.g., a metallization level). The first dielectric layer can include any suitable dielectric material. In some implementations, the first dielectric layer can include an oxide. In some implementations, the first dielectric layer can include a nitride. Examples of suitable dielectric materials that can be used to form the first dielectric layer include carbon-doped silicon oxides such as SiO2, SiOC, SiCOH, and Si3N4. The conductive material can include any suitable material. In some embodiments, the conductive material includes a transition metal. Examples of suitable conductive materials include Cu, W, Co, Mo, Ru, and the like.

[0020] More specifically, performing DoD selective deposition can include passivating the conductive material (e.g., conductive line) by exposing the first dielectric layer and conductive material to aniline (e.g., vapor-phase aniline). Aniline is an aromatic molecule that can include an amine functional group attached to a phenyl group (e.g., CHNH). During aniline exposure, aniline may exhibit weak or no adsorption to the first dielectric layer but strong adsorption to the surface of the conductive material (e.g., transition metal). The passivation layer can prevent (e.g., block) deposition precursors of subsequent dielectrics (e.g., oxides) from adsorbing onto the conductive layer (i.e., preventing nucleation of the deposition precursors) during a subsequent deposition process to form the second dielectric layer. Thus, the aniline passivation allows a second dielectric layer to be selectively deposited over the first dielectric layer in preference to conductive materials during a subsequent deposition process (e.g., without depositing the second dielectric layer over the passivated metal layer).

[0021] For example, for some conductive materials, aniline may react with the conductive material, causing dissociation. More specifically, this reaction may result in deprotonation (i.e., loss of an H atom from the aniline compound), which may result in the formation of a bond (e.g., a phenyl-N-metal bond) on the surface of the conductive material.

[0022] As another example, for some conductive materials (e.g., Ru), aniline can exhibit two preferred adsorption modes in which the bonds within the aniline compound are not broken. One adsorption mode is a π-bonding configuration in which the entire aniline compound is bonded via delocalized π electrons. The other adsorption mode is a donative bonding configuration in which aniline donates an electron pair from N to the surface of the conductive material, thereby forming a bond with the conductive layer (e.g., an N-metal bond).

[0023] Passivation can be performed using any suitable process parameters. Example process parameters for passivation include temperature, exposure time, pressure, etc. In some embodiments, the aniline exposure is performed at a temperature ranging from about 100°C to about 350°C. In some embodiments, the aniline exposure is performed at a temperature ranging from about 250°C to about 350°C. At sufficiently high temperatures (e.g., above 350°C), degradation of the aniline passivation can occur. Therefore, the passivation process can be performed below a threshold temperature (e.g., at or below about 350°C) to maintain the quality of the aniline passivation. In some embodiments, the pressure ranges from about 500 millitorr (mTorr) to about 10 torr. In some embodiments, the pressure ranges from about 750 mTorr to about 780 mTorr.

[0024] In some embodiments, the conductive material is exposed to aniline for about 60 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 50 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 40 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 30 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 20 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 10 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 5 minutes or less. In some embodiments, the conductive material is exposed to aniline for about 1 minute or less.

[0025] In some embodiments, a cleaning process can be performed before passivating the conductive material (i.e., pre-cleaning). The pre-cleaning process can optionally be performed to improve the selectivity of the second dielectric layer over the first dielectric layer and / or reduce the selectivity of the second dielectric layer over the conductive material. The pre-cleaning process can include a surface clean to remove native oxides on the surface of the conductive material. The pre-cleaning process can further remove contaminants from the surface of the conductive material. The pre-cleaning process can further reduce the growth of defects on the conductive material. For example, the pre-cleaning process can include a hot ethanol (EtOH) treatment, a hydrogen radical treatment, etc.

[0026] The pre-cleaning process can be performed using any suitable process parameters. Examples of process parameters for performing the pre-cleaning include time, temperature, pressure, etc. For example, the thermal EtOH treatment can be performed for a time ranging from about 1 minute to about 30 minutes (e.g., about 5 minutes) at a temperature ranging from about 200°C to about 300°C (e.g., about 250°C). In some embodiments, the pressure ranges from about 100 mTorr to about 10 torr. In some embodiments, the pressure ranges from about 500 mTorr to about 10 torr. In some embodiments, the pressure ranges from about 1 torr to about 10 torr.

[0027] After passivation (and optional pre-cleaning before passivation), a deposition process can be used to selectively form a second dielectric layer on the exposed surface of the first dielectric layer. The second dielectric layer can include any suitable dielectric material. In some embodiments, the second dielectric layer can include an oxide. For example, the second dielectric layer can include a metal oxide. Examples of suitable dielectric materials that can be used to form the second dielectric layer include hafnium dioxide (HfO), titanium dioxide (TiO), aluminum oxide (AlO), SiO, etc. In some embodiments, the second dielectric layer includes a nanolaminate that ensures an amorphous structure. The second dielectric layer can be deposited to a target thickness on the first dielectric layer (e.g., by performing an appropriate number of deposition cycles). As described above, the passivation layer formed during aniline passivation can prevent (e.g., block) the deposition precursor from adsorbing to the conductive material. Therefore, aniline passivation can prevent (e.g., inhibit) the second dielectric layer from forming on the conductive material. Aniline passivation therefore allows a negligible thickness of the dielectric layer (eg, less than about 1 nm thick) to be deposited on the conductive material during the deposition process.

[0028] The deposition process can be water-free and plasma-free. For example, water and / or plasma can cause desorption of an adsorbed passivation layer. Therefore, the conductive material can be exposed to aniline once prior to the deposition process (i.e., multiple exposures of the conductive material to aniline may not be necessary). Furthermore, because the deposition process does not use water, the first dielectric layer can be formed of a porous hydrophobic dielectric (e.g., SiCOH).

[0029] In some embodiments, the deposition process is a chemical vapor deposition (CVD) process. For example, the CVD process can be a pulsed CVD process. During the pulsed CVD process, a material can be formed by alternating deposition precursor pulses and purge gas pulses. The purge gas can be any suitable inert gas. For example, the purge gas can be argon gas (Ar), nitrogen gas (N), etc.

[0030] The deposition process can utilize any suitable deposition precursor and any suitable process parameters. In some embodiments, the deposition process utilizes a deposition precursor to form a metal oxide (e.g., a metal alkoxide precursor). Examples of deposition precursors include hafnium tert-butoxide (Hf(OtBu)) to form HfO, titanium isopropoxide (Ti(OiPr)) to form TiO, aluminum isopropoxide (Al(OiPr)) to form AlO, aluminum tri-sec-butoxide (Al[OCH(CH)C2H]) to form AlO, tetraethoxysilane or tetraethylorthosilicate (TEOS) (Si(OC2H)) to form SiO, tetrabutoxysilane or tetrabutylorthosilicate (TBOS) (Si(OC4H9)) to form SiO, and tetramethoxysilane or tetramethylorthosilicate (TMOS) (Si(OCH3)) to form SiO. The process parameters of the deposition process (eg, a CVD process) can depend on the deposition precursors used to form the second dielectric layer and the target thickness of the resulting second dielectric layer.

[0031] Examples of process parameters for performing a pulsed CVD process include temperature, number of deposition precursor pulses, pulse length (i.e., the time length of the deposition precursor pulses), purge length (i.e., the time length of the purge pulses between deposition precursor pulses), pressure, deposition precursor vapor pressure, purge gas pressure, etc. In some embodiments, the pulsed CVD process can be performed at a temperature ranging from about 100°C to about 400°C. In some embodiments, the pulsed CVD process can be performed at a temperature ranging from about 300°C to about 350°C. In some embodiments, the number of deposition precursor pulses ranges from about 1 pulse to about 1000 pulses. In some embodiments, the number of deposition precursor pulses ranges from about 4 pulses to about 500 pulses. In some embodiments, the number of deposition precursor pulses ranges from about 50 pulses to about 250 pulses. In some embodiments, the pulse length ranges from about 0.1 seconds to about 4 seconds. In some embodiments, the purge length ranges from about 0.1 seconds to about 10 seconds.

[0032] Further details regarding forming a device using aniline passivation to perform DoD selective deposition will now be described below with reference to Figures 1A-1D.

[0033] 1A-1D are cross-sectional views illustrating an exemplary method for forming a device 100 that implements dielectric-on-dielectric selective deposition using aniline passivation, according to some embodiments. As shown in FIG. 1A, a dielectric layer 110-1 can be provided, and multiple conductive lines, including conductive lines 120-1 and 120-2, can be formed within the dielectric layer 110-1. More specifically, the dielectric layer 110-1 can be an interlevel dielectric (ILD) layer, and the conductive lines 120-1 and 120-2 can correspond to a first metallization level within the device 100. Forming the multiple conductive lines can include forming multiple trenches within the dielectric layer 110-1 using an etching process and forming a conductive material within the multiple trenches to form the multiple conductive lines. More specifically, each trench corresponds to a respective conductive line. The dielectric layer 110-1 and the conductive lines 120-1 and 120-2 can, in embodiments, be included within a base structure on a substrate, such as a semiconductor wafer.

[0034] Although not shown, the base structure may include one or more additional layers, with the dielectric layer 110-1 and the conductive lines disposed on the one or more additional layers. For example, the device 100 may further include at least a substrate layer (e.g., a silicon (Si) substrate) (not shown) as an initial layer of the device.

[0035] Dielectric layer 110-1 can include any suitable dielectric material. In some implementations, dielectric layer 110-1 can include an oxide (e.g., a metal oxide). In some implementations, dielectric layer 110-1 can include a nitride (e.g., a metal nitride). Examples of suitable dielectric materials include SiO, carbon-doped silicon oxide (e.g., SiOC, SiCOH), SiN, etc. Conductive lines 120-1 and 120-2 can be formed from any suitable conductive material (e.g., a metal). In some embodiments, conductive lines 120-1 and 120-2 are formed from a conductive material including a transition metal. Examples of suitable conductive materials that can be used to form conductive lines 120-1 and 120-2 include Cu, W, Co, Mo, Ru, etc.

[0036] As shown in FIG. 1B, dielectric layer 130 is selectively deposited on dielectric layer 110-1. Deposition can be performed, for example, using a CVD process. Other deposition processes can also be performed to produce dielectric layer 130. Dielectric layer 130 can include any suitable dielectric material. In some implementations, dielectric layer 130 can include an oxide. For example, dielectric layer 130 can include a metal oxide. Examples of suitable dielectric materials that can be used to form the second dielectric layer include HfO2, TiO2, Al2O3, SiO2, etc.

[0037] More specifically, selectively depositing dielectric layer 130 includes performing a passivation process by exposing dielectric layer 110-1 and conductive lines 120-1 and 120-2 to aniline (e.g., vapor phase aniline). Exposing conductive lines 120-1 and 120-2 to aniline can create a passivated surface on the surfaces of conductive lines 120-1 and 120-2.

[0038] More specifically, the aniline reacts with the conductive lines 120-1 and 120-2 to form a passivation layer that adsorbs to the surfaces of the conductive lines 120-1 and 120-2. The passivation layer may include by-products of the aniline reaction that adsorb to the surfaces of the conductive lines 120-1 and 120-2. The passivation layer may prevent (e.g., inhibit) the growth of the dielectric layer 130 on the conductive lines 120-1 and 120-2 by preventing (e.g., blocking) the adsorption of deposition precursors during the deposition of the dielectric layer 130. In some embodiments, the passivation layer has a thickness of a monolayer.

[0039] The passivation process can be performed using any suitable process parameters. For example, the passivation process can be a thermal aniline exposure. In some embodiments, the passivation process is performed once to form a single passivation layer. Example process parameters for performing the passivation process include temperature, exposure time, pressure, etc. In some embodiments, the aniline exposure is performed at a temperature ranging from about 100°C to about 400°C. In some embodiments, the aniline exposure is performed at a temperature ranging from about 250°C to about 350°C. In some embodiments, the pressure is in the range of about 500 mTorr to about 10 torr. In some embodiments, the pressure is in the range of about 750 mTorr to about 780 mTorr.

[0040] In some embodiments, the conductive wires 120-1 and 120-2 are exposed to aniline for about 60 minutes or less. In some embodiments, the conductive wires 120-1 and 120-2 are exposed to aniline for about 50 minutes or less. In some embodiments, the conductive wires 120-1 and 120-2 are exposed to aniline for about 40 minutes or less. In some embodiments, the conductive wires 120-1 and 120-2 are exposed to aniline for about 30 minutes or less. In some embodiments, the conductive wires 120-1 and 120-2 are exposed to aniline for about 20 minutes or less. In some embodiments, the conductive wires 120-1 and 120-2 are exposed to aniline for about 10 minutes or less. In some embodiments, the conductive wires 120-1 and 120-2 are exposed to aniline for about 5 minutes or less. In some embodiments, the conductive wires 120-1 and 120-2 are exposed to aniline for about 1 minute or less.

[0041] In some embodiments, a pre-cleaning process can be performed before passivating the conductive lines 120-1 and 120-2. The pre-cleaning process can improve the selectivity of the dielectric layer 130 over the dielectric layer 110-1 and / or reduce the selectivity of the dielectric layer 130 over the conductive lines 120-1 and 120-2. The pre-cleaning process can include a surface clean to remove native oxides on the surfaces of the conductive lines 120-1 and 120-2. The pre-cleaning process can further remove contaminants from the surfaces of the conductive lines 120-1 and 120-2. The pre-cleaning process can further reduce the growth of defects on the conductive lines 120-1 and 120-2. For example, the pre-cleaning process can include a thermal EtOH treatment, a hydrogen radical treatment, etc. Illustratively, the pre-cleaning process can include sequential EtOH administrations at a temperature in the range of about 200°C to about 300°C (e.g., about 250°C) for a time in the range of about 4 minutes to about 6 minutes (e.g., about 5 minutes) prior to passivation. In some embodiments, the pressure ranges from about 100 mTorr to about 10 torr. In some embodiments, the pressure ranges from about 500 mTorr to about 10 torr. In some embodiments, the pressure ranges from about 1 torr to about 10 torr.

[0042] After passivation (and optional pre-cleaning before passivation), a deposition process can be used to form the dielectric layer 130. More specifically, the dielectric layer 130 can be selectively deposited on the exposed surfaces of the dielectric layer 110. The deposition process can be a water-free deposition process and a plasma-free deposition process. In some embodiments, the deposition process is a CVD process. For example, the CVD process can be a pulsed CVD process. Other deposition processes can also be used. The aniline passivation allows a negligible thickness of the dielectric layer (e.g., less than about 1 nm thick) to be deposited on the conductive material during the deposition process. This thin dielectric layer may be removed during further processing (e.g., during a subsequent metal deposition process and / or cleaning process).

[0043] The deposition process can utilize any suitable deposition precursor and any suitable process parameters. In some embodiments, the deposition process utilizes a deposition precursor to form a metal oxide (e.g., a metal alkoxide precursor). Examples of deposition precursors include hafnium tert-butoxide to form HfO, titanium isopropoxide to form TiO, aluminum isopropoxide to form AlO, aluminum tri-sec-butoxide to form AlO, TEOS to form SiO, TBOS to form SiO, TMOS to form SiO, etc. The process parameters of the deposition process (e.g., a CVD process) can depend on the deposition precursor used to form the second dielectric layer and the target thickness of the resulting second dielectric layer.

[0044] Example process parameters for performing a pulsed CVD process include temperature, number of pulses, pulse length (i.e., the length of time the deposition precursor is pulsed), purge length (i.e., the length of time a purge gas (e.g., Ar or N2) is introduced between pulses), deposition precursor vapor pressure, purge gas pressure, etc. For example, a pulsed CVD process can be performed at a temperature ranging from about 100°C to about 400°C. As another example, the pulse length can range from about 0.1 seconds to about 4 seconds. As yet another example, the purge length can range from about 0.1 seconds to about 10 seconds. Further details regarding the deposition process are described below with reference to Figures 2A-2B.

[0045] After forming the dielectric layer 130, an optional post-cleaning process can be performed. Performing the post-cleaning process can include removing a passivation layer and / or a thin dielectric layer from the surface of the conductive material. For example, performing the post-cleaning process can include heating the device to a temperature of 350°C or higher. Heating the device to a temperature of 350°C or higher can cause desorption of the passivation layer. As another example, performing the post-cleaning process can further include removing defects (e.g., portions of the dielectric material that may have formed on the conductive material during the deposition process). As another example, the post-cleaning process can be a plasma cleaning process. As yet another example, the post-cleaning process can be a remote plasma cleaning process.

[0046] As shown in FIG. 1C , after selectively depositing a dielectric layer 130 on the dielectric layer 110-1, a dielectric layer 110-2 may be formed on the plurality of conductive lines and the dielectric layer 130. More specifically, the dielectric layer 110-2 may be a second ILD layer. The dielectric layer 110-2 may include any suitable dielectric material. In some embodiments, the dielectric layer 110-2 may include an oxide. In some embodiments, the dielectric layer 110-2 may include a nitride. Examples of suitable dielectric materials include SiO , carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si N , etc. In some embodiments, the dielectric layer 110-2 includes the same dielectric material as the dielectric layer 110-1. In some embodiments, the dielectric layer 110-2 includes a different dielectric material than the dielectric layer 110-1.

[0047] 1D , at least one via 140 is formed. More specifically, via 140 can be formed in contact with at least conductive line 120-2. As further shown in this illustrative example, at least one conductive line 150 is formed. More specifically, conductive line 150 can correspond to a second metallization level that is different from the first metallization level (i.e., at least one metallization level higher than the first metallization level).

[0048] Forming via 140 and conductive line 150 may include forming a trench in dielectric layer 110-2, forming a via hole in dielectric layer 110-2, and forming a conductive material in the trench and via hole. In some embodiments, via 140 and conductive line 150 are formed simultaneously (e.g., using a dual damascene process). In some embodiments, via 140 and conductive line 150 are formed sequentially (e.g., using a single damascene process).

[0049] Via 140 and conductive line 150 may comprise any suitable conductive material (e.g., a metal). In some embodiments, via 140 and conductive line 150 are formed from a conductive material including a transition metal. Examples of suitable conductive materials that can be used to form via 140 and conductive line 150 include Cu, W, Co, Mo, Ru, etc. In some embodiments, via 140 and conductive line 150 may comprise the same material as conductive lines 120-1 and 120-2. In some embodiments, via 140 and conductive line 150 may comprise a different material than conductive lines 120-1 and 120-2.

[0050] As shown in FIG. 1D , via 140 in this example is a misaligned via with its edge positioned on dielectric layer 130 between conductive lines 120-1 and 120-2. The distance between via 140 and conductive line 120-1 is indicated in FIG. 1D by diagonal line “D.” Diagonal line D is longer than the horizontal line that would indicate the separation between via 140 and conductive line 120-1 in the absence of dielectric layer 130. Thus, the formation of dielectric layer 130 can improve the performance of device 100 by reducing shorting or capacitive coupling between via 140 and conductive line 120-1. Further details regarding the formation of device 100 are now described below with reference to FIGS. 2A-2B .

[0051] 2A illustrates an exemplary method 200 for performing DoD selective deposition using aniline passivation, according to some embodiments. Method 200 may be performed in an electronic device processing system. More specifically, method 200 may be performed in one or more process chambers of the electronic device processing system. Further details regarding electronic device processing systems are described below with reference to FIG. 3.

[0052] In step 210, a first conductive material is formed on the first dielectric layer. For example, a first dielectric layer can be provided, and the first conductive material can be formed on the first dielectric layer. In some embodiments, forming the first conductive material includes forming a plurality of conductive lines in the first dielectric layer. More specifically, the first dielectric layer can be an ILD layer, and the plurality of conductive lines can correspond to a first metallization level in the device. Forming the plurality of conductive lines can include forming a plurality of trenches in the first dielectric layer using an etching process, and forming a conductive material in the plurality of trenches to form the plurality of conductive lines. More specifically, each trench corresponds to a respective conductive line.

[0053] The first dielectric layer and the conductive material (e.g., a plurality of conductive lines) can be included in a base structure. The base structure can include one or more additional layers, with the first dielectric layer and the conductive material disposed on the one or more additional layers. For example, the device can further include at least a substrate layer (e.g., a silicon (Si) substrate) as an initial layer of the device.

[0054] The first dielectric layer can comprise any suitable dielectric material. In some implementations, the first dielectric layer can comprise an oxide. In some implementations, the first dielectric layer can comprise a nitride. Examples of suitable dielectric materials that can be used to form the first dielectric layer include SiO2, carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si3N4, etc. The conductive material can comprise any suitable conductive material (e.g., a metal). In some embodiments, the conductive material comprises a transition metal. Examples of suitable conductive materials include Cu, W, Co, Mo, Ru, etc.

[0055] In step 220, a second dielectric layer is selectively deposited on the first dielectric layer using a deposition process. The second dielectric layer can include any suitable dielectric material. In some embodiments, the second dielectric layer can include an oxide. For example, the second dielectric layer can include a metal oxide. Examples of suitable dielectric materials that can be used to form the second dielectric layer include HfO2, TiO2, Al2O3, SiO2, etc. More specifically, selectively depositing the second dielectric layer can include passivating the conductive material (e.g., the plurality of conductive lines) with aniline. Further details regarding selectively depositing the second dielectric layer are now described below with reference to FIG. 2B.

[0056] 2B illustrates an exemplary method 220 for selectively depositing a second dielectric layer on a first dielectric layer using aniline passivation, according to some embodiments. Method 220 can be performed in an electronic device processing system. More specifically, method 220 can be performed in one or more process chambers of the electronic device processing system.

[0057] In step 222, a pre-cleaning process is optionally performed. More specifically, a base structure including a conductive material formed on a first dielectric layer (e.g., a plurality of conductive lines disposed within the first dielectric layer) can be cleaned. The pre-cleaning process can improve the selectivity of a second dielectric layer formed on the first dielectric layer and / or reduce the selectivity of a second dielectric layer formed on the conductive material. The pre-cleaning process can include a surface clean to remove native oxides on the surface of the conductive material. The pre-cleaning process can further remove contaminants from the surface of the conductive material. The pre-cleaning process can further reduce the growth of defects on the conductive material. For example, the pre-cleaning can include a thermal EtOH treatment, a hydrogen radical treatment, etc. Illustratively, the pre-cleaning process can include continuous EtOH administration at a temperature in the range of about 200°C to about 300°C (e.g., about 250°C) for a time in the range of about 4 minutes to about 6 minutes (e.g., about 5 minutes) prior to passivation. In some embodiments, the pressure is in the range of about 100 mTorr to about 10 torr. In some embodiments, the pressure ranges from about 500 mTorr to about 10 torr. In some embodiments, the pressure ranges from about 1 torr to about 10 torr.

[0058] In step 224, the first conductive material is exposed to aniline. In some embodiments, the aniline includes vapor-phase aniline. More specifically, the first conductive material (and the first dielectric layer) can be exposed to aniline to generate a passivated surface of the conductive material. Aniline reacts strongly with the first conductive material to form a passivation layer that adsorbs onto the surface of the conductive material and prevents (e.g., blocks) the growth of a second dielectric layer on the conductive material. More specifically, the passivation layer can prevent (e.g., block) the deposition precursors used during a subsequent deposition process to form the second dielectric layer from adsorbing onto the surface of the first conductive material. In some embodiments, the first conductive material is exposed to aniline during a single passivation process to form a single passivation layer. In some embodiments, the passivation layer has a thickness of a single layer. However, the passivation layer can have any suitable thickness according to embodiments described herein.

[0059] The aniline exposure can be carried out at a suitable temperature. For example, the aniline exposure can be carried out at a temperature ranging from about 100°C to about 400°C. The aniline exposure can be carried out for any suitable time. In some embodiments, the conductive material is exposed to aniline for a time ranging from about 30 minutes to about 60 minutes. For example, the conductive material can be exposed to aniline for about 40 minutes.

[0060] In step 226, a second dielectric layer is formed using a deposition process. More specifically, the second dielectric layer can be selectively deposited on the exposed surface of the first dielectric layer. As described above, to form the second dielectric layer, a passivation layer formed on the conductive material prevents (e.g., blocks) adsorption of the deposition precursors used during the deposition process. The deposition process can be a waterless deposition process and a plasma-free deposition process. In some embodiments, the deposition process is a CVD process. For example, the CVD process can be a pulsed CVD process. Aniline passivation can allow the thickness of the dielectric layer deposited on the conductive material during the deposition process to be negligible (e.g., less than about 1 nm thick).

[0061] The deposition process can utilize any suitable deposition precursor and any suitable process parameters. In some embodiments, the deposition process utilizes a deposition precursor to form a metal oxide (e.g., a metal alkoxide precursor). Examples of deposition precursors include hafnium tert-butoxide to form HfO, titanium isopropoxide to form TiO, aluminum isopropoxide to form AlO, aluminum tri-sec-butoxide to form AlO, TEOS to form SiO, TBOS to form SiO, TMOS to form SiO, etc. The process parameters of the deposition process (e.g., a CVD process) can depend on the deposition precursor used to form the second dielectric layer and the target thickness of the resulting second dielectric layer.

[0062] Examples of process parameters for performing a pulsed CVD process include temperature, number of deposition precursor pulses, pulse length (i.e., the time length of the deposition precursor pulses), purge length (i.e., the time length of the purge pulses between deposition precursor pulses), pressure, deposition precursor vapor pressure, purge gas pressure, etc. In some embodiments, the pulsed CVD process can be performed at a temperature ranging from about 100°C to about 400°C. In some embodiments, the pulsed CVD process can be performed at a temperature ranging from about 300°C to about 350°C. In some embodiments, the number of deposition precursor pulses ranges from about 1 pulse to about 1000 pulses. In some embodiments, the number of deposition precursor pulses ranges from about 4 pulses to about 500 pulses. In some embodiments, the number of deposition precursor pulses ranges from about 50 pulses to about 250 pulses. In some embodiments, the pulse length ranges from about 0.1 seconds to about 4 seconds. In some embodiments, the purge length ranges from about 0.1 seconds to about 10 seconds.

[0063] As an illustrative example, assume that the first dielectric layer includes SiO2 and that the conductive material has been passivated by aniline exposure as described above. Further, assume that the second dielectric layer includes HfO2. HfO2 can be deposited on the SiO2 using a pulsed CVD process with a hafnium tert-butoxide precursor at a temperature ranging from about 250°C to about 350°C (e.g., about 300°C). The vapor pressure of the hafnium tert-butoxide precursor can be from about 0.1 mTorr to about 0.5 mTorr (e.g., about 0.3 mTorr). There can be a time interval of about 60 seconds between each pulse of the hafnium tert-butoxide precursor. A purge gas (e.g., Ar or N2) having a pressure of about 120 mTorr can be used during each purge pulse between the hafnium tert-butoxide precursor pulses. Approximately 60 pulses of hafnium tert-butoxide precursor can deposit approximately 5 nm of HfO2 on SiO2.

[0064] As another illustrative example, assume that the first dielectric layer includes SiO2 and that the conductive material has been passivated by aniline exposure as described above. Further, assume that the second dielectric layer includes Al2O3. The Al2O3 can be deposited on the SiO2 using a pulsed CVD process with an aluminum tri-sec-butoxide precursor at a temperature ranging from about 300°C to about 375°C (e.g., about 330°C). The vapor pressure of the aluminum tri-sec-butoxide precursor can be about 0.1 mTorr to about 0.5 mTorr (e.g., about 0.3 mTorr). There can be a time interval of about 60 seconds between each pulse of the aluminum tri-sec-butoxide precursor. A purge gas (e.g., Ar or N2) having a pressure of about 120 mTorr can be used during each purge pulse between the aluminum tri-sec-butoxide precursor pulses. Approximately 200 pulses of aluminum tri-sec-butoxide precursor can deposit approximately 5 nm of Al2O3 on SiO2.

[0065] In step 228, an optional post-cleaning process may be performed. More specifically, the post-cleaning process may be performed after forming the second dielectric layer. Performing the post-cleaning process may include removing a passivation layer from the surface of the conductive material. For example, performing the post-cleaning process may include heating the device to a temperature of 350° C. or higher. As another example, performing the post-cleaning process may further include removing defects (e.g., portions of the dielectric material that may have formed on the conductive material during the deposition process). As another example, the post-cleaning process may be a plasma cleaning process. As yet another example, the post-cleaning process may be a remote plasma cleaning process.

[0066] Referring again to FIG. 2A , in step 230, a third dielectric layer is formed over the second dielectric layer and the conductive material. For example, the third dielectric layer can be a second ILD layer. The third dielectric layer can include any suitable dielectric material. In some embodiments, the third dielectric layer can include an oxide. In some embodiments, the third dielectric layer can include a nitride. Examples of suitable dielectric materials that can be used to form the third dielectric layer include SiO 2 , carbon-doped silicon oxide (e.g., SiOC, SiCOH), Si 3 N 4 , etc. In some embodiments, the third dielectric layer includes the same dielectric material as the first dielectric layer (i.e., the first ILD layer). In some embodiments, the third dielectric layer includes a different dielectric material than the first dielectric layer.

[0067] In step 240, a second conductive material is formed on the third dielectric layer. In some embodiments, forming the second conductive material includes forming a via in the third dielectric layer. For example, a first end of the via can contact at least a portion of a first conductive line of the plurality of conductive lines. In some embodiments, forming the second conductive material further includes forming a second conductive line. More specifically, the second conductive line can be disposed at a second end of the via. The second conductive line can correspond to a second metallization level different from the first metallization level (i.e., at least one metallization level higher than the first metallization level).

[0068] Forming the via and the second conductive line can include forming a trench in the third dielectric layer, forming a via hole in the third dielectric layer, and forming a conductive material in the trench and the via hole. In some embodiments, the via and the second conductive line can be formed simultaneously (e.g., using a dual damascene process). In some embodiments, the via and the second conductive line can be formed sequentially (e.g., using a single damascene process).

[0069] The second conductive material may include any suitable conductive material (e.g., a metal). Examples of suitable conductive materials for the second conductive material include Cu, W, Co, Mo, Ru, etc. In some embodiments, the first conductive material includes the same material as the second conductive material. In some embodiments, the first conductive material includes a different material than the second conductive material. Further details regarding steps 210-240 are described above with reference to FIGS. 1A-1D.

[0070] 3 is a block diagram of an exemplary electronic device processing system ("system") 300 that can be used to form a device that performs DoD selective deposition using CVD, according to some embodiments. For example, system 300 can be used to form device 100 described above with reference to FIGS. 1A-1D and to perform method 200 described above with reference to FIGS. 2A-2B.

[0071] As shown, system 300 includes a passivation chamber 310, a transfer chamber 320, and a deposition chamber 330. Interface 340-1 can be disposed between passivation chamber 310 and transfer chamber 320, and interface 340-2 can be disposed between the transfer chamber and deposition chamber 330. In some embodiments, interfaces 340-1 and 340-2 are respective gate valves. Transfer chamber 320 can include a transfer robot (not shown). Transfer chamber 320, passivation chamber 310, and deposition chamber 330 can each be maintained under vacuum at controlled conditions (e.g., little or no humidity). Although not shown, system 300 can further include at least one load lock chamber and at least one factory interface to enable transfer of substrates from atmosphere to transfer chamber 320. Thus, substrates can be transferred between chambers without breaking vacuum and, therefore, without exposing the substrates to air and / or moisture.

[0072] The passivation chamber 310 can receive a substrate including a first dielectric layer and a conductive material and passivate the conductive material by exposing the conductive material to aniline. For example, the aniline can include vapor-phase aniline. The passivation chamber 310 can be operably coupled to at least one passivation gas reservoir 312. For example, the at least one passivation gas reservoir 312 can include an aniline reservoir. The at least one passivation gas reservoir 312 can further include a purge gas reservoir. The purge gas reservoir can include any suitable inert gas (e.g., Ar or N) for purging the passivation chamber 312 during the passivation process. The passivation process can be performed using any suitable passivation process parameters. Further details regarding passivating a conductive material with aniline are described above with reference to FIGS. 1A-2B.

[0073] After passivating the conductive material, the transfer robot can transfer the substrate to the deposition chamber 330. After receiving the substrate, the deposition chamber 330 can perform a deposition process to selectively form a second dielectric layer on the first dielectric layer. More specifically, the deposition process can be a water-free, plasma-free deposition process. In some embodiments, the deposition process is a CVD process. For example, the deposition process can be a pulsed CVD process.

[0074] The deposition chamber 330 can be operably coupled to a deposition precursor reservoir 332 and a purge gas reservoir 334. The deposition precursor reservoir 332 can contain any suitable deposition precursor for forming the second dielectric layer. The purge gas reservoir 334 can contain any suitable inert gas (e.g., Ar or N2) for purging the deposition chamber 330 during the deposition process. The deposition process can be performed using any suitable deposition process parameters. Further details regarding performing the deposition process are described above with reference to FIGS. 1A-2B.

[0075] In some embodiments, the deposition process is performed in the passivation chamber 310 (i.e., the passivation chamber 310 is a process chamber configured to perform the passivation process and the deposition process). In these embodiments, the deposition precursor reservoir 332 and the purge gas reservoir 334 can be operably coupled to the passivation chamber 310. In some embodiments, the passivation process is performed in the deposition chamber 330 (i.e., the deposition chamber 330 is a process chamber configured to perform the passivation process and the deposition process). In these embodiments, at least one passivation gas reservoir 312 can be operably coupled to the deposition chamber 330.

[0076] In some embodiments, system 300 may optionally include a cleaning chamber 350 for performing an optional cleaning process before passivation (i.e., a pre-cleaning process) and / or an optional cleaning process after formation of the second dielectric layer (i.e., a post-cleaning process). Interface 340-3 may be disposed between cleaning chamber 350 and transfer chamber 320. In some embodiments, cleaning chamber 350 is an in-situ cleaning chamber, and interface 340-3 is a gate valve. In some embodiments, cleaning chamber 350 is an ex-situ cleaning chamber, and interface 340-3 is a load lock chamber.

[0077] For example, the pre-cleaning process can be a thermal EtOH treatment. As another example, the pre-cleaning process can be a hydrogen radical treatment. The pre-cleaning process and / or post-cleaning process can be performed using any suitable pre-cleaning process parameters.

[0078] For example, performing the post-cleaning process may include heating the device to a temperature of 350° C. or greater. As another example, performing the post-cleaning process may further include removing defects (e.g., portions of dielectric material that may have formed on the conductive material during the deposition process). As another example, the post-cleaning process may be a plasma cleaning process. As yet another example, the post-cleaning process may be a remote plasma cleaning process. The post-cleaning process may be performed using any suitable post-cleaning process parameters.

[0079] The cleaning chamber 350 can be operably coupled to at least one cleaning gas reservoir 352. The at least one cleaning gas reservoir 352 can contain a suitable cleaning chemistry. For example, the at least one cleaning gas reservoir 352 can include an ethanol reservoir for performing a thermal EtOH clean. The at least one passivation gas reservoir 312 can further include a purge gas reservoir. The purge gas reservoir can include any suitable inert gas (e.g., Ar or N) for purging the cleaning chamber 352.

[0080] In some embodiments, the pre-cleaning process can be performed in the same chamber as the passivation (e.g., the passivation chamber 310 or the deposition chamber 330). In these embodiments, at least one cleaning gas reservoir 352 can be operably coupled to the passivation chamber 310 and / or the deposition chamber 330. In some embodiments, the post-cleaning process can be performed in the passivation chamber 310 and / or the deposition chamber 330. In these embodiments, at least one cleaning gas reservoir 352 can be operably coupled to the passivation chamber 310 and / or the deposition chamber 330. Further details regarding performing cleaning processes (e.g., pre-cleaning process and / or post-cleaning process) are described above with reference to FIGS. 1A-2B.

[0081] The foregoing description sets forth numerous specific details, such as examples of particular systems, components, methods, etc., to provide a thorough understanding of some embodiments of the present disclosure. However, it will be apparent to those skilled in the art that at least some embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known components or methods are not described in detail or are presented in simple block diagram form to avoid unnecessarily obscuring the present disclosure. Thus, the specific details described are merely exemplary. Particular embodiments may vary from these example details and still be construed as being within the scope of the present disclosure.

[0082] Throughout this specification, a reference to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification do not necessarily all refer to the same embodiment. In addition, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or." When the term "about" or "approximately" is used herein, it is intended to mean that the stated nominal value is accurate to within ±10%.

[0083] Although the operations of the methods herein are shown and described in a particular order, the order of the operations of each method may be changed such that certain operations may be performed in the reverse order or such that certain operations may be performed at least in part concurrently with other operations. In alternative embodiments, instructions or sub-operations of separate operations may be performed intermittently and / or alternately.

[0084] It should be understood that the above description is illustrative, and not restrictive. Many other embodiments will become apparent to those skilled in the art upon reading and understanding the above description. The scope of the present disclosure should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. forming a conductive material on the first dielectric layer; exposing the conductive material to aniline to create a passivated surface of the conductive material; forming a second dielectric layer on the first dielectric layer using a deposition process after exposing the conductive material to aniline, the deposition process being a waterless, plasmaless deposition process, and the second dielectric layer not being formed on the passivated surface of the conductive material; A method comprising:

2. 10. The method of claim 1, further comprising performing a pre-cleaning process to reduce native oxides on the surface of the conductive material prior to exposing the conductive material to aniline.

3. 10. The method of claim 1, wherein the conductive material comprises a conductive line associated with a metallization level of a device, and the first dielectric layer is an interlevel dielectric (ILD) layer of the device.

4. The method of claim 1 , wherein the deposition process is a pulsed chemical vapor deposition (CVD) process.

5. 5. The method of claim 4, wherein the pulsed CVD process is carried out at a temperature of about 350° C. or less.

6. The method of claim 1 , wherein the first dielectric layer comprises at least one of silicon dioxide, carbon-doped silicon oxide, or silicon nitride.

7. The method of claim 1 , wherein the conductive material comprises a transition metal.

8. The method of claim 1 , wherein the second dielectric layer comprises a metal oxide.

9. forming a third dielectric layer over the second dielectric layer and the conductive material; forming a second conductive material on the third dielectric layer; The method of claim 1 further comprising:

10. The method of claim 5 , wherein the second conductive material comprises a via and the first dielectric layer is an interlevel dielectric (ILD) layer.

11. 1. A system comprising at least one chamber, the at least one chamber comprising: exposing a conductive material formed on a first dielectric layer disposed on a substrate to aniline to create a passivated surface of the conductive material; forming a second dielectric layer on the first dielectric layer using a deposition process after exposing the conductive material to aniline, wherein the deposition process is a waterless, plasmaless deposition process, and the second dielectric layer is not formed on the passivated surface of the conductive material; The system is configured as follows:

12. 12. The system of claim 11, wherein the at least one chamber is further configured to perform a pre-cleaning process to reduce native oxides on a surface of the conductive material prior to exposing the conductive material to aniline.

13. The system of claim 11 , further comprising a deposition precursor reservoir and a purge gas reservoir, each operably coupled to the at least one chamber.

14. 14. The system of claim 13, wherein the deposition precursor reservoir maintains a deposition precursor selected from the group consisting of hafnium tert-butoxide, titanium isopropoxide, aluminum isopropoxide, aluminum-tri-sec-butoxide, tetraethyl orthosilicate (TEOS), tetrabutyl orthosilicate (TBOS), or tetramethyl orthosilicate (TMOS).

15. The system of claim 11 , wherein the deposition process is a pulsed chemical vapor deposition (CVD) process.

16. 16. The system of claim 15, wherein the pulsed CVD process is performed at a temperature of about 350°C or less.

17. The system of claim 11 , wherein the first dielectric layer comprises at least one of silicon dioxide, carbon-doped silicon oxide, or silicon nitride.

18. The system of claim 11 , wherein the conductive material comprises a transition metal.

19. The system of claim 11 , wherein the second dielectric layer comprises a metal oxide.

20. The at least one chamber comprises: forming a third dielectric layer over the second dielectric layer and the conductive material; forming a second conductive material on the third dielectric layer; The system of claim 11 further configured to:

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