Output circuits for artificial neural network arrays.

Abstract

Numerous examples of output circuits and related methods in artificial neural networks are disclosed. In one example, a system includes an array of non-volatile memory cells arranged in rows and columns, an output block for converting current from a column of the array to a first digital output during a first time period and to a second digital output during a second time period, a first output register for storing the first digital output during the first time period and outputting the stored first digital output during the second time period, and a second output register for storing the second digital output during the second time period and outputting the stored second digital output during a third time period.

Description

[Technical Field]

[0001] (Priority Claim) This application claims priority to U.S. patent application Ser. No. 18 / 077,993, filed December 8, 2022, entitled "Output Circuit for Artificial Neural Network Array," and U.S. provisional patent application Ser. No. 63 / 409,140, ​​filed September 22, 2022, entitled "Input Circuit and Output Circuit for Concurrent and Pipelined Operations in Artificial Neural Network Array."

[0002] FIELD OF THE INVENTION Numerous examples of output circuits and associated methods for implementing parallel and pipelined operations in artificial neural networks are disclosed. [Background technology]

[0003] Artificial neural networks mimic biological neural networks (the central nervous systems of animals, particularly the brain) and are used to estimate or approximate functions that can depend on multiple inputs and are generally unknown. Artificial neural networks typically contain layers of interconnected "neurons" that exchange messages between each other.

[0004] Figure 1 illustrates an artificial neural network, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the inputs and learn. Typically, a neural network contains multiple layers of inputs. There are typically one or more hidden layers of neurons and an output layer of neurons that provide the neural network's output. Neurons at each level make decisions, individually or collectively, based on the data they receive from the synapses.

[0005] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of suitable hardware technology. Indeed, practical neural networks rely on a very large number of synapses, which allows for high connectivity between neurons and therefore a very high degree of parallelization of computation. In principle, such complexity could be achieved using digital supercomputers or dedicated graphic processing unit clusters. However, in addition to high costs, these approaches also suffer from poor energy efficiency, compared to biological networks, which primarily perform low-precision analog computations and therefore consume much less energy. While CMOS analog circuits have been used in artificial neural networks, the synapses of most CMOS implementations are too large given the large number of neurons and synapses.

[0006] Applicant previously disclosed in U.S. Patent Application Publication No. 2017 / 0337466 A1, which is incorporated by reference, an artificial (analog) neural network that utilizes one or more non-volatile memory arrays as synapses. The non-volatile memory array operates as an analog neural memory and includes non-volatile memory cells arranged in rows and columns. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, each including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending therebetween, a floating gate disposed insulated above a first portion of the channel region, and a non-floating gate disposed insulated above a second portion of the channel region. Each of the plurality of memory cells stores a weight value corresponding to the number of electrons in the floating gate. The plurality of memory cells multiply the first plurality of inputs by the stored weight value to generate the first plurality of outputs. <Nonvolatile memory cell>

[0007] Nonvolatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), incorporated herein by reference, discloses an array of split-gate nonvolatile memory cells, which are a type of flash memory cell. Such a memory cell 210 is shown in FIG. 2. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 between the source region 14 and the drain region 16. A floating gate 20 is formed over and insulated from a first portion of the channel region 18 (and controls the conductivity of the first portion of the channel region 18) and over a portion of the source region 14. A word line terminal 22 (typically coupled to a word line) has a first portion disposed over and insulated from a second portion of the channel region 18 (and controls the conductivity of the second portion of the channel region 18), and a second portion extending upward above the floating gate 20. A floating gate 20 and a wordline terminal 22 are insulated from the substrate 12 by a gate oxide. A bitline 24 is coupled to the drain region 16.

[0008] The memory cell 210 is erased (electrons are removed from the floating gate) by applying a high positive voltage to the word line terminal 22, which causes electrons in the floating gate 20 to pass via Fowler-Nordheim (FN) tunneling from the floating gate 20 to the word line terminal 22 through the insulator between them.

[0009] The memory cell 210 is programmed by source side injection (SSI) of hot electrons (electrons are added to the floating gate) by applying a positive voltage to the word line terminal 22 and a positive voltage to the source region 14. Electrons flow from the drain region 16 toward the source region 14. The electrons accelerate and heat up when they reach the gap between the word line terminal 22 and the floating gate 20. Some of the heated electrons are injected into the floating gate 20 through the gate oxide due to electrostatic attraction from the floating gate 20.

[0010] The memory cell 210 is read by applying a positive read voltage to the drain region 16 and word line terminal 22 (turning on the portion of the channel region 18 below the word line terminal). When the floating gate 20 is positively charged (i.e., erased with electrons), the portion of the channel region 18 below the floating gate 20 is also turned on, and current flows through the channel region 18, which is sensed as an erased or "1" state. When the floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below the floating gate 20 is mostly or completely off, and no (or very little) current flows through the channel region 18, which is sensed as a programmed or "0" state.

[0011] Table 1 shows typical voltage / current ranges that may be applied to the terminals of memory cell 210 to perform read, erase, and program operations. Table 1: Operation of flash memory cell 210 of FIG. 2 [Table 1]

[0012] Other split-gate memory cell configurations, including other types of flash memory cells, are also known. For example, FIG. 3 shows a four-gate memory cell 310 including a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, all gates, except for the floating gate 20, are non-floating gates, meaning they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons injecting themselves from the channel region 18 into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0013] Table 2 shows typical voltage / current ranges that may be applied to the terminals of memory cell 310 to perform read, erase, and program operations. Table 2: Operation of the flash memory cell 310 of FIG. 3 [Table 2]

[0014] Figure 4 shows another type of flash memory cell, a three-gate memory cell 410. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase and read operations (erasure occurs through the use of an erase gate) are similar to those of Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and as a result, a higher voltage is applied to the source line during a program operation to compensate for the lack of control gate bias.

[0015] Table 3 shows typical voltage / current ranges that may be applied to the terminals of memory cell 410 to perform read, erase, and program operations. Table 3: Operation of flash memory cell 410 of FIG. 4 [Table 3]

[0016] Figure 5 shows another type of flash memory cell, a stacked gate memory cell 510. Memory cell 510 is similar to memory cell 210 of Figure 2, except that the floating gate 20 extends over the entire channel region 18, and a control gate 22 (where it is coupled to a word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erasing is accomplished by FN tunneling of electrons from the FG to the substrate, programming is accomplished by channel hot electron (CHE) injection in the region between the channel 18 and the drain region 16, and read operations are accomplished by electrons flowing from the source region 14 toward the drain region 16, similar to the read operation of memory cell 210, which has a higher control gate voltage.

[0017] Table 4 shows typical voltage ranges that may be applied to the terminals of memory cell 510 and substrate 12 to perform read, erase, and program operations. Table 4: Operation of flash memory cell 510 of FIG. 5 [Table 4]

[0018] The methods and means described herein may be applied to other non-volatile memory technologies such as, but not limited to, FINFET split-gate flash or stacked-gate flash memory, NAND flash, SONOS (silicon-oxide-nitride-oxide-silicon, charge traps in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge traps in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), CT (charge trap) memory, CN (carbon-tube) memory, OTP (one time programmable), and CeRAM (correlated electron ram).

[0019] In order to utilize a memory array containing one of the non-volatile memory cell types in the above artificial neural network, two modifications are made. First, as explained further below, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array. Second, continuous (analog) programming of the memory cells is provided.

[0020] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage is essentially analog, or at a minimum, capable of storing one of a number of discrete values ​​(such as 16 or 64 different values), making every memory cell in the memory array very precisely and individually tunable and making memory arrays ideal for storage and for fine-tuning adjustments to the synaptic weights of neural networks. <Neural network using nonvolatile memory cell array>

[0021] 6 conceptually illustrates a non-limiting example of a neural network utilizing the present example non-volatile memory array. This example uses a non-volatile memory array neural network for a face recognition application, although other suitable applications can also be implemented using a non-volatile memory array-based neural network.

[0022] S0 is the input layer, which in this example is a 32x32 pixel RGB image with 5-bit precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with each pixel having 5-bit precision). Synapse CB1 going from input layer S0 to layer C1 scans the input image with overlapping 3x3 pixel filters (kernels), applying different sets of weights to some instances and shared weights to other instances, and shifts the filters by one pixel (or two or more pixels, depending on the model). Specifically, the values ​​of nine pixels in the 3x3 portion of the image (i.e., referred to as filters or kernels) are provided to synapse CB1, which multiplies these nine input values ​​by the appropriate weights and, after summing the outputs of the multiplications, determines a single output value, which is applied by the first synapse of CB1 to generate one pixel of layer C1's feature map. The 3x3 filter is then shifted one pixel to the right in input layer S0 (i.e., adding a column of three pixels to the right and dropping a column of three pixels on the left), so that the nine pixel values ​​of this newly positioned filter are provided to synapse CB1, where they are multiplied by the same weights as above to determine a second single output value by the associated synapse. This process continues until the 3x3 filter has scanned the entire 32x32 pixel image of input layer S0 for all three colors and all bits (precision values). The process is then repeated using different sets of weights to generate different feature maps for layer C1 until all of layer C1's feature maps have been calculated.

[0023] In this example, there are 16 feature maps in layer C1, each having 30x30 pixels. Each pixel is a new feature pixel extracted from the multiplication of the input and the kernel, and therefore each feature map is a two-dimensional array. Thus, in this example, layer C1 comprises 16 layers of two-dimensional arrays. (Note that the layers and arrays referred to herein are logical, not necessarily physical, relationships; i.e., the arrays are not necessarily oriented in a physical two-dimensional array.) Each of the 16 feature maps in layer C1 is generated by one of 16 different sets of synaptic weights applied to the filter scans. The C1 feature maps can all target different aspects of the same image feature, such as boundary identification. For example, a first map (generated using a first set of weights shared by all scans used to generate this first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges or the aspect ratio of a particular feature, and so on.

[0024] Before going from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. The purpose of pooling function P1 is to average nearby locations (or a max function can be used), e.g., to reduce dependency on edge locations, and to reduce data size before going to the next stage. In layer S1, there are 16 15x15 feature maps (i.e., 16 different arrays of 15x15 pixels each). Synapse CB2 going from layer S1 to layer C2 scans the maps in layer S1 with a 4x4 filter with a filter shift of 1 pixel. In layer C2, there are 22 12x12 feature maps. Before going from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools values ​​from non-overlapping, contiguous 2x2 regions in each feature map. In layer S2, there are 22 6x6 feature maps. At synapse CB3 going from layer S2 to layer C3, an activation function (pooling) is applied, where every neuron in layer C3 connects to every map in layer S2 through a respective synapse in CB3. There are 64 neurons in layer C3. Synapse CB4 going from layer C3 to output layer S3 fully connects C3 to S3, i.e., every neuron in layer C3 connects to every neuron in layer S3. The output at S3 includes 10 neurons, where the neuron with the highest output determines the class. This output can indicate, for example, the identification or classification of the content of the original image.

[0025] Each layer of the synapse is implemented using an array or portion of an array of non-volatile memory cells.

[0026] Figure 7 is a block diagram of an array that can be used for this purpose. A vector-by-matrix multiplication (VMM) array 32 contains nonvolatile memory cells and is utilized as a synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes an array of nonvolatile memory cells 33, an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36, and a source line decoder 37, which decode the respective inputs to the nonvolatile memory cell array 33. Inputs to the VMM array 32 can come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. The source line decoder 37 in this example also decodes the output of the nonvolatile memory cell array 33. Alternatively, the bit line decoder 36 can decode the output of the nonvolatile memory cell array 33.

[0027] The non-volatile memory cell array 33 serves two purposes. First, the non-volatile memory cell array 33 stores the weights used by the VMM array 32. Second, the non-volatile memory cell array 33 effectively multiplies the inputs by the weights stored in the non-volatile memory cell array 33 and sums them for each output line (source line or bit line) to generate an output, which becomes the input to the next layer or the input to the last layer. Having the non-volatile memory cell array 33 perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic circuits and is also more power efficient due to in-memory computation.

[0028] The outputs of the non-volatile memory cell array 33 are fed to a differential summer (such as a summing op-amp or a summing current mirror) 38, which sums the outputs of the non-volatile memory cell array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of the positive and negative weights.

[0029] The summed output values ​​of the differential summer 38 are then provided to an activation function block 39, which normalizes the output. The activation function block 39 may provide a sigmoid, tanh, or ReLU function. The normalized output values ​​of the activation function block 39 become elements of a feature map as the next layer (e.g., C1 in FIG. 6) and are then applied to the next synapse to generate the next feature map layer or the final layer. Thus, in this example, the non-volatile memory cell array 33 constitutes multiple synapses (receiving inputs from a previous layer of neurons or from an input layer such as an image database), and the summing operational amplifiers 38 and the activation function block 39 constitute multiple neurons.

[0030] The inputs to the VMM array 32 of FIG. 7 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, or digital bits (in which case a DAC is provided to convert the digital bits to the appropriate input analog levels), and the outputs may be analog levels, binary levels, or digital bits (in which case an output ADC is provided to convert the output analog levels to digital bits).

[0031] FIG. 8 is a block diagram illustrating the use of multiple layers of VMM array 32, labeled in the figure as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 8, input (denoted Inputx) is converted from digital to analog by digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog input can be a voltage or current. The first layer's input D / A conversion can be performed by using a function or LUT (look up table) that maps input Inputx to the appropriate analog level of the matrix multiplier of input VMM array 32a. The input conversion can also be performed by an analog-to-analog (A / A) converter to convert an external analog input to the mapped analog input to input VMM array 32a.

[0032] The output generated by input VMM array 32a is provided as input to the next VMM array (hidden level 1) 32b, which generates an output that is provided as input to the next input VMM array (hidden level 2) 32c, and so on. The various layers of VMM array 32 function as layers of synapses and neurons of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a standalone physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. 8 includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). Those skilled in the art will appreciate that this is merely an example, and that a system may alternatively include more than two hidden layers and more than two fully connected layers. <Vector × Matrix Multiplication (VMM) Array>

[0033] 9 shows a neuron VMM array 900 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (located at the top of the array). Alternatively, a separate reference array can be located at the bottom.

[0034] In VMM array 900, control gate lines, such as control gate line 903, run vertically (thus, row-oriented reference array 902 is orthogonal to control gate line 903), and erase gate lines, such as erase gate line 904, run horizontally. Here, inputs to VMM array 900 are provided on control gate lines (CG0, CG1, CG2, CG3), and outputs of VMM array 900 appear on source lines (SL0, SL1). In one example, only even rows are used, and in another example, only odd rows are used. The current on each source line (SL0, SL1, respectively) performs the function of summing all the currents from the memory cells connected to that particular source line.

[0035] As described herein for neural networks, the non-volatile memory cells of VMM array 900, i.e., memory cells 310 of VMM array 900, may be configured to optionally operate in the sub-threshold region.

[0036] The nonvolatile reference memory cells and nonvolatile memory cells described herein are biased in weak inversion (subthreshold region) as follows: Ids=Io×e (Vg-Vth) / nVt =w×Io×e (Vg) / nVt , In the formula, w=e (-Vth) / nVt and where Ids is the drain-source current, Vg is the gate voltage of the memory cell, Vth is the threshold voltage of the memory cell, Vt is the thermal voltage = k × T / q, k is Boltzmann's constant, T is temperature in Kelvin, q is the electron charge, n is the slope coefficient = 1 + (Cdep / Cox), Cdep = capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer, Io is the memory cell current at a gate voltage equal to the threshold voltage, Io is (Wt / L) × u ​​× Cox × (n-1) × Vt 2 where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0037] When using an IV-log converter that converts input current to input voltage using a memory cell (such as a reference memory cell or peripheral memory cell) or transistor: Vg=n×Vt×log[Ids / wp×Io] where wp is the w of the reference or peripheral memory cell.

[0038] For a memory array used as a vector x matrix multiplier VMM array with current inputs, the output current is: Iout=wa×Io×e (Vg) / nVt , i.e. Iout=(wa / wp)×Iin=W×Iin W=e (Vthp-Vtha) / nVt where wa=w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cells, and Vtha is the effective threshold voltage of the main (data) memory cells. Note that the threshold voltage of a transistor is a function of the substrate body bias voltage, which is represented as Vsb, and can be modulated to compensate for various conditions at such temperature. The threshold voltage Vth can be expressed as: Vth = Vth0 + gamma(SQRT | Vsb-2 * φF)-SQRT|2 * φF|) where Vth0 is the threshold voltage with zero substrate bias, φF is the surface potential, and gamma is the body effect parameter.

[0039] The word line or control gate can be used as the input of the memory cell for the input voltage.

[0040] Alternatively, the flash memory cells of the VMM arrays described herein can be configured to operate in the linear region. Ids=beta×(Vgs-Vth)×Vds, beta=u×Cox×Wt / L W=α(Vgs-Vth) That is, the weight W in the linear region is proportional to (Vgs-Vth).

[0041] The word line or control gate or bit line or source line can be used as the input of a memory cell operating in the linear region, and the bit line or source line can be used as the output of the memory cell.

[0042] For the IV linear converter, memory cells (such as reference or peripheral memory cells) or transistors operating in the linear region can be used to linearly convert input and output currents to input and output voltages.

[0043] Alternatively, the memory cells of the VMM arrays described herein can be configured to operate in the saturation region. Ids=1 / 2×beta×(Vgs-Vth) 2 , beta=u×Cox×Wt / L Wα(Vgs-Vth) 2 , that is, the weight W is (Vgs-Vth) 2 is proportional to.

[0044] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region, and the bit line or source line can be used as the output of an output neuron.

[0045] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or combinations thereof (subthreshold, linear, or saturation) for each layer or layers of a neural network.

[0046] 7 is described in U.S. Patent No. 10,748,630, which is incorporated herein by reference. As described in that application, the source lines or bit lines can be used as neuron outputs (current sum outputs).

[0047] FIG. 10 shows a neuron VMM array 1000 that is particularly suited for the memory cells 210 shown in FIG. 2 and is utilized as a synapse between an input layer and the next layer. The VMM array 1000 includes a memory array 1003 of nonvolatile memory cells, a reference array 1001 of first nonvolatile reference memory cells, and a reference array 1002 of second nonvolatile reference memory cells. The reference arrays 1001 and 1002, arranged in columns of the array, function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second nonvolatile reference memory cells are diode-connected through a multiplexer 1014 (only partially shown) with current inputs flowing into them. The reference cells are tuned (e.g., programmed) to a target reference level, which is provided by a reference mini-array matrix (not shown).

[0048] Memory array 1003 serves two purposes. First, memory array 1003 stores weights in each memory cell that are used by VMM array 1000. Second, memory array 1003 effectively multiplies the inputs (i.e., the current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1001 and 1002 convert to input voltages provided to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1003, and then adds all the results (memory cell currents) to generate outputs for each bit line (BL0-BLN), which serve as inputs to the next layer or the last layer. By performing the multiplication and addition functions, memory array 1003 eliminates the need for separate multiplication and addition logic circuitry and is also power efficient. Here, voltage inputs are applied to word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0-BLN during a read (inference) operation. The current on each of the bit lines BL0-BLN performs the function of summing the currents from all the non-volatile memory cells connected to that particular bit line.

[0049] Table 5 shows the operating voltages and currents for the VMM array 1000. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 5: Operation of VMM Array 1000 in Figure 10 [Table 5]

[0050] FIG. 11 shows a neuron VMM array 1100 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of first nonvolatile reference memory cells, and a reference array 1102 of second nonvolatile reference memory cells. The reference arrays 1101 and 1102 extend in the row direction of the VMM array 1100. The VMM array is similar to the VMM 1000, except that the word lines extend vertically in the VMM array 1100. Here, inputs are provided to the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and outputs appear on the source lines (SL0, SL1) during a read operation. The current on each source line performs the function of summing all the currents from the memory cells connected to that particular source line.

[0051] Table 6 shows the operating voltages and currents for VMM array 1100. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit lines of the selected cell, the bit lines of the unselected cells, the source lines of the selected cell, and the source lines of the unselected cells. The rows indicate the read, erase, and program operations. Table 6: Operation of VMM Array 1100 in Figure 11 [Table 6]

[0052] 12 shows a neuron VMM array 1200 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 function to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In effect, the first and second nonvolatile reference memory cells are diode-connected through multiplexer 1212 (only a portion of which is shown), with the current inputs flowing through BLR0, BLR1, BLR2, and BLR3. Each of the multiplexers 1212 includes a respective multiplexer 1205 and cascoding transistor 1204 to ensure a constant voltage on the respective bit lines (e.g., BLR0) of the first and second non-volatile reference memory cells during a read operation, in which the reference cells are tuned to a target reference level.

[0053] Memory array 1203 serves two purposes. First, memory array 1203 stores the weights used by VMM array 1200. Second, memory array 1203 effectively multiplies the weights stored in the memory array by the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3; reference arrays 1201 and 1202 convert these current inputs to input voltages provided to control gates (CG0, CG1, CG2, and CG3)) and then adds all the results (cell currents) to generate an output that appears on BL0-BLN and serves as the input to the next layer or the last layer. Having the memory array perform the multiplication and addition functions eliminates the need for separate multiplication and addition logic circuits and is also power efficient. Here, the inputs are provided to the control gate lines (CG0, CG1, CG2, and CG3) and the outputs appear on the bit lines (BL0-BLN) during read operations. The current on each bit line performs the function of summing all the currents from the memory cells connected to that particular bit line.

[0054] VMM array 1200 performs one-way tuning of the non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If too much charge is added to the floating gate (causing the wrong value to be stored in the cell), the cell is erased and the series of partial programming operations starts over. As shown, two rows that share the same erase gate (e.g., EG0 or EG1) are erased together (known as a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0055] Table 7 shows the operating voltages and currents for VMM array 1200. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 7: Operation of VMM Array 1200 in Figure 12 [Table 7]

[0056] FIG. 13 shows a neuron VMM array 1300 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. The VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 or first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1300 is similar to the VMM array 1400, except that the VMM array 1300 implements bidirectional tuning, and each individual cell can be fully erased, partially programmed, and partially erased as needed to reach a desired amount of charge on the floating gate through the use of separate EG lines. As shown, reference arrays 1301 and 1302 convert input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 (through the action of diode-connected reference cells via multiplexer 1314), which are applied to the memory cells in the row direction. The current outputs (neurons) are in bit lines BL0 through BLN, each bit line summing all the currents from the non-volatile memory cells connected to that particular bit line.

[0057] Table 8 shows the operating voltages and currents for VMM array 1300. The columns in the table indicate the voltages applied to the word line of the selected cell, the word lines of the unselected cells, the bit line of the selected cell, the bit lines of the unselected cells, the control gate of the selected cell, the control gates of the unselected cells in the same sector as the selected cell, the control gates of the unselected cells in a different sector from the selected cell, the erase gate of the selected cell, the erase gates of the unselected cells, the source line of the selected cell, and the source lines of the unselected cells. The rows indicate read, erase, and program operations. Table 8: Operation of VMM Array 1300 in Figure 13 [Table 8]

[0058] 22 shows a neuron VMM array 2200 that is particularly suited to the memory cells 210 shown in FIG. 2 and that is used as part of the synapses and neurons between the input layer and the next layer. In the VMM array 2200, inputs INPUT0...., INPUT N are bit lines BL0, ...BL N and outputs OUTPUT1, OUTPUT2, OUTPUT3, and OUTPUT4 are generated on source lines SL0, SL1, SL2, and SL3, respectively.

[0059] 23 shows a neuron VMM array 2300 that is particularly suited for memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2, and INPUT3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0060] 24 shows a neuron VMM array 2400 that is particularly suited for the memory cells 210 shown in FIG. 2 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0061] 25 shows a neuron VMM array 2500 that is particularly suited for the memory cells 310 shown in FIG. 3 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUTM are the word lines WL0, ..., WL M Received and output OUTPUT0, ...OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0062] 26 shows a neuron VMM array 2600 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0,..., INPUT n are the vertical control gate lines CG0, ..., CG N and outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0063] 27 shows a neuron VMM array 2700 that is particularly suited for the memory cells 410 shown in FIG. 4 and that is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT N are the bit lines BL0, ..., BL N , 2701-(N-1) and 2701-N, which are coupled to the gates of the bit line control gates 2701-1, 2701-2, ..., 2701-(N-1) and 2701-N. Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0064] 28 shows a neuron VMM array 2800 that is particularly suited for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is utilized as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the word lines WL0, ..., WL M Received and output OUTPUT0, ..., OUTPUT N are the bit lines BL0, ..., BL N is generated.

[0065] 29 shows a neuron VMM array 2900 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical source lines SL0, ..., SL N and each source line SL i is coupled to the source lines of all memory cells in column i.

[0066] 30 shows a neuron VMM array 3000 that is particularly suitable for memory cells 310 shown in FIG. 3, memory cells 510 shown in FIG. 5, and memory cells 710 shown in FIG. 7, and is used as part of the synapses and neurons between the input layer and the next layer. In this example, inputs INPUT0, ..., INPUT M are the control gate lines CG0, ..., CG M Received at OUTPUT0, ..., OUTPUT N are the vertical bit lines BL0, ..., BL N and each bit line BL i is coupled to the bit lines of all memory cells in column i. <Long and short-term memory>

[0067] Prior art includes a concept known as long short-term memory (LSTM). LSTM units are often used within neural networks. LSTM allows a neural network to store information for any predetermined period of time and use that information in subsequent operations. A traditional LSTM unit includes a cell, an input gate, an output gate, and a forget gate. The three gates regulate the flow of information into and out of the cell and the duration for which information is stored within the LSTM. VMMs are particularly useful in LSTM units.

[0068] 14 shows an example LSTM 1400. In this example, the LSTM 1400 includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 1402 receives an input vector x1, an output vector (hidden state) h0 from cell 1401, and 、 Cell 1403 receives input vector x2, output vector (hidden state) h2 from cell 1402, and cell state c1 from cell 1402, and generates output vector h2 and cell state vector c2. Cell 1404 receives input vector x3, output vector (hidden state) h2 from cell 1403, and cell state c2 from cell 1403, and generates output vector h3. Additional cells can be used; an LSTM with four cells is merely an example.

[0069] Figure 15 shows an example implementation of an LSTM cell 1500 that can be used for cells 1401, 1402, 1403, and 1404 in Figure 14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from a previous cell, and an output vector h(t-1) from a previous cell, and produces a cell state vector c(t) and an output vector h(t).

[0070] LSTM cell 1500 includes sigmoid function devices 1501, 1502, and 1503, each of which applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. LSTM cell 1500 also includes tanh devices 1504 and 1505 for applying a hyperbolic tangent function to the input vector, multiplier devices 1506, 1507, and 1508 for multiplying two vectors, and adder device 1509 for adding the two vectors. The output vector h(t) can be provided to the next LSTM cell in the system or can be accessed for other purposes.

[0071] FIG. 16 shows LSTM cell 1600, an example implementation of LSTM cell 1500. For the convenience of the reader, the same numbering scheme from LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 each include multiple VMM arrays 1601 and activation function blocks 1602. VMM arrays, therefore, prove particularly useful in LSTM cells used in certain neural network systems. Multiplier devices 1506, 1507, and 1508 and summation device 1509 are implemented in digital or analog fashion. Activation function block 1602 can be implemented in digital or analog fashion.

[0072] An alternative example of LSTM cell 1600 (and another example of an implementation of LSTM cell 1500) is shown in Figure 17. In Figure 17, sigmoid function devices 1501, 1502, and 1503 and tanh device 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-multiplexed manner. The LSTM cell 1700 also includes a multiplier device 1703 for multiplying two vectors, an addition device 1708 for adding two vectors, a tanh device 1505 (which includes an activation function block 1702), a register 1707 for storing the value i(t) when i(t) is output from the sigmoid function block 1702, a register 1704 for storing the value f(t)×c(t−1) when that value is output from the multiplier device 1703 via multiplexer 1710, a register 1705 for storing the value i(t)×u(t) when that value is output from the multiplier device 1703 via multiplexer 1710, a register 1706 for storing the value o(t)×c(t) when that value is output from the multiplier device 1703 via multiplexer 1710, and a multiplexer 1709.

[0073] While LSTM cell 1600 includes multiple sets of VMM arrays 1601 and respective activation function blocks 1602, LSTM cell 1700 includes only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the example of LSTM cell 1700. LSTM cell 1700 requires one-quarter the space for the VMMs and activation function blocks compared to LSTM cell 1600, so LSTM cell 1700 requires less space than LSTM 1600.

[0074] It can be further appreciated that an LSTM unit typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Therefore, the example described below reduces the circuitry required outside the VMM array itself. <Gated Recurrent Unit>

[0075] Analog VMM implementations can be used for gated recurrent unit (GRU) systems. GRUs are the gating mechanism within recurrent neural networks. GRUs are similar to LSTMs, except that GRU cells generally contain fewer components than LSTM cells.

[0076] 18 shows an exemplary GRU 1800. GRU 1800 in this example includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives input vector x0 and generates output vector h0. Cell 1802 receives input vector x1 and output vector h0 from cell 1801 and generates output vector h1. Cell 1803 receives input vector x2 and output vector (hidden state) h1 from cell 1802 and generates output vector h2. Cell 1804 receives input vector x3 and output vector (hidden state) h2 from cell 1803 and generates output vector h3. Additional cells can be used; a GRU with four cells is merely an example.

[0077] FIG. 19 shows an example implementation of a GRU cell 1900 that may be used for cells 1801, 1802, 1803, and 1804 of FIG. 18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from a preceding GRU cell and generates an output vector h(t). GRU cell 1900 includes sigmoid function devices 1901 and 1902, each of which applies a number between 0 and 1 to components from the output vector h(t-1) and the input vector x(t). GRU cell 1900 also includes a tanh device 1903 for applying a hyperbolic tangent function to the input vector, multiple multiplier devices 1904, 1905, and 1906 for multiplying two vectors, an adder device 1907 for adding the two vectors, and a complement device 1908 for subtracting the input from 1 to generate the output.

[0078] FIG. 20 shows GRU cell 2000, which is an example of an implementation of GRU cell 1900. For the convenience of the reader, the same numbering scheme as GRU cell 1900 is used in GRU cell 2000. As can be seen from FIG. 20, sigmoid function devices 1901 and 1902 and tanh device 1903 each include multiple VMM arrays 2001 and activation function blocks 2002. Therefore, it can be seen that VMM arrays are particularly used in GRU cells used in specific neural network systems. Multiplier devices 1904, 1905, and 1906, summation device 1907, and complementary device 1908 are implemented in a digital or analog manner. Activation function block 2002 can be implemented in a digital or analog manner.

[0079] An alternative example of GRU cell 2000 (and another example implementation of GRU cell 1900) is shown in Figure 21. In Figure 21, GRU cell 2100 utilizes a VMM array 2101 and an activation function block 2102, which, when configured as a sigmoid function, applies a number between 0 and 1 to control the degree to which each component of the input vector contributes to the output vector. In Figure 21, sigmoid function devices 1901 and 1902 and tanh device 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-multiplexed manner. GRU cell 2100 also includes a multiplier device 2103 for multiplying two vectors, an addition device 2105 for adding the two vectors, a complementation device 2109 for subtracting an input from one to generate an output, a multiplexer 2104, a register 2106 for holding the value h(t-1)×r(t) as it is output from multiplier device 2103 via multiplexer 2104, a register 2107 for holding the value h(t-1)×z(t) as it is output from multiplier device 2103 via multiplexer 2104, and a register 2108 for holding the value h^(t)×(1-z(t)) as it is output from multiplier device 2103 via multiplexer 2104.

[0080] While GRU cell 2000 includes multiple sets of VMM array 2001 and activation function block 2002, GRU cell 2100 includes only one set of VMM array 2101 and activation function block 2102, which are used to represent multiple layers in the example of GRU cell 2100. GRU cell 2100 requires one-third the space for the VMM and activation function block compared to GRU cell 2000, so GRU cell 2100 requires less space than GRU cell 2000.

[0081] It can be further appreciated that a GRU system typically includes multiple VMM arrays, each of which requires functionality provided by specific circuit blocks outside the VMM array, such as adder and activation function blocks and high-voltage generation blocks. Providing separate circuit blocks for each VMM array would require a significant amount of space within a semiconductor device and would be somewhat inefficient. Therefore, the examples described below reduce the circuitry required outside the VMM array itself.

[0082] The input to the VMM array can be an analog level, a binary level, a pulse, a time modulated pulse, or a digital bit (in which case a DAC is required to convert the digital bit to the appropriate input analog level), and the output can be an analog level, a binary level, a timing pulse, a pulse, or a digital bit (in which case an output ADC is required to convert the output analog level to a digital bit).

[0083] Typically, for each memory cell in a VMM array, each weight W can be provided by a single memory cell, a differential cell, or two blended memory cells (the average of two cells). In the case of a differential cell, two memory cells are required to provide the weight W as a differential weight (W=W+-W-). In the case of two blended memory cells, two memory cells are required to provide the weight W as the average of the two cells.

[0084] FIG. 31 illustrates a VMM system 3100. In some examples, the weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W− (negative weight), where W=(W+)−(W−). In VMM system 3100, half of the bit lines are designated as W+ lines, i.e., bit lines connecting to memory cells that will store a positive weight W+, and the other half of the bit lines are designated as W− lines, i.e., bit lines connecting to memory cells that provide a negative weight W−. W− lines are interspersed alternately among the W+ lines. Subtraction operations are performed by summing circuits, such as summing circuits 3101 and 3102, that receive current from the W+ and W− lines. The outputs of the W+ and W− lines are combined together to effectively provide W=W+−W− for each pair of (W+, W−) cells of every pair of (W+, W−) lines. Although described above with respect to W- lines interspersed alternately among W+ lines, in other examples, the W+ and W- lines may be arbitrarily positioned anywhere within the array.

[0085] 32 shows another example: In a VMM system 3210, positive weights W+ are provided in a first array 3211 and negative weights W− are provided in a second array 3212 that is separate from the first array, and the resulting weights are appropriately combined together by a summing circuit 3213.

[0086] Figure 33 shows a VMM system 3300. The weights W stored in the VMM array are stored as a differential pair, W+ (positive weight) and W- (negative weight), where W = (W+) - (W-). VMM system 3300 includes array 3301 and array 3302. Half of the bit lines in each of arrays 3301 and 3302 are designated as W+ lines, i.e., bit lines connecting to memory cells that store a positive weight W+, and the other half of the bit lines in each of arrays 3301 and 3302 are designated as W- lines, i.e., bit lines connecting to memory cells that provide a negative weight W-. W- lines are interspersed alternately among the W+ lines. Subtraction operations are performed by adder circuits, such as adder circuits 3303, 3304, 3305, and 3306, that receive current from the W+ and W- lines. The outputs on the W+ and W- lines from each array 3301, 3302 are combined together, respectively, to effectively give W = W+ - W- for each pair of (W+, W-) cells on every pair of (W+, W-) lines. Additionally, the W values ​​from each array 3301 and 3302 may be further combined via adder circuits 3307 and 3308, meaning that each W value is the result of subtracting the W value from array 3302 from the W value from array 3301, and the final result from adder circuits 3307 and 3308 is one of two difference values.

[0087] Each non-volatile memory cell used in an analog neural memory system is erased and programmed to hold a very specific and precise amount of charge, or number of electrons, in its floating gate. For example, each floating gate should hold one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0088] Prior art VMM systems require significant area and incur significant latency in the input and output stages. At the input stage, multiple clock cycles are required to load activation data into row registers before programming operations. For example, with an 8-bit I / O, 8 bits of activation data are required for each row, which is typically 1024 or more rows, requiring one clock cycle per row, or 1024 clock cycles for 1024 rows, resulting in a latency of 10 ns to 10 μs. At the output stage, shifting out neuron output data incurs a similar latency. For example, with a 128-bit ADC, 128 clocks are required for an 8-bit output.

[0089] To increase the overall operating speed of an artificial neural network, it is desirable to reduce the latency in the input and output stages. Summary of the Invention

[0090] Numerous examples of output circuits and associated methods for implementing parallel and pipelined operations in artificial neural networks are disclosed.

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[0141] [Brief explanation of the drawings]

[0142] [Figure 1] FIG. 1 illustrates an artificial neural network. [Figure 2] 1 shows a prior art split-gate flash memory cell. [Figure 3] 1 illustrates another prior art split-gate flash memory cell. [Figure 4] 1 illustrates another prior art split-gate flash memory cell. [Figure 5] 1 illustrates another prior art split-gate flash memory cell. [Figure 6] FIG. 1 illustrates various levels of an exemplary artificial neural network that utilizes one or more non-volatile memory arrays. [Figure 7]FIG. 1 is a block diagram illustrating a VMM system. [Figure 8] FIG. 1 is a block diagram illustrating an example artificial neural network utilizing one or more VMM systems. [Figure 9] 1 shows another example of a VMM system. [Figure 10] 1 shows another example of a VMM system. [Figure 11] 1 shows another example of a VMM system. [Figure 12] 1 shows another example of a VMM system. [Figure 13] 1 shows another example of a VMM system. [Figure 14] 1 shows a prior art long-term memory system. [Figure 15] An exemplary cell for use in a long-term memory system is shown. [Figure 16] 16 illustrates an exemplary implementation of the cell of FIG. 15. [Figure 17] 16 illustrates another exemplary embodiment of the cell of FIG. 15. [Figure 18] 1 shows a prior art gated recurrent unit system. [Figure 19] 1 shows an exemplary cell for use in a gated recurrent unit system. [Figure 20] 20 illustrates an exemplary implementation of the cell of FIG. 19. [Figure 21] 20 illustrates another exemplary embodiment of the cell of FIG. 19. [Figure 22] 1 shows another example of a VMM system. [Figure 23] 1 shows another example of a VMM system. [Figure 24] 1 shows another example of a VMM system. [Figure 25] 1 shows another example of a VMM system. [Figure 26] 1 shows another example of a VMM system. [Figure 27] 1 shows another example of a VMM system. [Figure 28] 1 shows another example of a VMM system. [Figure 29] 1 shows another example of a VMM system. [Figure 30] 1 shows another example of a VMM system. [Figure 31] 1 shows another example of a VMM system. [Figure 32] 1 shows another example of a VMM system. [Figure 33] 1 shows another example of a VMM system. [Figure 34] 1 shows another example of a VMM system. [Figure 35A] 1 shows the input block for the VMM system. [Figure 35B] 1 shows the input block for the VMM system. [Figure 36] 1 shows the input block for the VMM system. [Figure 37A] 10 illustrates signals associated with input operations for a VMM array. [Figure 37B] 10 illustrates signals associated with input operations for a VMM array. [Figure 38A] 1 shows the input block for the VMM system. [Figure 38B] Indicates the input method. [Figure 39A] 1 shows the input block for the VMM system. [Figure 39B] 1 shows the input block for the VMM system. [Figure 39C] 1 shows the input block for the VMM system. [Figure 39D] 1 shows the input block for the VMM system. [Figure 40A] 1 shows the output block for the VMM system. [Figure 40B] 1 shows the output block for the VMM system. [Figure 40C] 1 shows the output block for the VMM system. [Figure 41] 1 shows waveforms for a VMM system. [Figure 42] 1 shows waveforms for a VMM system. [Figure 43]Shows waveforms for the VMM system. [Figure 44] Shows waveforms for the VMM system. [Figure 45] Shows the neural read operation method. [Figure 46] Shows the neural read operation method. [Figure 47] Shows the neural read operation method. [Figure 48] Shows the neural read operation method. [Figure 49] Shows the neural read operation method.

Mode for Carrying Out the Invention

[0143] <Structure of the VMM System> FIG. 34 shows a block diagram of a VMM system 3400. The VMM system 3400 includes a VMM array 3401, a row decoder 3402, a high voltage decoder 3403, a column decoder 3404, a bit line driver 3405 (such as a bit line control circuit for programming), an input circuit 3406, an output circuit 3407, a control logic 3408, and a bias generator 3409. The VMM system 3400 further includes a high voltage generation block 3410 including a charge pump 3411, a charge pump regulator 3412, and a high voltage level generator 3413. The VMM system 3400 further includes a (program / erase, or weight tuning) algorithm controller 3414, an analog circuit 3415, a control engine 3416 (which may include, but is not limited to, special functions such as arithmetic functions, activation functions, embedded microcontroller logic, etc.), a test control logic 3417, and a static random access memory (SRAM) block 3418 for storing intermediate data such as for the input circuit (e.g., activation data) or output circuit (neuron output data, partial sum output neuron data), or data input for programming (data input for the whole row or multiple rows, etc.).

[0144] The input circuit 3406 may include circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter or a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. The input circuit 3406 may implement one or more of normalization, linear or nonlinear up / downscaling functions, or arithmetic functions. The input circuit 3406 may implement a temperature compensation function for the input level. The input circuit 3406 may implement an activation function such as ReLU or sigmoid. The input circuit 3406 may store digital activation data that is applied as an input signal or combined with an input signal during program or read operations. The digital activation data may be stored in a register. The input circuitry 3406 may include circuitry for driving the array terminals, such as the CG, WL, EG, and SL lines, which may include sample-and-hold circuits and buffers. DACs can be used to convert digital activation data into analog input voltages that are applied to the array.

[0145] The output circuit 3407 may include circuits such as an ITV (current-to-voltage circuit), an ADC (analog-to-digital converter for converting the analog output of the neuron into digital bits), an AAC (analog-to-analog converter such as a current-to-voltage converter or a logarithmic converter), an APC (analog-to-pulse converter), or any other type of converter. The output circuit 3407 can convert the array output into activation data. The output circuit 3407 may implement activation functions such as a rectified linear activation function (ReLU) or a sigmoid. The output circuit 3407 may implement one or more of statistical normalization, regularization, up / downscaling / gain functions, statistical rounding, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, log) of the neuron output. The output circuit 3407 may implement temperature compensation functions for the neuron outputs or array outputs (such as bit line outputs) to keep the power consumption of the array approximately constant or to improve the accuracy of the array (neuron) output, such as by keeping the IV slope approximately the same over temperature changes. The output circuit 3407 may also include registers to store output data.

[0146] 35A shows input block 3500 used to provide input to VMM array 3401. Input block 3500 includes global digital-to-analog converter (DAC) 3501, row registers 3502-0 through 3502-n, each corresponding to one of the rows numbered 0 through n in the array, digital comparator blocks 3503-0 through 3503-n, each corresponding to one of the rows numbered 0 through n in the array, row sample and hold buffers 3504-0 through 3504-n, each corresponding to one of the rows numbered 0 through n in the array, and output signals 3505-0 through 3505-n, each corresponding to one of the rows numbered 0 through n in the array and denoted CGIN0, CGIN1, ..., CGINn-1, and CGINn, respectively. Signal GDACsup is the global DAC signal provided by global DAC 3501. Signals CGIN0 through CGINn couple to respective row inputs of array 3401. CLKDAC is the input clock of the GDACs to provide analog output values. In one example, these analog output values ​​correspond to counts of the CLKDAC clock.

[0147] Digital comparator block 3503 compares the value stored in the associated row register 3502 with signal CLKCOUNTx, which is the result of a counter that counts clock signals during a predetermined interval. If there is a match, the corresponding row S / H 3504 is enabled by the respective digital comparator block 3503 to sample the value from the global DAC 3501 into the respective row S / H buffer. This technique is referred to as global row DAC sampling. As noted above, each row in VMM array 3401 has a corresponding row register 3502, digital comparator block 3503, and row S / H 3504.

[0148] In operation, row registers 3502-0 through 3502-n are loaded with digital input bits DINx (where x is a number of bits, such as 8 or 16) for that particular row and receive a clock signal CLK. The CLK signal is used to load data from the digital input bits DINx into each row register 3502-x. Global DAC 3501 is shared by all rows and performs digital-to-analog conversion on the digital bits DINx stored in a particular row register 3502 in a time-multiplexed manner. The conversion is performed by each of digital comparator blocks 3503 comparing the digital input bits for a particular row with a digital count value, signal CLKCOUNTx. When the digital count value of signal CLKCOUNTx matches the contents of a respective row register 3502, that row's corresponding row sample-and-hold buffer 3504 samples the analog output from global DAC 3501 and holds that value, which is applied as the output signal 3505 for that particular row. The output signal 3504 may be applied to a control gate line or word line or erase gate during a programming operation in that particular row, for example, in the manner described above with respect to the other figures.

[0149] Alternatively, the row sample and hold buffer 3504 may be shared between two or more rows by time division multiplexing the row sample and hold buffer.

[0150] FIG. 35B shows an input block 3550 used to provide input to the VMM array 3401. Input block 3550 includes a global digital-to-analog converter (DAC) 3551, row registers 3552-0 to 3552-n, each corresponding to one of the rows numbered 0 to n in VMM array 3401, digital multiplexer (mux) blocks 3553-0 to 3553-n, each corresponding to a respective one of the rows numbered 0 to n, row sample-and-hold (S / H) buffers 3554-0 to 3554-n, each corresponding to a respective one of the rows numbered 0 to n, and output signals 3555-0 to 3555-n, designated CGIN0, CGIN1..., CGINn-1, and CGINn, respectively, each corresponding to a respective one of the rows numbered 0 to n. A digital mux block 3553 is used to multiplex the data in the row register 3552 onto a bus GDAC_DINx, which is applied as an input to a global DAC 3551. A corresponding row S / H buffer 3554 samples the value from the global DAC into a local S / H buffer 3554. Each row has its own row register 3552, S / H buffer 3554, and output signal 3555.

[0151] In operation, row registers 3552-0 through 3552-n are loaded with digital input bits DINx (where x is the number of bits, such as 8 or 16) for that particular row and receive a clock signal CLK. The CLK signal is used to load data from the digital input bits DINx into each row register 3552. A global digital-to-analog converter 3551 is shared by all rows and performs digital-to-analog conversion on the digital bits DINx stored in a particular row register 3552 in a time-multiplexed manner. The conversion is performed by multiplexing the row register data onto the data input (bus GDAC_DINx) of the global DAC 3551. The multiplexing of row register data onto the data input bus GDAC_DINx is enabled by a respective enable signal EN-x 3557-x for each row. A corresponding row sample-and-hold buffer 3554 samples the analog output from the global DAC 3551 and holds that value, which is applied as the output signal 3555 for that particular row. Output signal 3555 may be applied to a control gate line or word line during a programming operation in that particular row, for example, in the manner described above with respect to other figures.

[0152] Alternatively, the row sample and hold buffer 3554 may be shared among multiple rows by time division multiplexing the row sample and hold buffer.

[0153] FIG. 36 shows an input block 3600 that is used to provide input to the VMM array 3401 . Input block 3600 includes two global DACs 3601-0 and 3601-1, row registers 3602-0 to 3602-n, each corresponding to one of the rows numbered 0 to n in VMM array 3401, digital comparator blocks 3603 to 3603-n, each corresponding to one of the rows numbered 0 to n in VMM array 3401, row sample and hold buffers 3604-0 to 3604-n, each corresponding to one of the rows numbered 0 to n in VMM array 3401, and output signals 3605-0 to 3605-n, designated CGIN0, CGIN1..., CGINn-1, and CGINn, respectively, each corresponding to a respective one of the rows numbered 0 to n. Digital comparator block 3603 compares the value stored in each row register 3602 with signal CLKCOUNTx, which is the result of a counter counting clock signals during a predetermined interval. When the digital count value of signal CLKCOUNTx matches the contents of each row register 3602, each row S / H buffer 3604 is enabled to sample the value from global DAC 3601 into its respective S / H buffer 3604. Each row has its own row register 3602, digital comparator block 3603, and row S / H buffer 3604.

[0154] In operation, row registers 3602-0 through 3602-n are loaded with the digital input bits DINx (where x is the number of bits, such as 8 or 16 bits) for the associated row and receive a clock signal CLK. The CLK signal is used to load data from the digital input bits DINx into row registers 3602-x. Global DAC 3601 (consisting of multiple global DACs, such as 3601-0 and 3601-1) is shared by all rows. In one example, global DAC 3601-0 operates on the even rows and global DAC 3601-1 operates on the odd rows. Global DAC 3601 receives a clock signal CLKDAC and outputs an analog value corresponding to counts of CLKDAC clocks. Global DAC 3601 performs a digital-to-analog conversion on the digital bits DINx stored in the associated row register 3602 (via the GDAC_DINx bus). The row sample and hold buffer 3604 corresponding to that row samples the analog output from the global digital-to-analog converter 3601 and holds that value, which is applied as the output signal 3605 for that particular row. The output signal 3605 may be applied to control gate lines or word lines during programming operations in that particular row(s), for example, in the manner described above with respect to the other figures.

[0155] FIG. 37A shows waveform 3700 illustrating exemplary voltage levels of outputs CGIN0 and CGIN1 after respective sample and hold operations for respective GDACsup 3701 by row sample and hold buffer 3504 of FIG. 35A, row sample and hold buffer 3554 of FIG. 35B, or row sample and hold buffer 3604 of FIG. 36. Signal GDACsup 3701 is a voltage provided by a global DAC, such as global DAC 3501 of FIG. 35A, global DAC 3551 of FIG. 35B, and global DACs 3601-0 and 3601-1 of FIG. 36. GDACsup 3701 is a linear DAC voltage curve, i.e., the global DAC output represents a linear conversion of a digital input value to an analog value. Such a linear conversion is preferable for memory cells operating in the linear region. As an example, signal 3702 indicates the sampled voltage value (level) of row 0 (CGIN0), and signal 3703 indicates the sampled voltage value (level) of row 1 (CGIN1). Signal DAC_sampling_en 3704 is a control signal that enables the sample and hold operation. Four examples of sampling are shown at edges 3705, 3706, 3707, and 3708, which correspond to different voltages being sampled.

[0156] FIG. 37B shows waveform 3720 illustrating exemplary logarithmic voltage levels of outputs CGIN0 and CGIN1 after respective sample and hold operations for respective GDACsup 3721 by row sample and hold buffer 3504 of FIG. 35A, row sample and hold buffer 3554 of FIG. 35B, or row sample and hold buffer 3604 of FIG. 36. The use of logarithmic conversion of digital input values ​​to analog values ​​is suitable for memory cells operating in the subthreshold region. Alternatively, it can be used for memory cells operating in the saturation region. Signal GDACsup 3721 is a voltage supplied from a global DAC, such as global DAC 3501 of FIG. 35A, global DAC 3551 of FIG. 35B, and global DACs 3601-0 and 3601-1 of FIG. 36. GDACsup 3721 is a logarithmic DAC curve. As an example, signal 3722 indicates the sampled voltage value (level) of row 0 (CGIN0), and signal 3723 indicates the sampled voltage value (level) of row 1 (CGIN1). Signal DAC_sampling_en 3724 is a control signal that enables the sample and hold operation. Four examples of sampling are shown at edges 3725, 3726, 3727, and 3728, which correspond to different voltages being sampled.

[0157] The intelligent DAC sampling method is as follows: As shown in Figures 37A and 37B, enabling sampling is done only on the row register used for a particular input operation, meaning that sampling is enabled at the first minimum value of the row register and ends at the maximum value of the row register. This is to reduce the sampling time to be required based only on the range of values ​​of the row register's inputs (i.e., the values ​​of the activation inputs).

[0158] Furthermore, if the maximum number of rows are enabled for sampling at one time, for example, a maximum of 128 rows are enabled, so that, for example, if there are 180 rows enabled for the same input value, sampling will occur twice, once for 128 rows and a second time for 62 rows, or once for 90 rows and a second time for 90 rows. This is to reduce the load on the sampling circuitry in cases where a large load may cause undesirable settling times.

[0159] Figure 38 depicts input block 3800 used in VMM array 3401. Input block 3800 comprises sub-block 3810, SRAM 3418, registers 3801-0, 3801-1, ..., 3801-n, and address decoders 3804-0, 3804-1, ..., 3804-n. Sub-block 3810 may optionally comprise one of input blocks 3500, 3550, and 3600 from Figures 35A, 35B, and 36, respectively. Sub-block 3810 comprises registers 3802-0, 3802-1, ..., 3802-n, row sample-and-hold buffers 3803-0, 3803-1, ..., 3803-n, and possibly intermediate circuitry according to Figures 35A, 35B, and 36. In an example where sub-block 3810 includes input block 3500, register 3802 includes row register 3502, and row sample and hold buffer 3803 includes row sample and hold buffer 3504. In an example where sub-block 3810 includes input block 3550, register 3802 includes row register 3552, and row sample and hold buffer 3803 includes row sample and hold buffer 3554. In an example where sub-block 3810 includes input block 3600, register 3802 includes row register 3602, and row sample and hold buffer 3803 includes row sample and hold buffer 3604.

[0160] Address decoder 3804 receives an address for a data input load operation to load data into register 3802 or register 3801. The data may be activation data or input data, such as from an object or image to be classified or recognized in a neural network application. It outputs a signal to enable register 3801 or register 3802 indicating which register is being asserted for data in the load operation. The data input (not shown) typically varies from 8 to 256 bits.

[0161] Address decoder 3804 also receives an address for a read verify or program operation and outputs a signal indicating which row is asserted for the read verify or program operation to register 3801 or register 3802. Read-verify is a read operation used in weight tuning, where a cell is programmed to a target current representing the target weight in the neural network, and then the cell current is verified to ensure it approximates the target current during the weight tuning algorithm.

[0162] Registers 3802 use activation data stored in each such register to enable row sample and hold buffers 3803. In an exemplary implementation, there may be 1024 rows and 1024 instances of registers 3802, where 8 bits of activation data are stored in each register 3802.

[0163] The number of clock cycles R required to load data for register 3802 is R = number of rows x 8 (for 8-bit activation data) divided by the width of the data, e.g., 16-bit data (e.g., R = 1024 x 8 / 16 = 512).

[0164] Register 3801 is coupled to and includes one associated register for each register 3802. Each register 3801 is loaded with activation data for its associated register 3802, which may be done sequentially over R clock cycles. Then, during a first clock cycle, data from each register 3801 is loaded in parallel into its associated register 3802. Thus, registers 3802 are loaded from their respective registers 3801 in parallel in a single time period, rather than being loaded serially over R clock cycles. This significantly speeds up the timing of data in the load operation.

[0165] Optionally, SRAM 3418 can be used to sequentially load all registers 3802 during R clock cycles as a background operation.

[0166] Optionally, SRAM 3418 is used to sequentially load the data into registers 3801. Figure 38B illustrates an input method 3850 that can be implemented using the input block 3800 of Figure 38A. A first operation is to output, by a plurality of address decoders, a plurality of row enable signals in response to an address (3851). A next operation is to sequentially store, by a first plurality of registers, activation data in response to the plurality of row enable signals (3852). The sequential storing step optionally includes receiving activation data by the first plurality of registers from a static random access memory. A next operation is to store, in parallel, by a second plurality of registers, the activation data received from the first plurality of registers (3853). A next operation is to drive, by a plurality of row sample and hold buffers, rows of an array of non-volatile memory cells during a read neuron operation in response to the activation data received from the second plurality of registers (3854).

[0167] Figure 39A shows input block 3900. Input block 3900 comprises sub-block 3910, VMM array 3401, and address decoders 3904-0, 3904-1, ..., 3904-n. Sub-block 3910 may optionally comprise one of input blocks 3500, 3550, and 3600 from Figures 35A, 35B, and 36, respectively. Sub-block 3910 comprises registers 3902-0, 3902-1, ..., 3902-n, row sample-and-hold buffers 3903-0, 3903-1, ..., 3903-n, and possibly intermediate circuitry according to Figures 35A, 35B, and 36. In an example where sub-block 3910 includes input block 3500, row register 3902 includes row register 3502, and row sample and hold buffer 3803 includes row sample and hold buffer 3504. In an example where sub-block 3910 includes input block 3550, row register 3902 includes row register 3552, and row sample and hold buffer 3903l includes row sample and hold buffer 3554. In an example where sub-block 3910 includes input block 3600, row register 3902 includes row register 3602, and row sample and hold buffer 3903l includes row sample and hold buffer 3604.

[0168] Address decoder 3904 receives addresses for data input load operations to load data (not shown) into registers 3902. The data may be activation data or input data, such as from an object or image to be classified or recognized in a neural network application. It outputs signals to enable row registers 3902 indicating which registers are asserted for data in a load operation. The data input (not shown) typically varies from 8 to 256 bits.

[0169] Address decoder 3904 may also receive an address for a read verify or program operation and outputs a signal to row register 3902 indicating which row is asserted for the read verify or program operation. In this example, each row register stores activation data (e.g., 8 bits of activation data) as well as one or more tag bits, e.g., one for row enable and another for row DAC sampling. For example, row register 3902-0 includes tag bit 3905-0, row register 3902-1 includes tag bit 3905-1, row register 3902-n includes tag bit 3905-n, and so on. Tag bit (row enable tag bit) 3905 is used for row enable, which disables the activation input data stored in the row register regardless of whether the row is selected by address decoder 3904. For example, if tag bit 3905-0 for row 0 has a particular value (e.g., a “1” value), the activation data in row register 3902-0 is output. If tag bit 3905-0 has a different value (e.g., a "0" value), the activation data in row register 3902-0 is not output and row S / H buffer 3903-0 receives the Z state from row register 3902-0. Another tag bit (row S / H tag bit) is used for row DAC sampling to enable or disable sampling of the global DAC value into the local row S / H buffer 3903.

[0170] Figure 39B shows input block 3920. Input block 3920 is similar to input block 3900, except that it includes a second set of row registers (shadow registers) 3906-0, 3906-1, ..., 3906-n, each including a respective tag bit 3907-0, 3907-1, ..., 3907-n. Each row can toggle between row register 3902 and row register 3906. For example, during one operation, address decoder 3904 provides output to row register 3902, and during another operation, address decoder 3904 provides output to row register 3906. For example, during one operation, row register 3902-0 outputs data if tag bit 3905 is enabled, and during another operation, row register 3906 outputs data if tag bit 3907 is enabled. This toggling can be implemented by a multiplexer (not shown) or other control logic. In this way, activation data can be loaded into one set of row registers 3902 or 3906 while the other set is used to actively output that activation data according to a signal from address decoder 3904.

[0171] Figure 39C shows input block 3940. Input block 3940 is similar to input block 3900, except that it includes a second set of row registers 3908-0, 3908-1, ..., 3908-n, each including a respective tag bit 3909-0, 3909-1, ..., 3909-n. Each row can toggle between row register 3902 and row register 3908. For example, during one operation, address decoder 3904 provides output to row register 3902, and during another operation, address decoder 3904 provides output to row register 3908. For example, during one operation, row register 3902 outputs data if tag bit 3905 is enabled, and during another operation, row register 3908 outputs data if tag bit 3909 is enabled. This toggling can be implemented by a multiplexer (not shown) or other control logic. In this way, activation data can be loaded into one set of row registers 3902 or 3908 while the other set of row registers is used to actively output that activation data according to signals from address decoder 3904.

[0172] Figure 39D shows input block 3960. Input block 3960 is similar to input block 3940, except that it includes a second set of row sample-and-hold buffers 3911-0, 3911-1, ..., 3911-n for the same array input (e.g., CGINx). Each row can toggle between row register 3902 and row register 3908. For example, during one operation, address decoder 3904 provides output to row register 3902, and during another operation, address decoder 3904 provides output to row register 3908. Similarly, during one operation, row register 3902 outputs data according to tag bit 3905, and during another operation, row register 3908 outputs data according to tag bit 3909. Each row can toggle (using control signals (not shown)) between row S / H buffer 3903 and row S / H buffer 3911. This toggling can be implemented by a multiplexer (not shown) or other control logic. In this way, one set of row registers 3902 or 3908 can be loaded with activation data while the other set is being used to actively output that activation data according to a signal from address decoder 3904.

[0173] In one example, the first activation data and the first tag bit are loaded into row register 3902, and the second activation data and the second tag bit are loaded into row register 3908. The first activation data and the second activation data may be the same or different, and the first tag bit and the second tag bit may be the same or different.

[0174] FIG. 40A shows an input block 4000. The output block 4000 receives output currents from the VMM array 3401 (not shown), typically from bit lines or source lines of the VMM array 3401. The output block 4000 includes a current-to-voltage converter 4001, an analog-to-digital converter 4002, an output register 4003, and an output register 4004. The current-to-voltage converter 4001 converts the currents received from the VMM array 3401 into respective voltages whose values ​​reflect the values ​​of the currents received from the VMM array 3401. The analog-to-digital converter 4002 converts these respective voltages into bits that represent the values ​​of the voltages received from the respective current-to-voltage converters 4001, which therefore reflect the values ​​of the currents received from the VMM array 3401. The bits are then stored in either the output register 4003 or the output register 4004. The output operation can toggle between the output register 4003 and the output register 4004. For example, during a first operation during a first time period (e.g., one or more clock cycles), output data is loaded into output register 4003. During a second operation during a second time period (e.g., one or more clock cycles) after the first time period, that data is read from output register 4003 by another device in the system, and new output data is loaded into output register 4004. During a third operation during a third time period (e.g., one or more clock cycles) after the second time period, that new output data is read from output register 4004 by another device in the system, and optionally, the output data can be loaded into output register 4003, and the sequence repeats. This reduces the amount of latency associated with the output operation, as data can be read from the first output register by an external device while other data can be loaded into other output registers at the same time.

[0175] Optionally, output block 4000 optionally comprises column tag bits 4005 for enabling current-to-voltage converter 4001 and analog-to-digital converter 4002. Column tag bits 4005 may be included in either current-to-voltage converter 4001 or analog-to-digital converter 4002. Column tag bits 4005 may include a column tag bit for each column in VMM array 3401. Loading of column tag bits 4005 is similar to loading of row tag bits described above with reference to FIGS. 39A-39D. Function of column tag bits is similar to function of row tag bits described above with reference to FIGS. 39A-39D. For example, current-to-voltage converter 4001 and analog-to-digital converter 4002 may be configured to output data for a column when column tag bit 4005 for that column has a first value and not output data when column tag bit has a second value, depending on which one includes column tag bit 4005.

[0176] FIG. 40B shows input block 4020. Output block 4020 is the same as output block 4000, but with the addition of accumulator 4021. Accumulator 4021 can sum values ​​received from current-to-voltage converter 4001, analog-to-digital converter 4002, output register 4003, and output register 4004 over a period of time. This can be useful, for example, when neural read operations are performed on VMM array 3401 in a time-multiplexed manner by reading out half of the rows during a first time period and the other half of the rows during a second time period. The output from the first time period can be received by output register 4003, and the output from the second time period can be received by output register 4004, and the accumulator can sum the values ​​received from output register 4003 and output register 4004.

[0177] The output block 4000 optionally includes column tag bits 4005 for enabling the current-to-voltage converter 4001 and the analog-to-digital converter 4002. The column tag bits 4005 may be included in either the current-to-voltage converter 4001 or the analog-to-digital converter 4002. The column tag bits 4005 may include a column tag bit for each column in the VMM array 3401. The loading of the column tag bits 4005 is similar to the loading of the row tag bits described above with reference to Figures 39A-39D. The function of the column tag bits is similar to the function of the row tag bits described above with reference to Figures 39A-39D. For example, the current-to-voltage converter 4001 and the analog-to-digital converter 4002 may be configured to output data for a column when the column tag bit 4005 for that column has a first value and not output data when the column tag bit has a second value, depending on which one includes the column tag bit 4005.

[0178] 40C provides an exemplary circuit for output accumulator 4021. The output accumulator receives data from current-to-voltage converter 4001, analog-to-digital converter 4002, output register 4003, and output register 4004. The data is received by shifter 4042, which performs a shift function in response to EN_SHIFT. The output D1 of shifter 4042 is provided to adder 4043, which adds D1 to D2, which also receives D2 and is enabled by EN_ADD.

[0179] The output of the adder 4043 is provided to one or more accumulator registers 4044, which store the output of the adder 4043 and return it to the adder 4043 as D2 for the next addition operation. In one configuration where there are three or more accumulator registers 4044, one shifter 4042, and one adder 4043, the shifters 4042 and adders 4043 are shared between different outputs of the ITV 4001 and ADC 4002, or output registers 4003 or 4004. Each accumulator register is used for operations on a respective output of the ITV 4001 and ADC 4002, or output register 4003 or 4004. In this manner, the outputs of the current-to-voltage converter 4001, analog-to-digital converter 4002, output register 4003, and output register 4004 can be added over a period of time.

[0180] The shifter 4042 is used, for example, during serial input (DAC) mode, in which one bit of the activation input is read out at a time, and the amount of shift of the output bit depends on the binary position of the input bit. For example, the LSB (least significant bit) of the input bit results in no shift in the output, the (LSB+1) input bit results in a one-bit left shift, the (LSB+2) input bit results in a two-bit left shift, and so on; this read operation is performed eight times for the 8-bit activation input. The final output from the accumulator register 4044 is the result of the entire 8-bit activation input.

[0181] FIG. 41 shows waveforms 4100 for a first phase 4101 in which row registers are loaded with activation data, and a second phase 4102 in which neural read operations are performed using the activation data.

[0182] FIG. 42 shows a waveform 4200 of a random access read operation 4201.

[0183] FIG. 43 shows a waveform 4300 of a burst read operation 4301.

[0184] FIG. 44 shows a waveform 4400 of a neural read operation 4401.

[0185] Figure 45 shows a neural read operation 4500. The neural read operation 4500 begins (4501). Activation data is loaded into the row register (4502). Next, a group of N rows is enabled (4503). Next, a column address is input (4504). A read operation is performed (4505), which involves DAC sampling as shown in Figures 37A and 37B (utilizing the circuitry shown in Figures 35A-35B, 36, 38, and 39A-39D) and the (bit line) output circuit 3407 in Figure 34 (using the ITV to convert current to a voltage and the ADC to convert the voltage to a digital output), and the output data is the digital output from the ADC. The data is loaded into the output register (4506). The system determines whether another column address needs to be read. If yes, it returns to operation 4504. If not, the system determines whether another group of N rows needs to be read (4508). If yes, it returns to operation 4503. If no, the neural read operation is performed (4509), at which point the data output is optionally shifted out (4510) or the neural read operation ends. For each neural read operation, for a group of rows with column switching, the neural read time is the DAC latency of one row plus the N ITV+DAC latencies with N column multiplexing. For example, if the DAC latency is 2 μs and the ITV+ADC latency is 1 μs, the time to read out the entire row is 1 × (DAC latency) + 16 × (ITV+ADC latency) = 18 μs. Essentially, for the next column neural read, the DAC latency does not contribute any additional time.

[0186] Figure 46 illustrates a neural read operation 4600. The neural read operation 4600 begins (4601). Activation data is loaded into a first set of row registers (4603). The activation data is then loaded into a second set of row registers (4602). Concurrent with this event, the column address or row group is changed (4604). The read operation is performed (4605). The output data is loaded into the output registers (4606). If a read operation is not to be performed (4607), the process returns to operation 4604. If a read operation is to be performed, the system (using a logic controller (not shown)) determines (4608) whether data needs to be loaded from the second set of row registers into the first set of row registers. If no, a neural read operation is performed (4611). If yes, data is loaded from the second set of row registers into the first set of row registers (4609). The system then determines (4610) whether a neural read operation is to be performed. If yes, a neural read operation is performed 4611. If not, it returns to operation 4604.

[0187] Figure 47 shows a neural read operation 4700. First, activation data is loaded into a first set of row registers (4701). Then, activation data is loaded into a second set of row registers (4702). Concurrent with this event, the column address or row group is changed (4703). A read operation is performed (4704). Data is loaded into an output register (4705). If a read operation is to be performed (4706), the system proceeds to operation 4707. If no, the system returns to operation 4703. In operation 4707, the system determines whether the second set of row registers and their corresponding row S / H buffers are enabled. If yes, the operation is performed (4708). If no, the second set of row registers and their corresponding row S / H buffers are enabled, and the system returns to operation 4703 to continue the neural read operation.

[0188] Figure 48 shows a read operation 4800. Previously, digital output data has been loaded into Output Register 1 or Output Register 2. The output data is then shifted out of Output Register 1 or Output Register 2 (4801).

[0189] Figure 49 shows a neural read operation 4900. First, activation data is loaded into the row register (4901). Then, data is shifted out of output register 1 or output register 2 (4902). Concurrent with this event, the column address or row group is changed (4903). The neural read operation is performed (4904). Data is loaded into output register 1 or output register 2 (4905). If a neural read operation is to be performed (4906), the operation is performed (4907). If not, the system returns to operation 4903 and continues the neural read operation.

[0190] It should be noted that, as used herein, both the terms "over" and "on" are inclusive of "directly" (with no intermediate material, element, or gap disposed therebetween) and "indirectly" (with an intermediate material, element, or gap disposed therebetween). Similarly, the term "adjacent" includes "directly adjacent" (with no intermediate material, element, or gap disposed therebetween) and "indirectly adjacent" (with an intermediate material, element, or gap disposed therebetween); "attached" includes "directly attached" (with no intermediate material, element, or gap disposed therebetween) and "indirectly attached" (with an intermediate material, element, or gap disposed therebetween); and "electrically coupled" includes "directly electrically coupled" (with no intermediate material or element disposed therebetween that electrically connects the elements together) and "indirectly electrically coupled" (with an intermediate material or element disposed therebetween that electrically connects the elements together). For example, forming an element "over a substrate" can include forming the element directly on the substrate with no intermediate materials / elements therebetween, and forming the element indirectly on the substrate with one or more intermediate materials / elements therebetween.

Claims

1. 1. A system comprising: an array of non-volatile memory cells arranged in rows and columns; an output block for converting current from a column of the array to a first digital output during a first time period and to a second digital output during a second time period; a first output register for storing the first digital output during the first time period and for outputting the stored first digital output during the second time period; a second output register for storing the second digital output during the second time period and for outputting the stored second digital output during a third time period.

2. 2. The system of claim 1, further comprising an accumulator for summing data received from one or more of the output block, the first output register, and the second output register.

3. 3. The system of claim 2, wherein the output block comprises a current-to-voltage converter for converting the current from the column of the array into a voltage, and an analog-to-digital converter for converting the voltage into the first digital output.

4. The system of claim 3 , wherein the current-to-voltage converter and the analog-to-digital converter comprise column tag bits.

5. 5. The system of claim 4, wherein the current-to-voltage converter outputs data when the column tag bits have a first value and outputs no data when the column tag bits have a second value.

6. 5. The system of claim 4, wherein the analog-to-digital converter outputs data when the column tag bits have a first value and does not output data when the column tag bits have a second value.

7. The accumulator a shifter for receiving data from one or more of the output block, the first output register, and the second output register and generating a first output; an adder for receiving and summing the first output and the second output to generate a third output; an accumulator register for receiving and storing the third output and providing the third output to the adder as the second output.

8. 8. The system of claim 7, wherein the output block comprises a current-to-voltage converter for converting the current from the column of the array into a voltage, and an analog-to-digital converter for converting the voltage into the first digital output.

9. 2. The system of claim 1, wherein the output block comprises a current-to-voltage converter for converting the current from the column of the array into a voltage, and an analog-to-digital converter for converting the voltage into the first digital output.

10. 1. A method comprising: During a first time period, converting, by an output block, a current from a column of the array of non-volatile memory cells into a first digital output; storing the first digital output in a first output register; During a second time period, converting, by the output block, a current from a column of the array of non-volatile memory cells into a second digital output; storing the second digital output in a second output register; and outputting the stored first digital output from the first output register.

11. During a third time period, converting, by the output block, a current from a column of the array of non-volatile memory cells into a third digital output; storing the third digital output in the first output register; and outputting the stored second digital output from the second output register.

12. 12. The method of claim 11, further comprising summing, by an accumulator, data received from one or more of the output block, the first output register, and the second output register.

13. 13. The method of claim 12, wherein the output block comprises a current-to-voltage converter for converting the current from the column of the array into a voltage, and an analog-to-digital converter for converting the voltage into the first digital output.

14. 14. The method of claim 13, wherein the current-to-voltage converter and the analog-to-digital converter comprise column tag bits.

15. 15. The method of claim 14, wherein the current-to-voltage converter outputs data when the column tag bits have a first value and does not output data when the column tag bits have a second value.

16. 15. The method of claim 14, wherein the analog-to-digital converter outputs data when the column tag bits have a first value and does not output data when the column tag bits have a second value.

17. The accumulator a shifter for receiving data from one or more of the output block, the first output register, and the second output register and generating a first output; an adder for receiving and summing the first output and the second output to generate a third output; an accumulator register for receiving and storing the third output and providing the third output to the adder as the second output.

18. 13. The method of claim 12, wherein the output block comprises a current-to-voltage converter for converting the current from the column of the array into a voltage, and an analog-to-digital converter for converting the voltage into the first digital output.

19. 11. The method of claim 10, wherein the output block comprises a current-to-voltage converter for converting the current from the column of the array into a voltage, and an analog-to-digital converter for converting the voltage into the first digital output.

20. 1. A system comprising: an array of non-volatile memory cells arranged in rows and columns; an output block for converting currents from columns of the array to a first digital output during a first time period and to a second digital output during a second time period, the output block comprising a current-to-voltage converter for converting the currents from the columns of the array to a voltage and an analog-to-digital converter for converting the voltages to the first digital output and the second digital output; an accumulator for summing data received from said output block during said first time period and said second time period.

21. 21. The system of claim 20, wherein the current-to-voltage converter and the analog-to-digital converter comprise column tag bits.

22. 22. The system of claim 21, wherein the current-to-voltage converter outputs data when the column tag bits have a first value and does not output data when the column tag bits have a second value.

23. 22. The system of claim 21, wherein the analog-to-digital converter outputs data when the column tag bits have a first value and does not output data when the column tag bits have a second value.

24. a first output register for storing the first digital output during the first time period and for outputting the stored first digital output during the second time period; a second output register for storing the second digital output during the second time period and outputting the stored second digital output during a third time period; 22. The system of claim 21, comprising:

25. The accumulator a shifter for receiving data from one or more of the output block, the first output register, and the second output register and generating a first output; an adder for receiving and summing the first output and the second output to generate a third output; 21. The system of claim 20, further comprising: an accumulator register for receiving and storing the third output and providing the third output to the adder as the second output.

26. 1. A system comprising: an array of non-volatile memory cells arranged in rows and columns; a first output register for storing a first digital output during a first time period and outputting the stored first digital output during a second time period; a second output register for storing a second digital output during the second time period and outputting the stored second digital output during a third time period; an accumulator for summing data received from the first output register and the second output register.

27. 21. The system of claim 20, wherein the system comprises a column tag bit.

28. 22. The system of claim 21, wherein the accumulator receives data when the column tag bits have a first value and does not receive data when the column tag bits have a second value.

29. The accumulator a shifter for receiving data from one or more of an output block, the first output register, and the second output register and for generating a first output; an adder for receiving and summing the first output and the second output to generate a third output; 27. The system of claim 26, further comprising: an accumulator register for receiving and storing the third output and providing the third output to the adder as the second output.

30. 1. A system comprising: an array of non-volatile memory cells arranged in rows and columns; An output block, a first current-to-voltage converter for converting a current from the column of the array to a first voltage during a first time period, and a first analog-to-digital converter for converting the first voltage to a first digital output; an output block comprising: a second current-to-voltage converter for converting a current from the column of the array to a second voltage during a second time period; and a second analog-to-digital converter for converting the second voltage to a second digital output; an accumulator for adding the first digital output and the second digital output.

31. 31. The system of claim 30, wherein the first current-to-voltage converter and the first analog-to-digital converter comprise first column tag bits, and the second current-to-voltage converter and the second analog-to-digital converter comprise second column tag bits.

32. 32. The system of claim 31, wherein the first current-to-voltage converter outputs data when the first column tag bit has a first value and does not output data when the first column tag bit has a second value, and the second current-to-voltage converter outputs data when the second column tag bit has the first value and does not output data when the second column tag bit has the second value.

33. a first output register for storing the first digital output during the first time period and for outputting the stored first digital output to the accumulator during the second time period; a second output register for storing the second digital output during the second time period and for outputting the stored second digital output to the accumulator during a third time period.

34. 1. A system comprising: an array of non-volatile memory cells arranged in rows and columns; an output block for converting current from a column of the array to a first digital output during a first time period and to a second digital output during a second time period; a first output register for storing the first digital output during the first time period and for outputting the stored first digital output during the second time period; a second output register for storing the second digital output during the second time period and outputting the stored second digital output during a third time period; an accumulator for summing data received from one of: (i) the first output register during the first time period and the second output register during the second time period; or (2) the first output register during the first time period and the second output register during the second time period.

35. 35. The system of claim 34, wherein the output block comprises a current-to-voltage converter for converting the current from the column of the array into a voltage during the first time period, and an analog-to-digital converter for converting the voltage into the first digital output.

36. 36. The system of claim 35, wherein the current-to-voltage converter and the analog-to-digital converter comprise column tag bits.

37. 37. The system of claim 36, wherein the current-to-voltage converter outputs data when the column tag bits have a first value and does not output data when the column tag bits have a second value.

38. 37. The system of claim 36, wherein the analog-to-digital converter outputs data when the column tag bits have a first value and does not output data when the column tag bits have a second value.

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